Surface treatment of the IC package and process

Abstract

A package comprises a first IC die and a second IC die bonded to and over the first. A first surface region of the second IC die is hydrophobic, and the first and second IC dies are bonded to each other via dielectric-to-dielectric and metal-to-metal bonds. The package further comprises a first insulating material surrounding the first IC and the second IC die. This first insulating material contacts the first surface region.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 532,456, filed August 14, 2023, which is incorporated by reference into the present application. BACKGROUND

[0002] Since the development of the IC (Integrated Circuit), the semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). These improvements in integration density have largely resulted from repeated reductions in the minimum feature size, allowing more components to be integrated into a given area.

[0003] These integration improvements are essentially two-dimensional (2D) in nature, as the area occupied by the integrated components is largely on the surface of the semiconductor wafer. The increased density and corresponding reduction in IC area has generally overtaken the ability to bond an IC chip directly to a substrate. Interposers have been used to redistribute ball contact areas from those of the chip with a larger interposer area. Furthermore, interposers have enabled a three-dimensional package containing multiple chips. Other packages have also been developed to accommodate three-dimensional aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1, Fig. 2, Fig. 3, Fig. 4A, Fig. 4B, Fig. 4C, Fig. 5 and Fig. 6 illustrate cross-sectional views of various intermediate steps for singulating an IC die in accordance with various embodiments. Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14A and Fig. 14B illustrate cross-sectional views of various intermediate steps of packaging an IC die in accordance with various embodiments. Fig. 15, Fig. 16, Fig. 17, Fig. 18A and Fig. 18B illustrate cross-sectional views of various intermediate steps of packaging an IC die in accordance with various embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact and may also include embodiments in which additional structural elements may be formed between the first and second structural elements such that the first and second structural elements may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplification and clarity and does not in itself imply any relationship between the different embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "underlying," "beneath," "under," "overlying," "upper," and the like may be used herein for ease of description to describe the relationship of one element or structural element to another element(s) or structural element(s) as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0007] According to various embodiments, a singulation process is performed to separate individual semiconductor die from a wafer. The singulation process may include patterning trenches in the scribe line regions of the wafer and performing a surface treatment to provide hydrophobic sidewalls in the trenches. In some embodiments, the surface treatment is a fluorine-based treatment. The hydrophobic sidewalls may prevent a protective layer (e.g., a layer of backside anti-reflective coating (BARC) or the like) from being deposited in the trenches in a subsequent singulation step. A planarization process may then be performed to remove a backside of the wafer, separating the semiconductor die along the trenches.

[0008] The protective coating layer can protect the semiconductor die during the planarization process, and a cleaning process can be used to remove the protective layer after the planarization process. Because the protective layer is not deposited in the trenches, the cleaning process can remove the protective layer more effectively, improving yield and reducing wafer reconstructive tool (RW) failure. For example, if the protective layer fills the trenches, the semiconductor die cannot be successfully separated from the wafer, resulting in RW failure. As another example, the protective layer remaining on the sidewalls of the singulated semiconductor die can result in defects when the semiconductor die is packaged with other components in a semiconductor package.By converting the sidewalls of the trenches to be hydrophobic through fluorine-based treatment, such defects can be avoided and the yield can be improved.

[0009] Fig. 1 is a cross-sectional view of a wafer 40 having IC dies 50. The IC dies 50 are packaged in subsequent processing to form IC packages. Each IC die 50 may comprise a logic device (e.g., central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory device (e.g., dynamic random access memory die (DRAM die), static random access memory die (SRAM die), etc.), a power management device (e.g., power management integrated circuit die (PMIC die), a radio frequency die (RF die), a sensor device, a micro-electro-mechanical system device (MEMS device), a signal processing device (e.g.,Digital Signal Processing Die (DSP Die), a front-end device (e.g., analog front-end dies (AFE dies), the like, or combinations thereof (e.g., a system-on-a-chip die (SoC die). The IC dies 50 may be formed in the wafer 40, which may have different device regions that are singulated in subsequent steps to form a plurality of IC dies 50. In particular, the device regions may be separated by scribe line regions 48 in which the subsequent singulation process is performed. In some embodiments, the scribe line regions 48 provide test lines that can be used to perform electrical tests and / or yield tests during the manufacturing process. The IC dies 50 each include a semiconductor substrate 52, an interconnect structure 54, and bond pads 66 formed in an insulating bonding layer 68 are arranged.

[0010] The semiconductor substrate 52 may be a silicon substrate, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may contain other semiconductor materials, such as germanium; a compound semiconductor containing silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor containing silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer or graded substrates, may also be used. The semiconductor substrate 52 has an active surface (e.g., the upward-facing surface) and an inactive surface (e.g., the downward-facing surface).Components are located on the active surface of the semiconductor substrate 52. The components may be active components (e.g., transistors, diodes, etc.), capacitors, resistors, etc. The inactive surface may be free of components.

[0011] The interconnect structure 54 overlies the active surface of the semiconductor substrate 52 and is used to electrically connect the components of the semiconductor substrate 52 to form one or more integrated circuits. The interconnect structure 54 may include metallization structure(s) 54A in one or more of the dielectric layer(s) 54B. Acceptable dielectric materials for the dielectric layers 54B include oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; the like; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or the like. Other dielectric materials may also be used. The metallization structures 54A may include conductive vias and / or conductive lines to interconnect the components of the semiconductor substrate 52.The metallization structures 54A may be formed from a conductive material, such as a metal such as copper, cobalt, aluminum, gold, combinations thereof, or the like. The interconnect structure 54 may be formed by a damascene process, such as a single damascene process, a double damascene process, or the like. The interconnect structure 54 may further include metal pads 54C (e.g., aluminum pads, copper pads, or the like) connected to a topmost metallization structure 54A of the interconnect structure 54 via one or more passivation layers. An additional insulating layer (e.g., a passivation layer 54D) may be formed around the metal pads 54C to provide a planar surface on which the overlying structural elements (e.g., bond pads 66 and an insulating bonding layer 68, see . Fig. 5) are to be formed.

[0012] Fig. 2 to 4C are various views of intermediate steps during a dicing process to separate the IC dies 50 from the wafer 40. Starting with Fig. 2, trenches 58 are formed that extend through the interconnect structure 54 and into the semiconductor substrate 52. The trenches 58 may be patterned in the scribe line region 48 between adjacent IC dies 50. In some embodiments, the scribe line region 48 may be wide enough to accommodate the trenches 58 and a test line region for the wafer 40.

[0013] In some embodiments, the trenches 58 are formed using a combination of photolithography and etching processes. For example, the trenches 58 may be formed in the scribe line regions 48 using a plasma excision process. The plasma excision process may include forming a patterned mask 56 over the interconnect structure. The patterned mask 56 may be a photomask deposited over the interconnect structure 54 using a spin-on process and patterned by lithography (e.g., exposure and development) to define openings that expose the interconnect structure 54 in the scribe line 48. The plasma excision process etches portions of the interconnect structure 54 and the semiconductor substrate 52 through the structures (e.g., openings) in the patterned mask 55.In some embodiments, the plasma excision is a dry plasma process, such as reactive ion etching (RIE) using a fluorine-based plasma, an argon-based plasma, an oxygen-based plasma, a nitrogen-based plasma, or the like. The trenches 58 may extend through the interconnect structure 54 to a desired depth into the semiconductor substrate 552. However, the trenches 58 may not extend completely through the semiconductor substrate 52, and lower portions of the semiconductor substrate 52 may remain to connect the IC dies 50 to each other in the wafer 40.

[0014] In Fig. 3, a surface treatment is performed in the trenches 58 to form surface regions 60 on exposed surfaces of the trenches 58. The surface regions 60 may be hydrophobic. In some embodiments, the surface treatment is a fluorine-based treatment, such as a wet cleaning process using a fluorine-containing solution, a fluorine-based plasma process, or the like. In some embodiments, the fluorine-based plasma process may be performed at a temperature in a range of 25°C to 500°C and at a pressure of 0 Torr to 1.316×10 -3 Torr (one atmosphere). Other treatments that form hydrophobic surfaces can be applied in other embodiments. The surface treatment makes the surfaces of the trenches 58 hydrophobic, so that a subsequently formed protective layer (e.g., protective layer 62, see Fig. 4A) can be deposited over the interconnect structure 54 without being substantially deposited in the trenches 58. If the surface treatment is a fluorine-based treatment, the resulting surface regions 60 may also contain fluorine and be referred to as a fluorinated protective layer 60. For example, surface regions 60 may contain 5 weight percent (wt%) or more of fluorine, which advantageously results in hydrophobic surfaces in the trenches 58. It has been observed that when the surface regions 60 have less than 5 wt% fluorine, they can remain hydrophilic and do not substantially prevent deposition of the subsequently formed protective layer in the trenches 58. The surface regions 60 may further contain carbon, oxygen, silicon, nitrogen, or a combination thereof.The specific material composition of the surface regions 60 may depend on a material of the interconnect structure 54 and / or the semiconductor substrate 52 on which the surface regions 60 are formed. For example, portions of the surface regions 60 on the semiconductor substrate may contain fluorine and silicon, while portions of the surface regions 60 on the interconnect structure 54 may contain fluorine in combination with carbon, oxygen, nitrogen, and / or silicon. A thickness T1 of the surface regions 60 may range from 60 Å to 10 µm.

[0015] The surface treatment may be performed while the patterned mask 56 covers the interconnect structure 54. As a result, the surface regions 60 may be selectively formed in the trenches 58 without forming the surface regions 60 overlying the interconnect structure 54. For example, after the surface treatment, the top surface of the interconnect structure 54 may remain hydrophilic so that a protective layer may be deposited thereon (e.g., the protective layer 62, see Fig. 4A). After surface treatment, the patterned mask 56 can be removed. For example, if the patterned mask 56 is a photomask, the patterned mask 56 can be removed using an ashing process.

[0016] In Fig. 4A, a protective layer 62 is deposited over interconnect structure 54. In some embodiments, the protective layer 62 is a BARC layer deposited by a spin-on process or the like. As a result of the surface treatment and the hydrophobic surface regions 60, the protective layer 62 cannot be deposited significantly within the trenches 58. Preventing the protective layer 62 from being deposited in the trenches 58 achieves benefits such as reduced manufacturing defects and improved yield.

[0017] For example, Fig. 4B a material 62' of the protective layer 62 on an untreated substrate 52. Because the previously described surface treatment process has not been carried out and no surface area 60 in Fig. 4B, surfaces of the substrate 52 remain hydrophilic. In particular, the hydrophilic property of the substrate 52 can be measured by a contact angle θ1 at a liquid-vapor interface between the material 62' and the semiconductor substrate 52 that is less than 10°. The material 62' can be easily deposited on the hydrophilic surfaces (e.g., filling at least upper portions of the trenches 58), and the IC dies 50 may not completely separate after subsequent planarization processes (see Fig. 5). For example, the protective layer 62 may clog the trenches 58 and glue adjacent IC dies 50 together, preventing separation of the IC dies 50. Even if the IC dies 50 are completely singulated, the protective layer 62 may leave an undesirable residue on the sidewalls of the singulated IC dies 50. This residue may result in manufacturing defects (e.g., gap-filling voids) during subsequent packaging processes.

[0018] In contrast, Fig. 4C illustrates the material 62' of the protective layer 62 on the substrate 52 with a surface region 60 formed with the previously described surface treatment. The surface region 60 provides a hydrophobic surface that repels the material 62' and prevents the material 62' from being deposited within the trenches 58. The hydrophobic nature of the surface region 60 can be demonstrated by the contact angle θ2 at a liquid-vapor interface between the material 62' and the surface region 60 of greater than 10°. Because the surface regions 60 repel the protective layer 62, the IC dies 50 can be more easily singulated, and unwanted residue on sidewalls of the singulated IC dies 50 can be avoided.

[0019] As it is also Fig. 4A, an adhesive tape 64 is adhered to the wafer 40, such as to a top surface of the protective layer 62. The adhesive tape 64 supports the wafer 40 during subsequent singulation processes, and the protective layer 62 acts as an intermediate buffer between the wafer and the adhesive tape 64. For example, the protective layer 62 protects a top surface of the interconnect structure 54 from direct contact with the adhesive tape 64, which reduces the risk of damage to the interconnect structure 54.

[0020] In Fig. 5, a backside planarization process is performed to thin the semiconductor substrate 52. The planarization process may be performed to remove portions of the semiconductor substrate 52 beyond the trenches 58. In particular, the planarization process removes portions of the semiconductor substrate 52 that connect the IC dies 50 and exposes the trenches 48 from the backside of the semiconductor substrate 52. In some embodiments, the planarization process is a CMP process, a mechanical grinding process, an etch-back process, combinations thereof, or the like.

[0021] After the backside planarization process has been performed on the semiconductor substrate 52, the adhesive tape 64 may be removed, and a cleaning process may be performed to remove the protective layer 62. The cleaning process may be wet cleaning or the like using a suitable cleaning solution. In some embodiments, the cleaning solution may include deionized water (DI water), an alkali solution, an ammonia-based solution (e.g., containing Na, K, C, O, H, or the like), combinations thereof, or the like. Because the protective layer 62 is not substantially deposited within the trenches 58, the protective layer 62 may be more easily removed by the cleaning process without leaving behind a desired residue or portions that would adversely adhere the IC dies 50 to each other. As a result, the IC dies 50 may be completely separated from each other, as described by Fig. 6 is illustrated.

[0022] Fig. 6 illustrates a single IC die 50 according to the method previously described in Fig. 2 to 5. In the illustrated embodiment, the surface region 60 is formed as a result of the previously described singulation process on opposite sidewalls of the IC die 50. In other embodiments (e.g., when the IC die 50 is located at a wafer edge), at least one sidewall of the IC die 50 may be free of the surface region 60 (see, e.g., Fig. 14B and Fig. 18B).

[0023] Further, bond pads 66 are formed in an insulating bonding layer 68 on the front side 50F of the IC die 50. The bond pads 66 may be conductive pillars, pads, or the like to which external connections are made. The bond pads 66 may be formed from a metal, such as copper, aluminum, or the like, and may be formed by, for example, plating or the like. In some embodiments, the bond pads 66 may be electrically connected to conductive structural elements of the interconnect structure 54 (e.g., the metal pads 54C) through conductive vias (sometimes referred to as bond pad vias).

[0024] The bond pads 66 can be arranged in an insulating bonding layer 68 on the front side 50F of the IC die 50. The insulating bonding layer 68 can be made of a material suitable for subsequent dielectric-to-dielectric bonding, such as silicon oxide, silicon oxynitride, or the like. The insulating bonding layer 68 can be deposited on the interconnect structure, for example, by spin-coating, lamination, chemical vapor deposition (CVD), or the like. The bond pads 66 may be formed in the insulating bonding layer using, for example, a damascene process, and a planarization process (e.g., chemical mechanical polishing (CMP) or the like) may be performed so that top surfaces of the bond pads 66 and the insulating bonding layer 68 are coplanar (within process variations) and exposed at the front side 50F of the IC die 50.As described in more detail below, the planarized front side 50F of the IC die 50 is bonded directly to another package component, such as another IC die.

[0025] In some embodiments, the IC die 50 is a stacked device comprising a plurality of semiconductor substrates 52. For example, the IC die 50 may be a memory device comprising a plurality of memory dies, such as a hybrid memory cube (HMC) device, a high bandwidth memory (HBM) device, or the like. In such embodiments, the IC die 50 comprises a plurality of semiconductor substrates 52 interconnected by through-substrate vias or through-silicon vias (TSVs). Each of the semiconductor substrates 52 may (or may not) include a separate interconnect structure 54.

[0026] Fig. 7 to 14B are cross-sectional views of intermediate steps during a process for forming IC packages in accordance with some embodiments, where the IC dies 50 are packaged with other package components. Details of the IC dies 50 can be found in Fig. 7 to 14B have been simplified for ease of illustration. While Fig. 7 to 14B illustrate a particular package configuration (e.g., a system-on-integrated-chip packaging configuration (SoIC packaging configuration, System on Integrated Chip packaging configuration), however, it should be appreciated that other package configurations (e.g., integrated fan-out packaging (InFO packaging), chip-on-wafer-on-substrate packaging (CoWoS packaging, chip-on-wafer-on-substrate packaging) or the like) may be used as well.

[0027] In Fig. 7 to 14B, IC packages 150 (marked as 150A and 150B, see Fig. 14A and Fig. 14B) is formed by bonding IC dies 50 to an IC die 70 on a carrier substrate 100. Because the IC dies 50 are bonded above the IC die 70, the IC dies 50 and the IC die 70 may also be referred to as a top IC die 50 and a bottom IC die 70, respectively.

[0028] First, in relation to Fig. 7 illustrates the IC die 70 on a carrier substrate 100. The carrier substrate 100 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 100 may be a wafer, so that multiple packages can be formed simultaneously on the carrier substrate 100. An insulating bonding layer 102 is deposited on a top surface of the carrier substrate 100. The insulating bonding layer 102 may include a silicon-containing dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, deposited using a suitable deposition process, such as CVD, PVD, ALD, high-density plasma chemical vapor deposition (HDPCVD), or the like. In some embodiments, alignment marks 101 are optionally arranged in the insulating bonding layer 102. The alignment marks 101 can allow precise placement of structures (e.g.the IC die 70) on the carrier substrate 100. Optionally, a planarization step may then be performed to flatten a top surface of the insulating bonding layer 102 so that the insulating bonding layer 102 has a high degree of planarity.

[0029] The IC die 70 may be attached to the carrier substrate 100. The IC die 70 is arranged upside down so that the front sides 70F of the IC die 70 face the carrier substrate 100 and the back sides 70B of the IC die 70 face away from the carrier substrate 100. The IC die 70 includes a substrate 72, an interconnect structure 74, conductive vias 76 in the substrate 72, and an insulating bonding layer 78.

[0030] The substrate 72 may be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer semiconductor substrate, or the like. The substrate 72 may include a semiconductor material such as silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer or graded substrates, may also be used. The substrate 72 may be doped or undoped. In some embodiments, active devices such as transistors, diodes, and the like may be formed in and / or on the front side of the substrate 72.In some embodiments, passive components such as capacitors, resistors, or the like may be formed in addition to or instead of the active components on the front side of the substrate 72.

[0031] The interconnect structure 74 overlies the front surface of the substrate 72 and is used to electrically connect the components of the substrate 72. Therefore, the front side 70F of the IC die 70 may refer to a side of the substrate 72 on which the interconnect structure 74 and any components are disposed. The interconnect structure 74 may include one or more dielectric layers and respective metallization structures within the dielectric layers. Acceptable dielectric materials for the dielectric layers include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or the like.Other dielectric materials may also be used, such as a polymer such as polybenzoxazole (PBO), polyimide, a benzocyclobutene-based (BCB-based) polymer, or the like. The metallization structures may include conductive vias and / or conductive lines to connect any devices to each other and / or to an external device. The metallization structures may be formed from a conductive material, such as a metal such as copper, cobalt, aluminum, gold, combinations thereof, or the like. The interconnect structure 74 may be formed by a damascene process, such as a single damascene process, a double damascene process, or the like.

[0032] The conductive vias 76 are embedded in the substrate 72 and / or the interconnect structure 74. The conductive vias 76 are electrically coupled to metallization structures of the interconnect structure 74. The conductive vias 76 are sometimes referred to as TSVs. As an example of forming the conductive vias 76, recesses may be formed in the interconnect structure 74 and / or the substrate 72 by, for example, etching, milling, laser techniques, a combination thereof, and / or the like. A thin dielectric material may be formed in the recesses, such as using an oxidation technique. A thin barrier layer may be conformally deposited in the openings, such as by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, and / or the like.The barrier layer may be formed from an oxide, a nitride, a carbide, combinations thereof, or the like. A conductive material may be deposited over the barrier layer and in the openings. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, a combination thereof, and / or the like. Examples of conductive materials include copper, tungsten, aluminum, silver, gold, a combination thereof, and / or the like. Excess conductive material and the barrier layer are removed from a surface of the interconnect structure 74 or the substrate 72 by, for example, CMP. Remaining portions of the barrier layer and conductive material form the conductive vias 76. The conductive vias 76 are electrically connected to the metallization structures of the interconnect structure 74.

[0033] In some embodiments, the conductive vias 76 may be formed in a first region 71A of the IC die 70 without being formed in a second region 71B of the IC die 70. The second region 71B may correspond to a location where a dummy die may subsequently be bonded for improved heat dissipation (e.g., dummy die 80, see Fig. 10). In other embodiments, the conductive vias 76 may be formed uniformly across the IC die 70.

[0034] The IC die 70 may initially be formed as part of a wafer, which is substantially singulated to separate the IC die 70 from other components of the wafer. In the illustrated embodiments, the IC die 70 is singulated without performing the steps previously described with respect to Fig. 2-5. As such, sidewall surfaces of the IC die 70 may be hydrophilic and may be free of any surface areas. For example, sidewalls of the IC die 70 may be completely free of any fluorine-containing surface areas or may have less than 5 wt.% fluorine. In other embodiments, the singulation process may be substantially similar to that previously described in Fig. 2-5. In such embodiments, sidewalls of the IC die 70 may have surface areas that are hydrophobic (e.g., fluorine-containing surface areas with more than 5 wt.% fluorine). Such embodiments are described below in the embodiment of Fig. 15 to 18B.

[0035] An insulating bonding layer 78 is formed on the front side of the IC die 70, as on the interconnect structure 74. The insulating bonding layer 78 may be formed from a similar material using similar processes as the previously described insulating bonding layer 102. The IC die 70 may be attached to the carrier substrate 100 by bonding the insulating bonding layers 102 and 78 together using a dielectric-to-dielectric bonding process (e.g., oxide-to-oxide bonding). The dielectric-to-dielectric bond may be initiated by activating the insulating bonding layer 102 and / or the insulating bonding layer 78, followed by applying pressure, heat, and / or other bonding process steps to attach the insulating bonding layer 102 to the surfaces of the insulating bonding layer 78.Activation of the insulating bonding layer 102 and / or the insulating bonding layer 78 may be performed using, for example, a dry treatment, a wet treatment, a plasma treatment, exposure to H2, exposure to N2, exposure to O2, combinations thereof, or the like. In embodiments where a wet treatment is used, for example, an RCA cleaning process may be used. The activation treatment increases the number of OH groups on the surface(s) of the insulating bonding layer 102 and / or the insulating bonding layer 78. After surfaces of the insulating bonding layer 102 and / or the insulating bonding layer 78 have been activated, the insulating bonding layer 102 and the insulating bonding layer 78 may be brought into contact with each other at a relatively low temperature (e.g., room temperature) to form weak bonds.Annealing is then performed to strengthen the weak bonds and form a fusion bond. During annealing, the hydrogen from the OH bonds is outgassed, forming Si-O-Si bonds between the insulating bonding layer 102 and the insulating bonding layer 78, thereby strengthening the bonds (e.g., forming covalent bonds).

[0036] In Fig. 8, an insulating material 104 is formed over the carrier substrate 100 and around the IC die 70. In some embodiments, the insulating material 104 is a dielectric, gap fill material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, combinations thereof, or the like, deposited by PVD, CVD, or the like. In some embodiments, the insulating material 104 is a molded material or composite material formed by compression molding, transfer molding, or the like, followed by a curing process. The molded material may or may not include filler materials (e.g., silica fillers). The insulating material 104 may be formed over the front side 70F of the IC die 70 such that the IC die 70 is at least partially buried or covered. A planarization process may be performed to planarize the top surface of the insulating material 104 and the back surface 70B of the IC die 70.The planarization process may be CMP, etch-back, combinations thereof, or the like. In the illustrated embodiment, the IC die 70 is exposed by planarizing the insulating material 104 so that top surfaces of the IC die 70 and the insulating material 104 are substantially planar (within process variations). Planarization may also remove portions of the semiconductor substrate 72 to expose the conductive vias 76. The insulating material 104 surrounds and protects the IC die 70.

[0037] In Fig. 9, an insulating bonding layer 108 and bond pads 106 are located on the backside 70B of the IC die 70. The insulating bonding layer 108 and the bond pads 106 may be formed using similar processes from a similar material as the previously described insulated bonding layer 68 and bond pads 66, respectively. The insulating bonding layer 108 may be deposited to cover the backside 70B of the IC die 70 and the insulating material 104. The bond pads 106 may be formed over and in electrical communication with the conductive vias 76. In embodiments where the conductive vias 76 are not disposed in the second region 71B of the IC die 70, the bond pads 106 may not be formed over the second region 71B of the IC die 70.

[0038] In Fig. 10, IC die 50 is bonded to IC die 70. In some embodiments, IC die 50 performs a different function than IC die 70. For example, IC die 70 may be a logic processing die, and IC die 70 may be a memory die. In other embodiments, IC dies 50 and 70 may perform different functions than logic processing / storage, or IC dies 50 and 70 may perform the same function.

[0039] The IC die 50 and the IC die 70 are bonded directly front-to-back by a dielectric-to-dielectric bonding and metal-to-metal bonding process (sometimes referred to as hybrid bonding) such that the front side 50F of the IC die 50 is bonded to the back side 70B of the IC die 70. In particular, the insulating bonding layer 68 of the IC die 50 is bonded to the insulating bonding layer 108 on the IC die 70 by dielectric-to-dielectric bonding without using any adhesive material (e.g., die adhesive film), and the bonding pads 66 of the IC die 50 are bonded to the bonding pads 106 on the IC die 70 by metal-to-metal bonding without using any eutectic material (e.g., solder). The bonding may include surface activation, pre-bonding, and annealing. The surface activation may include activating the insulating bonding layer 108 and / or the insulating bonding layer 68 using, for example,a dry treatment, a wet treatment, a plasma treatment, exposure to H2, exposure to N2, exposure to O2, combinations thereof, or the like. In embodiments where a wet treatment is used, for example, an RCA cleaning process may be used. The activation treatment increases the number of OH groups at the surface(s) of the insulating bonding layer 108 and / or the insulating bonding layer 68. After surfaces of the insulating bonding layer 108 and / or the insulating bonding layer 68 have been activated, pre-bonding is performed by applying a small compressive force to press the IC die 50 against the IC die 70. The pre-bonding is performed at a low temperature, such as room temperature, such as a temperature in the range of about 15°C to about 30°C.The bonding strength of the insulating bonding layers 68 and 108 is then improved in a subsequent annealing step in which the insulating bonding layers 68 and 108 are annealed at a high temperature, such as a temperature in the range of about 100°C to about 450°C. After annealing, bonds, such as covalent bonds, are formed that bond the insulating bonding layers 68 and 108. The bond pads 66 and 106 are connected to each other with a one-to-one correspondence. The bond pads 66 and 106 may be in physical contact with each other after pre-bonding, or they may expand to be brought into physical contact during annealing. Further, the material of the bond pads 66 and 106 (e.g., copper) mixes during annealing, so that metal-to-metal bonds are also formed. Therefore, the resulting bonds are hybrid bonds that contain both dielectric-to-dielectric bonds and metal-to-metal bonds.The IC die 50 can be bonded to the first region 71A of the IC die 70, in which the conductive vias 76 are disposed. As a result, the circuit within the IC die 50 can be electrically connected to a circuit within the IC die 70 via the bond pads 68 and the conductive vias 76.

[0040] As well as through Fig. 10, a dummy die 80 is bonded over the second region 81B of the IC die 70. The dummy die 80 may be a bulk semiconductor die (e.g., silicon die) or the like that is free of any components disposed therein. The dummy die 80 may be provided to facilitate heat dissipation away from the IC die 70 in the completed package. In some embodiments, the dummy die 80 may be initially formed in a wafer and a singulation process similar to that previously described in Fig. 2 to 5 can be applied to separate the dummy die 80 from the wafer. In particular, a surface treatment may be performed on the dummy die 80 such that the dummy die 80 has hydrophobic sidewalls provided by surface regions 82. In embodiments where the surface treatment performed on the dummy die 80 is a fluorine-based treatment, the surface regions 82 also contain fluorine. In some embodiments, a fluorine concentration of the surface regions 82 may be at least 5 wt. % to provide the hydrophobic sidewalls and achieve the previously described benefits (e.g., clean separation and reduced residue on the dummy die 80). An insulating bonding layer 84 may be disposed on the dummy die 80, and the insulating bonding layer 84 may bond the dummy die 80 directly to the insulating bonding layer 108 using a dielectric-to-dielectric bonding process.In particular, the insulating bonding layers 84 and 108 may be bonded to each other using a process similar to the previously described bonding of the insulating bonding layers 78 and 102.

[0041] In Fig. 11, an insulating material 110 is formed over the insulating bonding layer 108 and around the IC die 50 and the dummy die 80. The insulating material 110 may be formed from a similar material using similar processes as the previously described insulating material 104. For example, in some embodiments, the insulating material 110 is a dielectric, gap fill material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, combinations thereof, or the like, deposited by PVD, CVD, or the like. In some embodiments, the insulating material 110 is a molded material or composite material formed by compression molding, transfer molding, or the like, followed by an aging process. The molded material may or may not include filler materials (e.g., silica fillers).A planarization process may be performed to planarize the top surface of the insulating material 110 and the backside 50B of the IC die 50. The planarization process may be a CMP, an etchback, combinations thereof, or the like. In the illustrated embodiment, the IC die 50 and the dummy die 80 are exposed by the planarization of the insulating material 110, so that top surfaces of the IC die 50, the dummy die 80, and the insulating material 104 are substantially planar (within process variations).

[0042] As a result of the previously Fig. 2 to 5, sidewalls of the IC die 50 and / or the dummy die 80 may be hydrophobic and include surface areas 60 and 82. The hydrophobic sidewalls of the IC die 50 repel any unwanted residue from previous process steps from accumulating on the sidewalls of the IC die and / or the dummy die 80. Therefore, the insulating material 110 may be deposited around the IC die 50 and the dummy die 80 with improved adhesion to the sidewalls of the IC die 50 and the dummy die 80, and manufacturing defects may be reduced.

[0043] In Fig. 12, a carrier substrate 120 is mounted over the IC die 50, the dummy die 80, and the insulating material 110. The carrier substrate 120 may be substantially similar to the previously described carrier substrate 100. To mount the carrier substrate 120, an insulating bonding layer 112A is deposited over the IC die 50, the dummy die 80, and the insulating material 110, and an insulating bonding layer 112B is deposited over the carrier substrate 120. The insulating bonding layers 112A and 112B may be formed from a similar material using similar processes as the previously described insulating bonding layer 102. The insulating bonding layers 112A and 112B may then be bonded together using a similar dielectric-to-dielectric bonding process as the bonding of the insulating bonding layers 78 and 102 described previously.The resulting bonded insulating bonding layers 112A and 112B may collectively be referred to as a bonded layer 112. As a result, the carrier substrate 120 is bonded over the IC die 50, the dummy die 80, and the insulating material 110.

[0044] In Fig. 13, the entire structure may be flipped, and the carrier substrate 100 may be removed from the front side 70F of the IC die 70. Removing the carrier substrate 100 may include a planarization process, such as CMP, grinding, etching back, combinations thereof, or the like. Removing the carrier substrate 100 may further remove the insulating bonding layer 102 and expose the IC die 70 and the insulating material 104.

[0045] In Fig. 14A and Fig. 14B, one or more passivation layers 114 are formed over the IC die 70 and the insulating material 110. The passivation layers 114 may include a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or the like), a polymer material (e.g., a polyimide, polybenzoxazole (PBO), polyimide, a benzocyclobutene-based (BCB-based) polymer, or the like), or combinations thereof. For example, the passivation layer 114 may include a dielectric layer 114A and a polymer layer 114B over the dielectric layer 114A. Other configurations of the passivation layer 114 are also possible.

[0046] Additionally, underbump metallurgies (UBMs) 116 are formed on and extending through the passivation layer 114. The UBMs 116 may be electrically connected to metallization structures in the interconnect structure 74 of the IC die 70. As an example of forming the UBMs 116, openings in the passivation layer 114 may be patterned to expose the interconnect structure 74. Patterning the openings may, in some embodiments, be achieved by a combination of photolithography and etching. In other embodiments, the openings in the passivation layer 114 may be achieved, for example, by laser drilling. A seed layer (not illustrated) is formed in the openings. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed from different materials.In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed on the seed layer and patterned. The photoresist may be formed by spin-on coating or the like and exposed to light for patterning. The pattern of the photoresist corresponds to the UBMs 116. Patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like.Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as using an acceptable etching process. The remaining portions of the seed layer and the conductive material form the UBMs 116.

[0047] Further, conductive interconnects 118 are formed on the UBMs 116. The conductive interconnects 118 may be ball grid array (BGA) interconnects, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, electroless palladium-immersion gold (ENEPIG) formed bumps, or the like. The conductive interconnects 118 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive interconnects 118 are formed by initially forming a layer of solder by evaporation, electroplating, printing, solder transfer, ball placement, or the like.Once a layer of solder has been formed on the structure, reflow may be performed to form the material into desired bump shapes. In another embodiment, the conductive interconnects 118 include metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal termination layer is formed on the metal pillars. The metal termination layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed by a plating process.

[0048] Therefore, semiconductor packages 150A and 150B are formed. Fig. 14A illustrates semiconductor package 150A, where surface regions 60 and surface regions 82 are formed on all sidewalls of IC die 50 and dummy die 80, respectively. As a result, all sidewalls of IC die 50 and dummy die 80 are hydrophobic and may contain fluorine. Fig. 14B illustrates semiconductor package 150B where surface regions 60 and surface regions 82 are formed only on a subset of sidewalls of IC die 50 and dummy die 80, respectively. As a result, some sidewalls of IC die 50 and dummy die 80 are hydrophobic and may contain fluorine, while other sidewalls of IC die 50 and dummy die 80 are hydrophilic and may contain substantially no fluorine (e.g., less than 5 wt. % fluorine).

[0049] Fig. 7 to 14B illustrate a packaging process where the IC dies 70 have not been subjected to a surface treatment (e.g., a fluorine-based treatment) to form hydrophobic sidewall regions. In other embodiments, a surface treatment may be applied to the IC dies 70 in a substantially similar process as previously described in Fig. 2-5. In such embodiments, sidewalls of the IC die 70 may have surface areas that are hydrophobic (e.g., fluorine-containing surface areas with more than 5 wt.% fluorine). Fig. 15 to 18B illustrate intermediate processing steps of packaging IC dies 70 having hydrophobic surface areas with IC dies 50. In Fig. 15 to 18B, similar reference numbers indicate similar elements that are used by similar processes as the embodiments of Fig. 7 to 14B, unless otherwise stated.

[0050] In Fig. 15, IC dies 70 are attached to a carrier substrate 100. Each of the IC dies 70 comprises a semiconductor substrate 72, an interconnect structure 74, and conductive vias 76 embedded in the semiconductor substrate 72, as previously described in Fig. 7. The IC dies 70 may initially be formed as part of a wafer and then formed using the process described previously in Fig. 2 to 5. In particular, trenches in the wafer could be structured along crack line regions, as previously described in Fig. 2. Then, a surface treatment, such as fluorine-based treatment, can be carried out in the trenches, as previously described in Fig. 3. The fluorine-based treatment creates surface regions 90 on sidewalls of the trenches (which also correspond to sidewalls of the semiconductor substrate 72 and the interconnect structure 74). In some embodiments, the surface regions 90 contain fluorine, such as fluorine at a concentration of 5 wt. % or more, to create hydrophobic sidewalls in the trenches. It has been found that when the surface regions 90 comprise less than 5 wt. % fluorine, they can remain hydrophilic and do not substantially prevent deposition of the subsequently formed protective layer in the trenches. The surface regions 90 may further contain carbon, oxygen, silicon, nitrogen, or a combination thereof. The particular material composition of the surface regions 90 may depend on a material of the interconnect structure 74 and / or the semiconductor substrate 72 on which the surface regions 90 are formed.For example, portions of the surface regions 90 on the semiconductor substrate 72 may contain fluorine and silicon, while portions of the surface regions 90 on the interconnect structure 74 may contain fluorine in combination with carbon, oxygen, nitrogen, and / or silicon. The thickness of the surface regions 90 may range from 60 Å to 10 µm.

[0051] After the surface treatment has been performed, a backside planarization process may be performed to remove portions of the semiconductor substrate 72 that connect the IC dies 70 to the wafer using a process similar to that in Fig. 5. The backside planarization process may or may not expose the conductive vias 76. During the backside planarization process, the wafer may be attached to an adhesive tape, and a protective layer may cover a front side of the wafer to prevent damage from direct contact with the adhesive tape. Due to the surface treatment and hydrophobic sidewalls in the trenches, the material of the protective layer is not deposited within the trenches, allowing improved separation of the IC dies 70 and avoiding unwanted surface residue on the sidewalls of the IC dies 70. The adhesive tape and the protective layer may then be removed as previously described, resulting in fully singulated IC dies 70. The singulated IC dies may then be bonded by insulating bonding layers 78 and 102 in a similar manner as previously described in Fig. 7 described to the carrier substrate 100. Although Fig. 15 illustrates two IC dies 70 bonded to the carrier substrate 100, any number of IC dies 70 may be bonded to the carrier substrate 100.

[0052] In Fig. 16, an insulating material 104 is applied around the IC dies 70 in a similar manner as previously described in Fig. 8. Due to the hydrophobic surface areas 90, surface residue on the sidewalls of the IC dies 70 can be reduced and the insulating material 104 can be deposited with improved adhesion and fewer defects (e.g., gaps) around the IC dies 70. Further, in Fig. 16, an insulating bonding layer 108 is deposited over the IC dies 70, and bond pads 106 are formed on the conductive vias 76 of the IC dies 70. The insulating bonding layer 108 and the bond pads 106 can be formed in a similar manner to the previously described Fig. 9. In embodiments where the IC dies 70 include regions free of the conductive vias 76, the bond pads 106 may also not be formed on the regions free of the conductive vias 76.

[0053] In Fig. 17, the IC dies 50 and the dummy dies 80 are bonded to the IC dies 70 in a similar manner as previously described in Fig. 10. For example, the IC dies 50 can be bonded directly to the IC dies 70 by dielectric-to-dielectric and metal-to-metal bonds, and the circuitry within the IC dies 50 can be electrically connected to the circuitry within the IC dies 70 through the conductive vias 76, the bond pads 106, and the bond pads 66. Further, the dummy dies 80 can be bonded directly to the IC dies 70 by dielectric-to-dielectric bonding via the insulating bonding layers 108 and 84. The IC dies 50 and the dummy dies 80 can have hydrophobic surface regions 60 and 82, respectively, as previously described. Further in Fig. 17, an insulating material 110 is applied around the IC dies 50 and the dummy dies 80 in a similar manner as previously in Fig. 11 described.

[0054] In Fig. 18A and Fig. 18B, a carrier substrate 200 is bonded to the IC dies 50, the dummy dies 80 and the insulating material 110, and the carrier substrate 100 is bonded in a similar manner as previously in Fig. 12 to 13. Further, one or more passivation layers 114 are deposited over the IC dies 70 and the insulating material 104 in a similar manner as previously described in Fig. 14A and Fig. 14B. Then, UBMs 116 and conductive connectors 118 are formed through the passivation layers 114 to electrically connect to the IC dies 50 and 70, as previously described in Fig. 14A and Fig. 14B was described.

[0055] Fig. Figure 18A illustrates semiconductor package 152A, where surface regions 90 are formed on all sidewalls of IC dies 70. As a result, all sidewalls of IC dies 70 are hydrophobic and may contain fluorine. Fig.Figure 18 illustrates semiconductor package 152B where surface regions 90 are formed only on a subset of the sidewalls of IC dies 70. As a result, some sidewalls of IC dies 70 are hydrophobic and may contain fluorine, while other sidewalls of IC dies 70 are hydrophilic and may contain substantially no fluorine (e.g., less than 5 wt.% fluorine).

[0056] According to various embodiments, a singulation process is performed to separate individual semiconductor die from a wafer. The singulation process may include patterning trenches in the scribe line regions of the wafer and performing a surface treatment to provide hydrophobic sidewalls in the trenches. In some embodiments, the surface treatment is a fluorine-based treatment. The hydrophobic sidewalls may prevent a protective layer (e.g., a backside anti-reflective coating (BARC) layer or the like) from being deposited in the trenches in a subsequent singulation step. A planarization process may then be performed to remove a backside of the wafer, thereby separating the semiconductor die along the trenches.

[0057] The protective coating layer can protect the semiconductor die during the planarization process, and a cleaning process can be used to remove the protective layer after the planarization process. Because the protective layer is not deposited in the trenches, the cleaning process can more effectively remove the protective layer, improving yield and reducing wafer recovery (RW) tool failure. For example, if the protective layer fills the trenches, the semiconductor die cannot be successfully separated from the wafer, resulting in RW failure. Furthermore, the hydrophobic sidewalls prevent unwanted residue from forming on the sidewalls of the IC die, helping to reduce manufacturing defects during later packaging steps.

[0058] In some embodiments, a package includes a first IC die; a second IC die over and bonded to the first IC die; and a first insulating material over the first IC and surrounding the second IC die. A first surface region of the second IC die is hydrophobic, and the first IC die and the second IC die are bonded to each other with dielectric-to-dielectric bonds and metal-to-metal bonds. The first insulating material contacts the first surface region. In some embodiments, the first surface region of the second IC die contains fluorine. In some embodiments, a fluorine concentration of the first surface region is at least 5 wt. %. In some embodiments, the first surface region further contains carbon, oxygen, silicon, nitrogen, or a combination thereof.In some embodiments, the package further includes a dummy die bonded to the first IC die with dielectric-to-dielectric bonds, wherein the first insulating material surrounds the dummy die. In some embodiments, a second surface region of the dummy die is hydrophobic and contains fluorine. In some embodiments, a third surface region of the first IC die is hydrophobic and contains fluorine. In some embodiments, the package further includes a second insulating material surrounding the first IC die, wherein the second insulating material contacts the third surface region.

[0059] In some embodiments, a package includes a first IC die, a first insulating material surrounding the first IC die; a second IC die over and bonded to the first IC die; and a second insulating material over the first IC and surrounding the second IC die. A first surface region of the second IC die contains fluorine, wherein a fluorine concentration of the first surface region is at least 5 wt. %, and the first surface region is disposed at an interface between the second insulating material and the second IC die. In some embodiments, a second surface region of the first IC die contains fluorine, and the second surface region is disposed at an interface between the first insulating material and the first IC die. In some embodiments, a fluorine concentration of the second surface region is at least 5 wt. %.In some embodiments, the package further comprises a dummy die bonded to the first IC die and arranged on a same plane as the second IC die, wherein a third surface region of the dummy die contains fluorine, wherein a fluorine concentration of the third surface region is at least 5 wt. %, and wherein the third surface region is arranged at an interface between the second insulating material and the second IC die. In some embodiments, the second IC die is bonded to the first IC die with dielectric-to-dielectric bonds and metal-to-metal bonds.

[0060] In some embodiments, a method comprises etching a trench through an interconnect structure and extending into a semiconductor substrate, the trench being disposed in a scribe line region disposed between a first IC die and a second IC die; performing a surface treatment in the first trench to form a first surface region in a first sidewall of the first IC die, the first surface region being hydrophobic; depositing a protective layer over the first IC die and covering the trench; applying an adhesive tape to a surface of the protective layer opposite the first IC die; performing backside planarization on a surface of the semiconductor substrate opposite the adhesive tape; and after performing the backside planarization, removing the protective layer and the adhesive tape to completely separate the first IC die from the second IC die.In some embodiments, the surface treatment is a fluorine-based treatment. In some embodiments, the fluorine-based treatment is a wet cleaning process using a fluorine-containing solution or a fluorine-based plasma process. In some embodiments, the method further comprises bonding the first IC die to a third IC die; and depositing an insulating material around the first IC die, wherein the insulating material contacts the first surface region. In some embodiments, the third IC die has a second surface region in a second sidewall of the third IC die, wherein the second surface region is hydrophobic.In some embodiments, the method further comprises bonding a dummy die to the third IC die, wherein the dummy die has a third surface region in a third sidewall of the dummy die, wherein the third surface region is hydrophobic, and wherein the insulating material contacts the third surface region. In some embodiments, etching the trench comprises etching the trench through a patterned photoresist on a top surface of the interconnect structure, and wherein performing the surface treatment comprises performing the surface treatment while the patterned photoresist covers the top surface of the interconnect structure.

[0061] The foregoing outlines features of some embodiments so that those skilled in the art will better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can already use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same benefits of the embodiments presented herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 532,456

[0001]

Claims

[1] Package, comprising: a first IC die; a second IC die over and bonded to the first IC die, wherein a first surface region of the second IC die is hydrophobic and wherein the first IC die and the second IC die are bonded to each other with dielectric-to-dielectric bonds and metal-to-metal bonds; and a first insulating material over the first IC and surrounding the second IC die, the first insulating material contacting the first surface region. [2] The package of claim 1, wherein the first surface region of the second IC die contains fluorine. [3] The package according to claim 2, wherein a fluorine concentration of the first surface region is at least 5 wt%. [4] The package of claim 2 or 2, wherein the first surface region further contains carbon, oxygen, silicon, oxygen or a combination thereof. [5] The package of any preceding claim, further comprising a dummy die bonded to the first IC die with dielectric-to-dielectric bonds, the first insulating material surrounding the dummy die. [6] The package of claim 5, wherein a second surface region of the dummy die is hydrophobic and contains fluorine. [7] Package according to one of the preceding claims, wherein a third surface region of the first IC die is hydrophobic and contains fluorine. [8] The package of claim 7, further comprising a second insulating material surrounding the first IC die, the second insulating material contacting the third surface region. [9] Package comprising: a first IC die; a first insulating material surrounding the first IC die; a second IC die over and bonded to the first IC die, wherein a first surface region of the second IC die contains fluorine, wherein a fluorine concentration of the first surface region is at least 5 wt%; and a second insulating material over the first IC and surrounding the second IC die, wherein the first surface region is disposed at an interface between the second insulating material and the second IC die. [10] The package of claim 9, wherein a second surface region of the first IC die contains fluorine, the second surface region being located at an interface between the first insulating material and the first IC die. [11] The package of claim 10, wherein a fluorine concentration of the second surface region is at least 5 wt%. [12] The package according to any one of claims 9 to 11, further comprising a dummy die bonded to the first IC die and arranged on a same plane as the second IC die, wherein a third surface region of the dummy die contains fluorine, wherein a fluorine concentration of the third surface region is at least 5 wt%, and wherein the third surface region is arranged at an interface between the second insulating material and the second IC die. [13] The package of any one of claims 9 to 12, wherein the second IC die is bonded to the first IC die with dielectric-to-dielectric bonds and metal-to-metal bonds. [14] Method comprising: Etching a trench through an interconnect structure and extending into a semiconductor substrate, the trench being disposed in a scribe line region disposed between a first IC die and a second IC die; performing a surface treatment in the trench to form a first surface region in a first sidewall of the first IC die, the first surface region being hydrophobic; Depositing a protective layer over the first IC die and covering the trench; Applying an adhesive tape to a surface of the protective layer opposite the first IC die; Performing backside planarization on a surface of the semiconductor substrate opposite the adhesive tape; and after performing backside planarization, removing the protective layer and adhesive tape to completely separate the first IC die from the second IC die. [15] The method of claim 14, wherein the surface treatment is a fluorine-based treatment. [16] The method of claim 15, wherein the fluorine-based treatment is a wet cleaning process using a fluorine-containing solution or a fluorine-based plasma process. [17] Method according to one of claims 14 to 16, further comprising: Bonding the first IC die to a third IC die; and Depositing an insulating material around the first IC die, wherein the insulating material contacts the first surface region. [18] The method of claim 17, wherein the third IC die has a second surface region in a second sidewall of the third IC die, the second surface region being hydrophobic. [19] The method of claim 18, further comprising bonding a dummy die to the third IC die, the dummy die having a third surface region in a third sidewall of the dummy die, the third surface region being hydrophobic, and the insulating material contacting the third surface region. [20] The method of any one of claims 14 to 19, wherein etching the trench comprises etching the trench through a patterned photoresist on a top surface of the interconnect structure, and wherein performing the surface treatment comprises performing the surface treatment while the patterned photoresist covers the top surface of the interconnect structure.

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