OPTICAL DEVICE AND MANUFACTURING PROCESS

Abstract

Optical devices and manufacturing methods are presented in which a multi-level connector is used to transmit and receive optical signals to and from an optical device. In embodiments, a multi-level connector receives optical signals from outside an optical device, the optical signals initially being in multiple stages. The multi-level connector then routes the optical signals to optical components of a single stage.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 535,402, filed August 30, 2023, entitled “Fan-In Si FAU Assembly for Multi-Row Fibers, and Edge Coupling with High Beachfront Density,” and U.S. Provisional Patent Application No. 63 / 608,012, filed December 8, 2023, entitled “Optical Device and Method of Manufacture,” which applications are incorporated by reference into the present application. BACKGROUND

[0002] Electrical signaling and processing is a technique for signal transmission and processing. Optical signaling and processing has been used in an increasing number of applications in recent years, particularly due to the use of signal transmission applications involving optical fiber.

[0003] Optical signaling and processing are typically combined with electrical signaling and processing to provide full-fledged applications. For example, optical fibers can be used for long-haul signal transmission, and electrical signals can be used for short-haul signal transmission, as well as processing and control. Therefore, devices incorporating long-haul optical components and short-haul electrical components are formed for conversion between optical signals and electrical signals, as well as for processing optical signals and electrical signals. Therefore, packages can include both optical (photonic) dies, which include optical devices, and electronic dies, which include electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1-9 illustrate formation of a first optical package in accordance with some embodiments. Fig. 10 illustrates bonding of the first optical package in accordance with some embodiments. Fig. 11A-11B illustrate formation of a first level active layer in accordance with some embodiments. Fig. 12A-12B illustrate formation of a second level active layer in accordance with some embodiments. Fig. 13 illustrates bonding of the first level active layer to a substrate in accordance with some embodiments. Fig. 14 illustrates exposing the first level active layer in accordance with some embodiments. Fig. 15 illustrates a singulation process in accordance with some embodiments. Fig. 16A-16B illustrate formation of a third level active layer in accordance with some embodiments. Fig. 17 illustrates mounting of the multi-level interconnection unit in accordance with some embodiments. Fig. 18A-18B illustrate attaching a multi-level connector in accordance with some embodiments. Fig. 19 illustrates optical signal paths in accordance with some embodiments. Fig. 20A-20B illustrate a multi-level interconnect device without multiple stages of optical components in accordance with some embodiments. Fig. 21 illustrates a multi-level constant width interconnect device in accordance with some embodiments. Fig. 22 illustrates a multi-level constant width interconnect bound to an interposer in accordance with some embodiments. Fig. 23-28D illustrate forming the first level active layer over an optical interposer in accordance with some embodiments. Fig. 29A-29C illustrate a staggered optical fiber array in accordance with some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements such that the first and second structural elements may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplification and clarity and does not in itself imply any relationship between the different embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "underlying," "beneath," "under," "overlying," "upper," and the like may be used herein for ease of description to describe the relationship of one element or structural element to another element(s) or structural element(s) as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0007] Embodiments will now be described with respect to specific embodiments in which a multi-level connector is used to provide multiple inputs to an optical device. However, the illustrated embodiments are intended to be illustrative and are not intended to limit the concepts shown in the precise embodiments described. Rather, the illustrated concepts may be incorporated into numerous embodiments, and all such embodiments may be included within the overall scope of the disclosure.

[0008] With reference now to Fig. 1 is an initial structure of an optical interposer 100 (recognizable in Fig. 5) in accordance with some embodiments. In the particular embodiment shown in Fig. 1, the optical interposer 100 is a photonic integrated circuit (PIC) and comprises, at this stage, a first substrate 101, a first insulating layer 103, and a material layer 105 for a first active layer 201 of first optical components 203 (not shown separately in Fig. 1, but with respect to Fig. 2 and discussed further below). In one embodiment, at the beginning of the manufacturing process of the optical interposer 100, the first substrate 101, the first insulating layer 103, and the material layer 105 for the first active layer 201 of first optical components 203 may collectively be part of a silicon-on-insulator (SOI) substrate. Considering first the first substrate 101, the first substrate 101 may be a semiconductor material such as silicon or germanium, a dielectric material such as glass, or any other suitable material that allows structural support of overlying devices.

[0009] The first insulating layer 103 may be a dielectric layer separating the first substrate 101 from the overlying first active layer 201, and may additionally, in some embodiments, serve as a portion of cladding material surrounding the subsequently fabricated first optical components 203 (discussed further below). In one embodiment, the first insulating layer 103 may be silicon oxide, silicon nitride, germanium oxide, germanium nitride, combinations thereof, or the like, formed using a method such as implantation (e.g., to form a buried oxide (BOX) layer) or deposited onto the first substrate 101 using a deposition method such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations thereof, or the like.However, any suitable material and manufacturing process may be used.

[0010] The material 105 for the first active layer 201 is initially (before patterning) a conformal material layer used at the beginning of the fabrication of the first active layer 201 of the first optical components 203. In one embodiment, the material 105 for the first active layer 201 may be a translucent material that may be used as a core material for the desired first optical components 203, such as a semiconductor material such as silicon, germanium, silicon germanium, combinations of these, or the like. In other embodiments, the material 105 for the first active layer 201 may be a dielectric material such as silicon nitride or the like. In other embodiments, the material 105 for the first active layer 201 may be III-V materials, lithium niobate materials, or polymers.In embodiments in which the material 105 of the first active layer 201 is deposited, the material 105 for the first active layer 201 may be deposited using a method such as epitaxial growth, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations thereof, or the like. In other embodiments in which the first insulating layer 103 is formed using an implantation process, the material 105 of the first active layer 201 may initially be part of the first substrate 101 prior to the implantation process to form the first insulating layer 103. However, any suitable materials and manufacturing methods may be used to form the material 105 of the first active layer 201.

[0011] Fig. 2 illustrates that once the material 105 for the first active layer 201 is ready, the first optical components 203 for the first active layer 201 are fabricated using the material 105 for the first active layer 201. In embodiments, the first optical components 203 of the first active layer 201 may be components such as optical waveguides (e.g., ridge waveguides, ridge waveguides, buried channel waveguides, diffused waveguides, etc.), couplers (e.g., grating couplers, edge couplers that are a narrowed waveguide with a width between about 1 nm and about 200 nm, etc.), directional couplers, optical modulators (e.g., silicon photonic Mach-Zehnder switches, microelectromechanical switches, micro-ring resonators, etc.), amplifiers, multiplexers, demultiplexers, optical-to-electrical converters (e.g., PN junctions), electrical-to-optical converters, lasers, combinations of these, or the like.However, any suitable first optical components 203 may be used.

[0012] To begin forming the first active layer 201 of first optical components 203 from the initial material, the material 105 for the first active layer 201 may be patterned into desired shapes for the first active layer 201 of first optical components 203. In one embodiment, the material 105 for the first active layer 201 may be patterned, for example, using one or more photolithographic masking and etching processes. However, any suitable method for patterning the material 105 for the first active layer 201 may be used. For some of the first optical components 203, such as waveguides or edge couplers, the patterning process may be all or at least most of the manufacturing used to form these first optical components 203.

[0013] Fig. 3 illustrates that for those components that use additional manufacturing processes, such as silicon photonic Mach-Zehnder switches that use resistive heating elements, additional processing may be performed either before or after patterning the material for the first active layer 201. For example, implantation processes, additional deposition and patterning processes for different materials (e.g., resistive heating elements, III-V materials for transducers), combinations of all these processes, or the like, may be used to help support the fabrication of the different desired first optical components 203. In a particular embodiment, and as specifically described in Fig. 3, in some embodiments, an epitaxial deposition of a semiconductor material 301 such as germanium (e.g., used for electrical / optical signal modulation and transversion) may be performed on a patterned portion of the material 105 of the first active layer 201. In such an embodiment, the semiconductor material 301 may be grown epitaxially to support fabrication, e.g., of a photodiode for an optical-to-electrical converter. All such fabrication processes and any suitable first optical components 203 may be fabricated, and all such combinations are intended to be fully within the scope of the embodiments.

[0014] Fig. 4 illustrates that once the individual first optical components 203 of the first active layer 201 are formed, a second insulating layer 401 may be deposited to cover the first optical components 203 and provide additional cladding material. In one embodiment, the second insulating layer 401 may be a dielectric layer that separates the individual components of the first active layer 201 from each other and from the overlying structures, and may additionally serve as another portion of cladding material surrounding the first optical components 203. In one embodiment, the second insulating layer 401 may be silicon oxide, silicon nitride, germanium oxide, germanium nitride, combinations of these, or the like, formed using a deposition technique such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of these, or the like.Once the material of the second insulating layer 401 is deposited, the material may be planarized using, for example, a chemical mechanical polishing process to planarize a top surface of the second insulating layer 401 (in embodiments in which the second insulating layer 401 is intended to completely cover the first optical components 203) or to planarize the second insulating layer 401 with top surfaces of the first optical components 203. However, any suitable material and manufacturing method may be used.

[0015] Fig. 5 illustrates that once the first optical components 203 of the first active layer 201 are fabricated and the second insulating layer 401 is formed, first metallization layers 501 are formed to electrically connect the first active layer 201 of the first optical components 203 to the control circuit, to each other, and to subsequently attached devices (in Fig. 5 not illustrated , but in relation to Fig. 6 and described further below). In one embodiment, the first metallization layers 501 are formed from alternating layers of dielectric and conductive material and can be formed by any suitable processes (such as deposition, damascene, dual damascene, etc.). In particular embodiments, multiple metallization layers can be used to interconnect the different first optical components 203, but the exact number of first metallization layers 501 depends on the design of the optical interposer 100.

[0016] Additionally, during the fabrication of the first metallization layers 501, one or more second optical components 503 may be formed as part of the first metallization layers 501. In some embodiments, the second optical components 503 of the first metallization layers 501 may include components such as couplers (e.g., edge couplers, grating couplers, etc.) for connecting to external signals, optical waveguides (e.g., ridge waveguides, ridge waveguides, buried channel waveguides, diffused waveguides, etc.), optical modulators (e.g., silicon photonic Mach-Zehnder switches, microelectromechanical switches, micro-ring resonators, etc.), amplifiers, multiplexers, demultiplexers, optical-to-electrical converters (e.g., PN junctions), electrical-to-optical converters, lasers, combinations of these, or the like.However, any suitable optical components may be used for the one or more second optical components 503.

[0017] In one embodiment, the one or more second optical components 503 may be formed by initially depositing a material for the one or more second optical components 503. In one embodiment, the material for the one or more second optical components 503 may be a dielectric material such as silicon nitride, silicon oxide, combinations of these, or the like, or a semiconductor material such as silicon deposited using a deposition method such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of these, or the like. However, any suitable material and deposition method may be used.

[0018] Once the material for the one or more second optical components 503 is deposited or otherwise formed, the material may be patterned into desired shapes for the one or more second optical components 503. In one embodiment, the material of the one or more second optical components 503 may be patterned, for example, using one or more photolithographic masking and etching processes. However, any suitable method for patterning the material for the one or more second optical components 503 may be used.

[0019] For some of the one or more second optical components 503, such as waveguides or edge couplers, the patterning process may be all or at least a large portion of the manufacturing used to form these components. Additionally, for those components that utilize further manufacturing processes, such as silicon photonic Mach-Zehnder switches that utilize resistive heating elements, additional processing may be performed either before or after patterning the material for the one or more second optical components 503. For example, implantation processes, additional deposition and patterning processes for different materials, combinations of all of these processes, or the like may be used to help facilitate the fabrication of the different desired one or more second optical components 503.All such manufacturing processes and any suitable one or more second optical components 503 may be manufactured, and all such combinations are intended to be fully within the scope of the embodiments.

[0020] Once the one or more second optical components 503 of the first metallization layers 501 are formed, a first bonding layer 505 is formed over the first metallization layers 501. In one embodiment, the first bonding layer 505 can be used for dielectric-to-dielectric and metal-to-metal bonding. In accordance with some embodiments, the first bonding layer 505 is formed from a first dielectric material 509, such as silicon oxide, silicon nitride, or the like. The first dielectric material 509 can be deposited using any suitable method, such as CVD, high-density plasma chemical vapor deposition (HDPCVD), PVD, atomic layer deposition (ALD), or the like. However, any suitable materials and deposition processes may be used.

[0021] Once the first dielectric material 509 is formed, first openings are formed in the first dielectric material 509 to expose conductive portions of the underlying layers in preparation for forming first bond pads 507 within the first bonding layer 505. Once the first openings are formed within the first dielectric material 509, the first openings may be filled with a seed layer and a plate metal to form the first bond pads 507 within the first dielectric material 509. The seed layer may be deposited over top surfaces of the first dielectric material 509 and the exposed conductive portions of the underlying layers and sidewalls of the openings and the second openings. The seed layer may include a copper layer.The seed layer may be deposited using processes such as sputtering, evaporation, or plasma-enhanced chemical vapor deposition (PECVD), or the like, depending on the desired materials. The plate metal may be deposited over the seed layer using a plating process such as electroplating or electroless plating. The plate metal may include copper, a copper alloy, or the like. The plate metal may be a filler material. A barrier layer (not separately illustrated) may be blanket deposited over top surfaces of the first dielectric material 509 and sidewalls of the openings and the second openings prior to the seed layer. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0022] After filling the first openings, a planarization process, such as CMP, is performed to remove excess portions of the seed layer and plate metal, thereby forming the first bond pads 507 within the first bonding layer 505. In some embodiments, a bond pad via (not separately illustrated) may also be used to connect the first bond pads 507 to underlying conductive portions and to connect the first bond pads 507 to the first metallization layers 501 through the underlying conductive portions.

[0023] Additionally, the first bonding layer 505 may also include one or more third optical components 511 incorporated within the first bonding layer 505. In such an embodiment, prior to the deposition of the first dielectric material 509, the one or more third optical components 511 may be fabricated using similar methods and similar materials as for the one or more second optical components 503 (described above), being waveguides and other structures formed at least partially by a deposition and patterning process. However, any suitable structures, materials, and any suitable fabrication methods may be used.

[0024] Fig. 6 illustrates bonding of a first semiconductor device 601 to the first bonding layer 505 of the optical interposer 100. In some embodiments, the first semiconductor device 601 is an electronic IC (EIC (Electronic Integrated Circuit) - e.g., a device without optical devices) and may include a semiconductor substrate 603, a layer of active devices 605, an overlying interconnect structure 607, a second bonding layer 609, and associated third bonding pads 611. In one embodiment, the semiconductor substrate 603 may be bonded to the first substrate 101 (e.g.,The active devices 605 may be similar to the first metallization layer 501 (a semiconductor material such as silicon or silicon germanium), the active devices 605 may be transistors, capacitors, resistors, and the like formed over the semiconductor substrate 603, the interconnect structure 607 may be similar to the first metallization layers 501 (without optical components), the second bonding layer 609 may be similar to the first bonding layer 505, and the third bonding pad 611 may be similar to the first bonding pads 507. However, any suitable devices may be used.

[0025] In one embodiment, the first semiconductor device 601 may be configured to work with the optical interposer 100 for a desired functionality. In some embodiments, the first semiconductor device 601 may be a high-bandwidth memory (HBM) module, an xPU, a logic die, a 3DIC die, a CPU, a GPU, an SoC die, a MEMS die, combinations of these, or the like. Any suitable device with any suitable functionality may be used, and all such devices are intended to be fully within the scope of the embodiments.

[0026] In one embodiment, the first semiconductor device 601 and the first bonding layer 505 may be bonded using a dielectric-to-dielectric and metal-to-metal bonding process. In a particular embodiment using a dielectric-to-dielectric and metal-to-metal bonding process, the process may be initiated by activating the surfaces of the second bonding layer 609 and the surfaces of the first bonding layer 505. Activating the top surfaces of the first bonding layer 505 and the second bonding layer 609 may include a dry treatment, a wet treatment, a plasma treatment, exposure to an inert gas plasma, exposure to H2, exposure to N2, exposure to O2, combinations thereof, or the like, as examples. In embodiments where a wet treatment is used, for example, RCA cleaning may be used.In another embodiment, the activation process may include other types of treatments. The activation process supports bonding of the first bonding layer 505 and the second bonding layer 609.

[0027] After the activation process, the optical interposer 100 and the first semiconductor device 601 may be cleaned, for example, using a chemical rinse, and then the first semiconductor device 601 is aligned with the optical interposer 100 and brought into physical contact. The optical interposer 100 and the first semiconductor device 601 are then subjected to heat treatment and contact pressure to bond the optical interposer 100 and the laser die 600. For example, the optical interposer 100 and the first semiconductor device 601 may be subjected to a pressure of about 200 kPa or less and a temperature between about 25°C and about 250°C to fuse the optical interposer 100 and the first semiconductor device 601.The optical interposer 100 and the first semiconductor device 601 may then be exposed to a temperature at or above the eutectic point for material of the first bond pads 507 and the third bond pads 611, e.g., between about 150°C and about 650°C, to melt the metal. In this way, the optical interposer 100 and the first semiconductor device 601 form a dielectric-to-dielectric and metal-to-metal bonded device. In some embodiments, the bonded dies are subsequently baked, annealed, pressed, or otherwise treated to strengthen or complete the bond.

[0028] Additionally, while specific processes have been described to initiate and solidify the bonds, these descriptions are intended to be illustrative and not limiting of the embodiments. Rather, any suitable combination of baking, annealing, pressing, or combination of processes may be used. All such processes are intended to be fully within the scope of the embodiments.

[0029] Fig. 6 additionally illustrates that once the first semiconductor device 601 is bonded, a first gap-fill material 613 is deposited to fill the space around the first semiconductor device 601 and provide additional support. In one embodiment, the first gap-fill material 613 may be a material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like, deposited to fill or overfill the spaces around the first semiconductor device 601. However, any suitable material and deposition method may be used.

[0030] Once the first gap fill material 613 is deposited, the first gap fill material 613 may be planarized to expose the first semiconductor device 601. In one embodiment, the planarization process may be a chemical mechanical planarization process, a grinding process, or the like. However, any suitable planarization process may be used.

[0031] Fig. 7 illustrates attachment of a first carrier substrate 701 to the first semiconductor device 601 and the first gap filling material 613. In one embodiment, the first carrier substrate 701 may be a carrier material that is transparent to the wavelength of light that is desired to be used, such as silicon, and may be bonded using, for example, an adhesive (not separately described in Fig. 7). However, in other embodiments, the first carrier substrate 701 may be bonded to the first semiconductor device 601 and the first gap fill material 613 using, for example, a bonding process. Any suitable method for attaching the first carrier substrate 701 may be used.

[0032] Fig. 8 illustrates removal of the first substrate 101 and, optionally, the first insulating layer 103, thereby exposing the first active layer 201 of first optical components 203. In one embodiment, the first substrate 101 and the first insulating layer 103 may be removed using a planarization process, such as a chemical mechanical polishing process, a grinding process, one or more etching processes, combinations thereof, or the like. However, any suitable method may be used to remove the first substrate 101 and / or the first insulating layer 103.

[0033] Once the first substrate 101 and the first insulating layer 103 are removed, a second active layer 801 of fourth optical components 803 may be formed on a backside of the first active layer 201. In one embodiment, the second active layer 801 of fourth optical components 803 may be formed using similar materials and similar processes as the second optical components 503 of the first metallization layers 501 (described above with respect to Fig. 5). For example, the second active layer 801 of fourth optical components 803 may be formed from alternating layers of a cladding material such as silicon oxide and a core material such as silicon nitride formed using deposition and patterning processes to form optical components such as waveguides and the like.

[0034] Fig. 9 illustrates formation of first device vias (TDVs) 901 and formation of a third bonding layer 903 to form a first optical package 900. In one embodiment, the first device vias 901 extend through the second active layer 801 and the first active layer 201 to provide rapid passage of power, data, and ground through the optical interposer 100. In one embodiment, the first device vias 901 may be formed by initially forming device via openings in the optical interposer. The device via openings may be formed by applying and developing a suitable photoresist (not shown) and removing portions of the second active layer 801 and the optical interposer 100 that are exposed.

[0035] Once the device via openings are formed within the optical interposer 100, the device via openings can be lined with a liner. The liner can be, for example, an oxide formed from tetraethyl orthosilicate (TEOS) or silicon nitride, although any suitable dielectric material can alternatively be used. The liner can be formed using a plasma-enhanced chemical vapor deposition (PECVD) process, although other suitable processes, such as physical vapor deposition or a thermal process, can also be used.

[0036] Once the liner is formed along the sidewalls and bottom of the device via openings, a barrier layer (also not independently illustrated) may be formed, and the remainder of the device via openings may be filled with a first conductive material. The first conductive material may include copper, although other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, and the like may be used. The first conductive material may be formed by electroplating copper onto a seed layer (not shown), thereby filling and overfilling the device via openings.Once the device via openings are filled, excess liner, barrier layer, seed layer, and first conductive material outside the device via openings can be removed by a planarization process such as chemical mechanical polishing (CMP), although any suitable removal process may be used.

[0037] Optionally, in some embodiments, once the first device vias 901 are formed, second metallization layers (in Fig. 9) may be formed in electrical connection with the first device vias 901. In one embodiment, the second metallization layers may be formed as described above with respect to the first metallization layers 501, such as by alternating layers of dielectric and conductive materials using damascene processes, dual damascene processes, or the like. In other embodiments, the second metallization layers may be formed using a plating process to form and shape the conductive material and then cover the conductive material with a dielectric material. However, any suitable structures and manufacturing methods may be used.

[0038] The third bonding layer 903 is formed to provide electrical connections between the optical interposer 100 and subsequently attached devices. In one embodiment, the third bonding layer 903 may be similar to the first bonding layer 505, including third bonding pads 909 (similar to the first bonding pads 507) and even fifth optical components 911 (similar to the third optical components 511). However, any suitable devices may be used.

[0039] Fig. 9 additionally illustrates placement of first external connectors 913 that may be formed to provide conductive areas for contact between the third bond pads 909 and other external devices. The first external connectors 913 may be conductive bumps (e.g., C4 bumps, ball grid arrays, microbumps, etc.) or conductive pillars, using materials such as solder and copper. In an embodiment where the first external connectors 913 are contact bumps, the first external connectors 913 may include a material such as tin or other suitable materials, such as silver, lead-free tin, or copper. In an embodiment where the first external connectors 913 are tin solder bumps, the first external connectors 913 may be formed by first forming a tin layer by conventionally used methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc.Once a tin layer is formed on the structure, reflow can be performed to form the material into the desired bump shape.

[0040] Fig. Figure 10 illustrates that once the first optical package 900 is formed, the first optical package 900 may be attached to an interposer substrate 1001, which is used to couple the first optical package 900 to other devices, for example, to form a chip-on-wafer-on-substrate (CoWoS) device. ® device). In one embodiment, the interposer substrate 1001 comprises a semiconductor substrate 1003, optionally third metallization layers (in Fig. 10), third device vias (TDVs) 1007, and second external connectors 1009. The semiconductor substrate 1003 may comprise bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid alignment substrates.

[0041] Optionally, first active devices (not separately illustrated) may be added to the semiconductor substrate 1003. The first active devices include a variety of active devices and passive devices, such as capacitors, resistors, inductors, and the like, that may be used to create the desired structural and functional design requirements for the semiconductor substrate 1003. The first active devices may be formed using any suitable methods, either within or elsewhere on the semiconductor substrate 1003.

[0042] The third metallization layers are formed over the semiconductor substrate 1003 and the first active devices and are designed to connect the different devices to form a functional circuit. In one embodiment, the third metallization layers are formed from alternating layers of dielectric (e.g., low-k dielectric materials, extremely low-k dielectric materials, ultra-low-k dielectric materials, combinations of these, or the like) and conductive material and can be formed by any suitable process (such as deposition, damascene, dual damascene, etc.). However, any suitable materials and processes may be used.

[0043] Additionally, if desired, the third metallization layers may further comprise optical interposer components that may interact with the fifth optical components 911 of the first optical package 900. In one embodiment, the optical interposer components may be formed using similar methods and materials as the third optical components 511 described above with respect to Fig. 5. However, any suitable methods and materials may be used.

[0044] Additionally, at any desired point in the manufacturing process, the third TDVs 1007 may be formed within the semiconductor substrate 1003 and, if desired, one or more layers of the third metallization layers to provide electrical connectivity from a front side of the semiconductor substrate 1003 to a back side of the semiconductor substrate 1003. In one embodiment, the third TDVs 1007 may be formed by initially forming through device via (TDV) openings in the semiconductor substrate 1003 and, if desired, one of the overlying third metallization layers (e.g., after the desired third metallization layer is formed, but before forming the next overlying third metallization layer).The TDV openings can be formed to a desired depth by applying and developing a suitable photoresist and removing portions of the underlying materials that are exposed. The TDV openings can be formed to extend into the semiconductor substrate 1003 to a depth greater than the final desired height of the semiconductor substrate 1003.

[0045] Once the TDV openings are formed within the semiconductor substrate 1003 and / or any third metallization layers, the TDV openings may be lined with a liner. The liner may be, for example, an oxide formed from tetraethyl orthosilicate (TEOS) or silicon nitride, although any suitable dielectric material may be used. The liner may be formed using a plasma-enhanced chemical vapor deposition (PECVD) process, although other suitable processes, such as physical vapor deposition or a thermal process, may be used.

[0046] Once the liner is formed along the sidewalls and bottom of the TDV openings, a barrier layer may be formed, and the remainder of the TDV openings may be filled with first conductive material. The first conductive material may include copper, although other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, and the like may be used. The first conductive material may be formed by electroplating copper onto a seed layer, filling, and overfilling the TDV openings. Once the TDV openings are filled, excess liner, barrier layer, seed layer, and first conductive material outside the TDV openings may be removed by a planarization process such as chemical mechanical polishing (CMP), although any suitable removal process may be used.

[0047] Once the TDV openings are filled, the semiconductor substrate 1003 may be thinned until the third TDVs 1007 are exposed. In one embodiment, the semiconductor substrate 1003 may be thinned using, for example, a chemical mechanical polishing process, a grinding process, or the like. Further, once exposed, the third TDVs 1007 may be recessed using, for example, one or more etching processes, such as a wet etching process, to deepen the semiconductor substrate 1003 such that the third TDVs 1007 extend from the semiconductor substrate 1003.

[0048] In one embodiment, the second external connectors 1009 may be placed on the semiconductor substrate 1003 in electrical connection with the third TDVs 1007 and may be, for example, a ball grid array (BGA) containing a eutectic material such as solder, although any suitable materials may be used. Optionally, an underbump metallization or additional metallization layers (in Fig. 10 not separately illustrated) between the semiconductor substrate 1003 and the second external connectors 1009. In one embodiment in which the second external connectors 1009 are solder bumps, the second external connectors 1009 may be formed using a ball drop process, such as a direct ball drop process. In another embodiment, the solder bumps may be formed by initially forming a tin layer by a suitable method such as evaporation, electroplating, printing, solder transfer, and then performing reflow to form the material into the desired bump shape. Once the second external connectors 1009 are formed, a test may be performed to ensure that the structure is suitable for further processing.

[0049] Once the interposer substrate 1001 is formed, the first optical package 900 may be attached to the interposer substrate 1001. In one embodiment, the first optical package 900 may be attached to the interposer substrate 1001 by aligning the first external connectors 913 with conductive portions of the interposer substrate 1001. Once the first external connectors 913 are aligned and in physical contact, they are reflowed by increasing the temperature of the first external connectors 913 beyond a eutectic point of the first external connectors 913, thereby shifting the material of the first external connectors 913 to a liquid phase. Once reflowed, the temperature is decreased to shift the material of the first external connectors 913 back to a solid phase, thereby bonding the first optical package 900 to the interposer substrate 1001.

[0050] Fig. 10 additionally illustrates bonding of a second semiconductor device 1011 and a third semiconductor device 1013 to the semiconductor substrate 1003. In some embodiments, the second semiconductor device 1011 is an electronic integrated circuit (EIC), such as a stacked device, comprising a plurality of semiconductor substrates interconnected. For example, the second semiconductor device 1011 may be a memory device, such as a high bandwidth memory module (HBM), a hybrid memory cube (HMC), or the like, comprising a plurality of stacked memory dies. In such embodiments, the second semiconductor device 1011 comprises a plurality of semiconductor substrates interconnected by through device vias (TDVs).Each of the semiconductor substrates may (or may not) include a layer of active devices and an overlying interconnect structure, a bond layer, and associated bond pads to interconnect the plurality of devices within the second semiconductor device 1011.

[0051] Of course, while the second semiconductor device 1011 is an HBM module in one embodiment, the embodiments are not limited to the second semiconductor device 1011 being an HBM module. Rather, the second semiconductor device 1011 may be any suitable semiconductor device, such as a processor die or other type of functional die. In particular embodiments, the second semiconductor device 1011 may be an xPU, a logic die, a 3DIC die, a CPU, a GPU, an SoC die, a MEMS die, combinations of these, or the like. Any suitable device with any suitable functionality may be used, and all such devices are intended to be fully included within the scope of the embodiments.

[0052] The third semiconductor device 1013 may be another EIC intended to operate with both the first optical package 900 and the second semiconductor device 1011. In some embodiments, the third semiconductor device 1013 may have different functionality than the second semiconductor device 1011 by being an xPU, a GPU, or an ASIC device, or may have the same functionality as the second semiconductor device 1011 by being another high-bandwidth memory device.

[0053] In one embodiment, both the second semiconductor device 1011 and the third semiconductor device 1013 may be bonded to the interposer substrate 1001 using, for example, third external interconnects 1015. The third external interconnects 1015 may be conductive bumps (e.g., ball grid arrays, microbumps, etc.) or conductive pillars using materials such as solder and copper. In an embodiment where the third external interconnects 1015 are contact bumps, the third external interconnects 1015 may include a material such as tin or other suitable materials, such as silver, lead-free tin, or copper. In an embodiment where the third external interconnects 1015 are tin solder bumps, the third external interconnects 1015 may be formed by initially forming a tin layer by such conventionally used methods as evaporation, electroplating, printing, solder transfer, ball placement, etc.Once a tin layer is formed on the structure, reflow can be performed to form the material into the desired bump shape.

[0054] Additionally, once the third external interconnects 1015 are placed, the second semiconductor device 1011 and the third semiconductor device 1013 are aligned with the interposer substrate 1001. Once aligned and in physical contact, the third external interconnects 1015 are melted by raising the temperature of the third external interconnects 1015 above a eutectic point of the third external interconnects 1015, thereby shifting the material of the third external interconnects 1015 to a liquid phase. Once melted, the temperature is lowered to shift the material of the third external interconnects 1015 back to a solid phase, thereby bonding the second semiconductor device 1011 and the third semiconductor device 1013 to the interposer substrate 1001.

[0055] Optionally, an underfill material (not separately illustrated) may be placed. The underfill material may reduce stress and protect the connection points from reflow of the third external interconnects 1015 and the first external connectors 913. The underfill material may be formed by a capillary flow process after attaching the first optical package 900, the second semiconductor device 1011, and the third semiconductor device 1013.

[0056] Once the second semiconductor device 1011, the third semiconductor device 1013, and the first optical package 900 are bonded to the interposer substrate 1001, the interposer substrate 1001 may be bonded to a second substrate 1021 with, for example, the second external connectors 1009. In one embodiment, the second substrate 1021 may be a package substrate, which may be a printed circuit board (PCB) or the like. The second substrate 1021 may include one or more dielectric layers and electrically conductive features, such as conductive lines and vias. In some embodiments, the second substrate 1021 may include vias, active devices, passive devices, and the like. The second substrate 1021 may further include conductive pads formed on the top and bottom surfaces of the second substrate 1021.

[0057] The second external connectors 1009 may be aligned with corresponding conductive connections on the second substrate 1021. Once the second external connectors 1009 are aligned, they may be reflowed to bond the second substrate 1021 to the interposer substrate 1001. However, any suitable bonding process may be used to connect the interposer substrate 1001 to the second substrate 1021.

[0058] Additionally, the second substrate 1021 may be prepared for further connections by placing fourth external connections (not separately illustrated) on an opposite side to the second substrate 1021 of the first optical package 900. In one embodiment, the fourth external connections may be formed using similar processes and materials as the second external connectors 1009. However, any suitable materials and processes may be used.

[0059] Fig. 11A-16 illustrate formation of a multi-level interconnect unit 1600 (e.g., a fan-in fiber array unit) for use with the first optical package 900. When viewed first from Fig. 11A, illustrates Fig. 11A, a first-level substrate 1101, a first lens 1103 formed within the first-level substrate 1101, a first-level active layer 1105 with sixth optical components 1107, and a first mirror 1109 bonded to a first support substrate 1111. In one embodiment, the first-level substrate 1101 may be similar to the one described above with respect to Fig. The first substrate 101 described in Figure 1 may be similar to the first substrate 101 described in Figure 1 in that it is a silicon substrate. However, any suitable material may be used.

[0060] The first lens 1103 is formed within the first-level substrate 1101. In one embodiment, the first lens 1103 may be formed by molding the material of the support substrate (e.g., silicon) using masking and etching processes. However, any suitable process may be used.

[0061] Additionally, if desired, a first anti-reflective coating (ARC) 1113 may be formed on the first lens 1103. In one embodiment, the first ARC 1113 may be one or more layers of materials that help prevent unwanted reflections when light is focused by the first lens 1103. In a particular embodiment, the one or more layers of material may be materials such as silicon oxide, silicon nitride, combinations thereof, or the like, formed using processes such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, oxidation, nitriding, combinations thereof, or the like.

[0062] In a particular embodiment, the first ARC 1113 may be formed using a first silicon oxide layer and a first silicon nitride layer formed over the first silicon oxide layer. A second silicon oxide layer and a second silicon nitride layer are deposited over the first silicon oxide layer and the first silicon nitride layer, forming an alternating stack of silicon oxide and silicon nitride. Once all desired layers have been deposited, the layers may be patterned using, for example, a photolithographic masking and etching process. However, any suitable combination of materials and processes may be used.

[0063] Additionally, if the recess formed by the first lens 1103 is not otherwise filled, a fill material may be deposited to fill the recess formed by the first lens 1103. In one embodiment, the fill material may be a cladding material such as silicon oxide deposited using a process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, combinations thereof, or the like. Once the recess is filled, the fill material may be planarized using a process such as chemical mechanical polishing to remove portions of the fill material outside the recess.

[0064] Once the first lens 1103 is formed, a first-level active layer 1105 with sixth optical components 1107 is formed over the first-level substrate 1101. In one embodiment, the first-level active layer 1105 with sixth optical components 1107 may be formed using similar materials and similar processes as those described above with respect to Fig. 8, the second active layer 801 of the fourth optical components 803 may be formed. However, any suitable materials and processes may be used.

[0065] In a particular embodiment, the sixth optical components 1107 comprise at least one integrated multiple coupler (IMC) (e.g., an edge coupler), such as a multiple waveguide edge coupler, arranged to combine optical signals (discussed below with reference to Fig. 19) and interacts with waveguides within the first optical package 900. However, any suitable optical components may be formed.

[0066] Once the first-level active layer 1105 is formed with sixth optical components 1107, the first mirror 1109 may be formed to extend into the first-level active layer 1105 and have a first alignment. In one embodiment, the first mirror 1109 may be formed by initially patterning the first-level active layer 1105 to form a recess. In one embodiment, the recess may be formed using one or more photolithographic masking and etching processes, such as one or more wet etching processes or dry etching processes. However, any suitable process may be used.

[0067] Once the recess is formed, the first mirror 1109 may be formed along sidewalls of the recess. In one embodiment, the first mirror 1109 may be a single layer of a reflective material such as aluminum, copper, copper, gold, aluminum, titanium nitride, combinations of these, or the like, or may otherwise be a multi-layer structure such as a Bragg reflector having alternating layers of different materials, such as alternating layers of silicon dioxide and amorphous silicon. The individual materials of the first mirror 1109 may be deposited using any suitable methods, such as chemical vapor deposition, physical vapor deposition, plating, combinations of these, or the like, and the individual layers may then be coated using, for example,a photolithographic masking and etching process (for example, to remove horizontal portions of the deposited materials). However, any suitable materials and methods may be used to form the first mirror 1109 along the sidewalls of the recess.

[0068] Additionally, if the formation of the first mirror 1109 does not completely fill the recess, the recess may be filled and planarized. In one embodiment, the recess may be filled and / or overfilled with a material similar to the cladding material of the first-level active layer 1105, deposited using a process such as chemical vapor deposition, followed by a planarization process such as a chemical mechanical polishing process. However, any suitable material and process may be used.

[0069] Once the first mirror 1109 is formed, the first-level active layer 1105 may be bonded to a first support substrate 1111. In one embodiment, the first support substrate 1111 may include a material such as glass, silicon, silicon germanium, combinations thereof, or the like, and the first support substrate 1111 may be bonded to the first-level active layer 1105 using, for example, a dielectric-to-dielectric bonding process. However, any suitable materials and bonding process may be used.

[0070] Fig. 11B illustrates a top-down plan view of the first-level active layer 1105 with the sixth optical components 1107 and the first mirror 1109. In one embodiment, each of the sixth optical components 1107 (e.g., waveguides) within the first-level active layer 1105 is aligned such that optical signals being transmitted and received are reflected by the first mirror 1109. However, since signals from overlying structures (e.g., a second mirror 1207—described further below with respect to Fig. 12A-12B) pass through the first level active layer 1105, the first mirror 1109 may be shaped and formed to allow passage of optical signals through the first mirror 1109. As such, the first mirror 1109 may not be formed as a single unit but rather with multiple sections, each section aligned to reflect an optical signal from one or more, but not all, of the sixth optical components 1107, while still allowing optical signals to be reflected, for example, from the second mirror 1207, to pass through the first mirror 1109.

[0071] Fig. 12A illustrates formation of a second lens 1201 on an opposite side of the first level substrate 1101 from the first lens 1103. In one embodiment, the second lens 1201 may be formed using similar processes as those described above with respect to Fig. 11A, and, if desired, a second ARC 1209 may be formed using similar processes as the first ARC 1113. However, any suitable processes may be used.

[0072] A second-level active layer 1203 with seventh optical components 1205 may be formed over the second lens 1201. In one embodiment, the second-level active layer 1203 and the seventh optical components 1205 may be formed using similar materials and methods as those described above with respect to Fig. 11A described first level active layer 1105 with sixth optical components 1107.

[0073] Fig. 12A additionally illustrates formation of a second mirror 1207 having a second orientation different from the first orientation. In one embodiment, the second mirror 1207 may be formed using similar processes and materials as those described above with respect to Fig. 11. However, any suitable processes and materials may be used.

[0074] Fig. 12B illustrates a top-down plan view of the second-level active layer 1203 with the seventh optical components 1205 and the second mirror 1207, wherein the seventh optical components 1205 are illustrated with a fan-in design. In one embodiment, and as shown in Fig. 12B, the second mirror 1207 is designed to receive reflections of optical signals from both the first mirror 1109 and a third mirror 1611 (in Fig. 12B not illustrated, but with respect to Fig. 16A-16B and described further below) and reflect the optical signals into the seventh optical components 1205. As such, the second mirror 1207 may be configured as a single unit (as shown in Fig. 12B) or may otherwise be formed and shaped with several separate sections (similar to the first mirror 1109 described above with respect to Fig. 11B). Any suitable shape may be used.

[0075] Fig. 13 illustrates bonding of the second-level active layer 1203 to a second-level substrate 1301. In one embodiment, the second-level substrate 1301 may be similar to the first-level substrate 1101 in that it is a silicon substrate and may be bonded using, for example, a dielectric-to-dielectric bonding process. However, any suitable material and bonding process may be used.

[0076] Additionally, if desired, at this point in the manufacturing process, the second-level active layer 1203 may be thinned after it has been bonded. In a particular embodiment, the second-level active layer 1203 may be thinned using a planarization process, such as a chemical mechanical polishing process. However, any suitable planarization process, such as a grinding process or one or more etching processes, may be used.

[0077] Fig. 14 illustrates that once the second-level substrate 1301 is bonded to the second-level active layer 1203, the first support substrate 1111 may be released and removed to expose the first-level active layer 1105. In one embodiment, the second-level substrate 1301 may be removed using a suitable method, such as one or more planarization processes (e.g., a chemical mechanical polishing process) or one or more etching processes. However, any suitable debonding process may be used.

[0078] Fig. 15 illustrates singulation of the first-level substrate 1101 and the second-level substrate 1301. In one embodiment, singulation may be performed using a saw to physically cut through the structures. In other embodiments, one or more masking and etching processes, or a combination of sawing and etching processes, may be used to singulate the structures. However, any suitable method or combination of methods may be used.

[0079] Fig. 16A illustrates bonding of the first level active layer 1105 to a third level substrate 1601 with a third lens 1603 and a fourth lens 1605 located on opposite sides of the third level substrate 1601. When viewing the third level substrate 1601, the third level substrate 1601 may be similar to that described above with respect to Fig. 11, by being a silicon substrate. However, any suitable materials may be used.

[0080] The third lens 1603 and the fourth lens 1605 may be formed on opposite sides of the third-level substrate 1601. In one embodiment, the third lens 1603 and the fourth lens 1605 may be formed using methods as for the first lens 1603, such as using one or more photolithographic masking and etching processes to shape the surfaces of the third-level substrate 1601, and, if desired, a third ARC 1613 and a fourth ARC 1615 may be formed using similar processes and materials as the first ARC 1613. However, any suitable methods may be used.

[0081] After the third lens 1603 and the fourth lens 1605 have been formed, a third-level active layer 1607 with eighth optical components 1609 may be formed. In one embodiment, the third-level active layer 1607 with eighth optical components 1609 may be formed using similar processes and similar materials as the first-level active layer 1105 with sixth optical components 1107 (discussed above with respect to Fig. 11A). However, any suitable methods and materials may be used.

[0082] Fig. 16A additionally illustrates formation of a third mirror 1611 having a third orientation, which is the same as the first orientation, within the third level active layer 1607. In one embodiment, the third mirror 1611 may be formed using similar processes and materials as the first mirror 1109 described above with respect to Fig. 11A. However, any suitable processes and materials may be used.

[0083] Once the third mirror 1611 is formed, the first-level active layer 1105 may be bonded to the third-level substrate 1601 to form a multi-level interconnect device 1600. In one embodiment, the first-level active layer 1105 may be bonded to the third-level substrate 1601 using, for example, a dielectric-to-dielectric bonding process. However, any suitable bonding process may be used.

[0084] Fig. Figure 16B illustrates a top-down plan view of the third level active layer 1607 with the eighth optical components 1609 and the third mirror 1611. In one embodiment, and as shown in Fig. 16B, the third mirror 1611 is configured to receive optical signals from the eighth optical components 1609 and reflect the optical signals to the fourth lens 1605. As such, the third mirror 1611 may be formed and shaped as a single unit or may otherwise be formed and shaped to include multiple separate sections. Any suitable shape may be used.

[0085] Fig. 17 illustrates attaching the multi-level interconnect device 1600 to the second substrate 1021 and the first optical package 900. In one embodiment, the multi-level interconnect device 1600 may be attached to the first optical package 900 using, for example, an optical adhesive 1701. In some embodiments, the optical adhesive 1701 includes a polymer material such as epoxy-acrylate oligomers and may have a refractive index between about 1 and about 3. However, any suitable material may be used.

[0086] Additionally, the multi-level interconnection unit 1600 may be attached to the second substrate 1021 to provide secondary support and help prevent warping of the second substrate 1021. In one embodiment, the multi-level interconnection unit 1600 may be attached to the second substrate 1021 using first spacers 1703, which may be a rubber material, a soft and supportive polymer material, combinations of these, or the like. However, any suitable material may be used.

[0087] Fig. Figure 18A illustrates connection of optical fibers 1803 from a ferrule 1805 to the multi-level interconnect unit 1600 using a multi-row connector 1801. In one embodiment, each of the optical fibers 1803 may comprise a core material, such as glass, surrounded by one or more cladding materials. Optionally, a surrounding cover material may be used to surround the outer cladding material to provide additional protection.

[0088] In a particular embodiment, the core material may have a thickness of approximately 10 µm. Additionally, the cladding material may have a thickness along one side of the core material of approximately 125 µm. However, any suitable dimensions may be used.

[0089] In one embodiment, the ferrule 1805 may be used to receive the plurality of optical fibers 1803 (shown in the figure), align the optical fibers 1803, and connect the optical fibers 1803 to the multi-row connector 1801. In one embodiment, the ferrule 1805 may be a mechanical transfer (MT) ferrule or the like, made of a material that can be used to protect, support, and align the individual optical fibers 1803. However, any suitable materials may be used. In one embodiment, the optical fibers 1803 may be inserted into openings located within the ferrule 1805.Once inserted, an adhesive material, such as an epoxy, silicone, a light-curable elastic polymer, combinations of these, or the like, can be injected or otherwise introduced into the openings within the ferrule 1805 to secure the optical fibers 1803 within the ferrule 1805. Additionally, a curing process, such as light curing, heat curing, or the like, can be used to harden the adhesive material. In this embodiment, the ferrule 1805 helps secure the optical fibers 1803 so that the optical signals provided by the optical fibers 1803 can be transmitted to the multi-level interconnect unit 1600.

[0090] The multi-row connector 1801 receives the optical fibers 1803 from the ferrule 1805 and separates them into more than one row. In the particular embodiment shown in Fig. 18A, the more than one row comprises two rows of optical fibers 1803, such as a first row 1811 and a second row 1813. However, any suitable number of rows, such as three rows or four rows, may be used.

[0091] In one embodiment, once the multi-row connector 1801 is attached to the multi-level interconnect unit 1600, each of the individual rows of optical fibers 1803 is aligned with a corresponding level within the multi-row connector 1801. In the particular embodiment using two rows, the first row 1811 is aligned so that optical signals from the first row pass into the eighth optical components 1609 of the third-level active layer 1607. Additionally, the second row 1813 is aligned so that optical signals from the second row pass into the sixth optical components 1107 of the first-level active layer 1105. In a particular embodiment, the first row 1811 may be separated from the second row 1813 by a first pitch P1 of between about 250 µm and about 500 µm. However, any suitable pitch may be used.

[0092] Once the multi-row connector 1801 is completed, the multi-row connector 1801 is connected to the multi-level interconnect unit 1600 and the second substrate 1021. In one embodiment, the multi-row connector 1801 may be attached to the multi-level interconnect unit 1600 using, for example, a second optical adhesive 1807 and a sidewall anti-reflection coating 1806. In some embodiments, the second optical adhesive 1807 and the sidewall anti-reflection coating 1806 may be formed using similar materials and methods as the optical adhesive 1701 and the first ARC 1113 described above with respect to Fig. 17 or Fig. 11 are described.

[0093] Additionally, the multi-row connector 1801 may be attached to the second substrate 1021 to provide secondary support and help prevent warping of the second substrate 1021. In one embodiment, the multi-row connector 1801 may be attached to the second substrate 1021 using second spacers 1809, which may be a rubber material, a soft and supportive polymer material, combinations of these, or the like. However, any suitable material may be used.

[0094] Fig. 18B illustrates a top-down plan view of the array of first spacers 1703 and second spacers 1809. In one embodiment, first spacers 1703 are located below multi-level interconnect unit 1600 (shown in Fig. 18B on the left side of the dashed line), while the second spacers 1809 are located under the multi-row connector 1801 (shown in Fig. 18B on the right side of the dashed line).

[0095] Fig. 19 illustrates an operation of the optical signals (shown in Fig. 19 by the arrows with dashed lines), the optical signals arrive from the ferrule 1805 and then enter the multi-row connector 1801, wherein the optical signals are split within the multi-row connector 1801 into the first row 1811 and the second row 1813. The optical signals from the second row 1813 enter the sixth optical components 1107 in the first-level active layer 1105, are reflected by the first mirror 1109 to the second mirror, and are reflected by the second mirror 1207 to enter the seventh optical components 1205 of the second-level active layer 1203. From the seventh optical components 1205, the optical signals can be guided into the first optical package 900 through, for example, edge couplers located within the seventh optical components 1205 and the second active layer 801 of the fourth optical components 803.

[0096] Additionally, the optical signals passing from the first row 1811 into the eighth optical components 1609 in the third-level active layer 1607 are reflected by the third mirror 1611, pass between separate elements of the first mirror 1109, and are reflected by the second mirror 1207 before entering the seventh optical components 1205 of the second-level active layer 1203. From the seventh optical components 1205, the optical signals may be routed into the first optical package 900 through, for example, edge couplers located within the seventh optical components 1205 and the second active layer 801 of the fourth optical components 803.

[0097] By using the multi-row connector 1801, more optical fibers 1803 can be connected to the first optical package 900. Specifically, the third-level active layer 1607 can be used to ensure compatibility with the multi-row connector 1801, the first-level active layer 1105 is used to provide height for alignment with the different rows of the multi-row connector 1801 without having to cut substrates, and the second-level active layer 1203 is used to help ensure that the seventh optical components 1205 are accurately aligned with the couplers of the first optical package 900.

[0098] Additionally, increasing the number of optical fibers 1803 enables higher bandwidth both into and out of the first optical package 900. As such, coupling losses from the optical fibers 1803 to the first optical package 900 can be reduced and a more efficient device can be formed.

[0099] Fig. 20A illustrates another embodiment in which the sixth optical components 1107 and the eighth optical components 1609 are not formed. Considering first the removal of the eighth optical components 1609, the eighth optical components 1609, the third-level active layer 1607, and the fourth lens 1605 are not formed during the manufacturing process as described above. Rather, the third mirror 1611 is formed directly within the third-level substrate 1601 using, for example, similar processes as described above with respect to Fig. 16A, such as structuring an opening, lining the opening with reflective material, and removing unwanted portions of the reflective material.

[0100] Additionally, the sixth optical components 1107 may also be removed and not fabricated during the formation of the first optical package 900, although the dielectric and / or cladding material may still be fabricated to support bonding. As such, the first mirror 1109 may be formed within the first level substrate 1101 using, for example, similar processes as described above with respect to Fig. 11A, such as structuring an opening, lining the opening with reflective material, and removing unwanted portions of the reflective material.

[0101] Additionally, in this embodiment, the first mirror 1109 may not be directly below the third mirror 1611, and the position of the first mirror 1109 may be offset from the position of the third mirror 1611. As such, the third lens 1603 and the first lens 1103 may be further offset from the position of the first mirror 1109 so as to be available for the transmission of optical signals from the third mirror 1611.

[0102] When considering the second-level active layer 1203, in this embodiment, the second lens 1201 and the second mirror 1207 may remain as discussed above to be able to reflect optical signals received from the first mirror 1109. However, in this embodiment, the second-level active layer 1203 may additionally include a fifth lens 2001 and a fourth mirror 2003. In one embodiment, the fifth lens 2001 and the fourth mirror 2003 are used to receive reflected optical signals from the third mirror 1611 and reflect the optical signals into the seventh optical components 1205 of the second-level active layer 1203, and the fifth lens 2001 and the fourth mirror 2003 may be formed using similar methods and materials as the first lens 1103 and the first mirror 1109 discussed above with respect to Fig. 11A, and, if desired, a fifth ARC 2005 may be formed with the fifth lens 2001 using similar methods and materials as the first ARC 1113. However, any suitable materials and methods may be used.

[0103] Fig. Figure 20B illustrates a top-down plan view of the second-level active layer 1203 in this embodiment. As can be seen in this embodiment, the second-level active layer 1203 includes both the second mirror 1207 (which may be a single continuous structure) and the fourth mirror 2003 (which may include multiple separate structures). As such, the seventh optical components 1205 (e.g., waveguides) that receive optical signals from the second mirror 1207 may pass between the separate sections of the fourth mirror 2003 to form a fan-in design and avoid interference between the individual components.

[0104] With reference again to Fig. 20A, in operation, the optical signals enter from the ferrule 1805 and then enter the multi-row connector 1801, where they are split within the multi-row connector 1801 into the first row 1811 and the second row 1813. The optical signals from the second row 1813 enter the first-level substrate 1101, are reflected by the first mirror 1109, and are reflected by the second mirror 1207 before entering the seventh optical components 1205 of the second-level active layer 1203. From the seventh optical components 1205, the optical signals are split between elements of the fourth mirror 2003 (see Fig. 20B) and into the first optical package 900.

[0105] Additionally, the optical signals from the first row 1811 enter the third-level substrate 1601 and are reflected by the third mirror 1611. Reflected by the third mirror 1611, the optical signal is reflected by the fourth mirror 2003 into the seventh optical components 1205 of the second-level active layer 1203. From the seventh optical components 1205, the optical signals are then guided into the first optical package 900.

[0106] Fig. Figure 21 illustrates another embodiment similar to that described above with respect to Fig. 19. However, in this embodiment, the multi-level interconnect unit 1600 has a constant width from a top surface of the multi-level interconnect unit 1600 to a bottom surface of the multi-level interconnect unit 1600. As such, the multi-level interconnect unit 1600 may not extend beyond the first optical package 900, and the first optical package 900 may have a height that is planar with the second semiconductor device 1011 and the third semiconductor device 1013.

[0107] Fig. Figure 22 illustrates another embodiment similar to the embodiment in Fig. 21 (e.g., wherein the multi-level interconnect unit 1600 has a constant width), but in which the multi-level interconnect unit 1600 is bonded to the interposer substrate 1001 and not to the second substrate 1021. In this embodiment, the multi-level interconnect unit 1600 may be bonded to the interposer substrate 1001 using a dielectric-to-dielectric bond and not to the first spacers 1703. The bonding process may be as described above with respect to Fig. 7, although any suitable bonding process may be used. A similar bonding process may be used in this embodiment to bond the first optical package 900, the second semiconductor device 1011 (if present and in Fig. 22 (not separately illustrated) and the third semiconductor device 1013. Such bonding allows easy integration with, for example, subsequently attached covers (not separately illustrated) for heat dissipation.

[0108] Additionally, while in this embodiment, the multi-level interconnect unit 1600 may be optically connected to the first optical package 900 as described above (e.g., directly from the multi-level interconnect unit 1600 to the first optical package 900), in other embodiments, the multi-level interconnect unit 1600 may be indirectly connected to the first optical package 900 through, e.g., the optical interposer components 2201 (described above with respect to Fig. 9, but in Fig. 22). As such, the optical signals travel from the seventh optical components 1205, through the optical interposer components 2201, and to the fifth optical components 911 to enter the first optical package 900.

[0109] Fig. Figure 23 illustrates the initial processes for fabricating another embodiment in which the first level active layer 1105 (previously described as part of the multi-level interconnect unit 1600) is directly integrated with the first optical package 900. In this embodiment, the process may be as described above with respect to Fig. 11A, wherein the first-level active layer 1105 with the sixth optical components 1107 and the first mirror 1109 is fabricated on the first-level substrate 1101 (without the first lens 1103) and then bonded to the first support substrate 1111 (using, for example, bonding films). However, any suitable structure may be used.

[0110] Fig. Figure 24 illustrates that once the first support substrate 1111 is bonded to the first-level active layer 1105, the first-level substrate 1101 may be thinned. In one embodiment, the first-level substrate 1101 may be thinned using one or more planarization processes, such as a chemical-mechanical planarization process. However, any suitable method may be used.

[0111] After the first-level substrate 1101 has been thinned, a first bonding layer 2401 is deposited on the first-level substrate 1101. In one embodiment, the first bonding layer 2401 may be a bonding material such as silicon oxide, silicon nitride, combinations thereof, or the like, deposited using a method such as a chemical mechanical polishing process. However, any suitable method and material may be used.

[0112] Fig. 25 illustrates that once the first level substrate 1101 is thinned, the first level substrate 1101 is adapted to the structure of Fig. 7 (and not to the first carrier substrate 701 as in Fig. 7). For example, in some embodiments, the first semiconductor device 601 is bonded and thinned, and the first gap fill material 613 is deposited and planarized, as above with respect to Fig. 7. However, any suitable processes may be used.

[0113] Once the gap fill material 613 is deposited, a second bonding layer 2501 is deposited over the first semiconductor device 601 and the first gap fill material 613. In one embodiment, the second bonding layer 2501 may be similar to the first bonding layer 2401, such as a silicon oxide deposited by chemical vapor deposition. However, any suitable methods and materials may be used.

[0114] Once the first bonding layer 2401 and the second bonding layer 2501 are formed, the first bonding layer 2401 is bonded to the second bonding layer 2501. In one embodiment, the first bonding layer 2401 and the second bonding layer 2501 may be bonded using a dielectric-to-dielectric bonding process. However, any suitable bonding process may be used.

[0115] Fig. 26 illustrates that once the first bonding layer 2401 and the second bonding layer 2501 are bonded, the first substrate 101 is removed. In one embodiment, the first substrate 101 may be removed using a planarization process, such as a chemical mechanical polishing process, a grinding process, one or more etching processes, combinations thereof, or the like. However, any suitable method for removing the first substrate 101 may be used.

[0116] Once the first substrate 101 is removed, the second active layer 801 of the fourth optical components 803 is formed along a backside of the first active layer 107. In one embodiment, the second active layer 801 of the fourth optical components 803 may be formed as described above with respect to Fig. 8. However, any suitable method may be used.

[0117] However, in this embodiment, in addition to forming the fourth optical components 803 within the second active layer 801, a fifth mirror 2701 is additionally formed within the second active layer 801. In one embodiment, the fifth mirror 2701 may be formed in a similar manner and using similar materials as the first mirror 1109 described above with respect to Fig. 11. However, any suitable methods and materials may be used.

[0118] Fig. 27 further illustrates that once the second active layer 801 with the fourth optical components and the fifth mirror 2701 is formed, the first device vias 901 and the third bonding layer 903 can be formed. Additionally, the first external connector 913 can be formed to form a second optical package 2700. Any suitable structures may be used.

[0119] Fig. Figure 28A illustrates that once the second optical package 2700 is prepared as described above, the second optical package 2700 can be bonded to the interposer substrate 1001 together with the multi-row connector 1801 (with the ferrule in Fig. 28A for clarity). In one embodiment, the second optical package 2700 may be configured as described above with respect to Fig. 10, while the multi-row connector 1801 can be connected as described above with respect to Fig. 18A (e.g., by using the second spacers 1809). However, any suitable bonding process may be used.

[0120] In this embodiment, the multi-row connector 1801 can be used to space the first row 1811 from the second row 1813 to align the first row 1811 and the second row 1813 with the desired portions of the second optical package 2700. In a particular embodiment, the first row 1811 and the second row 1813 can have a second pitch P2 of about 127 µm to about 250 µm. However, any suitable pitch may be used.

[0121] In operation, optical signals from the second row 1813 are directed directly into the second active layer 801 with the fourth optical components 803. However, the optical signals from the overlying first row 1811 are directed into the sixth optical components 1107 of the first-level active layer 1105, reflected by the first mirror 1109 through the first gap fill material 613, and to the fifth mirror 2701. The fifth mirror 2701 receives the optical signals and reflects them into the fourth optical components 803 of the second active layer 801.

[0122] Fig. Figure 28B illustrates a top-down plan view of the first-level active layer 1105. As can be seen in this embodiment, the first mirror 1109 may be formed in multiple individual sections, each section being aligned with a single one of the sixth optical components 1107 of the first-level active layer 1105. In this embodiment, the individual sections may be offset from one another, although in other embodiments, the individual sections may all be in a single line. However, any suitable configuration may be used.

[0123] Fig. 28C illustrates a top-down plan view of the second active layer 801 including the fourth optical components 803 and the fifth mirror 2701. As can be seen in this embodiment, the fifth mirror 2701 may be arranged in a similar manner to the first mirror 1109 (e.g., with individual sections offset from each other). Additionally, the fourth optical components 803 within the second active layer 801 may perform multiple functions, such as receiving optical signals directly from the second optical fiber 1813 and routing the optical signals around the fifth mirror 2701 (only one of which is illustrated for clarity), and also receiving signals reflected from the fifth mirror 2701 (again, only one of which is illustrated for clarity). However, any suitable fourth optical components 803 may be used with any desired routing.

[0124] Fig. 28D illustrates a view of the optical fibers 1803 in both the first row 1811 and the second row 1813. In this embodiment, the individual optical fibers 1803 are arranged in an array-like layout where optical fibers 1803 in the first row 1811 are arranged to be directly above corresponding optical fibers 1803 in the second row 1813. However, any suitable arrangement may be used.

[0125] Fig. 29A-29C illustrate another embodiment in which the optical fibers 1803 of the multi-row connector 1801 are arranged in a staggered formation. In this embodiment, the individual optical fibers 1803 are arranged side by side, rather than separated from each other. As such, the optical fibers 1803 in the first row and the optical fibers in the second row may have a third pitch P3 of about 127 µm to about 250 µm, such as about 108 µm. Additionally, the center of each of the optical fibers 1803 may be offset from the center of the optical fibers 1803 in the adjacent row.

[0126] Fig. 29B illustrates a top-down plan view of portions of the first-level active layer 1105 and portions of the second active layer 801. As can be seen in this embodiment, the first mirror 1109 may be formed in multiple individual sections, each section aligned with a single one of the sixth optical components 1107 of the first-level active layer 1105. Additionally, some of the fourth optical components 803 of the second active layer 801 may be distributed among and between each of the sixth optical components 1107. However, any suitable configuration may be used.

[0127] Fig.Figure 29C illustrates a view of the optical fibers 1803 in both the first row 1811 and the second row 1813. In this embodiment, the individual optical fibers 1803 are arranged in a staggered layout where optical fibers 1803 in the first row 1811 are adjacent to, and possibly between, corresponding optical fibers 1803 in the second row 1813. Additionally, centers of the optical fibers 1803 within the first row 1811 are offset from centers of the optical fibers 1803 within the second row 1813. However, any suitable arrangement may be used.

[0128] By using the first-level active layer 1105 above the second active layer 801, more optical fibers 1803 can be connected. By increasing the number of optical fibers 1803, a higher bandwidth is possible both into and out of the second active layer 801. As such, coupling losses from the optical fibers 1803 to the second active layer 801 can be reduced, and a more efficient device can be formed.

[0129] In one embodiment, a method of manufacturing an optical device comprises: receiving a multi-level interconnect, the multi-level interconnect comprising: a first level comprising a first mirror having a first orientation; a second level comprising a second mirror having a second orientation that is the same as the first orientation; and a third level comprising a third mirror, the third mirror having a third orientation that is different from the first orientation; and attaching the multi-level interconnect to a first optical package. In one embodiment, the third level further comprises fan-in waveguides. In one embodiment, the second mirror comprises a plurality of separate parts. In one embodiment, the first mirror is a single unit. In one embodiment, the multi-level interconnect has a constant width.In one embodiment, the first mirror is positioned with a semiconductor substrate. In one embodiment, the first plane further comprises waveguides aligned with the first mirror.

[0130] In another embodiment, a method of manufacturing an optical device comprises: attaching an electrical IC to an optical interposer; and bonding a first level active layer over the electrical IC and the optical interposer, the first level active layer comprising: first optical components; and a first mirror aligned with the first optical components. In one embodiment, after bonding, the first mirror is aligned with a second mirror located on an opposite side of the electrical IC from the first mirror, the second mirror located in a first active layer of second optical components. In one embodiment, the method further comprises attaching a multi-level interconnect device to the optical interposer.In one embodiment, the multi-plane interconnection unit comprises: a first optical fiber aligned with the first mirror; and a second optical fiber aligned with the second optical components. In one embodiment, a first center point of the first optical fiber is directly above a second center point of the second optical fiber. In one embodiment, the first optical fiber is in an offset configuration with the second optical fiber. In one embodiment, a pitch between the first optical fiber and the second optical fiber is about 108 µm.

[0131] In another embodiment, an optical device comprises: a multi-level junction unit, the multi-level junction unit comprising: a first level having a first mirror; a second level having a second mirror, a first lens, and a second lens; and a third level having a third mirror and a third lens; and a first optical package attached to the multi-level junction. In one embodiment, the first lens and the second lens are adjacent to the second mirror. In one embodiment, the first lens and the second lens are offset from the second mirror. In one embodiment, the third level has a fourth mirror aligned with the first lens and the second lens.In one embodiment, the optical device further comprises a multi-row connector attached to the multi-level interconnect unit, wherein a first row of optical fibers is aligned with the first mirror and wherein a second row of optical fibers is aligned with the second mirror. In one embodiment, the first level further comprises first optical components adjacent to the first mirror.

[0132] Structural elements of several embodiments have been set forth above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages of the embodiments presented herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 535,402

[0001] US 63 / 608,012

[0001]

Claims

[1] A method of manufacturing a semiconductor device, the method comprising: Receiving a multi-level connection unit, the multi-level connection unit comprising: a first plane having a first mirror with a first orientation; a second plane having a second mirror with a second orientation that is the same as the first orientation; and a third plane having a third mirror, the third mirror having a third orientation different from the first orientation; and Attaching the multi-level interconnect device to a first optical package, the first optical package comprising a semiconductor die. [2] The method of claim 1, wherein the third level further comprises fan-in waveguides. [3] A method according to claim 1 or 2, wherein the second mirror comprises a plurality of separate parts. [4] A method according to any preceding claim, wherein the first mirror is a single unit. [5] A method according to any one of the preceding claims, wherein the multi-level interconnection unit has a constant width. [6] A method according to any preceding claim, wherein the first mirror is positioned with a semiconductor substrate. [7] A method according to any preceding claim, wherein the first plane further comprises waveguides aligned with the first mirror. [8] A method of manufacturing a semiconductor device, the method comprising: Attaching an electrical IC to an optical interposer; and Bonding a first-level active layer over the electrical IC and the optical interposer, the first-level active layer comprising: first optical components; and a first mirror aligned with the first optical components. [9] The method of claim 8, wherein after bonding, the first mirror is aligned with a second mirror located on an opposite side of the electrical IC from the first mirror, the second mirror being located in a first active layer of second optical components. [10] The method of claim 9, further comprising attaching a multi-level interconnect device to the optical interposer. [11] The method of claim 10, wherein the multi-level connection unit comprises: a first optical fiber aligned with the first mirror; and a second optical fiber aligned with the second optical components. [12] The method of claim 11, wherein a first center point of the first optical fiber is directly above a second center point of the second optical fiber. [13] A method according to claim 11 or 12, wherein the first optical fiber is in an offset configuration with the second optical fiber. [14] The method according to claim 13, wherein a pitch between the first optical fiber and the second optical fiber is about 108 µm. [15] A semiconductor device comprising: a multi-level connecting unit, wherein the multi-level connecting unit comprises: a first plane having a first mirror; a second plane having a second mirror, a first lens and a second lens; and a third plane having a third mirror and a third lens; and a first optical package attached to the multi-level interconnect, the first optical package comprising a semiconductor die. [16] The semiconductor device according to claim 15, wherein the first lens and the second lens are located adjacent to the second mirror. [17] The semiconductor device according to claim 15, wherein the first lens and the second lens are offset from the second mirror. [18] The semiconductor device of claim 17, wherein the third plane includes a fourth mirror aligned with the first lens and the second lens. [19] The semiconductor device according to any one of claims 15 to 18, further comprising a multi-row connector attached to the multi-level connection unit, wherein a first row of optical fibers is aligned with the first mirror and wherein a second row of optical fibers is aligned with the second mirror. [20] A semiconductor device according to any one of the preceding claims 15 to 19, wherein the first plane further comprises first optical components adjacent to the first mirror.

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