Semiconductor device and manufacturing process therefor

Abstract

A method for fabricating a semiconductor device comprises the following steps. A dielectric layer is fabricated over a substrate. A 2D material layer is fabricated over the dielectric layer. An adhesive layer is fabricated over the 2D material layer. Source / drain electrodes are fabricated on opposite sides of the adhesive layer. A first dielectric high-k gate layer is fabricated over the adhesive layer, the adhesive layer containing a material different from that of the first dielectric high-k gate layer.

Description

BackgroundSemiconductor devices are used in various electronic fields of application such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers sequentially over a semiconductor substrate and patterning the various material layers by lithography to produce circuit components and elements on the substrate.The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the smallest feature width so that more components can be integrated on a given area. However, if the smallest structure width is reduced, there are other problems that should be addressed.Brief Description of the DrawingsAspects of the present disclosure may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be appreciated that, in accordance with practice in the industry, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. FIG. 1A is a cross-sectional view of a semiconductor device at various stages of manufacture in accordance with some embodiments of the present disclosure. FIG. 1B shows a schematic representation of a monolayer of an example transition metal dichalcogenide (TMD), in accordance with some example embodiments.FIGS. 2A, 2B, 2C, 3, 4, 5, 6, and 7A are sectional views of a semiconductor device at various stages of manufacture in accordance with some embodiments of the present disclosure. FIG. 7B is a diagram illustrating an ALD (atomic layer deposition) process for forming a second high-k gate dielectric layer, in accordance with some embodiments. FIG. 7C is an X-ray photoelectron spectroscopy (XPS) spectrum showing aspects of surface chemistry after forming the second high-k gate dielectric layer, in accordance with some embodiments.FIGS. 8A, 8B, and 8C are sectional views of semiconductor devices at different stages of manufacture, respectively, in accordance with some embodiments of the present disclosure.FIGS. 9A through 9C are enlarged views of a portion of FIG. 8A, in accordance with some embodiments. FIG. 10A shows transfer characteristics according to an example and a comparative example. FIG. 10B shows transfer characteristics according to examples. FIG. 10C is a graph showing a threshold voltage V TH( or V TG) as a function of a back gate voltage V BG according to examples.FIGS. 11A and 11B are diagrams showing a dielectric constant (k-value) of pure HfO x( which is undoped), and a dielectric constant (k-value) of HZO, respectively, depending on an applied voltage, according to some embodiments. FIG. 12A is a graph showing an ε eff- value (ε eff: equivalent effective dielectric constant) as a function of a physical thickness (t ox) on a monolayer MoS 2(1 L-MoS 2) according to an example and comparative examples. FIG. 12B is a graph showing a breakdown voltage (V BD) as a function of an effective oxide thickness (EOT) according to an example and comparative examples. FIG. 12C is a graph showing a gate leakage current (Jg) versus EOT according to an example and comparative examples. FIG. 12D is a graph illustrating EOT versus a thickness of a second high-k gate dielectric layer, according to an example. FIG. 12E is a graph showing gate leakage current (J G) versus top gate voltage (V TG) according to an example. FIG. 13A is a graph showing hysteresis △V TH as a function of an overvoltage (V ov) defined as a difference between a bias voltage (V TG) and a breakdown voltage (V TH) according to examples. FIG. 13B is a graph showing drain current (I D) and gate leakage current (J G) as a function of top gate voltage (V TG) according to an example.Detailed DescriptionThe following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements will be described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the description below, the formation of a first element over or on a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact. Moreover, in the present disclosure, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Moreover, spatially relative terms such as "lower", "lower", "lower(r)" / "lower", "higher", "upper(r)" / "upper" and the like may be used herein to easily describe the relationship of an element or structural element to one or more other elements or structural elements illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90° or in another orientation) and the spatially relative descriptors used herein interpreted accordingly. As used herein, the terms "about," "about," "approximately," or "substantially" generally mean within 20%, or 10%, or 5% of a given value or range. Numerical references used herein are approximations, meaning that the term "about", "about", "approximately" or "substantially" may be adopted unless expressly stated.In a recent development of a field effect transistor (FET), a channel region of the FET may be created in a two-dimensional (2D) material layer, which may provide the FET with better performance (e.g., as compared to FETs that do not have a 2D) material layer. As used herein, the term "2D material" may mean a crystalline material consisting of a single atomic layer, consistent with accepted definition in the solid state material art. As has widely accepted in the art, a 2D material may also be referred to as a "monolayer material.". In the present disclosure, the terms "2D material" and "monolayer material" are used interchangeably without distinguishing the meanings unless expressly stated otherwise.However, depositing a high-k dielectric layer on a 2D material layer begins with poor nucleation of the high-k dielectric layer. For example, a high-k gate dielectric layer forms cores as discontinuous particles on a surface of the 2D material layer.In embodiments of the present disclosure, an adhesion layer is provided for improving adhesion between a 2D material layer and a high-k gate dielectric layer, since the adhesion layer may form cores as a continuous film on a surface of the 2D material layer. The adhesion layer may improve the formation of a high-k gate dielectric layer or high-k gate dielectric stack over the 2D material layer to improve electrical properties, for example, reduce the pre-threshold lift (SS) and the effective oxide thickness (EOT). In addition, a higher effective dielectric constant (ε eff), a higher breakdown voltage (V BD) and a smaller gate leakage current (J G) are obtained.FIGS. 1A, 2A, 2B, 2C, 3, 4, 5, 6, 7A, and 8A are sectional views of a semiconductor device 10 at various stages of manufacture in accordance with some embodiments of the present disclosure. First, please refer to FIG. 1A. A dielectric layer 102 is formed on a substrate 100. The substrate 100 shown in FIG. 1A may be a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. An SOI substrate includes an insulating layer under a thin semiconductor layer, which is the active layer of the SOI substrate. The active layer semiconductor and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials such as germanium; silicon-germanium alloys; compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, and the like) or their alloys (e.g., Ga x Al 1-x As, Ga x Al 1-x N, In x Ga 1-x As, and the like); Oxide semiconductors (e.g., ZnO, SnO 2, TiO 2, Ga 2 O 3 and the like); or combinations thereof. The semiconductor materials may be doped or undoped. In some embodiments, substrate 100 is a silicon substrate doped with p-dopants. Other substrates that may be used are multilayer substrates, gradient substrates, or hybrid orientation substrates. In some embodiments, the substrate 100 has a thickness of about 500 μm to about 600 μm, e.g., about 550 μm.The dielectric layer 102 may be made of a nitride layer such as SiN x, or a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN). The dielectric layer 102 may be formed by chemical vapor deposition (CVD), such as gravure CVD (LPCVD) or plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any other suitable method. In some embodiments, the dielectric layer 102 has a thickness of about 80 nm to about 120 nm, e.g., about 100 nm.A 2D material layer 104 is formed over the dielectric layer 102. In some embodiments, the 2D material layer 104 is a 2D semiconductor layer, such as carbon nanotubes (CNT), graphene, transition metal dichalcogenide (TMD), or the like, or a combination thereof. The formation of the 2D material layer 104 may be performed using suitable processes. In some embodiments, the 2D material layer 104 includes a TMD monolayer material. In some embodiments, a TMD monolayer includes a layer of transition metal atoms sandwiched between two layers of chalcogen atoms. FIG. 1B shows a schematic illustration of a monolayer 204 of an example TMD, in accordance with some example embodiments. In FIG. 1B, a monomolecular thick TMD material layer contains transition metal atoms 204M and chalcogen atoms 2o4X. The transition metal atoms 204M may form a layer in a central portion of the monomolecular thick TMD material layer, and the chalcogen atoms 204X may form a first layer over the layer of transition metal atoms 204M and a second layer under the layer of transition metal atoms 204M. Transition metal atoms 204M may be W or Mo atoms, while chalcogen atoms 204X may be S, SE, or Te atoms. In the example of FIG. 1B, each of the transition metal atoms 204M connects (e.g., through covalent bonds) to six chalcogen atoms 204X, and each of the chalcogen atoms 204X connects (e.g., through covalent bonds) to three transition metal atoms 204M. Throughout the specification, the illustrated cross-linked layers comprising a layer of transition metal atoms 204M in combination with two layers of chalcogen atoms 204X are referred to as a TMD monolayer 204.In some embodiments where the 2D material layer 104 includes TMD monolayers, the TMD monolayers include molybdenum disulfide (MoS 2), tungsten disulfide (WS 2), tungsten diselenide (WSe 2) or the like. In some embodiments, MoS 2 and WS 2 may be formed on the dielectric layer 102 using suitable methods. For example, MoS 2 and WS 2 may be made by micromechanical deposition and bonding over dielectric layer 102, or by sulfurizing a molybdenum or tungsten film previously deposited over dielectric layer 102. In alternative embodiments, WSe 2 may be fabricated by micromechanical deposition and bonding over dielectric layer 102, or by selenizing a tungsten film previously deposited over dielectric layer 102 using thermally cracked Se molecules.In some other embodiments, where MoS 2 is formed by micromechanical deposition, 2D material layer 104 is formed on another substrate and then transferred to dielectric layer 102. For example, in some embodiments, a 2D material film is deposited on a first substrate by CVD, sputtering, or atomic layer deposition. Subsequently, a polymer film such as polymethyl methacrylate (PMMA) is formed on the 2D material film. After the polymer film is produced, the test specimens are heated, for example, by placing on a heating table. After heating, a corner of the 2D material film is peeled from the first substrate with, for example, forceps, and the test specimen is dipped in a solution to facilitate separation of the 2D material film from the first substrate. The 2D material film and the polymer film are then transferred to the dielectric layer 102. The polymer film is then removed from the 2D material film using a suitable solvent.In some embodiments where MoS 2 is formed by sulfurizing a previously deposited molybdenum (Mo) film over the dielectric layer 102, a Mo film may be deposited over the dielectric layer 102 by a suitable method, such as RF sputtering with a molybdenum target, to form the Mo film on the dielectric layer 102. After the Mo film is deposited, the substrate 100 and the Mo film are taken out of the sputtering chamber and exposed to air. As a result, the Mo film is oxidized to Mo oxides. The test specimen is then placed in the middle of a hot furnace for sulfurization. During sulfurization, Ar gas is used as a carrier gas, and S powder is placed in front of the gas flow. The S powder is heated to its vaporization temperature in the gas stream. During the high-temperature growth, there occurs simultaneously an Mo oxide separation and a sulfurization reaction. If the background sulfur is sufficient, the sulfur reaction is the dominant mechanism. Most of the surface Mo oxides have recently been converted into MoS 2. As a result, a uniform MoS 2- film is obtained on the substrate after sulfurization. With this method, the 2D material layer 104 can be formed uniformly on a large area of the dielectric layer 102.In some embodiments, forming the 2D material layer 104 also includes treating that layer to achieve desired electronic properties of that layer. The treatment processes include thinning (i.e., reducing the thickness of the 2D material layer 104) doping or strained to cause the 2D material layer 104 to exhibit certain semiconductor characteristics, e.g., a direct band gap. Thinning of the 2D material layer 104 may be accomplished with various suitable processes, all of which are part of the present disclosure. For example, plasma-based dry etching, e.g., reactive ion etching (RIE), may be used to reduce the number of monolayers of the 2D material layer 104. In the description below, the 2D material layer 104 (referred to herein as a 2D semiconducting material layer) may have semiconductor characteristics. In some cases, the 2D material layer 104 is a MoS 2- layer having a thickness of about 0.5 nm to about 0.8 nm, e.g., about 0.7 nm.Now, referring to FIG. 2A. In some embodiments, an adhesion layer 106 is formed on the 2D material layer 104. The adhesion layer 106 may be in physical contact with the 2D material layer 104. In some embodiments, the adhesion layer 106 is a nanofog film or oxide formed by atomic layer deposition (ALD). In some embodiments, the adhesion layer 106 is a dielectric layer. In some embodiments, the adhesion layer 106 is a metal oxide layer or an aluminum-containing layer, such as aluminum oxide. For example, the adhesion layer 106 includes AlO x- particles less than 1 nm on a surface of the 2D material layer 104. In some embodiments, the adhesion layer 106 is formed as follows: performing nano-fog ALD to provide uniform centers of crystallization; and subsequently performing a deposition process, such as ALD or other deposition methods such as CVD, LPCVD, PVD, plating, vapor deposition, irradiation with ion or energy beams, or the like, or a combination thereof, to achieve a desired thickness. In some embodiments, the adhesion layer 106 is formed at a low temperature by ALD. In some cases, the adhesion layer 106 has a thickness of about 0.8 nm to about 1.2 nm, e.g., about 1 nm.The adhesion layer 106 may also be formed by other suitable methods. Now, please refer to FIG. 2B. In some other embodiments, a metal layer 108 may be formed on the 2D material layer 104. For example, the metal layer 108 is an Al layer and is formed with an electron beam gun, by PVD, CVD, vapor deposition, irradiation with ion or energy beams, by plating, or a combination thereof. In FIG. 2C, an oxidation process S 100 may then be performed to oxidize the metal layer 108 to form an adhesion layer 106 including AlO x. The oxidation process S 100 is performed, for example, in an environment including ozone (O 3), H 2 O 2, H 2 O, N 2 O, or NO.In FIG. 3, a mask layer 110 is formed over the adhesion layer 106, which is then patterned to expose the 2D material layer 104. In some embodiments, mask layer 110 may be a photoresist material formed by spin coating and subsequently patterned using suitable lithography techniques. For example, the photoresist material may be exposed (exposed) and developed to remove portions of the photoresist material. In particular, a photomask (not shown) may be placed over the photoresist material, which may then be irradiated with a radiation beam provided by a radiation source, such as a UV (ultraviolet) source, a DUV (deep ultraviolet) source, an EUV (extreme ultraviolet) source, or an X-ray source. The radiation source may be, for example, a mercury lamp having a wavelength of about 436 nm (g-line) or about 365 nm (i-line); a krypton fluoride excimer laser (KrF excimer laser) having a wavelength of about 248 nm; an argon fluoride excimer laser (ArF excimer laser) having a wavelength of about 193 nm; a fluoride excimer laser (F 2- excimer laser) having a wavelength of about 157 nm; or another light source having an appropriate wavelength (e.g., less than about 100 nm). In another example, the light source is an EUV source having a wavelength of about 13.5 nm or less. After the mask layer 110 is formed and patterned, the adhesion layer 106 is etched using the mask layer 110 as an etch mask, thereby exposing the 2D material layer 104.Referring now to FIG. 4, on the mask layer 110 and the 2D material layer 104, an electrode layer 112 is formed by ALD, CVD, LPCVD, PVD, plating, vapor deposition, irradiation with ion or energy beams, or the like, or a combination thereof. In some embodiments, the electrode layer 112 includes a metal such as aluminum (Al), copper (Cu), tungsten (W), gold (Au), or the like, or a combination thereof. In some embodiments, the electrode layer 112 is conformally formed on the mask layer 110 and the 2D material layer 104.In FIG. 5, the mask layer 110 is removed by a peeling process, for example. The removal of the mask layer 110 also removes a higher-lying part of the electrode layer 112, such that other parts of the electrode layer 112 remain on opposite sidewalls of the adhesion layer 106 and serve as source / drain electrodes 114. The source / drain electrodes 114 are connected to the adhesion layer 106. In some examples, a top surface 106T of the adhesion layer 106 is lower than a top surface 114T of one of the source / drain electrodes 114.In FIG. 6, a first high-k gate dielectric layer 116 is formed on the source / drain electrodes 114 and the adhesion layer 106. The first high-k gate dielectric layer 116 extends, for example, along a sidewall of the source / drain electrodes 114 to over a top surface of one of the source / drain electrodes 114. The adhesion layer 106 is in physical contact with the first high-k gate dielectric layer 116, in some embodiments. The first high-k gate dielectric layer 116 extends along a top surface of the adhesion layer 106, for example. As a manufacturing method of the first high-k gate dielectric layer 116, molecular beam deposition (MBD), ALD, PECVD, or the like may be used. In some embodiments, the adhesion layer 106 has a dielectric constant that is lower than a dielectric constant of the first high-k gate dielectric layer 116. Throughout the specification, the k value of silicon oxide (SiO 2), which is about 3.9, is used for distinguishing low k values from high k values. Accordingly, k values lower than 3.8 are referred to as low k values, and the respective dielectric materials are referred to as low-k dielectric materials. Conversely, k values higher than 3.9 are referred to as high k values, and the respective dielectric materials are referred to as high-k dielectric materials.In some embodiments, the first high-k gate dielectric layer 116 is a metal oxide layer or a hafnium-containing layer. In some embodiments, the first high-k gate dielectric layer 116 includes hafnium oxide (HfO x). In some embodiments, the formation of the adhesion layer 106 and the subsequent formation of the first high-k gate dielectric layer 116 are in situ processes performed in, for example, a processing system such as an ALD cluster tool. In its true sense, the term "in situ" can also be used generally to refer to processes in which the device or processed substrate is not exposed to the external environment (i.e., external to the processing system). In other words, in some embodiments, the first high-k gate dielectric layer 116 may be deposited in situ later, after the deposition of the adhesion layer 106. That is, the first high-k gate dielectric layer 116 is formed on the adhesion layer 106 in situ (i.e., without vacuum interruption).In FIG. 7A, a second high-k gate dielectric layer 118 is formed on the first high-k gate dielectric layer 116. The second high-k gate dielectric layer 118 and the first high-k gate dielectric layer 116 form a high-k gate dielectric stack 119. As a manufacturing method of the second high-k gate dielectric layer 118, MBD, ALD, PECVD, or the like may be used. In some embodiments, the second high-k gate dielectric layer 118 is a metal oxide layer or a hafnium-containing layer. In some embodiments, the second high-k gate dielectric layer 118 has a composition different from a composition of the first high-k gate dielectric layer 116. For example, the first high-k gate dielectric layer 116 is an undoped layer, while the second high-k gate dielectric layer 118 is doped with, for example, zirconium.In some embodiments, the second high-k gate dielectric layer 118 has a dielectric constant that is different than a dielectric constant of the first high-k gate dielectric layer 116. For example, the second high-k gate dielectric layer 118 has a dielectric constant that is higher than that of the first high-k gate dielectric layer 116. In some embodiments, the second high-k gate dielectric layer 118 includes hafnium zirconium oxide (HZO). For example, the second high-k gate dielectric layer 118 is Hf x Zr y O, where a ratio of x to y is about 1:1 to about 1:4. In some embodiments, the second high-k gate dielectric layer 118 is Hf 0,3 Zr 0,7 O 2. FIG. 7B is a diagram illustrating an ALD process for forming the second high-k gate dielectric layer 118, in accordance with some embodiments. Referring to FIGS. 7A and 7B, in some embodiments where the second high-k gate dielectric layer 118 is formed by an ALD process, one or more first cycles S 200 and one or more second cycles S 202 are performed in the ALD process.Each of the first cycles S 200 includes steps S 204 and S 206. Each of the second cycles S 202 includes steps S 208 and S 210. In cycle S200, two half cycles (i.e., steps S204 and S206) are performed, one being a pulse with a first organometallic precursor P1 and the other being an oxidant pulse. The first metal organic precursor P 1, which is, for example, an Hf precursor such as Tetrakis(ethylmethylamido)hafnium (i.e., Hf[NHH 3 C 2 H 5]4, TEMAH), is provided to be chemically adsorbed to a surface of the first high-k gate dielectric layer 116. The oxidant, such as water, reacts with the adsorbed first organometallic precursor P 1 to form a monolayer of HfO x L_ 1. The TEMAH has the following formula (I): Other non-limiting examples of suitable Hf precursors are Hf(O t Bu) 4( hafnium tert-butoxide, HTB), Hf(NEt 2)4[ Tetrakis(diethylamido)hafnium TDEAH], Hf(NEtMe) 4[ Tetrakis(ethylmethylamido)hafnium TEMAH], Hf(NMe 2)4[ Tetrakis(dimethylamido)hafnium TDMAH], Hf(mmp) 4( hafnium methoxy propionate, Hf mmp), HfCl 4, tetrakis(N,N'dimethylacetamideinate), Hf, Cp 2 HfMe 2, Cp 2 Hf(Me)OMe, (tBuCp) 2 HfMe 2, CpHf(NMe 2)3 and Hf(N i Pr 2)4. Note that Cp represents cyclopentadienyl or alkylcyclopentadienyl, Me represents methyl, Et represents ethyl, and i Pr represents isopropyl. In step S 204, a non-reactive inert gas such as Ar or N 2 is used for discharging the excess first organometallic precursor P 1 and the excess oxidizing agent.In the second cycles S 202, two half cycles (i.e., steps S 208 and S 210) are performed, one being a pulse with a second organometallic precursor P 2 and the other being an oxidant pulse. In step S 208, the second organometallic precursor P 2, which is, for example, a Zr precursor such as tetrakis(ethylmethylamino)zirconium [TEMAZ, Zr[N(C 2 H 5) CH 3]4] is provided to be chemically adsorbed on a surface of the monolayer of HfO x L_ 1 produced in the first cycle S 200. The TEMAZ has the following formula (II): The oxidant, such as water, reacts with the adsorbed second organometallic precursor P2to form a monolayer of ZrO x L_2. In step S 210, a non-reactive inert gas such as Ar or N 2 is used for discharging the excess second organometallic precursor P 2 and the excess oxidizing agent. In some embodiments, steps S 204, S 206, S 208, and S 210 are repeated until a desired thickness is reached. A ratio of the first cycles S 200 to the second cycles S 202 may be adjusted to control an atomic ratio Zr / Hf in the second high-k gate dielectric layer 118. For example, the first cycles S 200 are performed about x times, and the second cycles S 202 are performed about y times.In some embodiments, the second high-k gate dielectric layer 118 is formed by thermal ALD or plasma enhanced ALD (PEALD). FIG. 7C is an X-ray photoelectron spectroscopy (XPS) spectrum showing aspects of surface chemistry after forming the second high-k gate dielectric layer 118, in accordance with some embodiments. Examples 1, 2 and 3 are shown in FIG. 7C. In some embodiments where the second high-k gate dielectric layer 118 is Hf x Zr y O, an atomic ratio Zr / Hf in the second high-k gate dielectric layer 118 may be controlled by adjusting a ratio of the first cycles S 200 to the second cycles S 202. In Example 1, the second high-k gate dielectric layer 118 is formed by PEALD using a ratio of the first cycles S 200 to the second cycles S 202 of about 1:2, wherein a ratio Zr / Hf of the second high-k gate dielectric layer 118 is about 2.32±0.2. The Zr in the second high-k gate dielectric layer 118 has an atomic percentage of about 70±2%. In Example 2, the second high-k gate dielectric layer 118 is formed by thermal ALD, a ratio of the first cycles S 200 to the second cycles S 202 may be about 1:2, and a ratio Zr / Hf of the second high-k gate dielectric layer 118 is about 2.16±0.2. In Example 3, the second high-k gate dielectric layer 118 is formed by thermal ALD, a ratio of the first cycles S 200 to the second cycles S 202 may be about 1:4, and a ratio Zr / Hf of the second high-k gate dielectric layer 118 is about 4.47±0.2.Now, please refer to FIG. 8A. An electrode layer is formed on the second high-k gate dielectric layer 118, and a mask layer (not shown) may be formed and patterned on the electrode layer to expose the second high-k gate dielectric layer 118. In some embodiments, the mask layer may be a photoresist material that is formed by a spin coating process and subsequently patterned using suitable lithography techniques. Details of the lithography methods for the mask layer are similar to those for the mask layer 110 discussed above with reference to FIG. 3, and thus the description is omitted here. After the mask layer is formed and patterned, the electrode layer is etched using the mask layer as an etch mask, thereby exposing the second high-k gate dielectric layer 118. The unetched electrode layer serves as a gate electrode 120. This results in a semiconductor device 10.FIGS. 8B and 8C are cross-sectional views of a semiconductor device 10 aand 10 b, respectively, at various stages of manufacture in accordance with some embodiments of the present disclosure. First, please refer to FIG. 8B. The semiconductor device 10 ais similar to the semiconductor device 10 of FIG. 8A, except that the second high-k gate dielectric layer 118 between the gate electrode 120 and the adhesion layer 106 is absent.The semiconductor device 10 bin FIG. 8C is similar to the semiconductor device 10 of FIG. 8A, except that the first high-k gate dielectric layer 116 between the gate electrode 120 and the adhesion layer 106 is absent. That is, the second high-k gate dielectric layer 118 is in contact with the adhesion layer 106. The second high-k gate dielectric layer 118 extends along a sidewall of the source / drain electrodes 114 to above the top of the source / drain electrodes 114.FIGS. 9A to 9C are enlarged views of a region R 1 of FIG. 8A, in accordance with some embodiments. In FIGS. 8A and 9A- 9C, high-k gate dielectric stack 119 may be characterized by EDS (energy dispersive spectroscopy) analysis through EDS imaging for a Zr signal for second high-k gate dielectric layer 118 and for an Al signal for adhesion layer 106. Therefore, there is a detectable boundary between the adhesion layer 106 and the high-k gate dielectric stack 119 formed by the first and second high-k gate dielectric layers 116, 118. For example, in FIG. 9A, the adhesion layer 106 has a thickness 11 of about 0.7 nm to about 1.3 nm, e.g., about 1 nm, and the high-k gate dielectric stack 119 has a thickness t 2 of about 4.5 nm to about 5.2 nm, e.g., about 4.9 nm. For example, in FIG. 9B, the adhesion layer 106 has a thickness t 3 of about 0.7 nm to about 1.3 nm, e.g., about 1 nm, and the high-k gate dielectric stack 119 has a thickness t 4 of about 3.5 nm to about 4.2 nm, e.g., about 3.9 nm. For example, in FIG. 9C, the adhesion layer 106 has a thickness t 5 of about 0.7 nm to about 1.3 nm, e.g., about 1 nm, and the high-k gate dielectric stack 119 has a thickness t 6 of about 2.1 nm to about 2.7 nm, e.g., about 2.4 nm.Example 4A dielectric layer is formed on a substrate. A 2D material layer is formed on the dielectric layer, and an adhesion layer is formed on the 2D material layer. Source / drain electrodes are formed on opposite sides of the adhesion layer. First and second high-k gate dielectric layers are sequentially formed on the source / drain electrodes and the adhesion layer, the first and second high-k gate dielectric layers each including HfO x deposited at a temperature of 200±10 °C and 250±10 °C, respectively. A gate electrode is formed on the second high-k gate dielectric layer.Comparative Example 1A dielectric layer is formed on a substrate. A 2D material layer is formed on the dielectric layer. Source / drain electrodes are formed on opposite sides of the adhesion layer. A first high-k gate dielectric layer is formed on the source / drain electrodes and the adhesion layer, the first high-k gate dielectric layer including HfO x deposited at a temperature of 200±10 ° C. A gate electrode is formed on the first high-k gate dielectric layer.Example 5A dielectric layer is formed on a substrate. A 2D material layer is formed on the dielectric layer. Source / drain electrodes are formed on opposite sides of the adhesion layer. A first and a second high-k gate dielectric layer are successively formed on the source / drain electrodes and the adhesion layer, the first high-k gate dielectric layer including HfO x deposited at a temperature of 200±10 °C, and the second high-k gate dielectric layer including HZO deposited at a temperature of 250±10 °C. A gate electrode is formed on the second high-k gate dielectric layer.FIG. 10A shows transfer characteristics according to Example 4 and Comparative Example 1. FIG. 10B shows transfer characteristics according to Example 4 and Example 5. As seen from FIG. 10A, Example 4 showed a reduced prethreshold swing (SS) of, for example, about 100±2 mV / dec. On the other hand, in Comparative Example 1, an increased SS was observed. As seen from FIG. 10B, Example 5 showed a reduced prethreshold swing (SS) of, for example, about 60±2 mV / dec.FIG. 10C is a graph showing a threshold voltage V TH( or V TG) as a function of a back gate voltage V BG according to Examples 4 and 5. As can be seen from FIG. 10C, Example 4 showed a reduced equivalent oxide thickness (EOT) of, for example, about 3.1±0.2 nm. Example 5 also showed a reduced EOT of, for example, about 2.2 ± 0.2 nm.FIGS. 11A and 11B are diagrams showing a dielectric constant (k-value) of pure HfO x( which is undoped), and a dielectric constant (k-value) of HZO, respectively, depending on an applied voltage, according to some embodiments. In FIG. 11A, the dielectric constant of pure HfO x is about 10±5, and in FIG. 11B, the dielectric constant of HZO is about 24±5, which is larger than the dielectric constant of pure HfO x.Example 6A dielectric layer is formed on a substrate. A monolayer of MoS 2(1 L-MoS 2) is prepared on the dielectric layer. An adhesion layer is formed on the monolayer of MoS 2. Source / drain electrodes are formed on opposite sides of the adhesion layer. First and second high-k gate dielectric layers are sequentially formed on the source / drain electrodes and the adhesion layer, the first high-k gate dielectric layer including HfO x and the second high-k gate dielectric layer including HZO. A gate electrode is formed on the second high-k gate dielectric layer.Comparative Example 2A dielectric layer is formed on a substrate. A monolayer of MoS 2(1 L-MoS 2) is prepared on the dielectric layer. Source / drain electrodes are formed on opposite sides of monolayer MoS 2. On the source / drain electrodes, a PTCDA layer (PTCDA: 3,4,9,10-perylenetetracarboxylic dianhydride) and an HfO x- layer are successively produced. A gate electrode is formed on the HfO x- layer.Comparative Example 3A dielectric layer is formed on a substrate. A monolayer of MoS 2(1 L-MoS 2) is prepared on the dielectric layer. Source / drain electrodes are formed on opposite sides of monolayer MoS 2. An AlO x- layer is formed on the source / drain electrodes. A gate electrode is formed on the AlO x- layer.Comparative Example 4A dielectric layer is formed on a substrate. A monolayer of MoS 2(1 L-MoS 2) is prepared on the dielectric layer. Source / drain electrodes are formed on opposite sides of monolayer MoS 2. An HfO x- layer is produced on the source / drain electrodes. A gate electrode is formed on the HfO x- layer.Comparative Example 5A dielectric layer is formed on a substrate. A monolayer of MoS 2(1 L-MoS 2) is prepared on the dielectric layer. Source / drain electrodes are formed on opposite sides of monolayer MoS 2. A ZrO x- layer is formed on the source / drain electrodes. A gate electrode is formed on the ZrO x- layer.FIG. 12A is a graph showing an ε eff- value (ε eff: equivalent effective dielectric constant) versus a physical thickness (t ox) on a monolayer MoS 2(1 L-MoS 2) according to Example 6 and Comparative Examples 2 to 5. As is apparent from Fig. 12A, Example 6 showed an increased ε eff- value. For example, in Example 6, the ε eff- value was larger than that in Comparative Examples 2 to 5.Comparative Example 6A dielectric layer is formed on a substrate. A monolayer of MoS 2(1 L-MoS 2) is prepared on the dielectric layer. Source / drain electrodes are formed on opposite sides of monolayer MoS 2. On the source / drain electrodes, a YO x- layer and a ZrO x- layer are sequentially formed. A gate electrode is formed on the ZrO x- layer.Comparative Example 7A dielectric layer is formed on a substrate. A monolayer of MoS 2(1 L-MoS 2) is prepared on the dielectric layer. Source / drain electrodes are formed on opposite sides of monolayer MoS 2. On the source / drain electrodes, a TiOPc layer (TiOPc: titanyl phthalocyanine) and an AlO x- layer are sequentially formed. A gate electrode is formed on the AlO x- layer.FIG. 12B is a graph showing a breakdown voltage (V BD) depending on an effective oxide thickness (EOT) according to Example 6 and Comparative Examples 2, 3, 6, and 7. As is apparent from FIG. 12B, Example 6 exhibited an increased V BD, which is higher than the V BD in Comparative Examples 2, 3, 6, and 7. For example, in Example 6, the V BD is about 12.4±2 MV / cm.Comparative Example 8A dielectric layer is formed on a substrate, the substrate being doped to serve as a back gate. A 2D material layer is formed on the dielectric layer. Source / drain electrodes are formed on opposite sides of the 2D material layer. A CaF 2- layer is formed on the source / drain electrodes and the 2D material layer.Comparative Example 9A dielectric layer is formed on a substrate, the substrate being doped to serve as a back gate. A 2D material layer is formed on the dielectric layer. Source / drain electrodes are formed on opposite sides of the 2D material layer. A SrTiO 3- layer is formed on the source / drain electrodes and the 2D material layer.Comparative Example 10An HfO x- layer is produced on a silicon substrate. Source / drain electrodes are formed on opposite sides of the HfO x- layer. A gate electrode is formed on the HfO x- layer.Comparative Example 11A SiO x- layer is formed on a silicon substrate. An HfO x- layer is produced on the SiO x- layer. Source / drain electrodes are formed on opposite sides of the HfO x- layer. A gate electrode is formed on the HfO x- layer.FIG. 12C is a graph showing a gate leakage current (Jg) depending on the EOT according to Example 6 and Comparative Examples 2, 3, 7, 8, 9, 10, and 11. As is apparent from FIG. 12C, Example 6 exhibited a reduced gate leakage current (Jg) lower than the gate leakage current (Jg) in Comparative Examples 2, 3, 7, 8, 9, 10, and 11.FIG. 12D is a graph showing EOT versus thickness of the second high-k gate dielectric layer according to Example 6. The second high-k gate dielectric layer in Example 6 exhibited a k value of about 24±2 at a thickness of about 3 nm to about 6 nm.FIG. 12E is a graph showing the gate leakage current (J G) as a function of a top gate voltage (V TG) according to Example 6. In FIG. 12E, curves 1002 represent the second high-k gate dielectric layer having a thickness of about 1.5±0.2 nm in Example 6. Curves 1004 represent the second high-k gate dielectric layer having a thickness of about 3±0.2 nm in Example 6. In FIG. 12E, low gate leakage currents are achieved in curves 1002 and 1004.FIG. 13A is a graph showing hysteresis ΔV TH depending on an overvoltage (V ov) defined as a difference between a bias voltage (V TG) and a breakdown voltage (V TH) according to Examples 5 and 6. In FIG. 13A, in example 6, reference numeral 1006 represents a second high-k gate dielectric layer having a thickness of about 1.5±0.2 nm, reference numeral 1008 represents a second high-k gate dielectric layer having a thickness of about 3±0.2 nm, and reference numeral 1010 represents a second high-k gate dielectric layer having a thickness of about 4±0.2 nm. In Example 4, reference numeral 1012 represents the second high-k gate dielectric layer having a thickness of about 5±0.2 nm. Since the thickness of the second high-k gate dielectric layer is smaller in Example 6, its ferroelectric characteristic is attenuated (or reduced), so that ΔV TH is reduced, thereby forming a high-k gate dielectric layer almost free of hysteresis.FIG. 13B is a diagram showing drain current (I D) and gate leakage current (J G) depending on top gate voltage (V TG) according to Example 6 with a second high-k gate dielectric layer having a thickness of about 1.5±0.2 nm. At a drain voltage V D of about 1 ± 0.2 V, the gate leakage current I G is very low.From the foregoing, it will be appreciated that the present disclosure provides advantages in various embodiments. It should be appreciated, however, that other embodiments may provide other benefits, not necessarily all benefits being mentioned herein, and no particular benefit is required for all embodiments. An advantage is that an adhesion layer is formed for improving adhesion between a 2D material layer and a first high-k gate dielectric layer. Another advantage is that the adhesion layer improves the formation of the first and / or second high-k gate dielectric layers on the 2D material layer to improve electrical properties, for example reducing the pre-threshold lift (SS) and the effective oxide thickness (EOT).In some embodiments, a method of manufacturing a semiconductor device includes the following steps. A dielectric layer is formed over a substrate. A 2D material layer is formed over the dielectric layer. An adhesion layer is formed over the 2D material layer. Source / drain electrodes are formed on opposite sides of the adhesion layer. A first high-k gate dielectric layer is formed over the adhesion layer, the adhesion layer including a material different from a material of the first high-k gate dielectric layer. In some embodiments, forming the adhesion layer on the 2D material layer includes forming a nanofog film on the 2D material layer by atomic layer deposition. In some embodiments, forming the adhesion layer on the 2D material layer further includes: after forming the nanofog film on the 2D material layer by atomic layer deposition, performing a deposition process for forming a film on the nanofog film, the film including the same material as the nanofog film. In some embodiments, the adhesion layer has a dielectric constant that is lower than a dielectric constant of the first high-k gate dielectric layer. In some embodiments, the adhesion layer is aluminum oxide. In some embodiments, the method further comprises forming a second high-k gate dielectric layer over the first high-k gate dielectric layer, the second high-k gate dielectric layer having a composition different from a composition of the first high-k gate dielectric layer. In some embodiments, the second high-k gate dielectric layer has a dielectric constant that is higher than a dielectric constant of the first high-k gate dielectric layer. In some embodiments, the first high-k gate dielectric layer is hafnium oxide and the second high-k gate dielectric layer is hafnium zirconium oxide. In some embodiments, forming the adhesion layer on the 2D material layer includes the steps of: forming a metal layer on the 2D material layer; and oxidizing the metal layer to form the adhesion layer.In some embodiments, a semiconductor device includes: a substrate; a dielectric layer over the substrate; a 2D material layer over the dielectric layer; an adhesion layer over the 2D material layer; a first hafnium-containing layer over the adhesion layer, the first hafnium-containing layer having a dielectric constant that is higher than a dielectric constant of the adhesion layer; and source / drain electrodes over the 2D material layer. In some embodiments, the semiconductor device further includes a second hafnium-containing layer over the first hafnium-containing adhesion layer, the second hafnium-containing layer having a dielectric constant different from the dielectric constant of the first hafnium-containing layer. In some embodiments, the second hafnium-containing layer has a dielectric constant that is higher than the dielectric constant of the first hafnium-containing layer. In some embodiments, the first hafnium-containing layer is hafnium zirconium oxide. In some embodiments, the first hafnium-containing layer is an undoped layer. In some embodiments, a top surface of the adhesion layer is lower than a top surface of one of the source / drain electrodes. In some embodiments, the adhesion layer is in physical contact with the first hafnium-containing layer. In some embodiments, the first hafnium-containing layer extends along a sidewall of the source / drain electrodes to over a top surface of one of the source / drain electrodes.In some embodiments, a method of manufacturing a semiconductor device includes the following steps. A nitride layer is formed over a semiconductor substrate. A 2D semiconductor layer is formed on the nitride layer. A first metal oxide layer is formed over the 2D semiconductor layer. The first metal oxide layer is patterned. A first deposition process is performed to form a second metal oxide layer on the first metal oxide layer. A gate electrode is formed over the second metal oxide layer. In some embodiments, after forming the first metal oxide layer, the method further comprises forming source / drain electrodes connected to the first metal oxide layer. In some embodiments, the method further comprises performing a second deposition process to form a third metal oxide layer on the second metal oxide layer, wherein the third metal oxide layer is doped with zirconium.Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other methods and structures to achieve the same objects and / or to achieve the same benefits as the embodiments presented herein. Those skilled in the art will also appreciate that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

A method of manufacturing a semiconductor device, comprising: forming a dielectric layer over a substrate; forming a 2D material layer over the dielectric layer; forming an adhesion layer over the 2D material layer; forming source / drain electrodes on opposite sides of the adhesion layer; and forming a first high-k gate dielectric layer over the adhesion layer, wherein the adhesion layer includes a material different from a material of the first high-k gate dielectric layer.The method of claim 1, wherein forming the adhesion layer on the 2D material layer comprises forming a nanofog film on the 2D material layer by atomic layer deposition.The method according to claim 2, wherein forming the adhesion layer on the 2D material layer further comprises: after forming the nanofog film on the 2D material layer by atomic layer deposition, performing a deposition process for forming a film on the nanofog film, the film including the same material as the nanofog film.The method of any preceding claim, wherein the adhesion layer has a dielectric constant that is lower than a dielectric constant of the first high-k gate dielectric layer.The method of any preceding claim, wherein the adhesion layer is alumina.The method of any preceding claim, further comprising: forming a second high-k gate dielectric layer over the first high-k gate dielectric layer, wherein the second high-k gate dielectric layer has a composition different from a composition of the first high-k gate dielectric layer.The method of claim 6, wherein the second high-k gate dielectric layer has a dielectric constant that is higher than a dielectric constant of the first high-k gate dielectric layer.The method of claim 6 or 7, wherein the first high-k gate dielectric layer is hafnium oxide and the second high-k gate dielectric layer is hafnium zirconium oxide.The method of claim 6, 7 or 8, wherein forming the adhesion layer on the 2D material layer comprises: forming a metal layer on the 2D material layer; and oxidizing the metal layer to form the adhesion layer.A semiconductor device, comprising: a substrate; a dielectric layer over the substrate; a 2D material layer over the dielectric layer; an adhesion layer over the 2D material layer; a first hafnium-containing layer over the adhesion layer, the first hafnium-containing layer having a dielectric constant that is higher than a dielectric constant of the adhesion layer; and source / drain electrodes over the 2D material layer.The semiconductor device of claim 10, further comprising: a second hafnium-containing layer over the first hafnium-containing adhesion layer, wherein the second hafnium-containing layer has a dielectric constant different from the dielectric constant of the first hafnium-containing layer.The semiconductor device of claim 11, wherein the second hafnium-containing layer has a dielectric constant that is higher than the dielectric constant of the first hafnium-containing layer.The semiconductor device according to claim 11 or 12, wherein the first hafnium-containing layer is hafnium zirconium oxide.The semiconductor device according to claim 11, 12 or 13, wherein the first hafnium-containing layer is an undoped layer.The semiconductor device according to any one of claims 10 to 14, wherein a top surface of the adhesion layer is lower than a top surface of one of the source / drain electrodes.The semiconductor device according to any one of claims 10 to 15, wherein the adhesion layer is in physical contact with the first hafnium-containing layer.The semiconductor device of any of claims 10 to 16, wherein the first hafnium-containing layer extends along a sidewall of the source / drain electrodes to over a top surface of one of the source / drain electrodes.A method of manufacturing a semiconductor device, comprising: forming a nitride layer over a semiconductor substrate; forming a 2D semiconductor layer on the nitride layer; forming a first metal oxide layer over the 2D semiconductor layer; patterning the first metal oxide layer; performing a first deposition process to form a second metal oxide layer on the first metal oxide layer; and forming a gate electrode over the second metal oxide layer.The method of claim 18, further comprising: after forming the first metal oxide layer, forming source / drain electrodes connected to the first metal oxide layer.The method of claim 18 or 19, further comprising: performing a second deposition process to form a third metal oxide layer on the second metal oxide layer, wherein the third metal oxide layer is doped with zirconium.

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