Wide dynamic range optical sensor using trench capacitors with sidewall structures

Abstract

An optical sensor and enclosed pixel circuits of an array of pixel circuits are described. Each pixel circuit may include a microlens, a color filter disposed adjacent to the microlens, and an epitaxial substrate layer disposed adjacent to the color filter opposite the microlens. To provide a trench capacitor for the pixel circuit, an isolation trench may be formed in the epitaxial substrate layer to have sidewalls with sidewall recesses formed therein that increase a surface area and thus a capacitance of the trench capacitor.

Description

TECHNICAL FIELDThis description relates to large dynamic range (HDR) sensors.BACKGROUNDMany devices such as cell phones, cameras, and computers typically use optical sensors such as image sensors. For example, a common imager sensor may include a focal plane array of pixels, each pixel including a light sensitive sensor, such as a photogate, photoconductor, or photodiode, for accumulating photogenerated charge in a portion of an underlying substrate. When photons fall on the photosensor, electron-hole pairs are generated. Conventional image sensors convert the electrons accumulated in the pixels into a voltage while the holes are generally disposed of into the substrate.A large dynamic range (HDR) in the context of image acquisition generally denotes a ratio between the highest detectable illumination intensity to a lowest detectable illumination intensity. For example, an HDR image sensor is capable of imaging a scene that includes both bright and dark portions. If an imaged scene includes portions that have an illuminance in excess of that detectable by an image sensor used, then the image sensor may saturate, resulting in areas of uniform brightness within a captured image that do not accurately reflect the actual brightness levels in the captured scene, for example.SUMMARYThe described techniques increase the per-pixel capacitance of an optical sensor by using deep trench capacitors (deep trench capacitors) with sidewall structures such as sidewall ribs. This allows a dynamic range of the optical sensor to be improved.In a general aspect, a semiconductor device includes a micro lens, a color filter disposed adjacent to the micro lens, an epitaxial substrate layer disposed adjacent to the color filter opposite to the micro lens, and a trench capacitor formed in the epitaxial substrate layer and having sidewall recesses.In another general aspect, an optical sensor including an array of pixel circuits, each pixel circuit comprising: a micro lens; a color filter disposed adjacent to the micro lens; an epitaxial substrate layer disposed adjacent to the color filter opposite the micro lens; and an isolation trench formed in the epitaxial substrate layer and having sidewalls with sidewall recesses formed therein, the sidewall recesses having insulating material disposed therein, and the isolation trench having conductive material disposed therein.In another general aspect, a method of manufacturing a semiconductor device includes: forming a trench in an epitaxial substrate layer, the trench having sidewall recesses, providing an insulating material in the sidewall recesses, and providing a conductive material in the trench adjacent to the insulating material. The method includes providing a color filter adjacent to a surface of the epitaxial substrate layer and forming a microlens adjacent to the color filter.The details of one or more implementations are set forth in the accompanying drawings and the following description. Other features will be apparent from the description and drawings and from the claims.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 illustrates an example implementation of a large dynamic range optical sensor (HDR) with trench capacitors having sidewall structures. FIG. 2 is a first alternative example of the HDR image sensor of FIG. 1. FIG. 3 is a second alternative example of the HDR image sensor of FIG. 1. FIG. 4 is an isometric view of example pixels of the HDR image sensors of FIGS. 1-3. FIG. 5 is an example plan view of the pixels of FIG. 4 with a deep trench capacitor on two walls of each pixel. FIG. 6A is a first example plan view of the pixels of FIG. 4 with separate deep trench capacitors on each of two walls of each pixel. FIG. 6B is a second example plan view of the pixels of FIG. 4 with separate deep trench capacitors on each of two walls of each pixel. FIG. 7 illustrates first example operations of an example process flow for fabricating the image sensors of FIGS. 1-6. FIG. 8 illustrates second example operations of an example process flow for fabricating the image sensors of FIGS. 1-6. FIG. 9 illustrates third example operations of an example process flow for fabricating the image sensors of FIGS. 1-6. FIG. 10 illustrates fourth example operations of an example process flow for fabricating the image sensors of FIGS. 1-6. FIG. 11 illustrates fifth example operations of an example process flow for fabricating the image sensors of FIGS. 1-6. FIG. 12 illustrates sixth example operations of an example process flow for fabricating the image sensors of FIGS. 1-6. FIG. 13 illustrates seventh example operations of an example process flow for fabricating the image sensors of FIGS. 1-6. FIG. 14 illustrates eighth example operations of an example process flow for fabricating the image sensors of FIGS. 1-6. FIG. 15 is a flow chart illustrating example operations for manufacturing the image sensors of FIGS. 1-6, which correspond to the example operations of FIGS. 7-14. FIG. 16 is a graph illustrating examples of capacitance per pixel versus dielectric thickness for example embodiments. FIG. 17 is a graph illustrating examples of capacitance per pixel versus trench depth for example embodiments.DETAILED DESCRIPTIONThe described techniques increase a per pixel capacitance of an optical sensor by using deep trench capacitors (deep trench capacitors) with sidewall structures such as corrugations. The sidewall structures increase a surface area of each of the deep trench capacitors relative to capacitors of conventional optical sensors, such that each capacitor may hold relatively more charge. Optical sensors produced as a result consequently have a greater dynamic range than conventional optical sensors which use capacitors without side wall structures.In some examples, trenches of the described deep trench capacitors may be formed (run) with sidewall structures over an entire depth of a substrate of the optical sensor. In other examples, the trenches of the described deep trench capacitors with sidewall structures may only partially extend through the substrate of the optical sensor.The described sidewall structures of pixel capacitors may be formed using any suitable technique. For example, sidewall corrugations may be formed using the Bosch process, which is a deep reactive ion etch (DRIE), or another suitable type of etching process.The described capacitors with sidewall structures may be formed on multiple sides of each pixel of an optical sensor. For example, a capacitor may be formed in an L-shape around two sides of a pixel, or separate capacitors may be formed on each of two sides of a pixel. In additional or alternative examples, two or more capacitors may be formed on a single side of a pixel.Thus, the described apparatus and techniques for increasing a dynamic range of an optical sensor may provide improved pixel capacity to enable sensing of a larger luminance range. Aspects described may be operative in conjunction with any suitable imaging system, such as a digital camera, smart phone, web camera, video camera, video surveillance system, or in-vehicle imaging system. Further, the technology disclosed for the optical sensor may be utilized with any suitable imaging system such as a camera system, video system, machine vision system, vehicle navigation system, monitoring system, motion sensing system, and the like.The imaging systems described may be configured to produce a digital HDR image for which both low-intensity signals and high-intensity signals from a single exposure are used. For example, described image sensors may include arrays of pixel circuits to detect light and transmit information that makes up an image by converting the variable attenuation of photon current into electrical signals. The described image sensors may be implemented in conjunction with any suitable technology, such as active pixel sensors in CMOS technology.In various embodiments, an imaging system may include a main lens to focus an image or scene onto an image sensor. For example, light may enter the imaging system through the main lens and strike the image sensor. The image sensor may capture and generate image data corresponding to one or more lines in the array of pixel circuits. The image data may include image pixel data corresponding to one or more pixel circuits in the array of pixel circuits. For example, image data may include information representing a measured voltage, current, or other magnitude due to light absorbed by each pixel circuit such that each image pixel includes an individual pixel intensity value.The image sensor processes received image data according to any suitable functions such as demosaicing, white balance, noise mitigation, color correction, and the like. The image sensor may further include various signal processing circuits and / or systems, such as sample-and-hold circuitry, an analog-to-digital converter, an amplifier, and the like, that are used to convert the pixel charge to a digital image.FIG. 1 illustrates an example implementation of a large dynamic range optical sensor (HDR) having trench capacitors 102 having sidewall structures 120. It should be understood that while reference is primarily made to image sensor structures in the following description, example implementations may be provided for other types of optical sensors.As shown in FIG. 1 and described in detail below, the sidewall structures 120 may be implemented as corrugations, each corrugation having a curvature that effectively increases a surface area and thus a capacitance of the trench capacitors 102 relative to trench capacitors that do not have sidewall structures 120.In FIG. 1, a pixel circuit 100 of an array of pixel circuits is configured to capture a portion of an image or scene. The pixel circuit 100 may be formed in conjunction with a first chip (e.g., an image sensor chip) and a second chip (e.g., an application specific integrated circuit (ASIC)) that are vertically stacked, as described in more detail below with reference to FIGS. 10 and 11. In the simplified example of FIG. 1, only relevant portions of an image sensor chip are illustrated, and a vertically stacked ASIC chip (or similar type of control chip) is omitted for clarity and brevity.A solid-state pixel structure corresponding to a portion of the pixel circuit 100 includes an epitaxial substrate layer 116 having a top surface covered with a silicon layer 112 (e.g., a passivation layer) formed of any suitable material, such as silicon dioxide (SiO 2) or silicon nitride (Si 3 N 4) to isolate and / or protect the epitaxial substrate layer 116.As shown and described in more detail below, the sidewall structures 120 may be formed as depressions in the epitaxial substrate layer 116. The epitaxial substrate layer 116 may be further insulated by insulating layers 106 disposed along and within the sidewall structures 120 and by a second oxide layer 118 disposed along the top surface between the epitaxial substrate layer 116 and the silicon layer 112.The pixel circuit 100 may further include a color filter 108 and a microlens 110. In example embodiments, a first side of the color filter 108 is disposed on a side of the silicon layer 112 opposite the epitaxial substrate layer 116, as shown in FIG. 1. The microlens 110 is disposed adjacent to a second side of the color filter 108 that is opposite to the silicon layer 112. This arrangement is commonly referred to as a backlighted (BSI) pixel, as described below with reference to Figures 10-14. The microlens 110 concentrates incident photons and generates electrons (and holes) that are accumulated in doped regions of the epitaxial substrate layer 116.The trench capacitor 102, including a conductive material 104 and insulating layers 106, may thus be used to store the accumulated charge for further image processing. For example, the insulating layers 106 may be formed in the recesses of the sidewall structures 120. The trench capacitor 102 may be connected to a ground bias potential via 114.The conductive material 104 may include any suitable conductive material such as doped polysilicon, copper, tungsten, or a transparent electrode such as indium tin oxide (ITO). The insulating layers 106 may comprise any material suitable for insulating the trench capacitor 102, including SiO 2, or may include one or more more more modern high-k (HiK) dielectric materials, such as hafnium oxide (HfO x), zirconium oxide (ZrO x), zirconium aluminate (ZrAlO x), tantalum pentoxide (Ta 2 O s) or aluminum oxide (Al 2 O 3). An additional HiK layer 119 may be included between the epitaxial substrate layer 116 and the oxide layer 118 as shown.In FIG. 1 and subsequent embodiments, the vertical orientation of the trench capacitor 102 generally allows for a large charge storage capacitance and a large dynamic range without sacrificing a pixel area exposed to light. This may provide smaller pixels and higher quantum yield, thereby providing improved sensor performance and lower cost.In addition, as mentioned above, the sidewall structures 120 provide an increased surface area that, while other factors are the same, results in increased capacitance relative to trench capacitors without the sidewall structures 120. As shown in the exploded view of FIG. 1, the sidewall structures 120 may be formed as recesses in the epitaxial substrate layer 116, each recess having a width 122 and a depth 124.The sidewall structures 120 should be understood to describe any concavity or opening within sidewalls of the epitaxial substrate layer 116. For example, the sidewall structures 120 may be concave surfaces that have been hollowed out or rounded inward with respect to the sidewalls of the surrounding epitaxial substrate layer 116. The sidewall structures 120 may also be said to form convex surfaces with respect to peaks formed between pairs of recesses. Various other suitable terms may be used to describe the sidewall structures 120, such as indentations, voids, or castellations.To provide the sidewall structures 120, a deep reactive ion etching (DRIE) process, such as the Bosch process, may be used. As illustrated below with reference to FIG. 7, in the Bosch process, an initial opening may be formed in the epitaxial substrate layer 116 using any suitable technique such as masking / etching. Then, the Bosch process may be implemented as a three-step processing cycle in which (1) a passivation layer is deposited within the opening on the exposed sidewalls and below the opening, (2) a first etch is anisotropically performed to remove only a portion of the passivation layer between the sidewalls of the opening (i.e., at the bottom of the opening) and thereby expose the epitaxial substrate layer 116 without removing the passivation layer from previously formed sidewall recesses, and (3) a second etch is isotropically performed to etch the exposed substrate at the bottom of the opening.When the exposed substrate is isotropically etched by the second etching, new ones of the various sidewall recesses 120 are formed. Repeating this three-step processing cycle (e.g., iterations or loops) multiple times therefore results in gradual formation of the opening and associated sidewall recesses, thereby forming sidewall structures 120 until a desired depth is reached within epitaxial substrate layer 116 for trench capacitor 102.Using the above-mentioned type of DRIE processes, it is possible to form the trench capacitors 102 highly accurately and custom while maintaining per pixel correspondence between corresponding capacitors of different pixels within the pixel circuit 100. That is, although it is generally known that capacitance changes directly in proportion to surface area, conventional surface area increasing techniques may be improper to increase the surface area of trench capacitors in conjunction with pixel circuit 100 or similar pixel circuits.For example, as just mentioned, it may be desirable to maintain the per pixel match between corresponding capacitors of different pixels in order to maintain the overall image quality of the captured images. For example, if the capacitances of adjacent pixels vary, one of the adjacent pixels may saturate at a different light intensity than the other of the adjacent pixels.Using the types of DRIE processing described herein, sidewall structures 120 may be formed in a uniform manner for all corresponding capacitors of the different pixels of pixel circuit 100. For example, as described with reference to FIGS. 4-6, each individual pixel of a pixel circuit may include two or more capacitors, and different such intra-pixel capacitors may have differences within the individual pixel with respect to each other, while inter-pixel capacitors have a uniform structure. In other words, pixels may have a uniform capacitor structure that may include different types of capacitors within each pixel.The described techniques may provide such matching of the capacitors between pixels while at the same time allowing a high degree of individual adjustment in designing individual capacitors within each pixel. For example, a desired number, width, and depth of each of the trench capacitors 102 may be readily implemented, and the width 122 and depth 124 may also be accurately controlled, as described below with reference to FIG. 7.For example, the DRIE process may be controlled by controlling various process parameters. Such process parameters may include, for example, gas flow rates for one or more of etch / deposit gases, etch / deposit durations, and / or processing power. As already mentioned, a total depth of the trench capacitors 102 may be determined by a total number of iterations of the three-stage etch process performed in cooperation with the various other relevant processing parameters.In addition, such process parameters may be varied during the formation of the various embodiments of the trench capacitor 102 to obtain customized / desired aspects of the sidewall structures 120. For example, FIG. 1 illustrates the sidewall structures 120 as being identical to each other over a length of the trench capacitor 102. However, in example implementations, aspects of the sidewall structures may vary along the length of the trench capacitor 102.For example, a first DRIE process may be implemented with first process parameters for a first number of iterations to obtain sidewall structures 120 with first values for a width 122 and / or a depth 124. Then, a second DRIE process with second process parameters may be implemented for a second number of iterations to obtain sidewall structures 120 with second values for the width 122 and / or the depth 124. To obtain a desired trench capacitor structure, multiple such DRIE processes may be performed (e.g., three or more). For example, sidewall structures 120 may be formed with a first set of sidewall structures with relatively small corrugations (recesses) closer to passivation layers 112, 118 and a second set of sidewall structures with relatively large corrugations (recesses) closer to vias 114. More generally, the sidewall structures 120 may be formed with "n" (e.g., 3 or more) sets of sidewall structures of different sizes of corrugations (recesses) along a length of the trench capacitors 102.In the example of FIG. 1, the trench capacitors 102 extend through an entire thickness of the epitaxial substrate layer 116. That is, the trench capacitors 102 extend between a lens-side surface of the epitaxial substrate layer 116 adjacent to the passivation layer 118 (also referred to as a backside of the image sensor) and an opposing surface of the epitaxial substrate layer 116 adjacent to the vias 114 (also referred to as a front side of the image sensor). In other words, the trench capacitors 102 may extend through an entire thickness of the epitaxial substrate layer 116 in a direction perpendicular to the color filter 108.However, in other example implementations, trench capacitors may only partially extend through the epitaxial substrate layer 116. For example, FIG. 2 illustrates a pixel circuit 200 in which like elements have like reference numerals with respect to FIG. 1 and in which trench capacitors 202 only partially extend through the epitaxial substrate layer 116, namely from the front surface at the via 114 to the back surface towards the color filter 108 and the microlens 110.FIG. 3 illustrates another example implementation in which a pixel circuit 300 includes trench capacitors 302 that extend partially through the epitaxial substrate layer 116. In FIG. 3, unlike the trench capacitors 202 in the example of FIG. 2, the trench capacitors 302 extend from a surface in a vicinity of the color filter 108 and the microlens 110 through the epitaxial substrate layer 116 toward, but without reaching, the opposite surface of the epitaxial substrate layer 116.In the example of FIG. 3, a metallization layer 310 is illustrated as being disposed between the trench capacitors 302 and the color filter 108. As further illustrated, metallization layer 310 includes an interlayer dielectric layer 312 in which various metal layers 316 are formed. The trench capacitors 302 are connected to the metal layers 316 via a via 314 analogous to the via 114 of FIGS. 1 and 2. The example embodiment of FIG. 3 may be referred to as a front side implementation because incident light traverses the metal layers 310 to reach the epitaxial substrate layer 116 and the trench capacitors 302.FIG. 4 is an isometric view of example pixels of the HDR image sensors of FIGS. 1-3, FIG. 4 illustrates an array of pixel circuits 400, wherein a first epitaxial substrate layer of a first pixel circuit 100 a(as an example of the pixel circuit 100) may be isolated from a second epitaxial substrate layer of a second pixel circuit 100 b, namely by a deep trench isolation region / regions that is / are used to form the type of trench capacitor(s) 102 of FIG. 1.In FIG. 4, analogously to the trench capacitor / capacitors 102 of FIG. 1, the trench capacitor / capacitors 402 may be arranged along a given sidewall adjacent to a corresponding pixel circuit / circuits, such as the pixel circuits 100 a, 100 b. That is, conductive material disposed within trench isolation regions forms a capacitor surface used to form a capacitor for an adjacent photodetector of each pixel circuit 100 a, 100 b.Referring to FIGS. 1-4, a total capacitance of a given pixel circuit 100 (such as 100 a, 100 bof FIG. 4 ) may be increased by extending the conductive material 104 along an additional sidewall of the epitaxial substrate layer 116. For example, as shown in FIG. 4, the trench capacitor 402 may include first and second capacitor surfaces extending continuously along two adjacent sidewalls of the pixel circuit 100 b. That is, the trench capacitor 402 extends along two surfaces of an epitaxial substrate layer 116. Using two adjacent sidewalls increases the overall surface area that can be used to form the capacitor, thereby allowing for a higher capacitance than using a single sidewall.FIG. 5 illustrates a top view of the example of FIG. 4, including a pixel circuit 500 aand a pixel circuit 500 b. As shown, a trench capacitor 502, which illustrates one implementation of the trench capacitor 402, extends continuously around two surfaces of an epitaxial substrate layer of the pixel circuit 500 a.FIG. 6A is a first example plan view of the pixels of FIG. 4 with separate deep trench capacitors on each of two walls of each pixel. FIG. 6A illustrates a pixel circuit 600 aand a pixel circuit 600 b. As illustrated for pixel circuit 600 a, a first trench capacitor 602 amay be formed on a first sidewall, while a second trench capacitor 602 bmay be formed on a second sidewall. Forming multiple capacitors 602 a, 602 bon separate sidewalls may increase the overall surface area of the sidewall structures 120 compared to the continuous trench capacitor 502 of FIG. 5.Moreover, as mentioned above and as also illustrated in FIG. 6A, within a single pixel, there may be differences in the intra-pixel capacitors while maintaining inter-pixel capacitor structures identical. For example, as shown, trench capacitor 602 amay be a partial depth trench capacitor (as in FIG. 2 ), while trench capacitor 602 bmay be a full depth trench capacitor (as in FIG. 1 ). Additionally or alternatively, it is possible that one trench capacitor (e.g., 602a) of a pixel circuit may include the sidewall recesses 120 of FIG. 1, while another trench capacitor (e.g., 602b) of the pixel circuit does not include the sidewall recesses.FIG. 6B is a second example plan view of the pixels of FIG. 4 with separate deep trench capacitors on each of two walls of each pixel. FIG. 6B illustrates a pixel circuit 601 aand a pixel circuit 601 b. As illustrated for the pixel circuit 601 a, the trench capacitor 603 amay be formed on a first sidewall, while the trench capacitors 603 band 603 cmay be formed on a second sidewall. Forming a plurality of trench capacitors 603 b, 603 con a sidewall may increase an overall surface area of the sidewall structures 120 compared to using a single trench capacitor per sidewall.FIG. 6B also illustrates that it is possible to include intra-pixel capacitor differences between capacitors on adjacent sidewalls while maintaining inter-pixel capacitor matching of an overall capacitor structure. That is, as shown, the adjacent sidewalls of the pixel circuit 601 aincludes the various trench capacitor structures 603 aand 603 b / 603 c, while an overall capacitor structure of the pixels 601 a, 601 bis the same.In accordance with FIG. 6A, other intra-pixel capacitor differences may also be implemented. For example, in FIG. 6B, intra-pixel capacitors may also be formed at different depths. For example, the trench capacitors 603 b, 603 cmay be formed at a depth less than or greater than the depth of the trench capacitor 603 a. Likewise, referring back to FIG. 6A, trench capacitor 602 amay be formed at a different (lesser or greater) depth than trench capacitor 602 b. More generally, any of the variations (or other variations) described herein may be used to form the types of trench capacitors having sidewall structures to form desired types of trench capacitors within a given pixel. For example, a given trench capacitor may be formed with multiple sets of recesses, each set having a different width 122 and / or depth 124 of recesses 120.For example, implementations with different intra-pixel capacitor depths may be advantageous in certain contexts, such as when designing global shutter pixel implementations. In such contexts, all sensor pixels are read simultaneously, and corresponding charge transfer requirements may benefit by having more / larger portions of the epitaxial substrate layer 116 intact. Thus, maintaining one or more of the trench capacitors in a pixel at a partial depth, possibly with one or more of the trench capacitors in the full depth pixel, may satisfy such charge transfer characteristics.FIGS. 7 through 14 illustrate example operations of an example process flow for fabricating the image sensors of FIGS. 1 through 6.In FIG. 7, an epitaxial substrate layer 716 is illustrated as having trenches 702 formed therein, the trenches 702 including sidewall recesses 720 along a length thereof, as shown. In FIG. 8, the trenches 702 are filled with insulating material 806. More specifically, for example, conformal SiO2deposition may be performed to form a uniform dielectric layer on the Si surface of the epitaxial substrate layer 716. In FIG. 9, by filling the trenches 702 with conductive material 904, trench capacitors 902 may be defined.Then, in FIG. 10, an ASIC chip 1002 having metal layers 1004 formed thereon may be mounted upside down, e.g., by hybrid bonding, to metal layers 1006 formed on the epitaxial substrate layer 716. As mentioned above with reference to FIGS. 1-3, vias 1014 may be used to connect trench capacitors 902 to metal layers 1006. The resulting structure including a bond line 1102 is illustrated in FIG. 11.For example, hybrid bonding may be used at the bond line 1102, which generally allows electrical connections to be formed while simultaneously forming a mechanically stable structure. Hybrid bond pads may be metal such as copper, nickel, gold, or other suitable metals known in the art. In other implementations, the hybrid bond pads may be of another non-metallic conductive material. Hybrid bonding may also be referred to as direct bond interconnect (DBI).In FIG. 12, in which the ASIC chip 1002 is not shown, the epitaxial substrate layer 716 of FIGS. 7 to 11 is thinned to obtain an epitaxial substrate layer 1216. In FIG. 13, a passivation layer 1318 is added along with an in-pixel metal grid 1302, e.g., an in-pixel grid of tungsten. In FIG. 14, a color filter 1408 and a microlens 1410 are added.FIG. 15 is a flow chart illustrating example operations for manufacturing the image sensors of FIGS. 1-6, which correspond to the example operations of FIGS. 7-14. In operation block 1502, as shown in FIG. 7 and described above, trenches having sidewall recesses may be formed in the epitaxial substrate layer of a first die. The first chip may be an image sensor chip. This may include using Bosch etching or other types of etching / masking to define trenches as described herein. In operation block 1504, a dielectric insulating layer may be deposited within the trenches as shown in FIG. 8 and described above. In operation block 1506, the trenches may be filled with conductive material to form capacitors or trench capacitors as shown in FIG. 9 and described above. In operation block 1508, as shown in FIGS. 10-11 and described above, a second die may be bonded to the first die. The second chip may be an ASIC chip or another type of chip configured to control elements on the first chip. The bond connection may be formed between the second die and metal layers on the epitaxial substrate layer of the first die, with vias connected to the trench capacitors. The metal layers and vias are formed in a step preceding this bonding step. In some implementations, the second chip is mounted upside down on the first chip. In operation block 1510, the epitaxial substrate layer may be thinned as shown in FIG. 12 and described above such that the epitaxial substrate layer has a predetermined thickness with a distance between a first surface and a second surface. The trench capacitors may extend through the entire thickness or only a portion of that thickness between the first and second surfaces of the epitaxial substrate layer. In operation block 1512, a passivation layer and an in-pixel grid as shown in FIG. 13 and described above may be added. The passivation layer and the in-pixel grid may be formed on a surface of the first chip opposite to the bonded second chip. In operation block 1514, a color filter and microlens array as shown in FIG. 14 and described above may be added.FIG. 16 is a graph illustrating examples of capacitance per pixel versus dielectric thickness for example embodiments. In FIG. 16, line 1602 indicates example results for a given trench depth for trenches with conventional straight walls. A line 1604 indicates example results for a given trench depth in the sidewall structures described herein. As shown, using the same insulating / conductive materials and for a given trench depth, the described techniques provide capacitance improvements over a range of dielectric thicknesses.FIG. 17 is a graph illustrating examples of capacitance per pixel versus trench depth for example embodiments. In FIG. 17, a line 1702 indicates example results for a given dielectric thickness for trenches with conventional straight walls. A line 1704 indicates example results for a given dielectric thickness in the sidewall structures described herein. As shown, the described techniques provide capacitance improvements over a range of trench depths using the same insulating / conductive materials and for a given dielectric thickness.The described techniques can thus be used to increase capacity per pixel, requiring minimal changes to existing pixel structures, and to enable multiple types of additional advantageous changes to existing pixel structures. For example, for a corrugation width 122 in FIG. 1 being "x", a resulting perimeter is π*x / 2=1.56x or about 56% increase in total perimeter (e.g., 9.36 μm instead of 6 μm). Using the described techniques, it is possible to achieve capacitances of 200 to 300 or more femtofarads per square micrometer, with corresponding capabilities of 120 to 140 dB in single exposure image acquisitions.Other implementations are also possible. For example, a total capacity of a pixel circuit may be further increased by the conductive material 104 extending not only along a second sidewall of the epitaxial substrate layer 116, but also along the top surface of the epitaxial substrate layer 116 itself. This creates additional surface area, by means of which a capacitor is formed, which enables an increased capacitance. When the conductive material 104 extends to the upper surface, use of a transparent electrode may be required to prevent photons passing through the microlens 110 and the color filter 108 from entering the photodetector portion of the pixel circuit 100.In a first example implementation, referred to herein as example 1, a semiconductor device comprises:a microlens;a color filter disposed adjacent to the micro lens;an epitaxial substrate layer disposed opposite the micro lens adjacent to the color filter; anda trench capacitor formed in the epitaxial substrate layer and having sidewall recesses.Example 2 includes the semiconductor device of example 1, wherein the trench capacitor extends through the entire thickness of the epitaxial substrate layer.Example 3 includes the semiconductor device of example 1, wherein the trench capacitor extends from a surface of the epitaxial substrate layer opposite the color filter and only partially through the epitaxial substrate layer.Example 4 includes the semiconductor device of example 1, wherein the trench capacitor extends from a surface of the epitaxial substrate layer adjacent to the color filter and only partially through the epitaxial substrate layer.Example 5 includes the semiconductor device of example 1, wherein the trench capacitor extends along two sidewalls of the epitaxial substrate layer.Example 6 includes the semiconductor device of example 1, wherein the trench capacitor is a first trench capacitor and is formed along a first sidewall of the epitaxial substrate layer, and the semiconductor device further comprises:a second trench capacitor formed along a second sidewall of the epitaxial substrate layer.Example 7 includes the semiconductor device of example 6, wherein the sidewall recesses of the first trench capacitor are first sidewall recesses and the second trench capacitor includes second sidewall recesses in the second sidewall.Example 8 includes the semiconductor device of example 6, wherein the first trench capacitor is formed to a first depth within the epitaxial substrate layer and the second trench capacitor is formed to a second depth within the epitaxial substrate layer that is different than the first depth.Example 9 includes the semiconductor device of example 1, wherein the trench capacitor is a first trench capacitor and is formed along a sidewall of the epitaxial substrate layer, and the semiconductor device further comprises:a second trench capacitor formed along the sidewall of the epitaxial substrate layer.Example 10 includes the semiconductor device of example 9, wherein the trench capacitor is formed to a first depth within the epitaxial substrate layer and the second trench capacitor is formed to a second depth within the epitaxial substrate layer that is different than the first depth.In an eleventh example implementation, referred to herein as example 11, an optical sensor includes an array of pixel circuits, each pixel circuit comprising:a microlens;a color filter disposed adjacent to the micro lens;an epitaxial substrate layer disposed opposite the micro lens adjacent to the color filter; andan isolation trench formed in the epitaxial substrate layer and having sidewalls with sidewall recesses formed therein, the sidewall recesses having insulating material disposed thereon, and the isolation trench having a conductive material disposed therein.Example 12 includes the optical sensor of claim 11, wherein the isolation trench extends only partially through the epitaxial substrate layer in a direction perpendicular to the color filter.Example 13 includes the optical sensor of example 11, wherein the isolation trench extends along two sidewalls of the epitaxial substrate layer.Example 14 includes the optical sensor of example 11, wherein the isolation trench is a first isolation trench and is formed along a first sidewall of the epitaxial substrate layer, and the optical sensor further comprises:a second isolation trench formed along a second sidewall of the epitaxial substrate layer.Example 15 includes the optical sensor of example 14, wherein the first isolation trench is formed to a first depth within the epitaxial substrate layer and the second isolation trench is formed to a second depth within the epitaxial substrate layer that is different than the first depth.Example 16 includes the optical sensor of example 11, wherein the isolation trench is a first isolation trench and is formed along a sidewall of the epitaxial substrate layer, and the optical sensor further comprises:a second isolation trench formed along the sidewall of the epitaxial substrate layer.In a seventeenth example implementation, referred to herein as example 17, a method of fabricating a pixel circuit of an optical sensor comprises:forming a trench in an epitaxial substrate layer, the trench having sidewall recesses;providing an insulating material in the sidewall recesses;providing a conductive material in the trench adjacent to the insulating material;providing a color filter adjacent a surface of the epitaxial substrate layer; andforming a microlens adjacent to the color filter.Example 18 includes the method of Example 17, further comprising:forming the trench using a Bosch etching process.Example 19 includes the method of Example 17, further comprising:forming the trench along a first sidewall of the epitaxial substrate layer; andforming a second trench along a second sidewall of the epitaxial substrate layer.Example 20 includes the method of Example 19, further comprising:forming the trench to a first depth within the epitaxial substrate layer; andforming the second trench to a second depth within the epitaxial substrate layer different from the first depth.It will be understood that in the foregoing description, when an element such as a layer, region, substrate, or component is referred to as being on another element, connected, electrically connected, coupled, or electrically coupled thereto, it may be directly on, connected, or coupled to the other element, or one or more intervening elements may be present. In contrast, there are no intervening elements or layers when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer. Although the terms "directly on", "directly connected to", or "directly coupled to" may not be used in the detailed description, elements shown as "directly on", "directly connected", or "directly coupled" may be referred to as such. The claims of the application may be changed as appropriate to indicate example relationships described in the specification or shown in the figures.As used in the specification and claims, a singular form may include a plural form unless a particular case with respect to context is clearly indicated. Spatially relative terms (e.g., above, above, upper / upper / upper, below, below, below, lower / lower / lower, and the like) are intended to include various orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms "above" and "below" may include "vertically above" and "vertically below", respectively. In some implementations, the term "adjacent" may include "laterally adjacent to" or "horizontally adjacent to.".Some implementations may be implemented using various semiconductor processing and / or packaging techniques. Some embodiments may be implemented using various types of semiconductor processing techniques in conjunction with semiconductor substrates, including, but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and / or the like.While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now be apparent to those skilled in the art. It is therefore to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of implementations. It is to be understood that they have been presented by way of example only, and not limitation, and that various changes in form and details may be made. Each portion of the apparatus and / or method described herein may be combined in any combination, except for mutually exclusive combinations. The implementations described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the various implementations described.While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now be apparent to those skilled in the art. It is therefore to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the embodiments.

Claims

A semiconductor device comprising: a micro lens; a color filter disposed adjacent to the micro lens; an epitaxial substrate layer disposed adjacent to the color filter opposite to the micro lens; and a trench capacitor formed in the epitaxial substrate layer and having sidewall recesses.The semiconductor device of claim 1, wherein the trench capacitor extends through an entire thickness of the epitaxial substrate layer.The semiconductor device of claim 1, wherein the trench capacitor extends from a surface of the epitaxial substrate layer opposite the color filter and only partially through the epitaxial substrate layer.The semiconductor device of claim 1, wherein the trench capacitor extends from a surface of the epitaxial substrate layer adjacent to the color filter and only partially through the epitaxial substrate layer.The semiconductor device of claim 1, wherein the trench capacitor extends along two sidewalls of the epitaxial substrate layer.The semiconductor device of claim 1, wherein the trench capacitor is a first trench capacitor and is formed along a first sidewall of the epitaxial substrate layer, and the semiconductor device further comprises: a second trench capacitor formed along a second sidewall of the epitaxial substrate layer.The semiconductor device of claim 6, wherein the sidewall recesses of the first trench capacitor are first sidewall recesses and the second trench capacitor includes second sidewall recesses in the second sidewall.The semiconductor device of claim 6, wherein the first trench capacitor is formed at a first depth within the epitaxial substrate layer and the second trench capacitor is formed at a second depth within the epitaxial substrate layer different from the first depth.The semiconductor device of claim 1, wherein the trench capacitor is a first trench capacitor and is formed along a sidewall of the epitaxial substrate layer, and the semiconductor device further comprises: a second trench capacitor formed along the sidewall of the epitaxial substrate layer.The semiconductor device of claim 9, wherein the trench capacitor is formed at a first depth within the epitaxial substrate layer and the second trench capacitor is formed at a second depth within the epitaxial substrate layer that is different than the first depth.An optical sensor including an array of pixel circuits, each pixel circuit comprising: a micro lens; a color filter disposed adjacent to the micro lens; an epitaxial substrate layer disposed adjacent to the color filter opposite the micro lens; and an isolation trench formed in the epitaxial substrate layer and having sidewalls with sidewall recesses formed therein, the sidewall recesses having insulating material disposed thereon, and the isolation trench having a conductive material disposed therein.The optical sensor of claim 11, wherein the isolation trench extends only partially through the epitaxial substrate layer in a direction perpendicular to the color filter.The optical sensor of claim 11, wherein the isolation trench extends along two sidewalls of the epitaxial substrate layer.The optical sensor of claim 11, wherein the isolation trench is a first isolation trench and is formed along a first sidewall of the epitaxial substrate layer, and the optical sensor further comprises: a second isolation trench formed along a second sidewall of the epitaxial substrate layer.The optical sensor of claim 14, wherein the first isolation trench is formed at a first depth within the epitaxial substrate layer and the second isolation trench is formed at a second depth within the epitaxial substrate layer that is different than the first depth.The optical sensor of claim 11, wherein the isolation trench is a first isolation trench and is formed along a sidewall of the epitaxial substrate layer, and the optical sensor further comprises: a second isolation trench formed along the sidewall of the epitaxial substrate layer.A method of manufacturing a pixel circuit of an optical sensor, comprising: forming a trench in an epitaxial substrate layer, the trench having sidewall recesses; providing an insulating material in the sidewall recesses; providing a conductive material in the trench adjacent to the insulating material; providing a color filter adjacent to a surface of the epitaxial substrate layer; and forming a microlens adjacent to the color filter.The method of claim 17, further comprising: forming the trench using a Bosch etching process.The method of claim 17, further comprising: forming the trench along a first sidewall of the epitaxial substrate layer; and forming a second trench along a second sidewall of the epitaxial substrate layer.The method of claim 19, further comprising: forming the trench to a first depth within the epitaxial substrate layer; and forming the second trench to a second depth within the epitaxial substrate layer different from the first depth.

Images