Semiconductor device structure and method for manufacturing the same

Abstract

A semiconductor device structure and methods for fabricating the same are described. The method comprises the following steps: forming a fin structure from a substrate; depositing a first semiconductor material on a first semiconductor layer of the fin structure; depositing a second semiconductor material on the first semiconductor material; depositing an interlayer dielectric layer over the second semiconductor material; forming an opening in the interlayer dielectric layer to expose the second semiconductor material; performing a first implantation process to form an amorphous region in the second semiconductor material and to implant a first species into the amorphous region; and performing a second implantation process to implant a second species into the amorphous region. The second species comprises fluorine, nitrogen, or carbon.The method further comprises performing an annealing process to recrystallize the amorphous region.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 600,058, filed November 17, 2023, which is incorporated by reference into the present application. BACKGROUND

[0002] The IC (semiconductor integrated circuit) industry has experienced exponential growth. Technological advances in IC materials and designs have spawned generations of ICs, with each generation having smaller and more complex circuits than the previous generation. Over the course of IC evolution, feature density (i.e., the number of interconnected devices per chip area) has generally increased, while feature size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This process of downsizing generally offers advantages by increasing production output and reducing associated costs. However, this downsizing has also increased the complexity of IC processing and manufacturing.

[0003] Therefore, there is a need to improve the processing and manufacturing of ICs. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure can best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for the sake of clarity of illustration. The Fig. 1-5 are perspective views of various stages of fabricating a semiconductor device structure according to some embodiments. The Fig. 6 - 20 are side sectional views of various stages of fabrication of the semiconductor device structure taken along line AA in Fig. 5, according to some embodiments. DETAILED DESCRIPTION

[0005] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0006] In addition, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0007] Various embodiments described below generally relate to implanting a species into a source / drain region to delay diffusion of another species from the source / drain region into a channel region. Diffusion of the species from the source / drain region to the channel region may cause Ge out-diffusion from an adjacent semiconductor layer into the channel region, which may adversely affect yield conduction.

[0008] While the embodiments of this disclosure are discussed with respect to nanostructure channel field-effect transistor (FET), such as gate-all-around (GAA) FETs, for example, horizontal gate-all-around (HGAA) FETs or vertical gate-all-around (VGAA) FETs, implementations of some aspects of the present disclosure may also be used in other processes and / or in other devices, such as planar FETs, fin FETs, and other suitable devices. One of ordinary skill in the art should readily recognize modifications that may be made without departing from the intended scope of this disclosure. In cases where gate-all-around (GAA) transistor structures are applied, the GAA transistor structures may be patterned using any suitable method.For example, the structures may be patterned using one or more photolithographic processes, such as double-patterning or multi-patterning processes. In general, double-patterning or multi-patterning processes combine photolithographic and self-aligned processes, which can create structures that, for example, have pitches smaller than those otherwise achievable with a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate, which is then patterned using a photolithographic process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0009] The Fig. 1-20 illustrate exemplary processes for fabricating a semiconductor device structure 100 according to embodiments of the present disclosure. It is understood that further operations may be performed before, during, and after processes described in the Fig. 1-20, and that some of the operations described below may be replaced or omitted in further embodiments of the method. The order of the operations / processes is not restrictive and may be interchanged.

[0010] The Fig. 1-5 are perspective views of various stages of fabricating a semiconductor device structure 100 according to some embodiments. As in Fig. 1, a semiconductor device structure 100 includes a stack of semiconductor layers 104 fabricated over a front surface of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include a crystalline semiconductor material, such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb), and indium phosphide (InP). In some embodiments, substrate 101 is a silicon-on-insulator (SOI) substrate with an insulating layer (not shown) sandwiched between two silicon layers for reinforcement. In one aspect, the insulating layer is an oxygen-containing layer.

[0011] The substrate 101 may have different regions doped with different dopants (e.g., dopants with p- or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for an n-type field-effect transistor (NFET) and boron for a p-type field-effect transistor (PFET).

[0012] The stack of semiconductor layers 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels in a multi-gate device, such as nanostructured channel FETs. In some embodiments, the stack of semiconductor layers 104 includes first semiconductor layers 106 and second semiconductor layers 108. In some embodiments, the stack of semiconductor layers 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layers 106 and the second semiconductor layers 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layers 106 may be made of Si, and the second semiconductor layers 108 may be made of SiGe.In some examples, the first semiconductor layers 106 may be made of SiGe, and the second semiconductor layers 108 may be made of Si. Alternatively, in some embodiments, each of the two semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GaAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or combinations thereof.

[0013] The first semiconductor layers 106 and the second semiconductor layers 108 are formed using a suitable deposition process, such as epitaxy. For example, the epitaxial growth of the layers of the stack of semiconductor layers 104 can be performed using a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0014] The first semiconductor layers 106 or parts thereof may form one or more nanostructure channels of the semiconductor device structure 100 in later manufacturing stages. The term nanostructure is used in this disclosure to refer to a material part with dimensions on the nanoscale or even microscale and with an elongated shape, regardless of the shape of the cross-section of this part. Consequently, the term refers to both elongated material parts with a round and substantially round cross-section and bar- or rod-shaped material parts with, for example, a cylindrical or substantially rectangular cross-section. The one or more nanostructure channels of the semiconductor device structure 100 may be enclosed by a gate electrode. The semiconductor device structure 100 may comprise a nanostructure transistor.The nanostructure transistors may be referred to as nanolayer transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or transistors with a gate electrode surrounding the channels. The use of the first semiconductor layers 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0015] Each first semiconductor layer 106 may have a thickness in a range between about 5 nm and about 30 nm. Each second semiconductor layer 108 may have a thickness equal to, or less than, the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness in a range between about 2 nm and about 50 nm. Three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately, as shown in Fig. 1; however, this is for illustrative purposes only and is not intended to limit the present disclosure beyond what is explicitly set forth in the claims. It should be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the stack of semiconductor layers 104, and the number of layers depends on the number of channels specified for the semiconductor device structure 100. In some embodiments, the stack of semiconductor layers 104 comprises two first semiconductor layers 106. In some embodiments, the stack of semiconductor layers 104 comprises three first semiconductor layers 106. In some embodiments, the stack of semiconductor layers 104 comprises four first semiconductor layers 106.

[0016] As in Fig. 2, fin structures 112 are formed from the stack of semiconductor layers 104. Each of the fin structures 112 has a top portion including the semiconductor layers 106, 108 and a well portion 116 formed from the substrate 101. The fin structures 112 may be formed using multiple patterning operations including photolithography and etching processes by patterning a hard mask layer (not shown) formed on the stack of semiconductor layers 104. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.The photolithographic process may include the steps of forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to a pattern, performing post-exposure curing processes, and developing the photoresist layer to form a masking element comprising the photoresist layer. In some embodiments, patterning to form the masking element may be performed using an electron beam (e-beam) lithographic process. The etching process creates trenches 114 in unprotected areas through the hard mask layer, through the stack of semiconductor layers 104, and into the substrate 101, leaving the plurality of extending fin structures 112. The trenches 114 extend along the x-direction. The trenches 114 may be formed using a dry etch (e.g.,RIE), wet etching and / or a combination thereof.

[0017] As in Fig. As shown in Figure 3, after the fin structures 112 are formed, an insulating material 118 is formed on the substrate 101. The insulating material 118 is used to fill the trenches 114 between adjacent fin structures 112 until the fin structures 112 are embedded in the insulating material 118. A planarization operation, such as a chemical mechanical polishing (CMP) process and / or an etch-back process, is then performed to expose the top surface of the fin structures 112. The insulating material 118 may be formed from silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-k dielectric material, or another suitable dielectric material.The insulating material 118 may be deposited using any suitable process, such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or flowable CVD (FCVD).

[0018] As in Fig. 4, the insulating material 118 is recessed to form isolation regions 120. By recessing the insulating material 118, parts of the fin structures 112, such as the stack of semiconductor layers 104, are exposed. By recessing the insulating material 118, the trenches 114 between the adjacent fin structures 112 are revealed. The isolation regions 120 may be formed using any suitable process, such as a dry etching process, a wet etching process, or a combination thereof. A top surface of the insulating material 118 may be level with or below a surface of the second semiconductor layers 108 that is in contact with the well portion 116 formed from the substrate 101. In some embodiments, the isolation regions 120 are shallow trench isolation (STI) regions.

[0019] As in Fig. 5, one or more sacrificial gate structures 130 (only one is shown) are formed over the semiconductor device structure 100. The sacrificial gate structures 130 are formed over a portion of the fin structures 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 are formed by sequentially depositing unpatterned layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 and then patterning these layers into the sacrificial gate structures 130. While only one sacrificial gate structure 130 is shown, in some embodiments, two or more sacrificial gate structures 130 may be arranged along the x-direction.

[0020] The sacrificial gate dielectric layer 132 may comprise one or more layers of dielectric material, such as a silicon oxide-based material. The sacrificial gate electrode layer 134 may comprise silicon, such as polycrystalline silicon or amorphous silicon. The mask layer 136 may comprise more than one layer, such as an oxide layer and a nitride layer. The portions of the fin structures 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serve as channel regions for the semiconductor device structure 100.

[0021] The Fig. 6-20 are side sectional views of various stages of fabrication of the semiconductor device structure 100 taken along line AA of Fig. 5, according to some embodiments. As in Fig. 6, a first gate spacer 138 is deposited on the exposed surfaces of the semiconductor device structure 100. For example, the first gate spacer 138 is deposited on the fin structures 112, the isolation regions 120, and the sacrificial gate structure 130. The first gate spacer 138 may be formed from a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxide carbide, SiCON, and / or combinations thereof. The first gate spacer 138 may be formed using any suitable process. In some embodiments, the first gate spacer 138 is a conformal layer formed using a conformal process, such as an atomic layer deposition (ALD) process.

[0022] As in Fig. 7, a second gate spacer 139 is deposited on the first gate spacer 138. The second gate spacer 139 may be any suitable dielectric material, such as SiO x , SiON, SiN, SiCON, or SiCO. The second gate spacer 139 may have a thickness in a range of about 0.5 nm to about 5 nm. The second gate spacer 139 may be formed using any suitable process. In some embodiments, the second gate spacer 139 is deposited using CVD, PECVD, or electron cyclotron resonance CVD (ECR-CVD) (ECT-CVD).

[0023] As in Fig. 8, horizontal portions of the first gate spacer 138 and the second gate spacer 139 are removed. In some embodiments, the horizontal portions of the first gate spacer 138 and the second gate spacer 139 are removed using an anisotropic etch process. The anisotropic etch process may be a selective etch process that leaves the mask layer 136, the stack of semiconductor layers 104, and the isolation regions 120 substantially untouched.

[0024] As in Fig. 9, the parts of the fin structures 112 that are not covered by the sacrificial gate structure 130 and the first gate spacer 138 and the second gate spacer 139 are recessed to a height that corresponds to the height of the top surfaces of the isolation regions 120 or is above or below this height. The recessing of the parts of the fin structures 112 may be performed using an etching process. The etching process may be a dry etch, such as RIE, NBE, or the like, or a wet etch, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH) or other suitable etchant. The well portions 116 are exposed on opposite sides of the sacrificial gate structure 130, as shown in Fig. 9 is shown.

[0025] As in Fig. As shown in FIG. 10, edge portions of every second semiconductor layer 108 of the stack of semiconductor layers 104 are removed horizontally along the x-direction. By removing the edge portions of the second semiconductor layers 108, voids are formed. In some embodiments, the edge portions of the second semiconductor layers 108 are removed with a selective wet etching process. In cases where the second semiconductor layers 108 are made of SiGe and the first semiconductor layers 106 are made of silicon, the second semiconductor layer 108 can be selectively etched with a wet etchant such as, among others, ammonium hydroxide- (NH 4 OH), tetramethylammonium hydroxide- (TMAH-), ethylenediamine-pyrocatechol- (EDP-), or potassium hydroxide- (KOH-) solution.

[0026] After removing the edge portions of every second semiconductor layer 108, a dielectric layer is deposited in the cavities to form dielectric spacers 144. The dielectric spacers 144 can be made of a dielectric low-k material such as SiON, SiCN, SiOC, SiOCN or SiN. The dielectric spacers 144 can be formed by first depositing a conformal dielectric layer using a conformal deposition process such as ALD and then performing an anisotropic etching process to remove portions of the conformal dielectric layer except for the dielectric spacers 144. The dielectric spacers 144 are protected by the first semiconductor layers 106 during the anisotropic etching process. The remaining second semiconductor layers 108 are capped between the dielectric spacers 144 along the x-direction.

[0027] As in Fig. 11, a first semiconductor material 150 is formed on the exposed well portions 116. In some embodiments, the first semiconductor material 150 comprises undoped silicon or undoped SiGe. The first semiconductor material 150 may first be formed on semiconductor surfaces, such as on the exposed well portions 116 and on the first semiconductor layers 106, using an epitaxial process. Subsequently, an etching process is performed to remove the portions of the first semiconductor material 150 formed on the first semiconductor layers 106. The first semiconductor material 150 formed on the exposed well portions 116 may form a concave top surface as a result of the etching process. In some embodiments, the first semiconductor material 150 has a thickness along the z-direction in a range of about 5 nm to about 50 nm.

[0028] Then, as in Fig. 12, a dielectric layer 152 may be formed on the first semiconductor material 150. The dielectric layer 152 may be formed by first forming a dielectric layer on the exposed surfaces of the semiconductor device structure 100 and then performing one or more etching processes to remove portions of the dielectric layer except for the dielectric layer 152. A mask layer (not shown), such as a bottom antireflective coating (BARC) layer, may be used to assist in removing the portions of the dielectric layer. The dielectric layer 152 may comprise any suitable dielectric material. In some embodiments, the dielectric layer 152 comprises SiN. The dielectric layer 152 may be formed using any suitable process.In some embodiments, the dielectric layer 152 is formed using CVD. Then, a second semiconductor material 154 is formed from the first semiconductor layers 106. The second semiconductor material 154 may be formed from one or more layers of Si, SiP, SiC, SiAs, SiSb, and SiCP for n-channel FETs, or Si, SiGe, or Ge for p-channel FETs. For p-channel FETs, p-type dopants, such as boron (B), may be incorporated into the second semiconductor material 154. For n-channel FETs, n-type dopants, such as phosphorus (P) or arsenic (As), may be incorporated into the second semiconductor material 154. In some embodiments, the doping concentration of the second semiconductor material 154 may be in a range of about 1 × 10 19 cm -3 up to about 2 × 10 21 cm -3 The second semiconductor material 154 can be formed by an epitaxial growth process using CVD, ALD, or MBE. As shown in Fig. 12, in some embodiments, the second semiconductor material 154 is selectively formed on semiconductor materials, such as the first semiconductor layers 106, and is not formed on dielectric materials, such as the dielectric layer 152 and the dielectric spacers 144. In some embodiments, the second semiconductor material 154 has facets that may correspond to crystalline planes of the material used for the first semiconductor layers 106.

[0029] Then, as in Fig. 12, a third semiconductor material 156 is formed from the second semiconductor material 154. The third semiconductor material 156 may be formed using an epitaxial growth process using CVD, ALD, or MBE. The third semiconductor material 156 may be formed from one or more layers of Si, SiP, SiC, and SiCP for n-FETs, or Si, SiGe, or Ge for p-FETs. For p-FETs, p-dopants such as boron (B) may be incorporated into the second semiconductor material 154. For n-FETs, n-dopants such as phosphorus (P) or arsenic (As) may be incorporated into the third semiconductor material 156. In some embodiments, the second semiconductor material 154 and the third semiconductor material 156 may comprise the same semiconductor materials but with different doping concentrations. The doping concentration of the third semiconductor material 156 may be substantially greater than the doping concentration of the second semiconductor material 154.In some embodiments, the doping concentration of the third semiconductor material 156 may be in a range of about 5 × 10 . 19 cm -3 up to about 4 × 10 21 cm -3 The third semiconductor material 156 may be grown epitaxially from the second semiconductor material 154. The quality of the third semiconductor material 156 may be enhanced by the facets of the second semiconductor material 154. In some embodiments, the dielectric layer 152 is not present, and the third semiconductor material 156 is grown from the first semiconductor material 150 and the second semiconductor material 154.

[0030] In some embodiments, a capping layer (not shown) may be formed on the third semiconductor material 156. The capping layer may comprise a semiconductor material. In some embodiments, the capping layer comprises the same material as the third semiconductor material. The capping layer may be grown epitaxially from the third semiconductor material 156.

[0031] In some embodiments, the second semiconductor material 154 and the third semiconductor material 156 may be doped in situ during growth. If the doping concentrations of the second semiconductor material 154 and the third semiconductor material 156 are greater than the respective ranges mentioned above, this may negatively impact the quality of the second semiconductor material 154 and the third semiconductor material 156. Consequently, subsequent processes may be performed to increase the doping concentration and / or the activation of dopants to reduce the electrical contact resistance.

[0032] The second semiconductor material 154 and the third semiconductor material 156 together may be the source / drain (S / D) region. In this disclosure, a source region and a drain region are used interchangeably, and their structures are substantially the same. Furthermore, the one or more source / drain regions may refer individually or collectively to a source or a drain, depending on the context. In some embodiments, pS / D regions and nS / D regions may be formed separately using one or more mask layers. In some embodiments, the second semiconductor material 154 and the third semiconductor material 156 are crystalline semiconductor materials.

[0033] Then, as in Fig. 12, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surfaces of the semiconductor device structure 100. The CESL 162 covers the second gate spacer 139, the isolation regions 120, and the third semiconductor material 156 (or the capping layer, if present). The CESL 162 may comprise an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or the like, or a combination thereof, and may be formed using CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, the CESL 162 is a single layer, as shown in Fig. 12. In some embodiments, the CESL 162 comprises two or more layers. Then, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162. The materials for the ILD layer 164 may include compounds with Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials, such as polymers, may also be used for the ILD layer 164. The ILD layer 164 may be formed using a PECVD process or other suitable deposition technique. In some embodiments, after the ILD layer 164 is formed, the semiconductor device structure 100 may be subjected to a thermal process to anneal the ILD layer 164.

[0034] After forming the ILD layer 164, a planarization operation, such as a CMP, is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed, as shown in Fig. 12 is shown.

[0035] Then, as in Fig. 13, the sacrificial gate structure 130 and the second semiconductor layers 108 are removed. By removing the sacrificial gate structure 130 and the semiconductor layers 108, an opening is formed between the first gate spacers 138 and between the first semiconductor layers 106. The ILD layer 164 protects the second semiconductor material 156 during the removal process. The sacrificial gate structure 130 may be removed using a plasma dry etch and / or a wet etch. The sacrificial gate electrode layer 134 may first be removed using any suitable process, such as dry etching, wet etching, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer 132, which may also be performed using any suitable process, such as dry etching, wet etching, or a combination thereof.In some embodiments, a wet etchant, such as a tetramethylammonium hydroxide (TMAH) solution, may be used to selectively remove the sacrificial gate electrode layer 134 without removing the first gate spacers 138, the ILD layer 164, and the CESL 162.

[0036] The second semiconductor layers 108 may be removed using a selective wet etching process. In cases where the second semiconductor layers 108 are made of SiGe and the first semiconductor layers 106 are made of Si, the chemicals used in the selective wet etching process remove the SiGe, while Si, the dielectric materials of the first gate spacers 138, and the dielectric spacers 144 remain substantially untouched. In one embodiment, the second semiconductor layers 108 may be removed using a wet etchant, such as, but not limited to, hydrogen fluoride (HF), nitric acid (HNO 3), hydrochloric acid (HCl) or phosphoric acid (H 3 PO 4 ) must be removed.

[0037] As in Fig. 14, after the nanostructure channels (i.e., the exposed portions of the first semiconductor layers 106) are formed, a gate dielectric layer 170 is formed to enclose the exposed portions of the first semiconductor layers 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as a gate structure 174. In some embodiments, an interfacial layer (IL) (not shown) is formed between the gate dielectric layer 170 and the exposed surfaces of the first semiconductor layers 106, and one or more work function layers (not shown) are formed between the gate dielectric layer 170 and the gate electrode layer 172.In some embodiments, the gate dielectric layer 170 comprises one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, another suitable dielectric material, and / or combinations thereof. Examples of high-k dielectric materials include HfO. 2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titania, hafnia-alumina alloy (HfO 2 -Al 2 O 3alloy), other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 may be formed using CVD, ALD, or any suitable deposition method. The work function layer may comprise polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, or other suitable materials. The gate electrode layer 172 may comprise one or more layers of conductive material, such as platinum (Pt), palladium (Pd), tantalum (Ta), ytterbium (Yb), aluminum (Al), silver (Ag), titanium (Ti), ruthenium (Ru), molybdenum (Mo), chromium (Cr), tungsten (W), copper (Cu), or a similar material, and / or combinations thereof. The gate electrode layer 172 may be formed using CVD, ALD, electroplating, or another suitable deposition method.The gate electrode layer 172 may also be deposited over the top surface of the ILD layer 164. The gate dielectric layer 170 and the gate electrode layer 172, which were formed over the ILD layer 164, are then removed, for example, using CMP, until the top surface of the ILD layer 164 is exposed.

[0038] It should be understood that the semiconductor device structure 100 may be subjected to further processes, such as a cut metal gate (CMG) process and / or a continuous poly on diffusion edge (CPODE) process. The CMG process separates the gate electrode layer 172 into multiple segments that can be individually controlled. The CPODE process creates isolation between devices.

[0039] As in Fig. As shown in Figure 15, an etch stop layer 166 and a second ILD layer 168 are formed over the ILD layer 164 and the gate electrode layer 172. The etch stop layer 166 may comprise the same material as the CESL 162 and may be formed using the same process as the CESL 162. The second ILD layer 168 may comprise the same material as the ILD layer 164 and may be formed using the same process as the ILD layer 164.

[0040] Then, as in Fig. 16, openings 180 may be formed in the second ILD layer 168, the etch stop layer 166, the ILD layer 164, and the CESL 162 to expose the third semiconductor material 156. In some embodiments, portions of the ILD layer 164 and the CESL 162 that are above the third semiconductor material 156 may be removed. In some embodiments, the capping layer (not shown) and a portion of the third semiconductor material 156 may also be removed. The openings 180 may be formed using an etching process, such as a dry etching process, a wet etching process, or a combination thereof. A patterned mask (not shown) may be formed over the second ILD layer 168, and the pattern of the patterned mask is transferred to the second ILD layer 168, the etch stop layer 166, the ILD layer 164, and the CESL 162.

[0041] As in Fig. 16, the semiconductor device structure 100 includes an IL 167 formed on the first semiconductor layers 106 and a work function layer 169 formed between the gate dielectric layer 170 and the gate electrode layer 172. Furthermore, the semiconductor device structure 100 includes a dielectric coating 196 and a dielectric material 198. The dielectric coating 196 and the dielectric material 198 may be an isolation structure formed using a CPODE process. In some embodiments, the dielectric material 198 comprises the same material as the etch stop layer 166.

[0042] As in Fig. 17, a coating 184 is formed on the vertical surfaces of the second ILD layer 168, the etch stop layer 166, and the first gate spacers 138. The coating 184 may comprise any suitable material. In some embodiments, the coating 184 is a nitride layer, such as a silicon nitride layer. In some embodiments, the coating 184 comprises the same material as the etch stop layer 166. The coating 184 may be formed by first forming a dielectric layer on the exposed surfaces of the semiconductor device structure 100 and subsequently performing an anisotropic etch process to remove portions of the dielectric layer formed on horizontal surfaces of the semiconductor device structure 100.For example, portions of the dielectric layer formed on the second ILD layer 168 and the third semiconductor material 156 are removed using an anisotropic etching process. The overlay 184 protects the second ILD layer 168 during subsequent processes.

[0043] In some embodiments, to reduce the electrical contact resistance, one or more processes may be performed to increase the doping concentration and / or the activation of dopants in the third semiconductor material 156 and / or the second semiconductor material 154. In some embodiments, an amorphization process and an annealing process are performed. In some embodiments, portions of the second semiconductor material 154 and the third semiconductor material 156 that are crystalline semiconductor materials are amorphized with the amorphization process. For example, a first species may be injected into the second semiconductor material 154 and the third semiconductor material 156 to create an amorphous region 186, as shown in Fig. 18. In some embodiments, the amorphous region 186 extends to a height between the topmost first semiconductor layer 106 and the adjacent first semiconductor layer 106 below the topmost first semiconductor layer 106.

[0044] In some embodiments, the amorphization process is an ion implantation process that incorporates the first species into the second semiconductor material 154 and the third semiconductor material 156 such that at least an upper portion of the third semiconductor material 156 and portions of the second semiconductor material 154 that are in contact with the uppermost first semiconductor layers 106 are converted into an amorphous structure (i.e., the amorphous region 186). The first species of the ion implantation process may be a Group IV element, such as C, Si, Ge; a Group III element, such as B, Al, Ga, In; a Group V element, such as P, As, Sb; or a Group VIII element, such as He, Ar, Xe. The implantation process may use an implantation energy in a range of about 0.3 keV to about 60 keV, a dosage of more than about 1 × 10 13 cm -2and a processing temperature in a range of about -150 degrees Celsius to about 500 degrees Celsius. In some embodiments, the projected range Rp of the first species is about 4 nm to about 5 nm, and the depth of the amorphous region 186 is about 5 nm to about 10 nm. In some embodiments, a bottom surface of the amorphous region 186 is located at a height between the topmost first semiconductor layer 106 and the first semiconductor layer 106 that is below the topmost first semiconductor layer 106. In some embodiments, the first species in the amorphous region 186 has a concentration gradient. As in Fig. 18, the amorphous region 186 comprises a first subregion 186a having a concentration of the first species of about 5 × 10 20 cm -3 , a second subregion 186b with a concentration of the first species of about 1 × 10 20 cm -3and a third subregion 186c with a concentration of the first species of about 1 × 10 19 cm -3 .

[0045] In some embodiments, the S / D region is an nS / D region, and the second semiconductor material 154 and the third semiconductor material 156 comprise SiP. The first species of the ion implantation process comprises phosphorus (P). With the higher concentration of P, the contact resistance of the S / D region can be reduced. However, during the subsequent annealing process, the first species can diffuse into the adjacent first semiconductor layer 106. In some embodiments, the first species can diffuse into the interface between the first semiconductor layer 106 and the dielectric spacer 144 and into the interface between the first semiconductor layer 106 and the first gate spacer 138. In some embodiments, the first species comprises phosphorus (P), and the phosphorus diffusion is based on phosphorus-vacancy (PV) pairs.The first species in the above-mentioned interfaces may cause the germanium (Ge) in the second semiconductor layer 108 to diffuse into the first semiconductor layer 106, thereby degrading the yield.

[0046] To delay the diffusion of the first species, a second species is incorporated into the amorphous region 186. In some embodiments, the second species is incorporated using a second ion implantation process. The second species comprises fluorine (F), carbon (C), or nitrogen (N). In some embodiments, the second species comprises F. Vacancies are introduced into the amorphous region 186 as F 3 V-clusters and act together with interstitial F i , as in equation F 3 V + I ←→ 3 F iAs a result, the diffusion of the first species is reduced during the subsequent annealing process by eliminating the vacancy and interstitial atom. This allows the PV pairs to be eliminated, resulting in delayed phosphorus diffusion during the subsequent annealing process. In some embodiments, the second ion implantation process implants the second species to a depth of about 5 nm to about 8 nm into the amorphous region 186, where a vacancy-rich region is located.

[0047] The second implantation process may have an implantation energy in a range of about 1 keV to about 2 keV, a dosage in a range of about 5 × 10 14 cm- 2 up to about 1 × 10 15 cm -2, a processing temperature in a range of about -60 degrees Celsius to about 450 degrees Celsius and an implantation angle with an inclination in a range of about 0 degrees to about 15 degrees and a rotation in a range of about 0 degrees to about 360 degrees. The concentration of the second species in the amorphous region 186 is between about 5 × 10 20 cm -3 and about 1 × 10 21 cm -3In some embodiments, the second species has an Rp that is greater than the Rp of the first species. The Rp of the second species may range from about 5 nm to about 7 nm. In some embodiments, the Rp of the second species is at least 1.3 nm deeper than the Rp of the first species. This makes the retardation of the diffusion of the first species more effective because the interaction region is about 5 nm to about 10 nm (FV cluster formation). The depth of the region with the second species may be shallower than the depth of the amorphous region 186. In some embodiments, the amorphous region 186 may prevent the later implanted second species from channeling through the interstices between the crystal lattice structure and penetrating to greater depths than desired.

[0048] In some embodiments, a third ion implantation process is performed to implant a third species into the amorphous region 186. The third species comprises fluorine (F), carbon (C), and / or nitrogen (N) and is different from the second species. The third ion implantation process may have the same process conditions as the second implantation process. By introducing the third species, the diffusion of the first species into the first semiconductor layers 106 may be further delayed. The third ion implantation process may be optional.

[0049] In some embodiments, as in Fig. 18, the amorphous region 186 formed by the ion implantation process is in contact with the first semiconductor layers 106. In some embodiments, as shown in Fig. 19, the amorphous region 186 formed by the ion implantation process does not extend to the second semiconductor material 154. The upper part of the third semiconductor material 156 is amorphized to produce the amorphous region 186, while the second semiconductor material 154, which is arranged on opposite sides of the amorphous region 186, remains crystalline. The size of the amorphous region 186 can be controlled with the implantation angle and / or the implantation energy and duration. Then, the second ion implantation process is performed to produce an amorphous region 187, as shown in Fig. 19. In some embodiments, the amorphous region 187 is wider and deeper than the amorphous region 186, and the amorphous region 186 is within the amorphous region 187. In other words, the second ion implantation process amorphizes the second semiconductor material 154 and the underlying portions of the third semiconductor material 156. The second species is implanted into both the first amorphous region 186 and the second amorphous region 187. In some embodiments, the first species in the amorphous region 186 is enclosed by the second species in the amorphous region 187. This further delays the diffusion of the first species in the amorphous region 186 into the first semiconductor layers 106. In some embodiments, the Fig. 19 described second ion implantation process a higher implantation energy compared to the one in Fig. 18 described second ion implantation process for forming the amorphous region 187. In some embodiments, the second species in the amorphous region 187 is adjacent to the first species in the amorphous region 186.

[0050] In some embodiments, the third ion implantation process is performed to implant the third species into the amorphous regions 186, 187. As described above, the third implantation process may be optional.

[0051] After the amorphization process and the second ion implantation process (and in some embodiments, the third ion implantation process), the annealing process is performed to recrystallize the amorphous region 186 (and in some embodiments, the amorphous region 187). In some embodiments, the annealing process may be a flash lamp annealing (FLA) process, a laser spike annealing (LSA) process, or a rapid thermal annealing (RTA) process. The annealing temperature may be in a range of about 1050 degrees Celsius to about 1200 degrees Celsius for FLA or LSA and in a range of about 900 degrees Celsius to about 1000 degrees Celsius for RTA. The residence time of the annealing process can range from about 0.1 ms to about 40 ms for FLA or LSA and from about 1 s to about 20 s for RTA.The chamber pressure during the annealing process can range from about 1 Torr to about 760 Torr.

[0052] After recrystallization of the amorphous regions 186, 187, the second semiconductor material 154 in contact with the uppermost first semiconductor layers 106 comprises the second species, such as F, N, or C, and the concentration of the second species in the second semiconductor material 154 in contact with the uppermost first semiconductor layers 106 is in a range of approximately 5 × 10 20 cm -3 up to about 1 × 10 21 cm -3. In some embodiments, the second semiconductor material 154 in contact with the topmost first semiconductor layers 106 also includes the third species, such as F, N, or C, which is different from the second species. In some embodiments, the second semiconductor material 154 in contact with the first semiconductor layers 106 located below the topmost first semiconductor layers 106 is free of the second and third species because the amorphous regions 186, 187 do not extend to the second semiconductor material 154 in contact with the first semiconductor layers 106 located below the topmost first semiconductor layers 106.As a result, the first species, the second species, and the third species in the amorphous regions 186, 187 are not implanted into the second semiconductor material 154 that is in contact with the first semiconductor layers 106 located below the topmost first semiconductor layers 106. In some embodiments, the second semiconductor material 154 that is in contact with the first semiconductor layers 106 located below the topmost first semiconductor layers 106 has a concentration gradient of the second species and the third species. For example, the concentration of the second species and the third species in the second semiconductor material 154 that is in contact with the first semiconductor layers 106 located below the topmost first semiconductor layers 106 decreases in a direction toward the substrate 101.

[0053] As in Fig.20, silicide layers 192 are formed on the S / D regions (second semiconductor material 154 and third semiconductor material 156). The silicide layer 192 may be formed using any suitable process. In some embodiments, a metal layer (not shown) is first formed on the semiconductor device structure 100. The metal layer may comprise Ti, Ni, Ru, Co, W, or another suitable metal. In some embodiments, the metal layer is a multilayer structure. The multilayer structure may include a metal layer and a metal nitride or metal oxide layer. The metal layer may be deposited using any suitable process, such as ALD, CVD, or PVD. After deposition of the metal layer, an annealing process is performed to cause the amorphous region 186 to react with the metal layer, thereby forming the silicide layers 192.The silicide layer 192 may comprise any suitable material, such as NiSi, TiSi, CoSi, RuSi, or wSi. Conductive contacts 194 are then deposited in the openings 180. The conductive contact 194 may be electrically conductive and may comprise a material including Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, and / or TaN, and the conductive contact 194 may be formed using any suitable method, such as electrochemical plating (ECP) or physical vapor deposition (PVD).

[0054] Embodiments of the present disclosure provide a semiconductor device structure and methods of fabricating the same. In some embodiments, the method includes performing an amorphization process on a portion of the third semiconductor material 156 to create an amorphous region 186 and to implant a first species into the amorphous region 186. A second implantation process may be performed to implant a second species into the amorphous region 186. The presence of the second species retards the diffusion of the first species by eliminating vacancies and interstitials. Some embodiments may achieve benefits. For example, by retarding the diffusion of the first species, the risk of Ge out-diffusion may be reduced, which in turn improves yield performance.

[0055] One embodiment is a method. The method comprises the following steps: forming a fin structure from a substrate; depositing a first semiconductor material on a first semiconductor layer of the fin structure; depositing a second semiconductor material on the first semiconductor material; depositing an interlayer dielectric layer over the second semiconductor material; forming an opening in the interlayer dielectric layer to expose the second semiconductor material; performing a first implantation process to form an amorphous region in the second semiconductor material and to implant a first species into the amorphous region; and performing a second implantation process to implant a second species into the amorphous region. The second species comprises fluorine, nitrogen, or carbon.The method further comprises performing an annealing process to recrystallize the amorphous region.

[0056] Another embodiment is a method. The method comprises the following steps: forming a fin structure from a substrate; depositing a first semiconductor material over the substrate; depositing an interlayer dielectric layer over the first semiconductor material; forming an opening in the interlayer dielectric layer to expose the first semiconductor material; performing a first implantation process to form a first amorphous region in the first semiconductor material and to implant a first species into the first amorphous region; performing a second implantation process to form a second amorphous region in the first semiconductor material and to implant a second species into the first amorphous region and the second amorphous region; performing an annealing process to recrystallize the first amorphous region and the second amorphous region.

[0057] Another embodiment is a semiconductor device structure. The structure comprises a plurality of semiconductor layers disposed above a substrate and a source / drain region disposed adjacent to the plurality of semiconductor layers. The source / drain region comprises a first semiconductor material in contact with each semiconductor layer of the plurality of semiconductor layers. A first portion of the first semiconductor material in contact with a topmost semiconductor layer of the plurality of semiconductor layers comprises a first species, and a second portion of the first semiconductor material in contact with a semiconductor layer of the plurality of semiconductor layers disposed below the topmost semiconductor layer has a concentration gradient of the first species. The source / drain region further comprises a second semiconductor material adjacent to the first semiconductor material.

[0058] Features of various embodiments have been described above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other methods and structures for achieving the same objectives and / or obtaining the same benefits as the embodiments presented herein. Those skilled in the art will also appreciate that such equivalent interpretations do not depart from the spirit and scope of the present disclosure and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 600,058

[0001]

Claims

[1] Procedure with the following steps: Producing a fin structure from a substrate; Depositing a first semiconductor material on a first semiconductor layer of the fin structure; Depositing a second semiconductor material on the first semiconductor material; Depositing an interlayer dielectric layer over the second semiconductor material; Creating an opening in the interlayer dielectric layer to expose the second semiconductor material; Performing a first implantation process to create an amorphous region in the second semiconductor material and to implant a first species into the amorphous region; Performing a second implantation process to implant a second species into the amorphous region, the second species comprising fluorine, nitrogen, or carbon; and Performing an annealing process to recrystallize the amorphous region. [2] The method of claim 1, wherein the second semiconductor material comprises SiP and the first species comprises phosphorus. [3] The method according to claim 1 or 2, wherein a concentration of the first species in the amorphous region is about 1 × 10 19 cm -3 up to about 5 × 10 20 cm -3 amounts. [4] A method according to any one of the preceding claims, wherein a concentration of the second species in the amorphous region is about 5 × 10 20 cm -3 up to about 1 × 10 21 cm -3 amounts. [5] The method of any preceding claim, wherein the fin structure comprises the first semiconductor layer, a second semiconductor layer located beneath the first semiconductor layer, and a third semiconductor layer located beneath the second semiconductor layer. [6] The method of claim 5, further comprising depositing the first semiconductor material on the second semiconductor layer and the third semiconductor layer. [7] The method according to claim 5 or 6, wherein a bottom surface of the amorphous region is located at a level between the first semiconductor layer and the second semiconductor layer. [8] Procedure with the following steps: Producing a fin structure from a substrate; depositing a first semiconductor material over the substrate; Depositing an interlayer dielectric layer over the first semiconductor material; Creating an opening in the interlayer dielectric layer to expose the first semiconductor material; Performing a first implantation process to create a first amorphous region in the first semiconductor material and to implant a first species into the first amorphous region; Performing a second implantation process to create a second amorphous region in the first semiconductor material and to implant a second species into the first amorphous region and the second amorphous region; and Performing an annealing process to recrystallize the first amorphous region and the second amorphous region. [9] The method of claim 8, wherein the first species comprises phosphorus and the second species comprises fluorine, nitrogen or carbon. [10] The method of claim 8 or 9, wherein the fin structure comprises a plurality of semiconductor layers. [11] The method of claim 10, further comprising depositing a second semiconductor material on each semiconductor layer of the plurality of semiconductor layers, wherein the first semiconductor material is deposited on the second semiconductor material. [12] A method according to any one of claims 8 to 11, wherein the second amorphous region is wider and deeper than the first amorphous region. [13] A method according to any one of claims 8 to 12, wherein the first amorphous region is located between parts of the second semiconductor material. [14] Method according to one of claims 8 to 13, wherein the parts of the second semiconductor material are part of the second amorphous region. [15] Semiconductor device structure comprising: a plurality of semiconductor layers disposed over a substrate; and a source / drain region disposed adjacent to the plurality of semiconductor layers, the source / drain region comprising: a first semiconductor material in contact with each semiconductor layer of the plurality of semiconductor layers, wherein a first portion of the first semiconductor material in contact with a topmost semiconductor layer of the plurality of semiconductor layers comprises a first species, and a second portion of the first semiconductor material in contact with a semiconductor layer of the plurality of semiconductor layers disposed below the topmost semiconductor layer has a concentration gradient of the first species; and a second semiconductor material adjacent to the first semiconductor material. [16] The semiconductor device structure of claim 15, wherein the first species comprises fluorine, nitrogen, or carbon. [17] The semiconductor device structure of claim 15 or 16, wherein the second semiconductor material comprises a second species. [18] A semiconductor device structure according to any one of claims 15 to 17, wherein a second species comprises phosphorus. [19] A semiconductor device structure according to any one of claims 15 to 18, wherein the second species has a concentration gradient that decreases in a direction toward the substrate. [20] The semiconductor device structure of any one of claims 15 to 19, further comprising a third semiconductor material disposed over the substrate and a dielectric layer disposed on the third semiconductor material, wherein the second semiconductor material is disposed on the dielectric layer.

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