SEMICONDUCTOR COMPONENT WITH A CRACK STOP STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Abstract

A semiconductor device (900) comprises a semiconductor region (100) comprising a central region (610) and an edge region (690), wherein the edge region (690) separates the central region (610) from a lateral chip edge (109). An interlayer dielectric (200) is formed on a horizontal first main surface (101) of the semiconductor region (100). In the edge region (690), a recess (211) extends through the interlayer dielectric (200). A crack stop structure (300) comprises a first region (310) formed in the recess (211).A dielectric layer structure (400) is formed on the interlayer dielectric (200) and the crack stop structure (300), wherein the dielectric layer structure (400) and the crack stop structure (300) are configured such that each horizontal plane (800) intersecting the dielectric layer structure (400) and the lateral chip edge (109) intersects an inclined surface (403) of the dielectric layer structure (400) in the edge region (690).

Description

TECHNICAL FIELDThe present disclosure relates to a semiconductor device having a crack stopper structure in a periphery region and a method of manufacturing a semiconductor device having a crack stopper structure.BACKGROUNDAfter processing a semiconductor wafer, wafer dicing cuts a wafer into identical semiconductor dies. Each semiconductor die comprises a semiconductor body and functional layers of dielectric and metallic materials on opposite main surfaces of the semiconducting region. The individual semiconductor dies may be encapsulated in chip packages suitable for use in electronic devices.Typically, wafer dicing involves mechanical processes such as scribing and breaking, or mechanical sawing using a rotating dicing blade. Mechanical wafer dicing is effective along dicing streets ("scribe lines") that form a regular rectangular grid. Scribing, breaking, and sawing along the dicing streets may create cracks that propagate from the dicing street into the adjacent region of a semiconductor die. Crack stop structures formed along the die edge stop propagation of cracks towards a central die region.U.S. Pat. No. 5,391,920 A describes metallic supply lines VDD, VSS, each of which forms a rectangular metallic frame around a central component region in an upper metallization layer. The connection pads for VDD and VSS are formed between the supply line VDD and the chip edge. In the region of the four corners of the frame, each supply line VDD, VSS comprises additional sections in a lower metallization layer. A thin oxide layer and a first interlayer dielectric separate the lower metallization layer from a silicon substrate. A second interlayer dielectric separates the upper metallization layer from the lower metallization layer. A series of laterally spaced vias extend from the upper metallization layer through the second interlayer dielectric to the lower metallization layer. A series of laterally spaced apart contact structures extend from the lower metallization layer through the first interlayer dielectric and the thin oxide layer to the silicon substrate. The lower metallization layer and the vias reduce the thermomechanical loading of the frames in the corners of the upper metallization layer.In the publication JP H09-199 449 A, a first metallization layer lies on a first interlayer dielectric in the component edge region. A second interlayer dielectric is formed over the first interlayer dielectric and the first metallization layer. Through an opening in the second interlayer dielectric, a bond pad formed in a second metallization layer makes contact with the first metallization layer. An upper dielectric layer covers the second interlayer dielectric and the second metallization layer and is opened over the bond pad. Between the bond pad and the chip edge, a continuous anti-peeling trench extends through the upper dielectric layer.There is a continuing need to protect a central region of a semiconductor die from defects induced by wafer dicing processes, particularly mechanical wafer dicing processes.SUMMARYA wafer typically includes layers of dielectric materials, the dielectric layers extending laterally into the dicing streets. Mechanical wafer dicing processes that cut into the dielectric layers generate local mechanical stress. The mechanical stress may damage the internal structure in regions of the dielectric layers along the dicing streets. The damage may result in cracks in a dielectric layer, wherein the cracks propagate towards a central region of the semiconductor die. The cracks may affect the performance and / or reliability of an integrated circuit and / or a circuit board including a semiconductor die obtained from the wafer through the wafer dicing process.According to the present disclosure, a semiconductor device includes a semiconductor region having a central region and an edge region separating the central region from a lateral chip edge. An interlayer dielectric is formed on a horizontal first main surface of the semiconductor region. In the edge region, a depression extends through the interlayer dielectric. A crack stopping structure includes a first region formed in the depression. A dielectric layer structure is formed on the interlayer dielectric and the crack stop structure, wherein the dielectric layer structure and the crack stop structure are configured such that each horizontal plane intersecting the dielectric layer structure and the lateral chip edge intersects an inclined surface of the dielectric layer structure in the edge region.Consequently, there is no horizontal plane in the dielectric layer structure and the interlayer dielectric intersecting the chip side edge and spanning the crack stop structure without interruption from a side of the edge region aligned with the chip side edge to a side aligned with the central region. Interfaces between different solid materials stop the propagation of cracks in the interlayer dielectric and the dielectric layer structure. No or only a very limited number of cracks may extend into the central region.Since the dielectric layer structure may completely cover the crack stop structure, the crack stop structure may be formed of (a) conductive material(s) and in contact with the semiconductor region without the risk of an electrical breakdown between the crack stop structure and other conductive structures by air and / or other materials with low breakdown strength, even if such other conductive structures are formed on the dielectric layer structure or are exposed through openings in the dielectric layer structure.The present disclosure also relates to a method of manufacturing a semiconductor device. An interlayer dielectric is formed on a first main surface of a semiconductor region including a central region and an edge region laterally surrounding the central region. A recess is formed that extends into the interlayer dielectric in the edge region. A crack stopping structure is formed that includes a first region formed in the recess. A dielectric layer structure is formed covering the interlayer dielectric and the crack stopper structure.Those skilled in the art will recognize additional features and advantages by reading the following detailed description and viewing the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings are provided for further understanding of the embodiments and form an integral part of this specification. The drawings illustrate embodiments of a semiconductor device and a method of manufacturing a semiconductor device and together with the description explain the principles underlying the embodiments. Other embodiments are described in the following detailed description and in the claims. Features of the various embodiments may be combined with each other. FIGS. 1A and 1B show simplified vertical and simplified horizontal cross-sections of a semiconductor device having a crack stop structure according to an embodiment. FIG. 2 shows a simplified vertical cross section of a semiconductor device having a crack stop structure formed in a lower part of a recess in an interlayer dielectric, according to an embodiment. FIG. 3 shows a simplified vertical cross-section of a semiconductor device with a crack stop structure overfilling a recess in an interlayer dielectric, according to an embodiment. FIG. 4 shows a simplified vertical cross-section of a semiconductor device having a crack stop structure with a first region formed in a recess in an interlayer dielectric and a second region formed on the interlayer dielectric outside the recess, according to an embodiment. FIG. 5 shows a simplified vertical cross-section of another semiconductor device having a crack stop structure with a first region formed in a recess in an interlayer dielectric and a second region formed on the interlayer dielectric outside the recess, according to an embodiment. FIGS. 6 and 7 show simplified vertical cross-sections of semiconductor devices including a crack stop structure having a first region formed in a lower region of a recess in an interlayer dielectric and a second region formed on the interlayer dielectric, according to other embodiments, wherein the crack stop structures have different vertical extents. FIG. 8 shows a simplified vertical cross section of a semiconductor device having a crack stop structure with laterally separated regions according to an embodiment. FIGS. 9A to 9D show simplified vertical cross sections of a portion of a semiconductor wafer for illustrating a method of manufacturing a semiconductor device having a crack stop structure in successive process stages according to another embodiment.DETAILED DESCRIPTIONIn the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments of a semiconductor device and method of making a semiconductor device. Structural or logical changes may be made to the illustrated embodiments. For example, features shown or described for one embodiment may be used in or in conjunction with other embodiments, resulting in another embodiment. The present disclosure is intended to encompass such modifications and variations. The embodiments are described in a manner that should not be construed as limiting. The drawings are not to scale and are for illustrative purposes only. Corresponding elements are denoted by the same reference numerals throughout the several drawings unless otherwise indicated.The terms "have," "include," "comprise," "have," and the like are open-ended, and the terms indicate the presence of certain structures, elements, or features, but do not exclude the presence of additional elements or features. The articles "a", "an", and "the / s" include both the plural and the singular, unless the context clearly indicates otherwise.The term "on" should not be construed to mean only "directly on". Rather, when an element is positioned "on" another element (e.g., a layer "on" another layer or "on" a substrate), another component (e.g., another layer) may be positioned between the two elements (e.g., another layer may be positioned between a layer and a substrate when the layer is "on" the substrate).Ranges given for physical dimensions include the limits. For example, a range for a parameter y reads from a to b as a≤y≤b. The same applies to ranges having a limit value such as "at most" and "at least.".An ohmic contact describes a non-rectifying electrical transition between two conductors, e.g. between a semiconductor material and a metal. The ohmic contact has a linear or approximately linear current-voltage curve (I-V curve) in the first and third quadrants of the I-V diagram according to Ohmic Law.A semiconductor device may include a semiconductor region including a central region and an edge region separating the central region from a lateral chip edge. An interlayer dielectric may be formed on a horizontal first main surface of the semiconductor region. In the edge region, a depression may extend through the interlayer dielectric. A crack stopping structure may include a first region formed in the recess. A dielectric layer structure may be formed on the interlayer dielectric and the crack stop structure, wherein the dielectric layer structure and the crack stop structure are configured such that each horizontal plane intersecting the dielectric layer structure and the lateral chip edge intersects an inclined surface of the dielectric layer structure in the edge region.The semiconductor region can be a homogeneous semiconductor body. Alternatively, the semiconductor region is a layer of a multilayer body, for example the semiconductor layer or a substrate layer of a silicon-on-insulator (SOI) body.The semiconductor region may include a central region and an edge region laterally surrounding the central region. The edge region may laterally separate the central region from the lateral chip edge. The lateral chip edge may include four straight portions, each of which is coplanar with a portion of a lateral outer surface of the semiconductor region. The edge region may comprise four portions, each of which extends at a uniform width along a portion of the lateral chip edge. In the central area, electrical elements and / or electrical circuits of an integrated circuit are formed, which define the electrical functionality of the semiconductor device. The integrated circuit may be a high voltage semiconductor device. For example, the functional electrical elements and electrical circuits of a gate driver circuit are formed in the central region. In the edge region, functional electrical elements of the integrated circuit may be completely absent.The semiconductor region has a horizontal first main surface on a front side. An interlayer dielectric may be formed on the horizontal first main surface. The interlayer dielectric may be formed directly on the first main surface. Alternatively, one or more other layers may be formed between the interlayer dielectric and the first main surface of the semiconductor region. The interlayer dielectric may have a uniform thickness and / or may be a homogeneous layer. Alternatively, the interlayer dielectric can be a layer stack comprising at least two sublayers of different composition and / or internal structure ("microstructure"). For example, the interlayer dielectric may comprise a thermally grown oxide sublayer of the material of the semiconductor region and one or more sublayers of silicon oxide deposited under different deposition conditions, wherein the thermally grown oxide sublayer is formed directly on the first main surface and the other sublayers are formed sequentially on the thermally grown oxide sublayer.The depression in the edge region may extend from a top surface of the interlayer dielectric into the interlayer dielectric. The recess may extend through the interlayer dielectric and expose a contact portion of the semiconductor region.The first region of the crack stop structure is formed in the depression. The crack stopping structure may include only the first region in the depression. Alternatively, the crack stopping structure may further include a second region formed outside the recess and in direct contact with the first region. The first portion of the crack stop structure may have an approximately uniform thickness directly over a central portion of a bottom of the recess. The second portion of the crack stop structure may have an approximately uniform thickness over the horizontal top surface of the interlayer dielectric. The horizontal top surface of the interlayer dielectric and a virtual separation plane between the first and second regions of the crack stop structure may be coplanar. The first region and the second region are partially arranged vertically one above the other. The second portion may comprise two separate sub-portions on opposite sides of the recess.Alternatively to the second region or in addition, the crack stop structure may include a third region separated from the first region.The first region of the crack stop structure is made of a material other than the interlayer dielectric. For example, the interlayer dielectric is based on a silicon oxide and the crack stop structure does not contain any compound with silicon and oxygen as main components, e.g. only as main components. The crack stop structure is in direct contact with the semiconductor region at the bottom of the recess and may be in direct contact with the interlayer dielectric along the sidewall of the recess.The dielectric layer structure formed on the interlayer dielectric and the crack stop structure may act as a passivation structure and may be in direct contact with the interlayer dielectric along at least a portion of the horizontal top surface of the interlayer dielectric. The dielectric layer structure may be in direct contact with the crack stop structure along the upper surface of the crack stop structure. The dielectric layer structure may have a uniform thickness over horizontal portions of the interlayer dielectric and the crack stop structure.The semiconductor region, the combination of interlayer dielectric and crack stop structure, and the dielectric layer structure are vertically stacked on one another along a vertical direction orthogonal to the first main surface. The lateral chip edge comprises the lateral outer surface of the semiconductor region and lateral side walls of the interlayer dielectric and the dielectric layer structure, wherein the lateral side walls of the interlayer dielectric and the dielectric layer structure and the lateral outer surface of the semiconductor region are coplanar.The dielectric layer structure includes horizontal surface portions and inclined surface portions connecting the horizontal surface portions. First inclined surface portions are formed along an interface between a bottom surface of the dielectric layer structure and inclined sidewalls of the crack stopper structure. Second inclined surface portions are formed between horizontal surface portions of the upper surface of the dielectric layer structure. The second inclined surface portions may be formed along interfaces to a package shape that is in direct contact with the upper surface of the dielectric layer structure and / or along interfaces to the ambient air.An angle between each inclined surface and a horizontal plane parallel to the first main surface may be in a range of 30 degrees to 90 degrees.When the recess, the interlayer dielectric, the dielectric layer structure, and the crack stopper structure are configured such that each horizontal plane intersecting the chip side edge in the dielectric layer structure intersects an inclined surface of the dielectric layer structure in the edge region, there is no horizontal plane spanning the crack stopper structure within the dielectric layer structure without discontinuity from a side of the edge region aligned with the chip side edge to a side aligned with the central region.Each crack in the interlayer dielectric, which is generated at the lateral chip edge and propagates in a horizontal plane towards the central region, terminates at the first crack stop structure lining or filling the recess. Each horizontal crack in the dielectric layer structure, which is generated at the lateral chip edge and propagates in a horizontal plane, terminates at one of the inclined surfaces of the dielectric layer structure.Cracks in the dielectric layer structure and in the interlayer dielectric, which are generated at the lateral chip edge and propagate in directions inclined to the horizontal plane, end at the first main surface of the semiconductor region, at horizontal surfaces of the dielectric layer structure in the edge region and / or at inclined surfaces of the dielectric layer structure in the edge region. No cracks or only a very small portion of the cracks propagate into the central region. The dielectric layer structure and the interlayer dielectric for the functional circuits remain undamaged. The reliability of the device can be improved.The semiconductor device may include a plurality of recesses and crack stops formed along one, two or more frame-like lines surrounding the central region. The recesses and crack stop bodies may be formed with similar or equal dimensions along each frame-like line and may be equidistant from each other. A distance between adjacent crack stop bodies may be smaller than a length of the crack stop bodies along the frame-like line, such that a large portion of cracks propagating from the lateral chip edge towards the central region terminate at one of the interfaces of the interlayer dielectric or the dielectric layer structure within the edge region.The crack stop structure laterally surrounds the central region.In particular, the semiconductor device may include a single crack stop structure forming a continuous frame around the central region. All cracks in the interlayer dielectric and / or the dielectric layer structure, which propagate substantially straight from the lateral chip edge in the direction of the central region, end within the edge region at one of the interfaces of the interlayer dielectric or the dielectric layer structure.The material(s) and / or the structure of the crack stop structure is / are selected such that the crack stop structure stops cracks propagating in the interlayer dielectric and / or the dielectric layer structure.According to an embodiment, the crack stop structure may be formed of a conductive material.The crack stop structure may be formed of one or more conductive materials. In particular, the crack stop structure may have the same composition as conductive lines and / or conductive structures of the integrated circuit formed in the central region, e.g. field plates. The crack stop structure and the conductive lines and / or conductive structures in the integrated circuit may be formed from different portions of the same conductive layer or layer stack. The formation of the crack stop structure may be fully compatible with the formation of the conductive lines and / or conductive structures and requires no more than a modification of a forcing process but no additional process.According to an embodiment, the dielectric layer structure may completely cover a portion of the crack stop structure that is in direct contact with the semiconductor portion.When the dielectric layer structure completely covers a crack stop structure formed of (a) conductive material(s) and in direct contact with the semiconductor region and a wafer level test applies a high voltage between the semiconductor region and an exposed conductive structure of the semiconductor die, the dielectric layer structure prevents any electrical breakdown by air and / or another low dielectric strength material between the crack stop structure and the exposed conductive structure. The exposed conductive structure may be a signal contact pad or a power supply pad formed in the central region.According to an embodiment, the crack stop structure may include a second region formed on the interlayer dielectric, the first region and the second region being connected.Horizontal portions of the first region and the second region may have a same vertical extent and a same material configuration. The first region and the second region may be different portions of a metallization layer. The metallization layer may comprise only the first region and the second region of the crack stop structure. Alternatively, the metallization layer may include, in addition to the first and second regions of the crack stop structure, third portions forming conductive lines and / or conductive structures electrically connecting electrical elements in the central region. The metallization layer may be a 3D layer deposited on horizontal surfaces that are displaced from each other along the vertical direction. The metallization layer may comprise copper, aluminum and / or a copper-aluminum alloy. The formation of the crack stop structure is based on a modification of the lithographic mask defining the electrical connections. No additional process step is required to form the crack stop structure.According to an embodiment, a width w 0 of the recess and vertical expansions w 2, w 3, w 4 of horizontal areas of the interlayer dielectric, the crack stop structure and the dielectric layer structure may be selected such that each horizontal plane intersecting the lateral chip edge in the dielectric layer structure intersects an inclined surface of the dielectric layer structure in the edge region at a distance from the lateral chip edge.Consequently, there is no horizontal plane spanning the crack stop structure within the dielectric layer structure from a side of the edge region aligned to the lateral chip edge to a side of the edge region aligned to the central region without interruption.According to an embodiment, a difference between a maximum vertical distance wx between an upper surface of the dielectric layer structure and the first main surface and a minimum vertical distance wy between the upper surface of the dielectric layer structure and the first main surface may be greater than or equal to a maximum thickness w 4 of the dielectric layer structure.For wx-wy≥w4, at least two sections of the dielectric layer structure have a vertical displacement with respect to one another which is greater than their vertical extent. Within the dielectric layer structure, there may not be a horizontal plane spanning the crack stop structure without interruption from an outer side of the crack stop structure aligned to the lateral chip edge to an inner side of the crack stop structure aligned to the central region.According to an embodiment, a width w0of the recess may be wide enough that the dielectric layer structure forms steps directly above the bottom of the recess.A height of the step may be at least 90% or about 100% of the vertical extension w 2 of the interlayer dielectric. A slot resulting from the steps laterally separates two vertical regions of the dielectric layer structure. The crack stopping structure blocks a wide variety of different types of cracks with high efficiency.According to an embodiment, a step height of the steps formed by the dielectric layer structure may be greater than a vertical extension w 4 of the dielectric layer structure.In particular, the lower edge of the dielectric layer structure directly above the depression may be closer to the first main surface of the semiconductor region ("deeper") than the upper surface of the crack stop structure. The crack stopping structure blocks a wide variety of different types of cracks with high efficiency.If the vertical extension w 2 of the interlayer dielectric is greater than the vertical extension w 4 of the dielectric layer structure, each linear crack generated at the lateral chip edge in the dielectric layer structure terminates at the latest at the slot even if the vertical extension w 4 of the dielectric layer structure is greater than the vertical extension w 3 of the horizontal regions of the crack stop structure.According to an embodiment, the crack stop structure may include a third region formed on the interlayer dielectric in the peripheral region, the third region being separated from the first region.The third region may be structurally and electrically separated from the semiconductor region, the first region of the crack stop structure, and optionally from the second region of the crack stop structure. In particular, the third region may be electrically floating or may be electrically connected to a conductive structure having an electrical potential different from an electrical potential of the semiconductor region. The third region may be formed between the first region and the lateral chip edge and / or between the first region and the central region. The third region may have the same vertical extent as the second region and may be a further portion of the metallization layer from which the first region or the first region and the second region are formed. The third region may provide a further crack stop for cracks propagating in the interlayer dielectric and / or the dielectric layer structure from the lateral chip edge towards the central region.The semiconductor device may include a plurality of third regions each formed on another auxiliary line surrounding the central region. Each auxiliary line may comprise four linear portions each parallel to one of the four lateral die faces. The total area of an auxiliary line occupied by third areas may be larger than the total area of the auxiliary line between the third areas.According to an embodiment, a gap may extend through the dielectric layer structure over the third region of the crack stop structure.The gap may expose a portion of the top surface of the third portion of the crack stopping structure. The gap and the third region of the crack stop structure may supplement one another to form a heterogeneous vertically extended crack stop which completely destroys the interlayer dielectric and the dielectric layer structure. Each horizontal crack which arises at the lateral chip edge and propagates in the dielectric layer structure and / or the interlayer dielectric at any angle to the horizontal plane in the direction of the central region terminates at the gap or the third region, independently of a ratio between the vertical extension w 3 of the crack stop structure and the vertical extension w 4 of the dielectric layer structure.If a wafer level test applies a high voltage between the semiconductor region and an exposed conductive structure formed in the central region, the dielectric layer structure prevents any electrical breakdown by air and / or another dielectric material having lower breakdown strength than the dielectric layer structure between the first and second regions of the crack stop structure on the one hand and other conductive structures formed on or exposed by openings in the dielectric layer structure on the other hand. Since the third region of the crack stop structure is separated from the potential of the semiconductor region, no electrical breakdown occurs through the gap.According to an embodiment, a vertical extension w 4 of a horizontal portion of the dielectric layer structure may be greater than a vertical extension w 3 of a horizontal portion of the crack stop structure.Additionally, if a combined vertical extension w 34 of the crack stop structure and the dielectric layer structure may be less than the vertical extension w 2 of the interlayer dielectric such that the slot between vertical portions of the dielectric layer structure extends into the recess in the interlayer dielectric, the crack stop structure provides a highly efficient crack stop for various types of cracks.According to an embodiment, the third region of the crack stop structure may laterally surround the central region.In particular, the crack stop structure may comprise a single third region forming a continuous frame around the central region. All cracks in the dielectric layer structure, which arise at or near the lateral chip edge and which spread substantially straight and / or planar in the direction of the central region, end within the edge region at one of the boundary surfaces of the dielectric layer structure.A method of manufacturing a semiconductor device may include forming an interlayer dielectric on a first main surface of a semiconductor region, the semiconductor region having a central region and an edge region laterally surrounding the central region. A recess may be formed extending into the interlayer dielectric in the edge region.A crack stop structure may be formed with a first portion of the crack stop structure formed in the recess. A dielectric layer structure may be formed covering the interlayer dielectric, and the crack stopper structure is formed.According to an embodiment, a conductive structure may be formed in the central region, wherein a metallization layer is deposited on the interlayer dielectric and patterned to simultaneously form from portions of the metallization layer the conductive structure in the central region and the crack stop structure in the edge region.FIG. 1A shows a vertical cross-section through a portion of a semiconductor device 900, for which FIG. 1B shows a horizontal cross-section.The semiconductor device 900 includes a semiconductor region 100. The semiconductor region 100 is a substrate layer of a multilayer body that also includes a semiconductor layer and an insulator layer separating the substrate layer and the semiconductor layer in device regions of the multilayer body. Alternatively, the semiconductor region 100 may be a self-supporting single semiconductor base.The semiconductor region 100 is based on a single-crystalline semiconductor. The single crystal semiconductor includes, as main constituent elements, Group IV elementary semiconductors such as silicon (Si) or germanium (Ge), Group IV compound semiconductors such as silicon carbide (SiC) or silicon germanium (SiGe), or Group III-V semiconductors such as gallium nitride (GaN), aluminum gallium nitride (AlGaN) and gallium arsenide (GaAs).The semiconductor region 100 has a first main surface 101 on a front side and an opposite second main surface on the back side. The first main surface 101 and the second main surface have the same shape and size and extend parallel to each other. A lateral outer surface 103 of the semiconductor portion 100 connects the edge of the first main surface 101 and the edge of the second main surface.The first main surface 101 is planar and may be continuous or may comprise two or more coplanar surface portions laterally separated by one or more trenches extending from the front side into the semiconductor region 100. The first main surface 101 extends along a horizontal plane defined by an x-axis and a y-axis extending orthogonally to the x-axis. A normal to the first main surface 101 defines a vertical direction along a z-axis. The semiconductor region 100 has a rectangular shape in the horizontal plane. The outer lateral surface 103 extends in the vertical direction.The semiconductor portion 100 comprises a central region 610 and an edge region 690 laterally surrounding the central region 610. The edge region 690 laterally separates the central region 610 from a lateral chip edge 109. The lateral chip edge 109 comprises four straight portions, each of which is coplanar with a portion of the lateral outer surface 103 of the semiconductor region 100.The edge region 690 includes four portions each having a uniform width. The four portions of the edge region 690 may have the same width. The central region 610 includes the electrical elements and electrical circuits of a gate driver circuit. The edge region 690 is free of functional elements of the gate driver circuit.An interlayer dielectric 200 is formed on the first main surface 101. The interlayer dielectric 200 is a homogeneous layer having a uniform vertical extension w 2. The interlayer dielectric 200 is in direct contact with the semiconductor region 100 and comprises or consists of silicon oxide(s), e.g. deposited SiO2or a combination of thermal and deposited SiO2 The density of the silicon oxide is uniform or varies along the vertical direction. Alternatively, the interlayer dielectric 200 comprises two or more dielectric sublayers, wherein at least one of the dielectric sublayers comprises or consists of thermal and / or deposited silicon oxide. The vertical extension w 2 of the interlayer dielectric is in a range from 100 nm to 3 μm, e.g. 500 nm to 1.5 μm.In the edge region 690, a recess 211 having a recess width w 0 extends down through the interlayer dielectric 200 to the first main surface 101. The recess 211 forms an opening in the interlayer dielectric 200 and exposes a contact portion 104 of the first main surface 101. The groove width w 0 is in a range from 200 nm to 8 μm, for example, from 500 nm to 5 μm. As illustrated in FIG. 1B, the depression 211 forms a closed rectangular frame around the central region 610.A crack stopping structure 300 includes a first region 310 formed in the recess 211 in direct contact with the contact portion 104. A second region 320 of the crack stop structure 300 is formed outside the depression 211 on a portion of the interlayer dielectric 200 directly adjoining the depression 211. The first region 310 and the second region 320 are structurally and electrically connected, can form a continuous layer and have the same vertical extent w 3. The vertical extension w 3 is in a range from 250 nm to 15 μm.As illustrated in FIG. 1B, the crack stop structure 300 may surround the central region 610 and form a substantially closed rectangular frame around the central region 610, wherein the edges of the crack stop structure 300 may be rounded. Alternatively, the crack stop structure 300 may surround the central region 610 and form an arbitrarily shaped closed frame, e.g. a circular or elliptical frame or a rectangular frame with two 45° angles side by side replacing each 90° angle.The material of the crack stop structure 300 may be an elemental metal, a metal compound, a metal alloy, and / or a highly conductive semiconductor material. For example, the crack stop structure 300 is made of a single layer comprising or consisting of aluminum or an aluminum alloy. Alternatively, the crack stop structure 300 may comprise a stack of more than one layer, e.g. more than one metal layer. For example, the crack stop structure 300 includes a plug including tungsten plus contact and / or barrier layers such as titanium, titanium silicide, titanium nitride in combination with an aluminum or an aluminum alloy formed as an overlapping cap after CMP of the plug material(s). Along the contact portion 104, a heavily doped region in the semiconductor region 100 and the crack stop structure 300 form an ohmic contact.A dielectric layer structure 400 is formed in direct contact with a horizontal upper surface 201 of the interlayer dielectric 200, inclined sidewalls of the crack stop structure 300 and a horizontal upper surface 301 of the crack stop structure 300. The dielectric layer structure 400 may be a homogeneous layer or may comprise two or more sub-layers of different insulating materials. For example, the dielectric layer structure 400 comprises a first sub-layer of doped silicate glass, e.g. PSG (phosphosilicate glass), e.g. BPSG (borophosphosilicate glass), and a second sub-layer containing silicon and nitrogen, e.g. Si 3 N 4, wherein the second sub-layer is formed on the first sub-layer. A polymer layer (not illustrated) may be formed on top of the dielectric structure 400. The polymer layer may consist of a polyimide or contain a polyimide.Horizontal regions of the dielectric layer structure 400 have a uniform vertical extension w 4 over horizontal portions of the interlayer dielectric 200 and the crack stop structure 300. The total vertical extension w 4 of the dielectric layer structure 400 is in a range from 250 nm to 3 μm.The dielectric layer structure 400 has a lower surface 402 with first portions in contact with the interlayer dielectric 200 and second portions in contact with the crack stop structure 300 and an upper surface 401 facing away from the interlayer dielectric 200 and the crack stop structure 300. The bottom surface 402 includes horizontal portions over horizontal portions of the interlayer dielectric 200 and the crack stop structure 300 and sloped surfaces 403 connecting the horizontal portions. The top surface 401 includes horizontal portions over horizontal portions of the interlayer dielectric 200 and the crack stop structure 300 and sloped surfaces 403 connecting the horizontal portions. An angle between each of the inclined surfaces 403 and the horizontal plane may be in a range of 30 degrees to 90 degrees. Transitions between the inclined surfaces and horizontal portions may be rounded.A lateral chip edge 109 comprises the lateral outer surface 103 of the semiconductor portion 100 and vertical end surfaces of the interlayer dielectric 200 and the dielectric layer structure 400. The lateral chip edge 109, the lateral outer surface 103 of the semiconductor portion 100 and the vertical end surfaces of the interlayer dielectric 200 and the dielectric layer structure 400 are coplanar.The recess 211, the interlayer dielectric 200, the dielectric layer structure 400 and the crack stop structure 300 are configured such that each horizontal plane 800 intersecting the dielectric layer structure 400 and the lateral chip edge 109 intersects an inclined surface 403 of the dielectric layer structure 400 in the edge region 690.In particular, the recess width w 0, the vertical extension w 2 of the interlayer dielectric 200, the vertical extension w 3 of the crack stop structure and the vertical extension w 4 of the dielectric layer structure 400 are selected such that each horizontal plane 800 intersecting the lateral chip edge 109 at a height of the dielectric layer structure 400 intersects at least one of the inclined surfaces 403 of the dielectric layer structure 400 in the edge region 690 and at a distance from the lateral chip edge 109.Then, there is no horizontal plane within the dielectric layer structure 400 spanning the crack stop structure 300 without interruption from a portion of the edge region 690 aligned to the lateral chip edge 109 to a portion of the edge region 690 aligned to the central region 610.Since the internal structure (structure) of the material of the crack stop structure 300 is different from the internal structure of the interlayer dielectric 200 and the dielectric layer structure 400, each crack in the interlayer dielectric 200 generated at the lateral chip edge 109 and propagating in a horizontal plane terminates at the first crack stop structure 300 lining the recess 211. Each horizontal crack, which is generated at the lateral chip edge 109 and propagates in the dielectric layer structure 400 in a horizontal plane, terminates at one of the inclined surfaces 403 of the dielectric layer structure 400.Cracks in the dielectric layer structure 400 and in the interlayer dielectric 200 which are generated at the lateral chip edge 109 and propagate in directions which are inclined to the horizontal plane end at the first main surface 101 of the semiconductor region 100, the first crack stop structure 300 or at inclined surfaces 403 or horizontal surfaces of the dielectric layer structure 400 within the edge region 690. No cracks propagate into the central region 610.The dielectric layer structure 400 completely covers the crack stop structure 300. When a crack stop structure 300 formed of conductive material(s) is in direct contact with the semiconductor region 100 and a high voltage is applied between the semiconductor region 100 and an exposed conductive structure on the front side of the semiconductor device 900 during a wafer level test, the dielectric layer structure 400 prevents any electrical breakdown by the air between the crack stop structure 300 and the exposed conductive structure.In FIG. 2 and in FIG. 3, the crack stopping structure 300 includes only a first region 310 formed entirely directly above the bottom of the recess 211. The crack stop structures 300 do not extend laterally beyond the recess 211 and do not include a region formed on the horizontal top surface 201 of the interlayer dielectric 200. The crack stop structures 300 may completely cover the sidewalls of the recess 211, or may be formed at a distance from the sidewalls of the recess 211.In FIG. 2, the vertical extension w 3 of the crack stop structure 300 is smaller than the vertical extension w 2 of the interlayer dielectric 200. A maximum vertical distance wx between the upper surface 401 of the dielectric layer structure 400 and the first main surface 101 is outside the recess 211. A minimum vertical distance wybetween the upper surface 401 of the dielectric layer structure 400 and the first main surface 101 is within the recess 211. The difference wx-wy is greater than the maximum thickness w 4 of the dielectric layer structure 400.In FIG. 3, the vertical extension w 3 of the crack stop structure 300 is greater than the vertical extension w 2 of the interlayer dielectric 200. The maximum vertical distance wx between the upper surface 401 of the dielectric layer structure 400 and the first main surface 101 is within the recess 211. A minimum vertical distance wy between the upper surface 401 of the dielectric layer structure 400 and the first main surface 101 is outside the recess 211. The difference wx-wy is greater than the maximum thickness w 4 of the dielectric layer structure 400.Both in FIG. 2 and in FIG. 3, each horizontal plane 800 intersecting the lateral chip edge 109 at a height of the dielectric layer structure 400 intersects at least one of the inclined surfaces 403 of the dielectric layer structure 400 in the edge region 690 at a distance from the lateral chip edge 109.FIGS. 4 to 7 show further examples with a recess width w 0 and vertical expansions w 2, w 3, w 4 of horizontal regions of the interlayer dielectric 200, the crack stop structure 300 and the dielectric layer structure 400, which are selected such that each horizontal plane 800 intersecting the lateral chip edge 109 at a height of the dielectric layer structure 400 intersects an inclined surface 403 of the dielectric layer structure 400 at a distance from the lateral chip edge in the edge region 690.In particular, a difference between a maximum vertical distance wx between an upper surface 401 of the dielectric layer structure 400 and the first main surface 101 and a minimum vertical distance wy between the upper surface 401 of the dielectric layer structure 400 and the first main surface 101 is greater than a maximum thickness w 4 of the dielectric layer structure 400.In particular, at least two horizontal portions of the dielectric layer structure 400 have a vertical displacement with respect to one another which is greater than the vertical extent w 4 of the dielectric layer structure 400. Within the dielectric layer structure 400, there may not be a horizontal plane 800 which intersects the lateral chip edge 109 at the height of the dielectric layer structure 400 and which spans the crack stop structure 300 without interruption from the outer side of the edge region 690 to the inner side.In FIG. 4, the well width w 0 and the vertical extents w 3, w 4 are selected such that a slot 212 is formed over the contact portion 104 that laterally separates two opposing vertical regions of the dielectric layer structure 400. Each of the two vertical regions of the dielectric layer structure 400 connects a horizontal region formed on the second region 320 of the crack stop structure 300 to a horizontal region formed on the first region 310 of the crack stop structure 300. A combined vertical extension w 34 of the crack stop structure 300 and the dielectric layer structure 400 is less than half of the recess width (w 3+w 4<0.5·w 0). Each horizontal plane 800 in the dielectric layer structure 400 intersecting the lateral chip edge 109 at the height of the dielectric layer structure 400 terminates at an inclined surface 403 of the dielectric layer structure 400 along the crack stop structure 300 or the slot 212.In FIG. 5, the recess width w 0 and the vertical extents w 3, w 4 are selected such that over the contact portion 104, the dielectric layer structure 400 does not form a slot or only a flat slot. The combined vertical extension w 34 of the crack stop structure 300 and the dielectric layer structure 400 is greater than half of the recess width (w 3+w 4>0.5·w 0). Each horizontal plane 800 in the dielectric layer structure 400 intersecting the lateral chip edge 109 at a height of the dielectric layer structure 400 terminates at an inclined surface 403 of the dielectric layer structure 400 along the crack stop structure 300.In FIG. 6, the combined vertical extension w 34 of the crack stopper structure 300 and the dielectric layer structure 400 is less than half of the recess width (w 3+w 4<0.5·w 0), and the vertical extension w 4 of the dielectric layer structure 400 is less than the vertical extension w 3 of the crack stopper structure 300 (w 4<w 3). Each horizontal plane 800 in the dielectric layer structure 400 intersecting the lateral chip edge 109 terminates at an inclined surface 403 of the dielectric layer structure 400 along the crack stop structure 300.In FIG. 7, the combined vertical extension w 34 of the crack stopper structure 300 and the dielectric layer structure 400 is less than half of the recess width (w 3+w 4<0.5·w 0), and the vertical extension w 4 of the dielectric layer structure 400 is greater than the vertical extension w 3 of the crack stopper structure 300 (w 4>w 3). Each horizontal plane 800 in the dielectric layer structure 400 intersecting the lateral chip edge 109 at the height of the dielectric layer structure 400 terminates at an inclined surface 403 of the dielectric layer structure 400 along the crack stop structure 300 or an inclined surface 403 of the slot 212 formed by the dielectric layer structure 400 above the recess 211.In each of FIG. 6 and FIG. 7, the vertical extension of the slot 212 is greater than a vertical extension w 4 of the dielectric layer structure 400, such that a portion of the top surface 401 of the dielectric layer structure 400 directly above the depression 211 is closer to the first main surface 101 ("deeper") than the horizontal top surface 301 of the crack stop structure 300. In this way, the slits 212 may help to a greater extent prevent the propagation of various types of cracks into the central region 610.When the vertical extension w 2 of the interlayer dielectric 200 is greater than the combined vertical extension w 34 of the crack stop structure 300 and the dielectric layer structure 400, as illustrated in FIGS. 6 and 7, the probability that different types of cracks generated at the lateral chip edge 109 in the dielectric layer structure 400 end at one of the sidewalls of the slot 212 is high. This applies independently of a relationship between the vertical extent w 4 of the dielectric layer structure 400 and the vertical extent w 3 of the horizontal regions of the crack stop structure 300, as illustrated in FIG. 7.FIG. 8 shows a crack stop structure 300 comprising a third region 330 formed on the interlayer dielectric 200 in the perimeter region 690.The first and second regions 310, 320 may have any of the configurations as described with reference to FIGS. 2 to 7. The third region 330 is structurally and electrically separated from the first region 310 and the second region 320 of the crack stop structure 300. The third region 330 is also electrically separated from the semiconductor region 100 and floating.FIG. 8 shows the third region 330 between the first region 310 and the lateral chip edge 109, but the third region 330 may just as well be between the first region 310 and the central region 610. The third region 330 has the same vertical extent w 3 as the second region 320. The first region 310, the second region 320, and the third region 330 are different portions of the same metallization layer. A lateral distance between the second region 320 and the third region 330 is large enough that a further slot 412 extends from the front side into the dielectric layer structure 400 between the second region 320 and the third region 330. The third region 330 laterally surrounds the central region 610.The dielectric layer structure 400 comprises a first sub-layer 410 formed directly on the interlayer dielectric 200 and the crack stop structure 300 and a second sub-layer 420 formed on the first sub-layer 410. The first sub-layer 410 comprises or consists of doped silicate glass, e.g. PSG. The second sub-layer 420 includes silicon and nitrogen as main components, e.g., Si 3 N 4.A gap 411 extends through the dielectric layer structure 400 over the third region 330 of the crack stop structure 300. The gap 411 exposes a portion of the horizontal top surface 301 of the third portion 330 of the crack stopping structure 300. The gap 411 and the third region 330 of the crack stop structure 300 supplement one another to form a vertically extended crack stop, which destroys the interlayer dielectric 200 and the dielectric layer structure 400. Any type of linear, non-linear, planar or non-planar crack which arises at the lateral chip edge 109 in the interlayer dielectric 200 or the dielectric layer structure 400 and propagates inwards ends at a sidewall of the gap 411 or at an inclined surface of the third region 330.If a high voltage is applied between the semiconductor region 100 and an exposed conductive structure in the central region 610 during a wafer level test, the dielectric layer structure 400 prevents an electrical breakdown by air between the first and the second region 310, 320 of the crack stop structure 300 on the one hand and the exposed conductive structures on the other hand. Since the third region 330 of the crack stop structure 300 is electrically separated from the potential of the semiconductor region 100, there is no electric breakdown through the gap 411.FIGS. 9A to 9D illustrate a method for manufacturing a semiconductor device 900 as shown in one of FIGS. 1A to 8. The semiconductor devices 900 having one of the crack stop structures 300 of FIGS. 1A to 8 may be manufactured based on the method illustrated in FIGS. 9A to 9D.An SOI substrate 990 includes a plurality of chip regions 600 separated by a grid-shaped dicing region 700. The SOI substrate 900 may include a substrate layer, an insulator layer, and a semiconductor layer (device layer). The insulator layer may be a silicon oxide layer that isolates the device layer from the substrate layer. The substrate layer may be a monocrystalline silicon layer. A thickness of the substrate layer may be in a range of 20 μm to 200 μm. The device layer may be a monocrystalline silicon layer. The device layer may have a thickness of 100 nm to 250 nm.Each die area 600 includes a central area 610 and an edge area 690, wherein the edge area 690 surrounds the central area 610 and separates the central area 610 from the adjacent dicing area 700. The central region 610 includes laterally separated application device regions 611. Dicing region 700 includes laterally separated tester regions 711.The SOI substrate 990 includes a continuous semiconductor region 100 forming a uniform thickness substrate layer that forms the common base for all die regions 600. In each application device region 611 and test device region 711, the SOI substrate 990 includes a semiconductor layer 120 and an insulator layer 110 separating the semiconductor layer 120 and the semiconductor region 100. The semiconductor layer 120 or the semiconductor layer 120 and the insulator layer 110 are absent in the illustrated portion of the edge region 690.The illustrated test device region 711 includes a field effect transistor having source and drain regions formed in the semiconductor layer 120. A gate dielectric 720 is formed on the semiconductor layer 120 and separates the semiconductor layer 120 and a gate electrode 730 formed on the gate dielectric 720. Field oxide structures 750 may be formed in the first main surface 101 along lateral edges of laterally separated regions of the insulator layer 110.The illustrated application device region 711 includes a semiconductor element having doped regions formed in the semiconductor layer 120.One or more dielectric materials are deposited on the SOI substrate 990 to form one or more dielectric layers. The deposited materials are patterned by a photolithography process to form an interlayer dielectric 200, wherein openings are formed in the interlayer dielectric 200.FIG. 9A shows the patterned interlayer dielectric 200. In the application device region 611, regions of the interlayer dielectric 200 are formed directly on the semiconductor layer 120. In the test device regions 711, regions of the interlayer dielectric 200 are formed directly on the field oxide structures 750, the semiconductor layer 120, the insulator layer 110 and the gate electrode 730.The openings in the interlayer dielectric 200 comprise a recess 211 extending through the interlayer dielectric 200 in the edge region 690 and exposing a contact portion 104 of the first main surface 101 and a contact trench 221 extending through the interlayer dielectric 200 in the central region 610 and exposing a contact portion of the semiconductor layer 120.One or more conductive materials are deposited on the interlayer dielectric 200 to form a continuous metallization layer 390. The conductive material may comprise or consist of aluminum.FIG. 9B shows the continuous metallization layer 390 lining the recess 211 and the contact trench 221 and covering the contact portion 104 of the first main surface 101 and the contact portion of the semiconductor layer 120. Additionally, the continuous metallization layer covers a horizontal top surface 201 of the interlayer dielectric 200. Horizontal portions of the continuous metallization layer 390 have the same, uniform vertical extension.The continuous metallization layer 390 is patterned by a photolithography process to form a crack stop structure in the edge region 690 and a contact structure in the application device region 611, wherein the contact structure in the central region 610 and the crack stop structure in the edge region 690 are simultaneously formed from different portions of the continuous metallization layer 390 of FIG. 9B.As illustrated in FIG. 9C, the crack stop structures 300 in the edge region 690 include a first region 310 formed in the recess 211 and a second region 320 formed outside the recess 211. Vertical regions of the crack stop structure 300 formed along the recess sidewalls connect horizontal regions of the crack stop structure 300 on the contact portion 104 and the horizontal top surface 201 of the interlayer dielectric 200.Accordingly, the contact structure 350 in the central region 690 includes a first region formed in the contact trench 221 and a second region formed outside the contact trench 221. Vertical regions of the contact structure 350 formed along the contact trench sidewalls connect horizontal regions of the contact structure 350 on the contact portion of the semiconductor layer 120 and the horizontal top surface 201 of the interlayer dielectric 200.One or more dielectric materials are deposited to form one or more dielectric layers. The deposited materials are patterned by a photolithography process to form a dielectric layer structure 400, the photolithography process defining openings in the dielectric layer structure 400. The openings in the dielectric layer structure 400 expose conductive structures.According to FIG. 9D, the dielectric layer structure 400 covers the interlayer dielectric 200 and the crack stop structure 300 in the edge regions 690. A first opening 391 in the dielectric layer structure 400 exposes the contact structure 350 in the application device region 611. A second opening 392 in the dielectric layer structure 400 extends through the interlayer dielectric 200 and exposes the gate electrode 730 in the test device region 711 of the dicing region 700.A wafer level test is performed. Probes contact a back side of the semiconductor portion 100, the gate electrodes 730 and the contact structures 350. When a high voltage is applied through the test needles between the semiconductor region 100 and the contact structure 350, the dielectric layer structure 400 prevents an electrical breakdown by air between the crack stop structure 300 and the contact structure 350.A mechanical dicing process separates the die regions 600 by sawing or scribing and breaking the SOI substrate along dicing streets in the dicing region 700. The mechanical dicing process removes at least a portion of the material in the dicing region 700. The crack stop structure 300 prevents cracks generated by the dicing process in the interlayer dielectric 200 and / or the dielectric layer structure 200 from reaching the central region 610.

Claims

A semiconductor device (900) comprising: a semiconductor region (100) comprising a central region (610) and an edge region (690) separating the central region (610) from a lateral chip edge (109); an interlayer dielectric (200) formed on a horizontal first main surface (101) of the semiconductor region (100), wherein in the edge region (690) a recess (211) extends through the interlayer dielectric (200) downwardly to the first main surface (101), wherein the recess (211) forms a closed frame around the central region (610); a crack stopping structure (300) comprising a first region (310) formed in the recess (211), wherein the crack stopping structure (300) is in direct contact with the semiconductor region (100) at the bottom of the recess (211), forms a continuous frame, and laterally surrounds the central region (610); A dielectric layer structure (400) formed on the interlayer dielectric (200) and the crack stop structure (300), wherein the dielectric layer structure (400) and the crack stop structure (300) are configured such that each horizontal plane (800) intersecting the dielectric layer structure (400) and the chip side edge (109) intersects an inclined surface (403) of the dielectric layer structure (400) in the edge region (690), and wherein the dielectric layer structure (400) completely covers a portion of the crack stop structure (300) in direct contact with the semiconductor region (100).The semiconductor device according to the preceding claim, wherein the crack stopper structure (300) is formed of a conductive material.The semiconductor device of any of the preceding claims, wherein the crack stopping structure (300) comprises a second region (320) formed on the interlayer dielectric (200), and wherein the first region (310) and the second region (320) are connected.The semiconductor device of any of the preceding claims, wherein a width w0 of the recess (211) and vertical extents w2, w3, w4 of horizontal areas of the interlayer dielectric (200), the crack stop structure (300) and the dielectric layer structure (400) are selected such that each horizontal plane (800) intersecting the dielectric layer structure (400) and the lateral chip edge (109) intersects an inclined surface (403) of the dielectric layer structure (400) in the edge region (690) at a distance from the lateral chip edge.The semiconductor device according to any one of the preceding claims, wherein a difference between a maximum vertical distance wx between a top surface (401) of the dielectric layer structure (400) and the first main surface (101) and a minimum vertical distance wy between the top surface (401) of the dielectric layer structure (400) and the first main surface (101) is greater than a maximum thickness w4 of the dielectric layer structure (400).The semiconductor device according to any one of the preceding claims, wherein a width w0 of the recess (211) is wide enough that the dielectric layer structure (400) forms steps directly above the bottom of the recess (211).The semiconductor device according to the preceding claim, wherein a step height of the steps formed by the dielectric layer structure (400) is greater than a vertical extension w4 of the dielectric layer structure (400).The semiconductor device of any of the preceding claims, wherein the crack stopping structure (300) comprises a third region (330) formed on the interlayer dielectric (200) in the peripheral region (690), the third region being separated from the first region (310).The semiconductor device of the preceding claim, wherein a gap (411) extends through the dielectric layer structure (400) over the third region (330) of the crack stop structure (300).The semiconductor device according to any one of the two preceding claims, wherein a vertical extension w4 of a horizontal portion of the dielectric layer structure (400) is greater than a vertical extension w3 of a horizontal portion of the crack stopping structure (300).The semiconductor device of any of the three preceding claims, wherein the third region (330) laterally surrounds the central region (610).A method of manufacturing a semiconductor device (900), the method comprising: forming an interlayer dielectric (200) on a first main surface (101) of a semiconductor region (100), the semiconductor region (100) comprising a central region (610) and an edge region (690) laterally surrounding the central region (610); forming a recess (211) extending in the edge region (690) through the interlayer dielectric (200) down to the first main surface (101), the recess (211) forming a closed frame around the central region (610); forming a crack stop structure (300) comprising a first region (310) formed in the recess (211), wherein the crack stop structure (300) at the bottom of the recess (211) is in direct contact with the semiconductor region (100), forms a continuous frame, and laterally surrounds the central region (610); and forming a dielectric layer structure (400) covering the interlayer dielectric (200) and completely covering a region of the crack stop structure (300) in direct contact with the semiconductor region (100).The method of the preceding claim, further comprising: forming a conductive structure (350) in the central region (610), wherein a metallization layer is deposited on the interlayer dielectric (200) and patterned to simultaneously form the conductive structure in the central region (610) and the crack stop structure (300) in the edge region (690) from portions of the metallization layer.

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