METAL OXIDE SEMICONDUCTORS AND MANUFACTURING PROCESSES

Abstract

Semiconductor structure (200A, 200B), comprising: a substrate (10); and a capacitor above the substrate (10), comprising: a silicide layer (26) over the substrate (10); a first dielectric layer (32) above the silicide layer (26); a metal gate structure (36) above the first dielectric layer, wherein an upper section of the metal gate structure (36) is located above the substrate (10) and a lower section of the metal gate structure (36) projects into the substrate (10); a second dielectric layer (46) over the metal gate structure (36); and a conductive structure (48) above the second dielectric layer, wherein the substrate (10) has: a doped region surrounding the lower section (35A-C) of the metal gate structure (36); and Source / drain regions (22) arranged in the doped region, wherein the lower section of the metal gate structure (36) is arranged between the source / drain regions (22), and wherein the silicide layer (26) extends over the source / drain regions (22).

Description

BACKGROUND

[0001] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a wide variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density has mostly resulted from repeated reductions in the minimum feature size, allowing more components or devices to be integrated into a given area or device. While existing strategies for integrating capacitive devices, such as metal-oxide-semiconductor-supported (MOS-supported) capacitors, have generally been adequate, they have not been entirely satisfactory in all aspects. For example, improving device performance at smaller length scales to meet various goals for modern devices remains a challenge.

[0002] US 2007 / 0057343A1 discloses a metal-insulator-metal (MIM) capacitor on a semiconductor substrate. The base consists of a semiconductor substrate with a top surface and surface areas selected from a shallow trench insulation (STI) region and a doped well with coplanar outer surfaces to the semiconductor substrate. An additional MIM capacitor plate is either a bottom electrode on the STI region in the semiconductor substrate or a doped well in the top surface of the semiconductor substrate. A high-k (HiK) dielectric capacitor layer is formed on or above the bottom MIM capacitor plate. A second MIM capacitor plate is formed on the high-k dielectric layer above the bottom MIM capacitor plate.

[0003] US 2013 / 0175666A1 discloses semiconductor devices with an integrated capacitor. In one implementation, the semiconductor devices comprise a substrate with a dopant material of a first conductivity type. Several trenches are formed within the substrate. The semiconductor devices also include a diffusion region with a dopant material of a second conductivity type, which is formed near the trenches. A capacitor is formed within the trenches and at least partially over the substrate. The capacitor comprises at least a first electrode, a second electrode, and a dielectric formed between the first and second electrodes.

[0004] DE 11 2014 000 519 T5 describes a method for manufacturing an integrated circuit, comprising: depositing a first dielectric layer; depositing a masking layer of a self-organizing material over the first dielectric layer; structuring the masking layer, wherein the structuring comprises a non-ablative process which causes the masking layer to self-organize into separate structures; structuring the first dielectric layer using the structured masking layer and depositing a metal-insulator-metal (MIM) capacitor over the structured first dielectric layer, wherein the structured first dielectric layer has a substantially ribbed profile, comprising at least one recess having a topography that is itself ribbed.

[0005] US 2013 / 0178021A1 discloses: A transistor region of a first semiconductor layer and a capacitor region within the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. The first and second regions of the second semiconductor layer are located in the transistor region, and a third region of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third regions of the second semiconductor layer, respectively. After the formation of a dielectric layer, the dummy gate structure is removed, creating a first cavity. At least one region of the dielectric layer above the third silicide region is removed, creating a second cavity.A gate dielectric is formed in the first cavity and a capacitor dielectric in the second.

[0006] US 2018 / 0076040A1 discloses a method for forming pure silicon oxide layers on silicon-germanium (SiGe) layers and a FET device with a pure silicon oxide interface layer of a metal-gate structure on a SiGe channel layer of the FET device. For example, one method comprises growing a first silicon oxide layer on the surface of a SiGe layer by means of a first oxynitriding process, wherein the first silicon oxide layer contains nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer by means of a second oxynitriding process, which is essentially the same as the first oxynitriding process, wherein the second silicon oxide layer is essentially free of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer, and the second silicon oxide layer comprises a pure silicon dioxide layer.

[0007] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. In fact, the dimensions of the various elements may have been enlarged or reduced as appropriate for clarity of description. The Fig. 1, Fig. 5 and Fig. Figure 6 each shows a schematic top view of an exemplary semiconductor device according to some embodiments. The Fig. 2 and Fig. Figure 3 each shows a schematic cross-sectional view of the exemplary semiconductor device of Fig. 1 along line AA' according to some embodiments. Fig. Figure 4 shows a schematic cross-sectional view of the exemplary semiconductor device of Fig. 1 along line BB' according to some embodiments. Fig. Figure 7 shows a schematic cross-sectional view of the exemplary semiconductor device of the Fig. 5 or Fig. 6 along line CC' according to some embodiments. Fig. Figure 8 shows a schematic cross-sectional view of the exemplary semiconductor device of the Fig. 5 or Fig. 6 along line CC' according to some embodiments. Fig. Figure 9 shows a schematic cross-sectional view of the exemplary semiconductor device of the Fig. 5 or Fig. 6 along line CC' according to some embodiments. The Fig. 10A, Fig. 10B and Fig. Figures 10C each show a flowchart of an exemplary process for manufacturing a semiconductor device according to some embodiments. The Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22 and Fig. Figures 23 each show a schematic cross-sectional view of an exemplary semiconductor device during intermediate stages of the exemplary process of the Fig. 10A, Fig. 10B and / or 10C according to some embodiments. DETAILED DESCRIPTION

[0009] The following disclosure provides many different embodiments or examples for implementing various features of the specified subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first element over or on top of a second element in the following description may cover embodiments in which the first and second elements are in direct contact, and may also cover embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various described embodiments and / or configurations.

[0010] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and similar terms can be used here for the sake of simplicity to describe the relationship of an element or section to one or more other elements or sections, as shown in the figures. These spatially relative terms are intended to cover various orientations of the device used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative terms used here can be interpreted accordingly.

[0011] This disclosure specifies metal oxide semiconductor devices (MOS devices) such as MOS capacitors and their manufacturing processes. Intermediate stages in the fabrication of various embodiments of this disclosure are shown. In the different views and exemplary embodiments of this disclosure, the same reference numerals are used to denote identical elements.

[0012] Fig. Figure 1 shows a top view of an embodiment of a semiconductor structure 200A. The semiconductor structure 200A includes a device area 202A and a device area 204A, wherein the device area 202A comprises several semiconductor devices 100A and the device area 204A comprises several semiconductor devices 150. In the present embodiments, the semiconductor devices 100A include MOS devices such as MOS capacitors, MOS transistors, the like, or combinations thereof. In some embodiments, the semiconductor devices 100A include MOS capacitors, which are arranged in an array within the semiconductor structure 200A. In some embodiments, the semiconductor devices 150 include, for example, logic devices connected to the array of semiconductor devices 100A.

[0013] Each semiconductor device 100A has a first region R1 surrounded by a second region R2, wherein regions R1 and R2 have different structures, as described in detail below. The first region R1 has at least one conductive structure (e.g., a conductive structure 48) over a substrate (e.g., a substrate 10), and the second region R2 has another metal structure (e.g., a metal structure 36) over the substrate. It should be noted that parts of the semiconductor structure 200A have been omitted from the following figures for clarity. For example, active elements (e.g., metal gate structures) of the semiconductor structure 200A adjacent to an interlayer dielectric (ILD) layer have been omitted.

[0014] Referring to Fig. 2, which shows a cross-sectional view of the first region R1 of the semiconductor device 100A along the line AA' of Fig. As shown in Figure 1, the semiconductor device 100A is positioned above a substrate 10 and separated (or isolated) by insulating structures 12. The substrate 10 comprises a semiconductor substrate, for example, a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 10 may consist of a wafer, for example, a silicon wafer. In general, an SOI substrate has a layer of semiconductor material formed on an insulating layer. The insulating layer may consist, for example, of a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, usually a silicon or glass substrate. Other substrates may also be used, for example, multilayer or gradient substrates.In some embodiments, the semiconductor material of substrate 10 may include silicon; germanium; a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0015] In some embodiments, the substrate 10 contains an intrinsic semiconductor material, for example, intrinsic silicon. In other embodiments, the substrate 10 contains a semiconductor material doped with a suitable dopant corresponding to a conductivity type of the semiconductor device 100A. For example, if the semiconductor device 100A is configured as an n-device, the substrate 10 may contain an n-type dopant. Exemplary n-type dopants include phosphorus, arsenic, the like, or combinations thereof, and exemplary p-type dopants include boron, gallium, indium, the like, or combinations thereof.

[0016] Referring to Fig. 2 The semiconductor device 100A has a doped well 14 arranged above or within the substrate 10, wherein the doped well 14 contains a dopant whose conductivity type differs from that of the semiconductor device 100A. For example, if the semiconductor device 100A is configured as an n-type device, the doped well 14 contains a p-type dopant. In some embodiments, the doped well 14 extends over the entire substrate 10 and is configured as the doped substrate of the semiconductor device 100A.

[0017] The semiconductor device 100A has a doped layer (or impurity layer) 20 in the doped well 14. In the illustrated embodiments in which the semiconductor device 100A is configured as an n-type device, the doped layer 20 contains an n-type dopant. In embodiments in which the semiconductor device 100A is configured as a p-type device, the doped layer 20 contains a p-type dopant. In the present embodiments, the doped layer 20 is a heavily doped layer containing an n-type dopant.

[0018] With reference to the Fig. 1 and Fig. 2 The semiconductor device 100A is surrounded by insulating structures 12. In some embodiments, each insulating structure 12 separates two adjacent doped layers and / or conductive elements in the substrate 10. In some embodiments, the insulating structure 12 comprises at least one dielectric layer with an oxide, such as silicon oxide (SiO₂ and / or SiO₂), a nitride, the like, or combinations thereof. In some embodiments, the insulating structure 12 comprises a shallow trench insulation (STI) structure.

[0019] In some embodiments, the semiconductor device 100A further comprises doped layers 11 adjacent to the insulating structures 12. The doped layers 11 contain one or more dopants with the same conductivity as the doped well 14, but in a higher concentration. For example, in the embodiments shown, the doped well 14 contains a p-type dopant in a first concentration, and the doped layers 11 contain the p-type dopant in a second concentration higher than the first. In some embodiments, the doped layers 11 provide sites for connecting the substrate 10 and / or the doped well 14 to a contact 50, which forms a substrate contact for the MOS capacitor structure of the semiconductor device 100A. In some embodiments, the doped layers 11 are optional and are omitted from the semiconductor device 100A.

[0020] Still referring to Fig. Figure 2 of the semiconductor device 100A has a pair of source / drain regions 22 in the doped layer 20. The source / drain regions 22 each contain a dopant suitable for forming the semiconductor device 100A of a specific conductivity type. For example, to form an n-type semiconductor device 100A, the source / drain regions 22 in the illustrated embodiments contain an n-type dopant. In the present embodiments, the source / drain regions 22 each contain a dopant of the same conductivity type as the doped layer 20, but in a different concentration. For example, the concentration of the n-type dopant in the source / drain regions 22 is higher than in the doped layer 20, for example by at least one order of magnitude.

[0021] In some embodiments, the source / drain regions 22 are formed adjacent to the insulating structures 12, with a lower surface of each insulating structure 12 extending vertically to below a lower surface of each source / drain region 22. In this respect, the source / drain regions 22 are electrically isolated by the insulating structures 12 from an adjacent device (e.g., another semiconductor device 100A in the array of semiconductor structure 200A).

[0022] The semiconductor device 100A further comprises a silicide layer 26 that extends laterally over an upper surface of the doped layer 20, including an upper surface of each of the source / drain regions 22. In other words, sidewalls of the silicide layer 26 essentially coincide with sidewalls of the doped layer 20 that are spaced laterally along the x-axis. As shown in Fig. As shown in Figure 2, the silicide layer 26 lies completely over an upper surface of the doped layer 20. In the illustrated embodiments, the silicide layer 26 is arranged laterally between two opposing insulating structures 12. In the present embodiments, the silicide layer 26 comprises a metal silicide material with at least one metal selected from Ti, W, Mo, Ni, Co, or the like. Other silicide materials may also be applicable to the present disclosure.

[0023] Still referring to Fig. 2 The semiconductor device 100A further comprises a stack S1 of dielectric layers and conductive layers (or metal structures) above the silicide layer 26. In the present embodiments, the stack S1 includes a first dielectric layer 32, the metal structure 36, an interface layer 44, a second dielectric layer 46, and the conductive structure (e.g., metal structure) 48, which are stacked vertically along the Z-axis in that order above the silicide layer 26. In the present embodiments, the stack S1 lies entirely above the top surface of the doped layer 20. In other words, a bottom surface of the stack S1, i.e., the first dielectric layer 32, lies entirely above the top surface of the doped layer 20.

[0024] The semiconductor device 100A has gate spacers 38 extending along side walls of the stack S1. The gate spacers 38 can contain a suitable dielectric, such as silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof. The gate spacers 38 can have one or more layers of suitable dielectrics.

[0025] In the present embodiments, the stack S1 has a first dielectric layer 32 above the silicide layer 26. In these embodiments, the first dielectric layer 32 extends laterally over a portion of the silicide layer 26 located between the source / drain regions 22. In some embodiments, the first dielectric layer 32 is configured as a gate dielectric layer. Thus, the first dielectric layer 32 can contain any suitable dielectric, for example, silicon oxide, silicon nitride, a high-k dielectric (i.e., with a higher relative permittivity than that of silicon oxide, which is about 3.9), the like, or combinations thereof. The high-k dielectric can include an oxide or silicate of Hf, Al, Y, Zr, La, Mg, Ba, Ti, Pb, the like, or combinations thereof. The high-k dielectric can additionally or alternatively include a composite oxide such as a compound of ZrO₂, Al₂O₃, and ZrO₂ (Za A b Z c , where a, b and c satisfy a suitable stoichiometric ratio), a compound of Al2O3, ZrO2, Al2O3 (A a Z b A c , where a, b and c satisfy a suitable stoichiometric ratio) or a compound of ZrO2, Al2O3, ZrO2, Al2O3, ZrO2 (Z a A b Z c A d Z e , where a, b, c, d and e satisfy a suitable stoichiometric ratio). In some embodiments, the first dielectric layer 32 has a multilayer structure.

[0026] Stack S1 has a metal structure 36 above the first dielectric layer 32. In the present embodiments, the metal structure 36 is configured as a metal gate structure. Accordingly, the metal structure 36 has at least one metal gate electrode. In some embodiments not shown separately, the metal gate structure further has one or more exit work metal layers, each containing a composite metal or a single metal. The metal gate electrode contains any suitable metal, such as tungsten (W), copper (Cu), ruthenium (Ru), aluminum (Al), gold (Au), cobalt (Co), the like, or combinations thereof. The exit work metal layer can contain an n-type exit work metal with a work function in the range of about 3.9 to about 4.5, a p-type exit work metal with a work function in the range of about 4.5 to about 5.2, or a combination thereof.The exemplary exit work layers include TiN, TaN, Ru, Mo, Al, W, HfN, Ir, Pt, PtSi, MoN, ZrSi2, MoSi2, NiSi. X , WN, Ti, Ta, Ag, TaSi X , TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr and the like. The metal gate electrode can be formed over one or more exit work metal layers. In some embodiments, the metal structure 36 does not have an exit work metal layer. Thus, the metal structure 36 has only the metal gate electrode. In some embodiments, the metal structure 36 has additional layers, such as a cover layer, an adhesive layer, the like, or combinations thereof.

[0027] Stack S1 further comprises an interface layer 44 and a second dielectric layer 46 above the metal structure 36. In the present embodiments, the interface layer 44 and the second dielectric layer 46 are each formed in a U-shape, having sidewalls that extend along the gate spacers 38. In other words, the sidewalls of the interface layer 44 are vertically aligned with sidewalls of the metal structure 36.

[0028] In some embodiments, the second dielectric layer 46 is configured as a gate dielectric layer. Thus, the second dielectric layer 46 can contain any suitable dielectric, for example, silicon oxide, silicon nitride, a high-k dielectric specified herein, the like, or combinations thereof. In some embodiments, the second dielectric layer 46 has the same composition as the first dielectric layer 32. In some embodiments, the second dielectric layer 46 has a different composition than the first dielectric layer 32. In some embodiments, the interface layer 44 contains an oxide, for example, silicon oxide. In the present embodiments, the interface layer 44 contains a dielectric with a lower dielectric constant (i.e., a lower k-value) than a dielectric contained in the second dielectric layer 46.For example, the interface layer 44 can contain silicon oxide, which has a relative dielectric constant of less than about 3.9, and the second dielectric layer 46 can contain a high-k dielectric, for example a metal oxide or a metal silicide, which has a relative dielectric constant of more than about 3.9. In some embodiments, the interface layer 44 is optional.

[0029] Still referring to Fig. In the stack S1, a conductive structure 48 is located above the second dielectric layer 46, the second dielectric layer 46 surrounding the lower and sidewall surfaces of the conductive structure 48. In the embodiments shown, an upper surface of the conductive structure 48 is substantially coplanar with an upper surface of both the second dielectric layer 46, the interface layer 44, and the gate spacer 38. In some embodiments, the conductive structure 48 is configured as a metal gate structure, similar to the metal structure 36 described in detail above. For example, the conductive structure 48 has at least one metal gate electrode and one or more exit work metal layers, which were described in detail above with respect to the metal structure 36. In some embodiments, the conductive structure 48 has the metal gate electrode but no exit work metal layer.Accordingly, in some embodiments the conductive structure 48 is alternatively referred to as metal structure 48. In some embodiments, the conductive structure 48 contains conductive polysilicon instead of a metal.

[0030] In some embodiments, sections of the semiconductor device 100A in the first region R1 are different from those in Fig. 2 shown arranged. With reference to Fig. Figure 3 shows that the semiconductor device 100A has a stack S2 arranged similarly to stack S1. In stack S2, the interface layer 44 and the second dielectric layer 46 do not contain sections extending along the gate spacers 38, so their sidewalls are vertically aligned with those of the metal structure 36 and the conductive structure 48. Furthermore, the gate spacers 38 are configured to surround only the sidewalls of the metal structure 36, and additional gate spacers 39 are configured to extend along the sidewalls of stack S2, including those of the interface layer 44, the second dielectric layer 46, and the conductive structure 48. As shown, the gate spacers 38 and the gate spacers 39 are stacked together and vertically aligned to form gate spacers 40.

[0031] For example, in Fig. As shown in Figure 2, in the present embodiments, the connection of the silicide layer 26 and the stack S1 in the first region R1 of the semiconductor device 100A provides a MOS capacitor with an “M1I1M2I2M3” stack structure, where M1, M2, and M3 each denote a conductive plate (or conductive layer, metal layer, metal plate) and I1 and I2 each denote an insulator (or a dielectric layer). Accordingly, the semiconductor device 100A provides two MOS capacitors connected in parallel, a first capacitor M1I1M2 and a second capacitor M2I2M3. A total capacitance C comp The capacitance of the MOS capacitor provided in the first area R1 of the semiconductor device 100A is a sum of the capacitance of the first capacitor M1I1M2 and the capacitance of the second capacitor M2I2M3.

[0032] In the present embodiments, the conductive plate M1 corresponds to the silicide layer 26, the dielectric layer I1 corresponds to the first dielectric layer 32, the conductive plate M2 corresponds to the metal structure 36, the dielectric layer I2 corresponds to the second dielectric layer 46 (and the interface layer), and the conductive plate M3 corresponds to the conductive structure 48. In existing technologies, a MOS capacitor generally has an “MtIM2” structure, where “M1” typically corresponds to a semiconductor substrate of the MOS capacitor, “I” typically corresponds to an insulator (e.g., an oxide-containing gate dielectric layer), and “M2” typically corresponds to a metal gate structure. Accordingly, forming an additional insulator (e.g., the second dielectric layer 46 and / or the interface layer 44) and an additional conductive plate (e.g.,the conductive structure 48) in the stack S1 and the formation of a silicide layer (e.g. the silicide layer 26), below and in contact with the stack S1 means of increasing the capacitance of the MOS capacitor in a compact design, thereby improving the performance of the device without significantly increasing the planar dimensions of the device.

[0033] In some embodiments, the semiconductor device 100A further comprises several contacts in the first region R1, configured to connect components of the device to interconnect elements subsequently formed (not shown). For example, in Fig. As shown in Figure 2, the semiconductor device 100A can have source / drain contacts 54A and 54B, which are connected to a respective source / drain region 22, and gate contacts 58A and 58B, which are connected to the metal structure 36 and the conductive structure 48, respectively. In some embodiments, the source / drain contacts 54A and 54B are connected to the contact 50, which is electrically connected to the doped well 14 (e.g., the doped layers 11).

[0034] With reference to the Fig. 1 and Fig. 4, which shows a cross-sectional view of the second region R2 of the semiconductor device 100A along line BB' of Fig. As shown in Figure 1, the second region R2 has a stack S3 arranged above the silicide layer 26, wherein the stack S3 includes only the first dielectric layer 32 and the metal structure 36, but not the second dielectric layer 46, the interface layer 44, or the conductive structure 48. Thus, the stack S3 forms a MOS capacitor with a stack structure of M1IM2 with the silicide layer 26. In some embodiments, the stack S3 enables the connection of the gate contact 58A to the metal structure 36.

[0035] Fig. Figure 5 shows a top view of an embodiment of a semiconductor structure 200B. The semiconductor structure 200B includes a device area 202B and a device area 204B, wherein the device area 202B has several semiconductor devices 100B and the device area 204B has several semiconductor devices 150 as described above. In the present embodiments, the semiconductor devices 100B include MOS capacitors whose structure is similar to that of the semiconductor devices 100A described above.

[0036] Each semiconductor device 100B has a third region R3 surrounded by a fourth region R4, which differs in structure from the third region R3, similar to how the first region R1 is surrounded by the second region R2 in semiconductor device 100A. For example, in the Fig. 5 and Fig. Figure 7 shows a cross-sectional view of the third area R3 along line CC' of Fig. Figure 5 shows that the conductive structure 48 above the substrate 10 belongs to the third area R3 and the metal structure 36 above the substrate 10 belongs to the fourth area R4.

[0037] Unlike semiconductor device 100A, the third region R3 of semiconductor device 100B has several embedded structures 60A, 60B, and 60C in the doped layer 20, which are collectively referred to as embedded structures 60. With reference to the Fig. 5 and Fig. 7 Lower sections of the silicide layer 26 and lower sections of the stack S1, which include sections of the first dielectric layer 32 and the metal structure 36, extend into the doped layer 20 in such a way that they form the embedded structures 60. In this respect, the embedded structures 60 resemble columns that are enclosed in or surrounded by the doped layer 20.

[0038] In the present embodiments, the embedded structures 60A-60C provide additional surface area for at least one of the conductive plates M1, M2, and M3 in the MOS capacitor with the stacked structure M1I1M2I2M3, which is described in detail above. With reference to Fig. 7. The embedded structures 60, for example, increase the surface area of ​​the silicide layer 26, corresponding to M1, and of a metal structure 36, corresponding to M2. As described above, the total capacity C compThe capacitance of the MOS capacitor with the stack structure M1I1M2I2M3 is the sum of the capacitance of the first capacitor M1I1M2 and the capacitance of the second capacitor M2I2M3. Accordingly, the vertical extension of the silicide layer 26 and parts of the stack S1 into the doped layer 20, so that they form the embedded structures 60, increases the surface area of ​​the conductive plates M1 and M2, thereby increasing the capacitance of the first capacitor M1I1M2 and thus the total capacitance C. comp of the MOS capacitor with the stack structure M1I1M2I2M3 increased.

[0039] Still referring to Fig. In the embodiments shown, the embedded structures 60 each have a depth D1 along the Z-axis, a first width W1 along the X-axis, and a second width W2 along the Y-axis. In some embodiments, the depth D1 is significantly greater than at least the first width W1. In the present embodiments, the embedded structures 60 do not penetrate the doped layer 20, so that the depth D1 is less than the depth of the doped layer 20. In some examples, the depth D1 can be greater than 0 and less than about 300 nm. In some embodiments, the smaller of the first width W1 and the second width W2, also referred to as the critical dimension (CD) of the semiconductor device 100B, is at least about 40 nm.In some embodiments, the side walls of the silicide layer 26, the first dielectric layer 32, and the metal structure 36 in each embedded structure 60 are essentially vertical along the Z-axis, i.e., they exhibit little to no lateral deviations along the X-axis. In some embodiments, the increase in the total capacitance C. comp by adjusting the dimensions of the embedded structures 60. For example, increasing the depth D1, the first width W1, the second width W2, or any of their connections can increase the total capacity C. comp increase the MOS capacitor.

[0040] In some embodiments, the aspect ratio (AR), defined as the ratio of the depth D1 to the width W1 of each of the embedded structures 60, is approximately 1 to approximately 10. In some embodiments, increasing the AR of the embedded structure 60 generally results in a higher capacitance between the conductive plates M1 and M2 (i.e., the silicide layer 26 and the metal structure 36). However, if the AR is too high (e.g., significantly higher than approximately 10), it may become difficult to obtain trenches of the desired dimensions due to limitations associated with the photolithography and etching processes used to form such trenches.

[0041] In some embodiments, the depth D1 is greater than a depth D2 of the insulating structures 12, which is greater than a depth D3 of the source / drain regions 22. In some embodiments, the depth D1 may be less than the depth D2. In some embodiments, the embedded structures 60 are configured to have different depths (e.g., depths D1), different widths (e.g., first widths W1 and / or second widths W2), or both. Furthermore, although three embedded structures 60 are shown, the number of embedded structures 60 may vary between one and, inclusive, ten. In some embodiments, the number of embedded structures 60 is determined based on a width W3 of the stack S1 along the X-axis, with the embedded structures 60 being spaced apart along the width W3.A larger number of the embedded structures 60 can be used as long as the dimensions of each embedded structure 60 are permissible according to the design rules for a given width W3 of the stack S1 and are not too large to negatively affect the processes for manufacturing the components of the semiconductor device 100B, including, for example, a metal filling process (or deposition process).

[0042] In some embodiments, with reference to Fig. 5. The embedded structures 60 each have a column configuration, wherein the widths W1 and W2 are similar or substantially the same, such that the embedded structures 60 each have a square shape in plan view. In some embodiments, with reference to Fig. 6 The semiconductor device 100B includes embedded structures 61A, 61B, and 61C, which are collectively referred to as embedded structures 61 and each have a different configuration than the embedded structure 60. For example, the embedded structures 61 each have a bar configuration, with the second width W2 being significantly larger than the first width W1, so that the embedded structures 61 each have an elongated shape (e.g., a rectangular shape) in plan view. In this respect, the embedded structure 61 extends along a length of the conductive structure 48 (e.g., along the Y-axis in Fig. 6) extended and in the third area R3 along the width W3 of the conductive structure 48 (e.g. along the X-axis in Fig. 7) spaced apart. Since the embedded structures 60 and 61 are shown to have the same first width W1 as in the Fig. As shown in 5 or 6, it should be noted that Fig. Figure 7 also shows the embodiment of the semiconductor device 100B, which shows the embedded structures 61 in a cross-sectional view along line CC' of Fig. 6.

[0043] Fig. Figure 8 shows an embodiment of the semiconductor device 100B in area R3, which is described in Fig. The embodiment shown in 7 is similar. However, the embodiment shown in Fig. Figure 8 shows the semiconductor device 100B with additional gate spacers 39 extending from the gate spacers 38 and contacting the side walls of the interface layer 44, the second dielectric layer 64, and the conductive structure 48. In this respect, the Fig. 7 embodiment of the semiconductor device 100B shown analogous to the one in Fig. 2 embodiment of the semiconductor device 100A shown, and the one in Fig. The embodiment of the semiconductor device 100B shown in Figure 8 is analogous to the one in Figure 8. Fig. 3 shown embodiment of the semiconductor device 100A.

[0044] With reference to Fig. Figure 9, in some embodiments, features an embodiment of the semiconductor device 100B with embedded structures 62A, 62B, and 62C, collectively referred to as embedded structures 62, which are similar to the embedded structures 60, except that the surfaces of the doped layer 20 in contact with the embedded structures 62 exhibit roughness and waviness. In this respect, portions of the sidewalls of the silicide layer 26, the first dielectric layer 32, and the metal structure 36 in each of the embedded structures 62 extend laterally toward or diverge in that direction toward the doped layer 20, as shown in Figure 9. Fig. Figure 9 shows. In some non-restrictive examples, such an extension or deviation (e.g., along the X-axis) can be less than about 10% of a width W4 of the metal structure 36 in the embedded structure 62, where the width W4 is defined between two averaged lines extending vertically (e.g., along the Z-axis) through the surface roughness on the opposite sidewalls of the metal structure 36. In some embodiments, such surface roughness results in portions of the metal structure 36 being embedded in the first dielectric layer 32 along sidewalls of the embedded structures 62. In the present embodiments, the surface roughness of the embedded structures 62 is configured such that the surface areas of the conductive plates M1 and M2 are further increased, which together increases the capacitance of the first capacitor M1I1M2 compared to the embedded structures 60.

[0045] The Fig. Figures 10A to 10C show a flowchart of a method 300 for forming a semiconductor device 400 according to one or more embodiments of the present disclosure. The semiconductor device 400 may partially or completely resemble the semiconductor devices 100A and 100B described in detail above. In this respect, the method 300 is applicable for forming at least parts of the semiconductor devices 100A and 100B, for example, for forming the first region R1 of the semiconductor device 100A and the third region R3 of the semiconductor device 100B. In some embodiments, operations of the method 300 may be combined with cross-sectional views of the semiconductor device 400 in a plane defined by the X and Z axes at various manufacturing stages, as shown in the Fig. Figures 11 to 23 are shown and defined. It is noted that Process 300 serves only as an example and is not intended to limit the present disclosure. Accordingly, it should be clear that further processes before, during, and after Process 300 are defined. Fig. 10A to 10C may be provided and some further processes can only be briefly described here.

[0046] With reference to the Fig. 10A and Fig. In step 302, substrate 10 is provided for semiconductor device 400.

[0047] As in Fig. As shown in Figure 11, in some embodiments, in step 302, the doped well 14 is first formed in the substrate 10, wherein the doped well 14 contains a dopant whose conductivity type differs from that of the semiconductor device 400. Still with reference to the Fig. 10A and Fig. 11 The doped layer (or contaminant layer) 20 is subsequently formed in the doped tub 14 such that the doped tub 14 surrounds a lower surface and side wall surfaces of the doped layer 20.

[0048] In some embodiments, the doped layer 20 is formed by performing a series of structuring and doping processes. For example, a structured mask layer (not shown) can be formed over the doped well 14, exposing sections of the doped well 14. The structured mask layer can contain a photoresist material that can be structured using photolithography techniques. In general, photolithography techniques use a photoresist material that is deposited, irradiated (or exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material, forming the structured mask layer, protects the underlying material from subsequent processing steps such as doping or etching.The structured mask layer can alternatively or additionally contain a dielectric such as an oxide, which is structured, for example, by photolithography techniques. Subsequently, a doping process is carried out on the exposed sections of the doped well 14 to form the doped layer 20. The doping process can consist of an implantation process, a diffusion process, or the like. After the doping process is carried out, the structured mask is removed from the semiconductor device 400 by any suitable process such as plasma ashing or resist removal.

[0049] Still referring to Fig. In step 302, several insulating structures 12 are formed in the doped well 14 adjacent to the doped layer 20. The insulating structures 12 can be formed by structuring a mask layer (not shown) that exposes sections of the doped well 14 between adjacent doped layers 20. The mask layer can be structured by a photolithography process similar to the one described above for forming the doped layer 20, followed by an etching process in which the structured mask layer is used as an etching mask to form trenches (not shown) projecting into the doped well 14. The etching process can include dry etching, wet etching, reactive ion etching (RIE), the like, or combinations thereof. Subsequently, the at least one dielectric layer in the trenches is deposited by any suitable process, such as high-density plasma capillary deposition (HDPCVD), flowable capillary deposition (FCVD) (e.g.,CVD-assisted deposition of material, for example an oxide, in a remote plasma system, followed by an annealing or curing process to densify the deposited material into another material, rotational coating, the like, or combinations thereof. Other dielectrics and / or other formation processes can be used to form the insulating structures 12. Subsequently, a planarization process such as a chemical-mechanical polishing / planarization process (CMP process) can be carried out to remove excess material from the at least one dielectric layer. The structured mask layer can also be removed by the planarization process or by another suitable process.

[0050] In some embodiments, the doped layers 11 (see e.g. the) are subsequently placed in the doped well 14 next to the insulating structures 12. Fig. 2 to 4). The doped layers 11 can be formed by a series of structuring and doping processes similar to those described above with respect to the formation of the doped layer 20. In some embodiments, the doped layers 11 are omitted.

[0051] With reference to the Fig. 10A and Fig. In step 304, the source / drain regions 22 are formed in the doped layer 20. The source / drain regions 22 can be formed by any suitable doping process, such as an implantation process or a diffusion process. In some embodiments, a structured mask layer (not shown) is first formed over the substrate 10, exposing portions of the doped layer 20 that correspond to the locations of the source / drain regions 22. The method for forming the structured mask layer is similar to that described above regarding the structured mask layer used in forming the doped layer 20. Subsequently, a suitable doping process is performed to introduce the n-doper into the exposed portions of the doped layer 20, creating the source / drain regions 22.After the doping process has been carried out, the structured mask layer is removed by any suitable process described here.

[0052] Although not shown, in some embodiments the formation of the source / drain regions 22 involves a series of etching and epitaxial processes. For example, sections of the doped layer 20 corresponding to the locations of the source / drain regions 22 are first removed in an etching process (e.g., using a structured mask) to form source / drain depressions. Subsequently, one or more epitaxial processes are performed to grow the source / drain regions 22 within the source / drain depressions. The epitaxial growth processes can be implemented using any suitable process, such as metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid-phase epitaxy (LPE), gas-phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or combinations thereof.

[0053] With reference to the Fig. 10A and Fig. In step 306, trenches 24A, 24B and 24C are formed in the doped layer 20.

[0054] In the present embodiments, the grooves 24A-24C are formed in a region of the doped layer 20 along the X-axis between the source / drain regions 22, with each of the grooves 24A-24C being embedded in the doped layer 20. In this respect, the grooves 24A-24C do not extend through the entire thickness of the doped layer 20, so that a lower surface of each of the grooves 24A-24C is separated from the underlying doped basin 14 by a section of the doped layer 20.

[0055] In some embodiments, the trenches 24A-24C are designed such that they each have the first width W1 along the X-axis, the second width W2 along the Y-axis (see, for example, the Fig. 5 and Fig. 6) and have a depth D1 along the Z-axis. In some embodiments, the first width W1, also referred to as the critical dimension (CD) of the semiconductor device 400, is at least about 40 nm. In some embodiments, the trenches 24A-24C are configured to have different depths, different widths, or both. Although in Fig. Figure 12 further shows three trenches; the number of trenches can vary between one and ten inclusive. A higher number of trenches may be possible as long as the number of trenches is permissible according to design rules and is not so high as to negatively affect subsequent steps of the process 300, for example, a metal filling (or deposition) process. In some embodiments, the trenches 24A-24C are formed in a column configuration to support the embedded structures 60 as shown in Figure 12. Fig. 5 shown. In some embodiments, the trenches 24A-24C are formed in a beam configuration to support the embedded structures 61 as shown in Fig. 6 shown to produce.

[0056] The trenches 24A-24C can be formed by a series of structuring and etching processes. For example, a structured mask (not shown) with openings corresponding to the locations of the trenches 24A-24C is formed over the semiconductor device 400. The procedure for forming such a structured mask is similar to that described above with respect to the structured mask layer used in forming the doped layer 20. Sections of the doped layer 20 are then removed by a suitable etching process 502, for example, a dry etching process (or plasma etching process), using the structured mask layer as the etching mask. The duration of the etching process 502 can be controlled such that the trenches 24A-24C are formed to a depth of D1.After forming the trenches 24A-24C, the structured mask layer is removed from the semiconductor device 400 by a suitable process such as plasma ashing or resist peeling.

[0057] With reference to the Fig. 10A and Fig. 13 In step 308, the silicide layer 26 is formed above the doped layer 20 and the source / drain areas 22.

[0058] In the present embodiments, the silicide layer 26 is formed over the silicon-containing semiconductor surfaces of the semiconductor device 400. For example, the silicide layer 26 is formed over a top surface of the doped layer 20, sidewall and bottom surfaces of the doped layer 20 that are exposed in the grooves 24A-24C, and the source / drain regions 22. In this context, the silicide layer 26 is not formed over the insulating structures 12.

[0059] The silicide layer 26 can be formed by any suitable process. For example, the silicide layer 26 can be formed by depositing a metal-containing precursor in the presence of a gas using a suitable deposition technique such as CVD. In some embodiments, the deposition process is carried out at an elevated temperature. The metal-containing precursor can include TiCl4, WCl5, MoCl5, Ni(CO)4, Co2(CO6)[HCC(C(CH3)3)], the like, or combinations thereof, and the gas can include hydrogen (H2), argon (Ar), or a combination thereof. The deposited metal-containing precursor subsequently reacts with silicon in the doped layer 20 and the source / drain regions 22, forming the silicide layer 26. Any unreacted metal, such as Ti, W, Mo, Ni, Co, or the like, from the metal-containing precursor can be removed after completion of the silicide process.

[0060] With reference to the Fig. 10A and Fig. In step 310, the first dielectric layer 32 is formed over the substrate 10.

[0061] In the present embodiments, the first dielectric layer 32 is deposited as a covering layer (not shown) over the semiconductor device 400. For example, sections of the first dielectric layer 32 are formed over the silicide layer 26 both inside and outside the trenches 24A-24C. In this respect, the first dielectric layer 32 and the silicide layer 26 partially fill the trenches 24A-24C. The first dielectric layer 32 can be formed by any suitable deposition technique, such as chemical oxidation, thermal oxidation, CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), the like, or combinations thereof.

[0062] With reference to the Fig. 10A and Fig. In step 312, a dummy gate structure 35 is formed over the trenches 24A-24C, which includes the first dielectric layer 32 and a dummy gate electrode 33.

[0063] The dummy gate electrode 33 can contain any suitable material, for example a polysilicon layer, and can be configured as a covering layer (not shown) over the semiconductor device 400. In the present embodiments, the dummy gate electrode 33 completely fills the trenches 24A-24C, as shown in Fig. 14 shown.

[0064] The dummy gate electrode 33 and the first dielectric layer 32 are subsequently patterned to form the dummy gate structure 35. The dummy gate structure 35 can be formed by a series of patterning and etching processes similar to those used to form the trenches 24A-24C. For example, a patterned mask layer (not shown) is first formed as an etch mask over the dummy gate electrode 33. An etching process, such as a dry or wet etching process, is then implemented to remove portions of the dummy gate electrode 33 and the first dielectric layer 32 exposed by the patterned mask layer, leaving the dummy gate structure 35 over the doped layer 20. After the etching process is completed, the patterned mask layer is removed by a suitable process such as plasma ashing or resist removal.

[0065] In the present embodiments, the dummy gate structure 35 is inserted between the source / drain regions 22 and extends laterally (e.g., along the X-axis) over a width W3 across the trenches 24A-24C. Accordingly, the dummy gate structure 35 has an upper section 35D above lower sections 35A, 35B, and 35C, which correspond to the trenches 24A, 24B, and 24C, respectively. In this respect, the lower sections 35A-35C are extensions of the dummy gate structure 35 embedded in the doped layer 20.

[0066] With reference to the Fig. 10A and Fig. 14 In step 314, the gate spacers 38 are formed along side walls of the dummy gate electrode 33.

[0067] The gate spacers 38 can be formed by first depositing a dielectric layer conformally over the dummy gate structure 35 using a suitable deposition process such as thermal oxidation, CVD or the like, and subsequently removing sections of the dielectric layer using a suitable etching process such as a directed or anisotropic dry etching process, leaving the gate spacer 38 along sidewalls of the dummy gate structure 35.

[0068] With reference to the Fig. 10A and Fig. In step 316, an intermediate dielectric layer (ILD layer) 42 is formed over the dummy gate structure 35 and the source / drain areas 22.

[0069] The ILD layer 42 can contain any suitable dielectric, for example silicon oxide, a low-k dielectric, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), the like, or combinations thereof, and can be deposited by any suitable process such as CVD, PECVD, FCVD, or the like. Subsequently, a planarization process, such as a CMP process, is implemented to remove portions of the ILD layer 42 from an upper surface of the dummy gate structure 35, leaving the ILD layer 42 over the sidewalls of the gate spacers 38 and the upper surfaces of the source / drain regions 22.

[0070] In some embodiments, a contact etch stop layer (CESL; not shown) is formed over the semiconductor device 400 prior to the formation of the ILD layer 42. The ILD layer 42 and the CESL contain different materials to ensure etch selectivity between them in subsequent fabrication processes. The CESL can contain any suitable dielectric such as silicon nitride, silicon oxynitride, silicon oxide, the like, or combinations thereof, and can be formed by a suitable formation process such as CVD, ALD, PVD, the like, or combinations thereof.

[0071] With reference to the Fig. 10A and Fig. In step 318, the dummy gate structure 35 is removed from the semiconductor device 400, creating a gate trench 37 between the gate spacers 38.

[0072] In some embodiments, the dummy gate structure 35 is removed by one or more etching processes, such as a dry or wet etching process, to form the gate groove 37 between the gate spacers 38. In this context, the bottom sections 35A-35C are partially removed such that the first dielectric layer 32 is exposed in the grooves 24A-24C. In some embodiments, the first dielectric layer 32 is used as an etch stop layer when etching the dummy gate electrode 33. In the present embodiments, the first dielectric layer 32 remains in the grooves 24A-24C, as shown in Fig. 15 shown.

[0073] In some embodiments, the method 300 continues with the formation of the semiconductor device 400 by proceeding from step 318 to step 330 as in Fig. 10B shows the transition. With reference to the Fig. 10B and Fig. In step 330, the metal structure 36 is formed over the first dielectric layer 32 in such a way that it partially fills the gate trench 37.

[0074] In the present embodiments, lower sections of the metal structure 36 are formed above the first dielectric layer 32 such that they completely fill the trenches 24A-24C, while an upper section of the metal structure 36 is formed in the gate trench 37 without completely filling it. The lower sections of the metal structure 36, the first dielectric layer 32, and the silicide layer 26 in the trenches 24A-24C each form the embedded structures 60A-60C, similar to those described in Fig. Figure 7 is shown. In addition, sections of the metal structure 36 are formed above an upper surface of the ILD layer 42.

[0075] In the present embodiments, the metal structure 36 is configured as a metal gate structure. Accordingly, the metal structure 36 comprises at least one metal gate electrode. In some embodiments, the metal gate structure further comprises one or more exit work metal layers, each containing a composite metal or a single metal. Different layers of the metal structure 36 can be formed by any suitable deposition process, such as CVD, PVD, ALD, plating (e.g., electroplating, electroless plating, etc.), the like, or combinations thereof.

[0076] With reference to the Fig. 10B and Fig. In step 332, the second dielectric layer 46 is formed over part of the metal structure 36 in the gate trench 37.

[0077] In the present embodiments, the second dielectric layer 46 is deposited as a covering layer (not shown) over the semiconductor device 400. For example, sections of the second dielectric layer 46 are formed conformally over the metal structure 36 in the gate groove 37, and sections of the second dielectric layer 46 are formed over the ILD layer 42. In this respect, the second dielectric layer 46 and the metal structure 36 partially fill the gate groove 37, and sections of the second dielectric layer 46 are formed along sidewalls of the gate spacers 38. The second dielectric layer 46 can be formed by any suitable deposition technique, such as CVD, ALD, PVD, the like, or combinations thereof.

[0078] In some embodiments, the interface layer 44 is formed over the metal structure 36 before the second dielectric layer 46 is formed. Similar to the second dielectric layer 46, the interface layer 44 is deposited as a cover layer (not shown) over the semiconductor device 400, such that sections of the interface layer 44 conform to the metal structure 36 in the gate groove 37, and sections of the interface layer 44 are formed over the ILD layer 42. In this context, sections of the interface layer 44 are formed along the side walls of the gate groove 37 between the side walls of the second dielectric layer 46 and the side walls of the gate spacers 38. The interface layer 44 can be formed by any suitable deposition technique, such as CVD, ALD, PVD, the like, or combinations thereof.

[0079] With reference to the Fig. 10B and Fig. In step 334, a conductive structure 48 is formed over the second dielectric layer 46 in such a way that it fills the gate trench 37.

[0080] In some embodiments, the conductive structure 48 is configured as a metal gate structure, similar to the metal structure 36 described in detail above. In the present embodiments, the conductive structure 48 is formed as a covering layer (or multiple layers; not shown) over the semiconductor device 400. For example, sections of the conductive structure 48 are formed over the second dielectric layer 46 such that they completely fill the gate groove 37, and sections of the conductive structure 48 are formed over the second dielectric layer 46 on the top surface of the ILD layer 42. In this context, after the formation of the conductive structure 48, a CMP process is performed to planarize the conductive structure 48, the second dielectric layer 46, and the interface layer 44 with the top surface of the ILD layer 42, as shown in Fig. 17 shown. Accordingly, in the resulting stack S1, the second dielectric layer 46 and the interface layer 44 are configured to have a U-shape, each surrounding the bottom and sidewall surfaces of the conductive structure 48.

[0081] With reference to Fig. 18 In some embodiments, instead of forming the trenches 24A-24C in step 306, where the sidewalls of the trenches 24A-24C are essentially smooth and vertical, the trenches 25A-25C are formed in step 306 using an etching process 504 that differs from the etching process 502. For example, after forming a structured mask layer over the doped layer 20 between the source / drain regions 22, the etching process 504 is carried out using a periodically oscillating plasma of different composition to generate roughness along the sidewalls and bottom surface of the trenches 25A-25C. In some embodiments, the execution of the etching process 504 involves alternating applications of an etching gas (i.e., a first plasma) and a protective gas (i.e., a second plasma) over the semiconductor device 400.The etching gas is configured to remove portions of the doped layer 20 to form and deepen the trenches 25A-25C, while the protective gas is configured to deposit a polymeric (or passivating) layer over the etched surfaces (e.g., sidewall surfaces) of the trenches 25A-25C. The etching gas and the protective gas are applied cyclically to deepen the trenches 25A-25C, resulting in roughness on the surfaces exposed in the trenches 25A-25C. In some embodiments, the surface roughness increases the surface area of ​​the doped layer 20 exposed in the trenches 25A-25C, which in turn increases the surface area of ​​the embedded structures 62A-62C formed in the trenches 25A-25C, similar to the process described in [reference missing]. Fig. Semiconductor device 100B shown in 9.

[0082] Steps 308-318 and 330-334 are then carried out in a similar manner to those described above, resulting in a semiconductor device 400 having the embedded structures 62A-62C corresponding to the trenches 25A-25C, as shown in Fig. Figure 19 shows. In the present embodiments, the embedded structures 62A-62C, which are collectively referred to as embedded structure 62, each comprise the lower sections of the silicide layer 26, the first dielectric layer 32 and the metal structure 36.

[0083] In some embodiments, the method 300 continues with the formation of the semiconductor device 400 by proceeding from step 318 to step 350 as in Fig. 10C shows transitioning. With reference to the Fig. 10C and Fig. 20 In step 350, the metal structure 36 is formed over the first dielectric layer 32 in such a way that it completely fills the gate trench 37.

[0084] In the present embodiments, the metal structure 36 is formed in a process similar to that described above with respect to step 330. For example, the lower sections of the metal structure 36 are formed over the first dielectric layer 32 such that they completely fill the trenches 24A-24C, creating the embedded structures 60A-60C, each extending into the doped layer 20 and lying laterally between the source / drain regions 22. Unlike step 330, however, the upper section of the metal structure 36 completely fills the gate trench 37. In this respect, a process for depositing the metal structure 36 is terminated when a covering layer of the metal structure 36 (not shown) completely fills the gate trench 37. The metal structure 36 is subsequently planarized with the ILD layer 42 by a CMP process, as shown in Fig. 20 shown.

[0085] With reference to the Fig. 10C and Fig. In step 352, the second dielectric layer 46 is formed over the metal structure 36 and the ILD layer 42.

[0086] In the present embodiments, the second dielectric layer 46 is deposited as a covering layer over the metal structure 36 and the ILD layer 42. In some embodiments, the interface layer over the metal structure 36 and the ILD layer 42 is deposited before the second dielectric layer 46 is deposited. The second dielectric layer 46 and the interface layer 44 can be formed in a process similar to that described above with respect to step 332.

[0087] With reference to the Fig. 10C and Fig. In step 354, the conductive structure 48 is formed over the second dielectric layer 46, generating the stack S2. In the present embodiments, the conductive structure 48 is formed over the second dielectric layer 46 as a covering layer by a process similar to that described above with respect to step 334.

[0088] With reference to the Fig. 10C and Fig. 22 In step 356, the stack S2 is structured so that its side walls are aligned with those of the underlying metal structure 36.

[0089] In some embodiments, the stack S2, which comprises the conductive structure 48, the second dielectric layer 46, and the interface layer 44, is structured by a series of photolithography and etching processes. For example, a structured mask layer (not shown) with openings corresponding to the sections of stack S2 to be removed is formed over the semiconductor device 400. The method for forming such a structured mask layer is similar to that described above with respect to the formation of the doped layer 20. Sections of stack S2 are then removed by a suitable etching process, such as a dry etching process (or plasma etching process), using the structured mask layer as the etching mask. The etching process is terminated when the underlying ILD layer 42 has been exposed.After structuring the stack S2, the structured mask layer is removed from the semiconductor device 400 by any suitable process such as plasma ashing or resist peeling.

[0090] With reference to the Fig. 10C and Fig. In step 358, the gate spacers 39 are subsequently formed along the side walls of the structured stack S2, which includes the structured conductive structure 48, the structured second dielectric layer 46, and the structured interface layer 44, such that the gate spacers 39 extend vertically from the gate spacers 38. In this context, the gate spacer 38 and the gate spacers 39 are collectively referred to as the gate spacer 40.

[0091] In some embodiments, the gate spacers 39 are configured as a dielectric seal that surrounds the side walls of the structured conductive structure 48, the structured second dielectric layer 46, and the structured interface layer 44, thereby isolating the layers from subsequently formed elements. In this context, the gate spacers 39 can alternatively be referred to as a dielectric seal 39. In some embodiments, the gate spacers 39 and the gate spacers 38 have the same composition. In other embodiments, the gate spacers 39 and the gate spacers 38 have different compositions. The gate spacers 39 can be formed by a process similar to that used to form the gate spacers 38 in step 314.

[0092] For embodiments in which the trenches 25A-25C are formed by the etching process 504 in step 306 as in Fig. As shown in Figure 18, steps 308-318 and 350-358 are subsequently implemented in a similar manner to those described above to form a semiconductor device 400 having the embedded structures 62A-62C as shown in Figure 18. Fig. 23 shown.

[0093] Although not shown, in some embodiments step 306 is omitted so that no trenches are formed in the doped layer 20. In other words, the subsequent layers (e.g., the silicide layer 26, the first dielectric layer 32, the metal structure 36, and the conductive structure 48) are formed entirely over a top surface of the doped layer 20 and are not partially embedded in it. An exemplary trenchless embodiment is shown in Fig. 2, which corresponds to an embodiment of the semiconductor device 400 formed by steps 308-318 and 330-334, and in Fig. Figure 3 shows an embodiment of the semiconductor device 400 formed by steps 308-318 and 350-358.

[0094] In the present embodiments, the Fig. 17 embodiment of the semiconductor device 400 shown (in which the optional doped layers 11 are omitted for simplicity) of the semiconductor device 100B in Fig. 7; the in Fig. The embodiment of semiconductor device 400 shown in Figure 19 corresponds to semiconductor device 100B in Figure 19. Fig. 9; and those in Fig. The embodiment of semiconductor device 400 shown in Figure 22 corresponds to semiconductor device 100B in Figure 22. Fig. 8.

[0095] Additional steps can be taken after completing procedure 300 as described in the Fig.10A-10C. For example, an additional ILD layer (not shown) can be formed over the conductive structure 48 and the ILD layer 42. Furthermore, various contacts such as the substrate contact 50, the source / drain contacts 54A and 54B, the gate contacts 58A and 58B are configured to be electrically connected to a section of the doped well 14, the source / drain regions 22, the metal structure 36, and the conductive structure 48, respectively.

[0096] One aspect of this description concerns a semiconductor structure. The semiconductor structure comprises a substrate and a silicide layer over the substrate. The semiconductor structure has a first dielectric layer over the silicide layer. The semiconductor structure has a first metal structure over the first dielectric layer. The semiconductor structure has a second dielectric layer over the first metal structure. The semiconductor structure further comprises a conductive structure over the second dielectric layer.

[0097] Another aspect of this description concerns a semiconductor structure. The semiconductor structure has a substrate and a capacitor above the substrate. The capacitor has a silicide layer above the substrate. The capacitor has a first dielectric layer above the silicide layer. The capacitor has a metal gate structure above the first dielectric layer, with an upper portion of the metal gate structure extending above the substrate and a lower portion extending into the substrate. The capacitor has a second dielectric layer above the metal gate structure. The capacitor further has a metal structure above the second dielectric layer.

[0098] Another aspect of this description concerns a method for fabricating a semiconductor structure. The method includes providing a substrate with a doped region. The method includes structuring the doped region to form trenches. The method includes forming a silicide layer in the trenches. The method includes forming a first dielectric layer over the silicide layer. The method includes forming a dummy gate over the first dielectric layer, the dummy gate having a lower section that fills the trenches and an upper section over the lower section. The method includes forming gate spacers along the sidewalls of the dummy gate. The method includes replacing the dummy gate with a metal gate. The method includes forming a second dielectric layer over the metal gate.The process also includes forming a metal structure over the second dielectric layer.

Claims

[1] Semiconductor structure (200A, 200B), comprising: a substrate (10); and a capacitor above the substrate (10), comprising: a silicide layer (26) over the substrate (10); a first dielectric layer (32) above the silicide layer (26); a metal gate structure (36) above the first dielectric layer, wherein an upper section of the metal gate structure (36) is located above the substrate (10) and a lower section of the metal gate structure (36) projects into the substrate (10); a second dielectric layer (46) over the metal gate structure (36); and a conductive structure (48) above the second dielectric layer, wherein the substrate (10) has: a doped region surrounding the lower section (35A-C) of the metal gate structure (36); and Source / drain regions (22) arranged in the doped region, wherein the lower section of the metal gate structure (36) is arranged between the source / drain regions (22), and wherein the silicide layer (26) extends over the source / drain regions (22). [2] Semiconductor structure (200A, 200B) according to claim 1, wherein the lower section of the metal gate structure (36) has at least one column structure surrounded by the first dielectric layer and the silicide layer (26). [3] Semiconductor structure (200A, 200B) according to claim 2, wherein the column structure has multiple columns. [4] Semiconductor structure (200A, 200B) according to one of the preceding claims, wherein the lower section of the metal gate structure (36) has a rough surface. [5] Semiconductor structure (200A, 200B) according to one of the preceding claims, wherein the second dielectric layer (46) extends along both a bottom surface and a side wall surface of the conductive structure (48). [6] Semiconductor structure (200A, 200B) according to one of claims 1 to 4, wherein the second dielectric layer (46) extends only along a lower surface, but not along a side wall surface of the conductive structure (48). [7] Semiconductor structure (200A, 200B) according to one of the preceding claims, further comprising a spacer (38-40) along a side wall of the metal gate structure (36) and the conductive structure (48). [8] Semiconductor structure (200A, 200B) according to one of the preceding claims, wherein the metal gate structure (36) has at least one exit work metal layer. [9] Semiconductor structure (200A, 200B) according to one of the preceding claims, wherein the second dielectric layer (46) contains a high-k dielectric. [10] Semiconductor structure (200A, 200B) according to one of the preceding claims, further comprising a third dielectric layer between the metal gate structure (36) and the second dielectric layer, wherein the third dielectric layer has a different composition than the second dielectric layer (46). [11] Method for fabricating a semiconductor structure (200A, 200B), comprising: Providing a substrate (10) with a doped region; Structuring the doped area to form trenches (24A-C, 25A); Formation of a silicide layer (26) in the trenches (24A-C, 25A); Formation of a first dielectric layer over the silicide layer (26); Forming a dummy gate over the first dielectric layer, wherein the dummy gate has a lower section (35A-C) that fills the trenches (24A-C, 25A) and an upper section (35D) over the lower section (35A-C); Forming gate spacers (38-40) along side walls of the dummy gate; Replacing the dummy gate with a metal gate; Formation of a second dielectric layer over the metal gate; and Formation of a conductive structure (48) above the second dielectric layer. [12] Method according to claim 11, wherein replacing the dummy gate comprises: Removing the dummy gate so that a gate trench (37) is formed between the gate spacers (38-40); and Partial filling of the gate trench (37) with the metal gate, so that by forming the second dielectric layer sections of the second dielectric layer are formed along side walls of the gate spacers (38-40) in the gate trench (37) and the subsequent formation of the conductive structure (48) fills the gate trench (37). [13] Method according to claim 12, wherein the partial filling of the gate trench (37) comprises: Formation of an exit metal layer above the first dielectric layer, and Formation of a gate electrode (33) above the exit work metal layer. [14] Method according to any one of claims 11 to 13, wherein the gate spacers (38-40) are first gate spacers (38-40), and wherein the second dielectric layer (46) and the conductive structure (48) are formed over upper surfaces of the first gate spacers, the method further comprising: Etching of the conductive structure (48) and the second dielectric layer; and Forming second gate spacers (38-40) along side walls of the etched conductive structure (48) and the etched second dielectric layer such that the second gate spacers extend from the first gate spacers. [15] Method according to any one of claims 11 to 14, further comprising forming source / drain regions (22) in the doped region, wherein the trenches (24A-C, 25A) are formed in a section of the doped region which is arranged between the source / drain regions (22).

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