TREATING THE DIELECTRIC FILMS UNDER THE SOURCE / DRAIN REGIONS SUB-PAGES

Abstract

One process comprises: forming a gate stack over a semiconductor region, etching the semiconductor region to create a source / drain cavity adjacent to the gate stack, depositing a first dielectric layer, with a portion of the first dielectric layer located in the source / drain cavity, performing a treatment process on the first dielectric layer, depositing a second dielectric layer on top of the first dielectric layer, and etching the second dielectric layer and the first dielectric layer. A first portion of the first dielectric layer and a second portion of the second dielectric layer remain at the bottom of the source / drain cavity to form a dielectric region. A source / drain region is deposited within the source / drain cavity and over the dielectric region.

Description

BACKGROUND

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate. These layers are then patterned using lithography to form circuit components and elements.

[0002] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the smallest possible feature size, allowing more components to be integrated into a given area. However, as the smallest possible feature sizes are reduced, additional problems arise that must be solved.

[0003] US 2022 / 0 352 348 A1 describes a method for selectively etching a dielectric layer deposited in a source / drain recess of a semiconductor device.

[0004] DE 10 2023 105 387 A1 describes a manufacturing method of a nano-FET device in which epitaxial source / drain regions are formed, wherein a two-level trench isolation structure with different k-values ​​is provided below the epitaxial regions.

[0005] US 2021 / 0 202 742 A1 describes a method of manufacturing a semiconductor structure with gate-all-around transistors, wherein an insulating layer is provided between the source / drain structure and a fin and epitaxial growth is carried out. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be exaggerated or reduced as needed for clarity of discussion. Fig. 1-4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, and 14B illustrate cross-sectional views of intermediate stages in the formation of a gate-all-around (GAA) transistor, according to some embodiments. Fig. 15 to 19A and 20A illustrate cross-sectional views of intermediate stages in the formation of dielectric layers and overlying source / drain regions according to some embodiments. Fig. 19B, Fig. 20B, Fig. 19C and Fig. 20C illustrate cross-sectional views of intermediate stages in the formation of dielectric regions and overlying source / drain regions according to some embodiments. Fig. 21 illustrates the deposition of a dielectric layer and the subsequent post-treatment process according to some embodiments. Fig. Figure 22 illustrates the comparison of samples that are untreated with the samples that have been treated, according to some embodiments. Fig. 23 illustrates a process flow for forming a GAA transistor according to some embodiments. Fig. 24 illustrates a process flow for forming dielectric regions and overlying source / drain regions according to some embodiments. DETAILED DESCRIPTION

[0007] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements such that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not automatically create a relationship between the various embodiments and / or devices discussed.

[0008] Furthermore, spatially relative terms such as "underlying," "beneath," "lower," "overlying," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated 90 degrees, or other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0009] A gate-all-around (GAA) transistor is provided, comprising a dielectric region having a treated dielectric layer underlying a source / drain region. Methods for forming the dielectric region are provided. According to some embodiments, after deposition of a dielectric layer in source / drain recesses, a treatment process is performed to improve the quality of the one or more dielectric layers. The dielectric layer is more resistant to subsequent etching and cleaning processes. The leakage current between the source / drain regions and the underlying substrate is thereby reduced. The parasitic capacitance between the gate electrode and source / drain regions is also reduced.

[0010] Although GAA transistors are used as an example to discuss the concepts of the present disclosure, the embodiments may also be applied to other types of transistors, such as fin field-effect transistors (FinFETs). The embodiments discussed herein are intended to provide examples to enable making or using the subject matter of this disclosure. Those of ordinary skill in the art will readily recognize modifications that may be made without departing from the intended scopes of various embodiments. Like reference numerals are used to refer to like elements throughout the various views and illustrative embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0011] Fig. 1-4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, and 14B illustrate cross-sectional views of intermediate stages in the formation of a GAA transistor according to some embodiments of the present disclosure. The corresponding processes are also described in the Fig. The process flow shown in Figure 23 is schematically reflected.

[0012] In Fig. 1 shows a perspective view of wafer 10. Wafer 10 includes a multilayer structure with a multilayer stack 22 on a substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, or the like, while other substrates and / or structures, such as semiconductor-on-insulator (SOI), strained SOI, silicon germanium on insulator, or the like, may be used. Substrate 20 may be doped as a p-type semiconductor, although in other embodiments, it may also be doped as an n-type semiconductor.

[0013] According to some embodiments, the multilayer stack 22 is formed by a series of deposition processes for depositing alternating materials. The respective process is described as process 202 in the Fig. 23. According to some embodiments, the multilayer stack 22 includes first layers 22A formed from a first semiconductor material and second layers 22B formed from a second semiconductor material different from the first semiconductor material.

[0014] According to some embodiments, the first semiconductor material of a first layer 22A is formed of or comprises SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or the like. According to some embodiments, the deposition of the first layers 22A (e.g., SiGe) is performed by epitaxial growth, and the corresponding deposition method may be vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced-pressure CVD (RPCVD), or the like. According to some embodiments, the first layer 22A is formed to a first thickness in the range between about 3 nm and about 30 nm.However, any suitable thickness may be used without departing from the scope of the embodiments.

[0015] After the first layer 22A is deposited over the substrate 20, a second layer 22B is deposited over the first layer 22A. According to some embodiments, the second layer 22B is formed from or comprises a second semiconductor material such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, or the like, wherein the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments in which the first layer 22A is silicon germanium, the second layer 22B may be formed from silicon, or vice versa. It is understood that any suitable combination of materials may be used for the first layers 22A and the second layers 22B.

[0016] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a similar thickness as the first layer 22A. The second layer 22B may also be formed to a different thickness than the first layer 22A. According to some embodiments, the second layer 22A has a thickness in the range between about 4 nm and 7 nm, while the second layer 22B has a thickness in the range between about 8 nm and 12 nm, for example.

[0017] After the second layer 22B is formed over the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until a desired topmost layer of the multilayer stack 22 is formed. According to some embodiments, the first layers 22A have the same or similar thickness to each other, and the second layers 22B have the same or similar thickness to each other. The first layers 22A may also have the same thickness as—or different thicknesses than—the second layers 22B. According to some embodiments, the first layers 22A are removed in subsequent processes and are alternatively referred to as sacrificial layers 22A throughout the description. According to alternative embodiments, the second layers 22B are sacrificial layers and are removed in subsequent processes.

[0018] According to some embodiments, one or more pad oxide layers and one or more hard mask layers (not shown) may be formed over the multilayer stack 22. These layers are patterned and are used to subsequently pattern the multilayer stack 22.

[0019] With reference to Fig. 2, the multilayer stack 22 and a portion of the underlying substrate 20 are structured in one or more etching processes so that trenches 23 are formed. The respective process is described as process 204 in the Fig. 23. The trenches 23 extend into the substrate 20. The remaining portions of the multilayer stacks are referred to below as multilayer stacks 22'. Below the multilayer stacks 22', some portions of the substrate 20 remain, which are referred to below as substrate strips 20'. The multilayer stacks 22' include the semiconductor layers 22A and 22B. The semiconductor layers 22A are alternatively referred to below as sacrificial layers, and the semiconductor layers 22B are alternatively referred to below as nanostructures. The portions of the multilayer stacks 22' and the underlying substrate strips 20' are collectively referred to as semiconductor strips 24.

[0020] In the embodiments illustrated above, the GAA transistor structures may be patterned using any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligning processes, thereby creating structures that, for example, have pitches smaller than those otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligning process.The sacrificial layer is then removed and the remaining spacers can then be used to pattern the GAA structure.

[0021] Fig. Figure 3 illustrates the formation of isolation regions 26, which are also referred to as shallow trench isolation (STI) regions throughout the description. The respective process is designated as process 206 in the Fig. 23. The STI regions 26 may include a liner oxide (not shown), which may be a thermal oxide formed by the thermal oxidation of a surface layer of the substrate 20. The liner oxide may also be a deposited silicon oxide layer formed, for example, using ALD, high-density plasma chemical vapor deposition (HDPCVD), CVD, or the like. The STI regions 26 may also include a dielectric material over the liner oxide, where the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin-on coating, HDPCVD, or the like.A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, can then be performed to level the top surface of the dielectric material, and the remaining portions of the dielectric material are STI regions 26.

[0022] The STI regions 26 are then recessed so that the upper portions of the semiconductor stripes 24 protrude higher than the upper surfaces 26T of the remaining portions of the STI regions 26 to form protruding fins 28. The protruding fins 28 comprise multilayer stacks 22' and the upper portions of the substrate stripes 20'. The recessing of the STI regions 26 may be performed by a dry etching process, using, for example, NF3 and NH3 as the etching gases. A plasma may be generated during the etching process. Argon may also be included. According to alternative embodiments of the present disclosure, the recessing of the STI regions 26 is performed by a wet etching process. The etching chemical may include, for example, HF.

[0023] With reference to Fig. 4, dummy gate stacks 30 and gate spacers 38 are formed on the top surfaces and sidewalls of the (protruding) fins 28. The respective process is described as process 208 in the Fig. 23. The dummy gate stacks 30 may include dummy gate dielectrics 32 and dummy gate electrodes 34 over the dummy gate dielectrics 32. The dummy gate dielectrics 32 may be formed by oxidizing the surface portions of the protruding fins 28 to form oxide layers or by depositing a dielectric layer, such as a silicon oxide layer. Dummy gate electrodes 34 may be formed from, for example, polysilicon or amorphous silicon; however, other materials, such as amorphous carbon, may also be used.

[0024] Each of the dummy gate stacks 30 may also include one or more hard mask layers 36 over the dummy gate electrode 34. The hard mask layers 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or multiple layers thereof. The dummy gate stacks 30 may intersect a single one or more of the protruding fins 28 and the STI regions 26 between protruding fins 28. The dummy gate stacks 30 also have longitudinal directions that are perpendicular to the longitudinal directions of the protruding fins 28. The formation of dummy gate stacks 30 includes forming a dummy gate dielectric layer, depositing a dummy gate electrode layer over the dummy gate dielectric layer, depositing one or more hard mask layers, and then patterning the formed layers by one or more patterning processes.

[0025] Next, gate spacers 38 are formed on the sidewalls of dummy gate stacks 30. According to some embodiments of the present disclosure, gate spacers 38 are formed from a dielectric material, such as silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), silicon dioxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or the like, and may have a single-layer structure or a multi-layer structure including multiple dielectric layers. The formation process of gate spacers 38 may include depositing one or more dielectric layers and then performing one or more anisotropic etch processes on the one or more dielectric layers. The remaining portions of the one or more dielectric layers are gate spacers 38.

[0026] Fig. 5A and Fig. 5B illustrate cross-sectional views of the Fig. 4 shown structure. Fig. Figure 5A illustrates the reference cross section A1-A1 in Fig. 4, which extends through the portions of protruding fins 28 not covered by gate stacks 30 and gate spacers 38 and perpendicular to the gate longitudinal direction. Fin spacers 38 located on the sidewalls of protruding fins 28 are also illustrated. Fig. Figure 5B illustrates the reference cross section BB in Fig. 4, which runs parallel to the longitudinal directions of protruding fins 28.

[0027] With reference to the Fig. 6A and Fig. 6B, the portions of protruding fins 28 that are not directly beneath the dummy gate stacks 30 and the gate spacers 38 are recessed by an etching process to form recesses 42. The respective process is described as process 210 in the Fig. 23. For example, a dry etching process using C2F6, CF4, SO2, a mixture of HBr, Cl2, and O2, a mixture of HBr, Cl2, O2, and CH2F2, or the like may be performed to etch the multilayer semiconductor stacks 22' and the underlying substrate strips 20'. The bottoms of recesses 42 are at least level with the bottoms of multilayer semiconductor stacks 22' or may be lower than them (as in Fig. 6B). The etching may be anisotropic, so that the side walls of multilayer semiconductor stacks 22' facing recesses 42 are vertical and straight, and in Fig. 6B shown.

[0028] With reference to Fig. 7A and Fig. 7B, sacrificial semiconductor layers 22A are laterally recessed to form lateral recesses 41, which are recessed starting from the edges of the respective overlying and underlying nanostructures 22B. The respective process is described as process 212 in the Fig. 23. The lateral recess of sacrificial semiconductor layers 22A may be achieved by a wet etching process using an etchant that is more selective for the material (e.g., silicon germanium (SiGe)) of the sacrificial semiconductor layers 22A than for the material (e.g., silicon (Si)) of the nanostructures 22B and the substrate 20. For example, in an embodiment in which sacrificial semiconductor layers 22A are formed from silicon germanium and the nanostructures 22B are formed from silicon, the wet etching process may be performed using an etchant such as hydrochloric acid (HCl). The wet etching process may be performed using a dipping process, a spraying process, a spin-on process, or the like.

[0029] According to alternative embodiments, the lateral recessing of sacrificial semiconductor layers 22A is performed by an isotropic dry etching process or a combination of a dry etching process and a wet etching process.

[0030] With reference to the Fig. 8A and Fig. 8B, inner spacers 44 are formed. The respective process is described as process 214 in the Fig. 23. According to some embodiments, the formation of the inner spacers 44 includes depositing a conformal dielectric layer extending into the lateral recesses 41 ( Fig. 7B). Next, an etching process (also referred to as a spacer trimming process) is performed to trim the portions of the spacer layer outside the side recesses 41, leaving the portions of the spacer layer in the side recesses 41. The remaining portions of the spacer layer are referred to as inner spacers 44.

[0031] With reference to the Fig. 9A and Fig. 9B, dielectric regions 46 and epitaxial source / drain regions 48 are formed in recesses 42. The respective process is described as process 216 in the Fig. 23. According to some embodiments, the source / drain regions 48 may impart stress to the nanostructures 22B used as the channels of the corresponding GAA transistors, thereby improving performance. Depending on whether the resulting transistor is a p-type transistor or an n-type transistor, a p-type or n-type impurity may be doped in-situ during epitaxy. If the resulting transistor is a p-type transistor, for example, silicon germanium boron (SiGeB), silicon boron (SiB), or the like may be grown. Conversely, if the resulting transistor is an n-type transistor, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like may be grown.

[0032] After recesses 42 have been filled with epitaxial regions 48, further epitaxial growth of epitaxial regions 48 causes a horizontal expansion of epitaxial regions 48, and facets may be formed. Further growth of epitaxial regions 48 may also cause neighboring epitaxial regions 48 to merge with each other. Vacancies (air gaps) may be generated among the merged epitaxial regions 48.

[0033] The Fig. 15-18, 19A, 19B, 19C, 20A, 20B and 20C illustrate the details in the formation of the dielectric regions 46 and the source / drain regions 48 (as in the Fig. 9A and Fig. 9B) according to some embodiments. The Fig. 15-18, 19A, 19B, 19C, 20A, 20B and 20C are also shown in the Fig. 24, wherein the process flow 300 illustrates the details of the process 216 as shown in the process flow 200.

[0034] Fig. 15 illustrates region 45 in Fig. 8B, in which recesses 42 and inner spacers 44 were formed. Next, the dielectric layer 46B is deposited. The respective process is described as process 302 in the Fig. 24. According to some embodiments, the dielectric layer 46B comprises a dielectric material comprising oxygen, such as SiON, SiO, SiOC, or the like. The corresponding precursors may include a silicon-containing precursor and an oxygen-containing precursor. The silicon-containing precursor may comprise bis(diethylamino)silane ((BDEAS) (SiH2[N(CH2CH3)2]2), silane, disilane, or the like, or a combination thereof. The oxygen-containing precursor may be selected from CO2, O2, NO2, or the like, and combinations thereof. A carrier gas, including Ar, He, or the like, or a combination thereof, may be used.

[0035] Fig. 21 illustrates an example formation process for depositing dielectric layer 46B according to some embodiments. The deposition of dielectric layer 46B may be performed using atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), chemical vapor deposition (CVD), or the like. The illustrated example process is performed using PEALD, which includes repeating multiple ALD cycles, although only a single one of the ALD cycles is depicted here. The illustrated ALD cycle is repeated.

[0036] The example process uses BDEAS and CO2 as the precursors and Ar as the carrier gas, although other precursors and carrier gases can be used. The plasma can be turned on at specific times to initiate (and accelerate) the reaction and treatment. Each gas and the plasma can be represented by a line, which, when at a higher position, represents that the gas is being supplied or the plasma is turned on, and when at a lower position, represents that the gas is stopped or the plasma is turned off.

[0037] According to some embodiments, CO2 and Ar are continuously supplied in an ALD cycle. The flow rate of the oxygen-containing precursor, such as CO2, can range between about 1 slm and about 10 slm. The BDEAS is pulsed and is adsorbed onto the wafer 10 and then purged by the subsequently supplied Ar and CO2. The pulse duration (supply duration) can range between about 0.5 seconds and about 2.5 seconds. After purging the BDEAS, the plasma is turned on by applying radio frequency (RF) power to react CO2 with the adsorbed BDEAS, thereby forming SiCO according to some embodiments. The ALD cycle is repeated until the thickness of the dielectric layer 46B reaches a suitable value, for example, in the range between about 0.5 nm and about 2.5 nm.

[0038] According to some embodiments, the temperature of wafer 10 during deposition of dielectric layer 46B may range between about 75°C and about 390°C, or may range between about 75°C and about 100°C. The plasma may be generated using inductively coupled plasmas (ICPs) or capacitively coupled plasmas (CCPs). The RF duty cycle (to generate the plasma) may range between about 0.2 seconds and about 1.2 seconds, or may range between about 0.2 seconds and about 0.4 seconds. The RF power may range between about 15 watts and about 600 watts.

[0039] After the dielectric layer 46B has been deposited, a treatment process 47 (also referred to as a post-treatment process) is carried out by switching on the RF power and thus the plasma, as also shown in Fig. 21. The treatment process 47 is also shown in Fig. 15. The respective process is shown as process 304 in the Fig. 24. The deposited dielectric layer 46B may include defects and may have dangling bonds. According to some embodiments, the treatment process 47 may add oxygen atoms to the dangling bonds to remove the defects. The treated dielectric layer 46B thereby becomes denser. For example, the density of the dielectric layer 46B may be about 3 percent to about 5 percent higher than before the treatment process 47. Furthermore, due to the removal of the dangling bonds, the etch rate of the dielectric layer 46B is reduced in the subsequent etch and cleaning processes. According to some embodiments, the process gas used for the treatment process 47 may be selected from CO2, O2, NO2, or the like, or combinations thereof. The flow rate of the process may range between about 1 slm and about 10 slm.

[0040] According to some embodiments, the treatment process may be performed at the same location (in the same vacuum environment) as the deposition of dielectric layers 46B and 46A. For example, the treatment process may be performed after a delay period during which CO2 and Ar are continuously supplied. According to some embodiments, the flow rate of CO2 and Ar is kept unchanged. According to alternative embodiments, the flow rate of CO2 and Ar may be increased or decreased, and then treatment process 47 is performed.

[0041] According to alternative embodiments, the treatment process may be performed at a different location than the deposition of dielectric layers 46B. The vacuum environment used for treatment process 47 may be the same as the vacuum environment for deposition of dielectric layer 46B (but in different chambers) or may be different from the vacuum environment for deposition of dielectric layer 46B (with a vacuum interruption in between).

[0042] According to some embodiments, the temperature of the wafer 10 during the treatment process 47 may range between about 75°C and about 390°C, and may range between about 75°C and about 100°C. The plasma may be generated using ICP or CCP. The RF duty cycle (for generating the plasma) may range between about 0.2 seconds and about 1.2 seconds, or may range between about 0.4 seconds and about 0.8 seconds. The post-treatment time may also be longer than the RF duty cycle within the ALD cycles. The RF power of the post-treatment may range between about 15 watts and about 600 watts. The RF power used in the post-treatment may also be higher than the RF power used during the ALD cycles. For example, the RF power of the post-treatment may range between about 400 watts and about 600 watts.

[0043] According to some embodiments, the treatment process 47 is performed as an isotropic treatment process in which no bias power is applied. According to alternative embodiments, the post-treatment is performed by an anisotropic treatment process in which a bias power is applied. The bias power may be lower than about 15 watts. To ensure that the portions of the dielectric layer 46B at the lower corners of the recesses 42 are treated, the post-treatment may also be performed by an inclined treatment, wherein the inclination angle is adjusted so that the ions of the treatment gas can directly reach the lower corners of the recesses 42. For example, Fig. 15 shows an arrow 43 representing the direction in which the ions (generated by the treatment processes, including oxygen ions) reach the lower corner portions of the dielectric layer 46B. The tilt angle α, i.e., the angle of incidence of the ions relative to a vertical direction, is chosen to ensure that the ions are not blocked by the upper portion of the gate stacks 30. The tilt angle α can be greater than zero degrees and less than the illustrated tilt angle α and is related to the aspect ratio of the recesses 42.

[0044] Fig. 16 illustrates the deposition of the dielectric layer 46A. The respective process is described as process 306 in the Fig. 24. Dielectric layer 46A is formed from a different material than dielectric layer 46B. Dielectric layer 46A may include a higher nitride atomic percentage than dielectric layer 46B to achieve higher etch selectivity between dielectric layers 46B and 46A in subsequent etch and cleaning processes. For example, dielectric layer 46A may be formed from or include silicon nitride (SiN), SiOCN, SiCN, or the like.

[0045] According to some embodiments, the dielectric layer 46A includes sidewall portions 46A-S, bottom portions 46A-B, and top portions 46A-T that have different properties due to the topology and nature of the deposition process. For example, in subsequent etching and cleaning processes, the sidewall portions 46A-S of the dielectric layer 46A have the etch rate ER-S, the top portions 46A-T of the dielectric layer 46A have the etch rate ER-T, and the bottom portions 46A-B of the dielectric layer 46A have the etch rate ER-B. The following relationship of etch rates may exist: ER-S > ER-T > ER-B. The sidewall portions 46A-S are therefore vulnerable to damage in subsequent processes.

[0046] Fig. 17 illustrates the etching of the dielectric layer 46A according to some embodiments. The respective process is described as process 308 in the Fig. 24. The etching may be isotropic, and the etching gas or etching solution is selected based on the materials of the dielectric layers 46A and 46B. During the etching process, the dielectric layer 46B is not etched (or is etched, but at a lower etch rate). Since the sidewall portions 46A-S are etched faster than the top portions 46A-T, some portions of the top portions 46A-T may remain after the etching process (if any).

[0047] The etching may involve a dry etching process or a wet etching process. In the dry etching process, a fluorine-containing gas such as CF4, NF3, SF6, CHF3, ClF3, or a combination thereof may be used. Other gases such as O2, N2, H2, Ar, NO, and the like may also be added. In a wet etching process, a chemical solution such as H3PO4 may be used.

[0048] At the bottom of the recesses 42, some lower portions 46A-B of the dielectric layer 46A remain. This is due in part to the fact that the etch rate ER-B of the lower portions 46A-B is lower than that of the sidewall portions 46A-S, and in part to the high aspect ratio of the recesses 42.

[0049] Fig. 18 illustrates the etching of dielectric layer 48B, which may be performed using a chemical that etches dielectric layer 48B but does not etch dielectric layer 46A (or etches it, but at a lower etch rate). The respective process is described as process 310 in the Fig. 24. The etching may also include a dry etching process or a wet etching process. For example, when dry etching is performed, the etching gas may contain, for example, a mixture of NF3 and NH3, a mixture of HF and NH3, or HF. When wet etching is performed, a diluted HF solution may be used.

[0050] After the etching process, dielectric regions 46, including the remaining portions of dielectric layers 46B and 46A, remain at the bottoms of recesses 42. Some portions of dielectric layers 46B and 46A may also remain at the top of dummy gate stacks 30 (if any).

[0051] In a subsequent process, as in the Fig. 19A, Fig. 19B and Fig. 19C, a pre-cleaning process 49 may be performed to prepare the wafer 10 for the subsequent epitaxial process. The respective process is shown as process 312 in the Fig. 24. According to some embodiments, the pre-cleaning process 49 is performed by a dry etching process, which may remove residues and unwanted chemicals left over from the previous processes. For example, according to some embodiments, the etching gas may be HF gas. The etching gas may be the same gas as the gas used for etching the dielectric layer 46B, or it may be a different gas. For example, HF may be used for both etching the dielectric layer 46B and the pre-cleaning process 49.

[0052] According to some embodiments, the process gas used for the pre-cleaning process 49 is capable of etching the material of the dielectric layer 46B. Through the treatment process 47 ( Fig. 15), the density of the dielectric layer 46B is increased, and / or the dangling bonds of the dielectric layer 46B are removed. This results in the etch rate of the dielectric layer 46B being reduced in the pre-clean process 49. For example, with some of the pre-clean chemistries, such as HF, the etch rate of the dielectric layer 46B prior to the treatment process 47 would be significantly higher than the etch rate of the dielectric layer 46A. This results in the sidewall portions of the dielectric layer 46B in the regions 51 being undesirably removed if the treatment process 47 is not performed, creating vacancies in the regions 51.

[0053] The subsequently deposited epitaxial semiconductor regions 48 fill the vacancies and can contact the substrate 20. This increases the leakage current between the source / drain regions 48 ( Fig. 19A) and the substrate 20. The parasitic capacitance between the source / drain regions 48 and the subsequently formed gate electrode also increases.

[0054] The post-treatment of the dielectric layer 46B reduces the etching rate of the dielectric layer 46B during the pre-cleaning process. For example, assume that the process gas used for the pre-cleaning process 49 has an etching rate ER-46A for etching the dielectric layer 46A, an etching rate ER-46B1 for etching the dielectric layer 46B that was not treated by the treatment process 47, and an etching rate ER-46B2 for etching the dielectric layer 46B that was treated by the treatment process 47. Then, the etching rate ER-46B2 is smaller than the etching rate ER-46B1, and the ratio ER-46B2 / ER-46A becomes smaller than the ratio ER-46B1 / ER-46A due to the treatment process 47. The etch rate ratio ER-46B2 / ER-46B1 may also be less than 1 and may range between about 0.6 and about 1.

[0055] According to some embodiments, the treatment process 47 causes the etch rate ER-46B2 of the treated dielectric layer 46B to be lower than the etch rate ER-46A of the dielectric layer 46A in the pre-clean process 49. According to alternative embodiments, the treatment process 47 causes the etch rate ER-46B2 of the treated dielectric layer 46B to be reduced, but still equal to, or slightly higher than, the etch rate ER-46A of the dielectric layer 46A during the pre-clean process. Accordingly, in the pre-clean process, the sidewall portions of the dielectric layer 46B in the regions 51 are not etched or are etched less, leaving a significant portion. The adverse increase in leakage current and the adverse increase in parasitic capacitance are eliminated.

[0056] According to some embodiments, an additional treatment process 47' ( Fig. 18) may be performed at a time after the dielectric layer 46A has been etched and before the dielectric layer 46B is etched. According to some embodiments, an additional treatment process 47" ( Fig. 19A, Fig. 19B and Fig. 19C) may be performed after etching the dielectric layer 46B and before the pre-cleaning process 49. The details of the treatment processes 47' and 47" may be substantially the same as those of the post-treatment process 47 and will not be repeated here. The treatment processes 47' and 47" also have the effect of densifying and removing dangling bonds from the dielectric layer 46B and the effect of reducing the etch rate of the dielectric layer 46B in the pre-cleaning process 49. According to some embodiments, one or more of the treatment processes 47, 47', and 47" may be performed in any combination to achieve the intended effect, while others of the treatment processes 47, 47', and 47" may not be performed.

[0057] According to some embodiments, as in Fig. 19A, after the pre-cleaning process, the top surface of the dielectric regions 46 is concave. This may be because, in the pre-cleaning process, the etching rate of the dielectric layer 46B is lower than that of the dielectric layer 46A. The top edges 46B-TOP of the dielectric layer 46B are therefore higher than the top surfaces of the dielectric layer 46A. The top edges 46B-TOP of the dielectric layer 46B may be at the same height as, or lower than, the bottom surface 22B-BOT of the lowest semiconductor nanolayer 22B. According to some embodiments, the top surfaces of the dielectric regions 46 are lower than the bottom surface 22B-BOT and are represented by dashed lines 46-TOP'.

[0058] According to alternative embodiments, as in Fig. 19B, the dielectric regions 46 have convex top surfaces after the pre-cleaning process. This may be because the etch rate of the dielectric layer 46B is higher than that of the dielectric layer 46A in the pre-cleaning process. The top edges 46B-TOP of the dielectric layer 46B are therefore lower than the top surfaces of the dielectric layer 46A. The top edges 46B-TOP of the dielectric layer 46B may be at the same height as, or lower than, the bottom surface 22B-BOT. According to some embodiments, the top surfaces of the dielectric regions 46 are lower than the bottom surface 22B-BOT and are represented by dashed lines 46-TOP'.

[0059] According to further alternative embodiments, as in Fig. 19C, the dielectric regions 46 have planar top surfaces after the pre-cleaning process. This may be because, in the pre-cleaning process, the etch rate of the dielectric layer 46B is the same as that of the dielectric layer 46A. The top edges 46B-TOP of the dielectric layer 46B are therefore at the same height as the top surfaces of the dielectric layer 46A. The top edges 46B-TOP of the dielectric layer 46B may be at the same height as, or lower than, the bottom surface 22B-BOT. According to some embodiments, the top surfaces of the dielectric regions 46 are lower than the bottom surface 22B-BOT and are represented by dashed lines 46-TOP'.

[0060] In the embodiments described in the Fig. 19A and Fig. 19B, when the dielectric regions 46 have top sides 46-TOP', which is shown in dashed lines, the height difference ΔH1 ( Fig. 19A) between the bottom surface 22B-BOT and the top edges of the dielectric layer 46B (which are part of 46-TOP') may be equal to or less than about 0.6 nanometers or equal to or less than (ΔH3) / 2, where ΔH3 ( Fig. 19A) is the height difference between the bottom surface 22B-BOT and the top surfaces (which are also the bottom surface of the dielectric regions 46) of the bulk portion of the substrate 20. Otherwise, the parasitic capacitance between the subsequently formed source / drain regions 48 ( Fig. 20A, Fig. 20B and Fig. 20C) and the gate electrodes 68 inappropriately increase.

[0061] The recess depth ΔH2 of the top surface of the dielectric regions 46 may also be equal to or less than (ΔH3) / 2. Otherwise, the dielectric regions 46 may have cracks, and a leakage current may occur between the subsequently formed source / drain regions 48 ( Fig. 20A) and the substrate 20.

[0062] Fig. 20A, Fig. 20B and Fig. 20C illustrate the formation of epitaxial source / drain regions 48. The respective process is shown in the Fig. 24 shown process flow 300 as process 314 and is shown in the Fig. 23 shown process flow 200 as process 216. Fig. 20A, Fig. 20B and Fig. 20C correspond to the Fig. 19A, Fig. 19B and 19C respectively and also show the source / drain regions 48. The formation of source / drain regions 48 was described with reference to the Fig. 9A and Fig. 9B discussed.

[0063] Next, a contact etch stop layer (CESL) 50 and an inter-layer dielectric (ILD) 52 are formed as shown in the Fig. 20A, Fig. 20B and Fig. 20C. These structural elements are also shown in the Fig. 10A and Fig. 10B, as will be discussed later. Replacement gate stacks 70 are also formed, and the formation processes are shown in the Fig. 11A, Fig. 11B, Fig. 12A and Fig. 12B. The formation details of these structural elements are discussed below with reference to Fig. 10A and Fig. 10B to Fig. 14A and Fig. 14B discussed.

[0064] Fig. 10A and 10B to 14A and 14B illustrate the details of some of the Fig. 20A, Fig. 20B and Fig. 20C. These figures may have the corresponding numbers followed by a letter A or B. The figure with the figure number that has the letter A indicates that the corresponding figure shows the same reference cross-section as the reference cross-section A2-A2 in Fig. 4. The figures with the figure numbers that have the letter B indicate that the corresponding figures show the same reference cross-section as the reference cross-section BB in Fig. 4.

[0065] Fig. 10A and Fig. 10B illustrate cross-sectional views of the structure after the formation of a contact etch stop layer (CESL) 50 and an interlayer dielectric (ILD) 52. The respective process is described as process 218 in the Fig. 23. The CESL 50 may be formed from silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed using CVD, ALD, or the like. The ILD 52 may include a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or any other suitable deposition method. The ILD 52 may be formed from an oxygen-containing dielectric material, which may be a silicon oxide-based material formed using tetraethyl orthosilicate (TEOS) as a precursor, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.

[0066] The CESL 50 and the ILD 52 are planarized by a planarization process, such as a CMP process or a mechanical grinding process. The respective process is described as process 220 in the Fig. 23. According to some embodiments, the planarization process may remove hard masks 36 to expose dummy gate electrodes 34, as shown in Fig. 10A. According to alternative embodiments, the planarization process may expose and stop on hard masks 36. According to some embodiments, after the planarization process, the top surfaces of dummy gate electrodes 34 (or hard masks 36), gate spacers 38, and the ILD 52 are at the same height, within process variations.

[0067] Next, dummy gate electrodes 34 and dummy gate dielectrics 32 (and hard masks 36, if any remain) are removed in one or more etching processes to form recesses 58, as shown in the Fig. 11A and Fig. 11B. The respective process is shown as process 222 in the Fig. 23. According to some embodiments, dummy gate electrodes 34 and dummy gate dielectrics 32 are removed by one or more anisotropic dry etch processes. For example, the etch process may be performed using one or more reactant gases that selectively etch dummy gate electrodes 34 and dummy gate dielectrics 32 at faster rates than the ILD 52. Each recess 58 exposes and / or overlies portions of multilayer stacks 22' that include the future channel regions in subsequently completed transistors.

[0068] Then, the sacrificial layers 22A are removed to enlarge the gaps 58 between the nanostructures 22B. The respective process is described as process 224 in the Fig. 23. The sacrificial layers 22A may be removed by performing an isotropic etching process, such as a wet etching process, using etchants selective for the materials of the sacrificial layers 22A, while the nanostructures 22B, the substrate 20, and the STI regions 26 remain relatively unetched compared to the sacrificial layers 22A. According to some embodiments, where the sacrificial layers 22A include, for example, SiGe, and the nanostructures 22B include, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to remove the sacrificial layers 22A.

[0069] With reference to the Fig. 12A and Fig. 12B, the gate dielectrics 62 and the gate electrodes 68 are formed, thereby forming replacement gate stacks 70. The respective process is described as process 226 in the Fig. 23. According to some embodiments, each gate dielectric 62 includes an interface layer and a high-k dielectric layer on the interface layer. The interface layer may be formed from (or comprise silicon oxide), which may be deposited by a conformal deposition process, such as ALD or CVD, or by an oxidation process. According to some embodiments, the high-k dielectric layers include one or more dielectric layers. For example, the one or more high-k dielectric layers may include a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.

[0070] Gate electrodes 68 are also formed. During formation, conductive layers are first formed on the high-k dielectric layer, and the remaining portions of recesses 58 are filled. The gate electrodes 68 may include a metal-containing material, such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multilayers thereof. For example, the gate electrodes 68 may include any number of layers, any number of work function layers, and possibly a fill material. The gate dielectrics 62 and the gate electrodes 68 also fill the spaces between adjacent nanostructures 22B and fill the spaces between the lower nanostructures 22B and the underlying substrate strips 20'.After filling the recesses 58, a planarization process, such as a CMP process or a mechanical grinding process, is performed to remove the excess portions of the gate dielectrics and gate electrode material 68 located above the top surface of the ILD 52. The gate electrodes 68 and the gate dielectrics 62 are collectively referred to as the gate stack 70 of the resulting transistors.

[0071] In the Fig. 13A and Fig. 13B, the gate stacks 70 are recessed such that recesses are formed directly above the gate stacks 70 and between opposing portions of gate spacers 38. A gate mask 74 comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled into each of the recesses, followed by a planarization process to remove excess portions of the dielectric material extending above the ILD 52. The respective process is shown as process 228 in the Fig. 23 illustrates the process flow 200 shown.

[0072] As through the Fig. 13A and Fig. 13B, the ILD 76 is deposited over the ILD 52 and over gate masks 74. The respective process is shown as process 230 in the Fig. 23. Optionally, an etch stop layer (not shown) may be deposited prior to the formation of the ILD 76. According to some embodiments, the ILD 76 is formed by FCVD, CVD, PECVD, or the like. The ILD 76 is formed from a dielectric material that may be selected from silicon oxide, PSG, BSG, BPSG, USG, or the like.

[0073] In the Fig. 14A and Fig. 14B, the ILD 76, the ILD 52, the CESL 50, and gate masks 74 are etched to form recesses (occupied by contact plugs 80A and 80B) that expose areas of source / drain regions 48 and / or gate stacks 70. The recesses may be formed by etching using an anisotropic etch process, such as RIE, NBE, or the like. Although Fig. 14B illustrates that contact plugs 80A and 80B have the same cross-section, contact plugs 80A and 80B can also be formed with different cross-sections in various embodiments, thereby reducing the risk of a short circuit with each other.

[0074] After the recesses have been formed, silicide regions 78 are formed over source / drain regions 48. The respective process is described as process 232 in the Fig. 23. Contact plugs 80B are then formed over the silicide regions 78. Furthermore, contacts 80A (which may also be referred to as gate contact plugs) are formed in the recesses, which contacts are located over and contact the gate electrodes 68. The respective process is described as process 234 in the process shown in Fig. 23. In this way, a transistor 82 is formed.

[0075] Fig.Figure 22 illustrates some experimental results obtained using some samples. The X represents the V-trigger voltages, that is, the voltages required to turn on parasitic transistors in the structure of the embodiments, so that current is conducted as leakage current to the substrate 20. An exemplary specification is that the V-trigger voltage must be greater than 1.6 volts. The Y-axis represents the normal quantile of several samples. The samples shown in the left half of the figure are from the samples where the formation of dielectric regions does not include treatment 47. It can be observed that some samples have V-trigger voltages of less than 1.3 volts, and all samples have V-trigger voltages of less than 1.45 volts, so these samples do not meet the specification.

[0076] The samples shown in the right half of the figure are from the samples where the formation of dielectric regions includes treatment process 47. It can be observed that all samples have V-trigger voltages greater than 1.6 volts, so these samples meet the specification.

[0077] The embodiments of the present disclosure are characterized by several advantageous features. Post-treatment processes during the formation of the lower dielectric layer avoid inappropriate etching of the corner portions of the lower dielectric layer. Leakage currents between the source / drain regions and the underlying substrate are reduced or eliminated. The parasitic capacitance between the source / drain regions and the gate electrodes is also reduced.

[0078] According to some embodiments of the present disclosure, a method includes: forming a gate stack over a semiconductor region; etching the semiconductor region to form a source / drain recess adjacent to the gate stack; depositing a first dielectric layer, wherein a portion of the first dielectric layer is located in the source / drain recess; performing a treatment process on the first dielectric layer; depositing a second dielectric layer on the first dielectric layer; etching the second dielectric layer and the first dielectric layer, leaving a first portion of the first dielectric layer and a second portion of the second dielectric layer at a bottom of the source / drain recess to form a dielectric region; and depositing a source / drain region in the source / drain recess and over the dielectric region.

[0079] In one embodiment, depositing the first dielectric layer comprises depositing an oxygen-containing dielectric layer, and depositing the second dielectric layer comprises depositing a nitrogen-containing dielectric layer. In one embodiment, the treatment process is performed using an oxygen-containing process. In one embodiment, the treatment process comprises a plasma treatment process. In one embodiment, the method further comprises performing a pre-cleaning process after forming the dielectric region and before depositing the source / drain region. In one embodiment, the pre-cleaning process is performed using an HF gas.

[0080] In one embodiment, the first dielectric layer is deposited using plasma-enhanced atomic layer deposition comprising multiple cycles, and wherein the treatment process comprises applying radio frequency power to generate a plasma. In one embodiment, depositing the first dielectric layer comprises introducing a process gas as a precursor, and wherein the treatment process is also performed using the process gas to generate the plasma.

[0081] In one embodiment, depositing the first dielectric layer comprises introducing a first process gas as a precursor, and wherein the treatment process is performed using a second process gas, different from the first process gas, to generate the plasma. In one embodiment, the treatment process is performed using carbon dioxide (CO2) as a process gas. In one embodiment, the semiconductor region comprises a semiconductor nanolayer, wherein the semiconductor nanolayer is included in a protruding structural element comprising additional semiconductor nanolayers stacked on top of the semiconductor nanolayer.

[0082] According to some embodiments of the present disclosure, a method comprises: forming a protruding feature comprising: a first sacrificial nanolayer over a bulk semiconductor substrate; a first semiconductor nanolayer over the first sacrificial nanolayer; a second sacrificial nanolayer over the first semiconductor nanolayer; and a second semiconductor nanolayer over the second sacrificial nanolayer; forming a gate stack on a sidewall and on a top surface of the protruding feature; etching the protruding feature to form a recess, wherein a first bottom of the recess is lower than a second bottom of the first semiconductor nanolayer; depositing a first dielectric layer into the recess; performing a treatment process on the first dielectric layer; depositing a second dielectric layer on the first dielectric layer;Etching sidewall portions of the first dielectric layer and the second dielectric layer, leaving a dielectric region at the first bottom of the recess, the dielectric region comprising a first lower portion of the first dielectric layer and a second lower portion of the second dielectric layer; and forming a source / drain region on the dielectric region.

[0083] In one embodiment, a top surface of the dielectric region is lower than the second bottom surface of the first semiconductor nanolayer. In one embodiment, a top surface of the dielectric region is level with the second bottom surface of the first semiconductor nanolayer. In one embodiment, the method further comprises, after forming the dielectric region, performing a pre-cleaning process, wherein the treatment process results in the first lower portion of the first dielectric layer having a lower etch rate during the pre-cleaning process than the first dielectric layer at a time prior to the treatment process.

[0084] In one embodiment, the treatment process is performed using an oxygen-containing process gas. In one embodiment, the method further comprises: removing the first sacrificial nanolayer and the second sacrificial nanolayer; and forming a replacement gate stack, wherein the replacement gate stack includes portions in spaces left behind by the first sacrificial nanolayer and the second sacrificial nanolayer to be removed.

[0085] According to some embodiments of the present disclosure, a method comprises: etching a semiconductor nanolayer to form a source / drain recess, wherein the source / drain recess comprises a first bottom that is lower than a second bottom of the semiconductor nanolayer; depositing a first dielectric layer, wherein a portion of the first dielectric layer is located in the source / drain recess, the first dielectric layer comprising a first dielectric material; performing a treatment process on the first dielectric layer to convert the first dielectric material to a second dielectric material; depositing a second dielectric layer on the first dielectric layer;Etching the second dielectric layer and the first dielectric layer, leaving a first portion of the first dielectric layer and a second portion of the second dielectric layer at a bottom of the source / drain recess to form a dielectric region; performing a pre-cleaning process using an etching gas, the etching gas capable of etching the first dielectric material at a first etching rate and capable of etching the second dielectric material at a second etching rate, and the second etching rate being lower than the first etching rate; and growing a semiconductor region in the source / drain recess through an epitaxial process.

[0086] In one embodiment, the pre-cleaning process results in the dielectric region having a concave top surface. In one embodiment, the pre-cleaning process results in the dielectric region having a convex top surface.

Claims

[1] Procedure which includes: Forming a gate stack (30) over a semiconductor region (24); etching the semiconductor region (24) to form a source / drain recess (42) adjacent the gate stack (30); depositing a first dielectric layer (46B), wherein a portion of the first dielectric layer (46B) is located in the source / drain recess (42); performing a treatment process (47) on the first dielectric layer (46B); depositing a second dielectric layer (46A) on the first dielectric layer (46B); Etching the second dielectric layer (46A) and the first dielectric layer (46B), leaving a first portion of the first dielectric layer (46B) and a second portion of the second dielectric layer (46A) at a bottom of the source / drain recess (42) to form a dielectric region (46); and Depositing a source / drain region (48) in the source / drain recess (42) and over the dielectric region. [2] The method of claim 1, wherein depositing the first dielectric layer (46B) comprises depositing an oxygen-containing dielectric layer and depositing the second dielectric layer (46A) comprises depositing a nitrogen-containing dielectric layer. [3] The method of claim 1 or 2, wherein the treatment process (47) is carried out using an oxygen-containing process. [4] Method according to one of claims 1 to 3, wherein the treatment process (47) comprises a plasma treatment process. [5] The method of any one of claims 1 to 4, further comprising performing a pre-cleaning process (49) after forming the dielectric region (46A, 46B) and before depositing the source / drain region (48). [6] The method of claim 5, wherein the pre-cleaning process (49) is performed using an HF gas. [7] The method of claim 1, wherein the first dielectric layer (46B) is deposited using plasma enhanced atomic layer deposition comprising multiple cycles, and wherein the treatment process (47) comprises turning on a radio frequency power to generate a plasma. [8] The method of claim 7, wherein depositing the first dielectric layer (46B) comprises introducing a process gas as a precursor, and wherein the treatment process (47) is also performed using the process gas to generate the plasma. [9] The method of claim 7, wherein depositing the first dielectric layer (46B) comprises introducing a first process gas as a precursor, and wherein the treatment process (47) is performed using a second process gas different from the first process gas to generate the plasma. [10] A method according to any one of claims 1 to 9, wherein the treatment process (47) is carried out using carbon dioxide as a process gas. [11] The method of any one of claims 1 to 10, wherein the semiconductor region (24) comprises a semiconductor nanolayer (22B), the semiconductor nanolayer (22B) being contained in a protruding structural element (22) comprising additional semiconductor nanolayers (22A) stacked on the semiconductor nanolayer (22B). [12] Procedure which includes: Forming a protruding structural element (22) comprising: a first sacrificial nanolayer (22A) over a bulk semiconductor substrate (20); a first semiconductor nanolayer (22B) over the first sacrificial nanolayer (22A); a second sacrificial nanolayer (22A) over the first semiconductor nanolayer (22B); and a second semiconductor nanolayer (22B) over the second sacrificial nanolayer (22A); forming a gate stack (30) on a sidewall and on a top surface of the protruding structural element (22); Etching the protruding structural element (22) to form a recess (42), wherein a first bottom of the recess (42) is lower than a second bottom of the first semiconductor nanolayer (22B); Depositing a first dielectric layer (46B) into the recess (42); performing a treatment process (47) on the first dielectric layer (46B); depositing a second dielectric layer (46A) on the first dielectric layer (46B); Etching sidewall portions (46A-S) of the first dielectric layer (46B) and the second dielectric layer (46A), leaving a dielectric region (46) at the first bottom of the recess (42), the dielectric region (46) comprising a first lower portion of the first dielectric layer (46B) and a second lower portion (46A-B) of the second dielectric layer (46A); and Forming a source / drain region (48) on the dielectric region (46). [13] The method of claim 12, wherein a top surface of the dielectric region (46) is lower than the second bottom surface of the first semiconductor nanolayer (22B). [14] The method of claim 12, wherein a top surface of the dielectric region (46) is level with the second bottom surface of the first semiconductor nanolayer (22B). [15] The method of any one of claims 12 to 14, further comprising, after forming the dielectric region (46), performing a pre-cleaning process (49), wherein the treatment process (47) results in the first lower portion of the first dielectric layer (46B) having a lower etch rate during the pre-cleaning process (49) than the first dielectric layer (46B) at a time prior to the treatment process (47). [16] Method according to claim 12 or 15, wherein the treatment process (47) is carried out using an oxygen-containing process gas. [17] A method according to any one of claims 12 to 16, further comprising: Removing the first sacrificial nanolayer (22A) and the second sacrificial nanolayer (22A); and Forming a replacement gate stack (70), wherein the replacement gate stack (70) comprises portions in spaces left behind by the first sacrificial nanolayer (22A) and second sacrificial nanolayer (22A) to be removed. [18] Procedure which includes: Etching a semiconductor nanolayer (22B) to form a source / drain recess (42), the source / drain recess (42) comprising a first bottom that is lower than a second bottom of the semiconductor nanolayer (22B); Depositing a first dielectric layer (46B), wherein a portion of the first dielectric layer (46B) is located in the source / drain recess (42), the first dielectric layer (46) comprising a first dielectric material; performing a treatment process (47) on the first dielectric layer (46B) to convert the first dielectric material into a second dielectric material; depositing a second dielectric layer (46A) on the first dielectric layer (46B); Etching the second dielectric layer (46A) and the first dielectric layer (46B), leaving a first portion of the first dielectric layer (46B) and a second portion of the second dielectric layer (46A) at a bottom of the source / drain recess (42) to form a dielectric region (46); Performing a pre-cleaning process (49) using an etching gas, wherein the etching gas is capable of etching the first dielectric material at a first etching rate and is capable of etching the second dielectric material at a second etching rate, and wherein the second etching rate is lower than the first etching rate; and Growing a semiconductor region (48) in the source / drain recess (42) by an epitaxial process. [19] The method of claim 18, wherein the pre-cleaning process (49) results in the dielectric region (46) having a concave top surface. [20] The method of claim 18, wherein the pre-cleaning process (49) results in the dielectric region (46) having a convex top surface.

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