Semiconductor structure with stress relief layer and method for producing the same

Abstract

A structure includes a bottom die; a top die disposed over and connected to the bottom die; a stress relief layer having a first portion contacting a sidewall of the top die and a second portion contacting a top surface of the bottom die; and a dielectric gap fill region on the stress relief layer. The dielectric gap fill region includes a dielectric liner and a dielectric layer over the dielectric liner, the stress relief layer having a lower density than the dielectric liner.

Description

background

[0001] Integrated circuit packages may include a plurality of package components, such as device dies and package substrates, bonded together to increase functionality and integration. Stresses may arise due to differences between the various materials of the plurality of package components. These stresses can lead to deflection of the package components, which in turn causes non-bonding problems. Some conductive structural elements intended to be bonded together fail to bond, resulting in circuit failure.

[0002] US 9,761,540 B2 discloses a semiconductor device including a redistribution layer (RDL). A chip is mounted on the RDL within a chip mounting area. The RDL is electrically connected to the chip. A molding compound covers and encapsulates the chip. A first stress relief function is embedded in the molding compound within a peripheral region adjacent to the chip mounting area. A second stress relief function is embedded in the molding compound within the chip mounting area. The first stress relief function is made of a first material. The second stress relief function is made of a second material that is different from the first material.

[0003] DE 11 2012 004 143 T5 and US 2014 / 0 038 360 A1 describe further prior art.

[0004] The invention is defined in the claims. Short description of the drawings

[0005] Aspects of the present disclosure can best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Rather, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. The Fig. 1 to 7, 8A and 9A show illustrations of a method of manufacturing a package with a stress relief layer according to some embodiments. The Fig. 8B and Fig. 9B show illustrations of the fabrication of a package with exposed top dies according to some embodiments. The Fig. 10 and Fig. 11 illustrate a reconfigured wafer and a package sawn from the reconfigured wafer, respectively, according to some embodiments. Fig. 12 shows a process flow for manufacturing a package according to some embodiments. Detailed description

[0006] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present disclosure, reference numbers and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structural element to one or more other elements or structural elements illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90° or in another orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0008] A package including a stress relief layer and a method for fabricating the same are provided. According to some embodiments of the present disclosure, an upper die is bonded to a lower die, which may be a lower wafer. A stress relief layer is formed on a sidewall of the upper wafer and extends onto some portions of a top surface of the lower die. The stress relief layer may have a low elastic modulus and low density so that it can relieve stresses applied by an encapsulation material (gap fill material) that is later deposited on the stress relief layer.

[0009] Embodiments discussed herein are intended to provide examples for enabling making or using the subject matter of the present disclosure, and one of ordinary skill in the art should readily recognize modifications that may be made without departing from the intended scope of various embodiments. Throughout the illustrations and illustrative embodiments, similar reference numerals are used to refer to similar components. While method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0010] The Fig. 1 to 7, 8A, and 9A show illustrations of a method for manufacturing a package with a stress relief layer according to some embodiments. The corresponding processes are also schematically indicated in a process flow 200, which is shown in Fig. 12 is shown.

[0011] Fig. 1 shows a cross-sectional view during the fabrication of a package component 20. According to some embodiments, the package component 20 is a device wafer containing identical device dies 20'. The device dies 20' may include active devices and optionally passive devices (not shown). In alternative embodiments, the package component 20 is an interposer die that does not include active devices and may or may not include passive devices. In still further alternative embodiments, the package component 20 is or includes a package, such as an integrated fan-out (InFO) package, a redistribution structure with redistribution lines, or the like.

[0012] According to some embodiments, the package component 20 includes a semiconductor substrate 22 and structural elements fabricated on a top surface of the semiconductor substrate 22. The semiconductor substrate 22 may be fabricated from or include crystalline silicon, crystalline germanium, crystalline silicon germanium, carbon-doped silicon, or a III-V compound semiconductor. The semiconductor substrate 22 may also be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate.

[0013] In some embodiments, package component 20 includes integrated circuit devices fabricated on top of semiconductor substrate 22. The integrated circuit devices may, in some embodiments, be complementary metal oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, and / or the like.

[0014] In some embodiments, the package component 20 includes vias 26, also referred to as silicon vias (TSVs) 26 or semiconductor vias (also TSVs) 26. The TSVs 26 can be electrically connected to the integrated circuit devices. In some embodiments, the TSVs 26 extend from the top surface of the semiconductor substrate 22 (or from a level higher than the top surface of the semiconductor substrate 22) to an intermediate level of the semiconductor substrate 22. The intermediate level of the semiconductor substrate 22 is located between the top and bottom surfaces of the semiconductor substrate 22. The TSVs 26 are each enclosed by a dielectric isolation layer (not shown) used to electrically isolate the corresponding TSV 26 from the semiconductor substrate 22.

[0015] An interconnect structure 32 is formed over the semiconductor substrate 22 and the integrated circuit devices. The interconnect structure 32 may include an interlayer dielectric (ILD; not individually shown) that fills spaces between gate stacks of transistors (not shown) in the integrated circuit devices. In some embodiments, the ILD is formed from silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), or the like. The ILD may be formed by spin coating, flowable chemical vapor deposition (FCVD), or the like. In some embodiments of the present disclosure, the ILD may also be formed using a deposition method such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or the like.

[0016] The interconnect structure 32 may further include contact pins (not shown) used to electrically connect the integrated circuit devices to upper metal lines and vias. In some embodiments of the present disclosure, the contact pins are made of (or comprise) a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. Fabrication of the contact pins may include: creating contact openings in the ILD; filling the contact openings with one or more conductive materials; and performing a planarization process, such as a chemical mechanical polishing (CMP) process or a machine grinding process, to align top surfaces of the contact pins with the top surface of the ILD.

[0017] In some embodiments, the interconnect structure 32 includes a plurality of dielectric layers 34 (including the ILD) and a plurality of conductive features, such as metal lines / metal pads 36 and vias 38, within the dielectric layers 34. The dielectric layers 34, in some embodiments, may be low-k dielectric layers, also referred to as inter-metal dielectrics (IMDs). Dielectric constants (k values) of the low-k dielectric layers may be, for example, less than about 3.5 or 3.0. The low-k dielectric layers may include a carbonaceous low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), or the like.

[0018] Single and / or dual damascene processes may be used to form metal lines and vias 36 in the dielectric layers 34. In a single damascene process for forming a metal line or via, a trench or via opening is first created in one of the dielectric layers 34, and then the trench or via opening is filled with a conductive material. A planarization process, such as a CMP process, is then performed to remove excess portions of the conductive material that are higher than the top surface of the dielectric layer, leaving a metal line or via in the corresponding trench or via opening.

[0019] In a dual damascene process, a trench and a via opening are created in a dielectric layer, with the via opening being positioned beneath and connected to the trench. Conductive materials are then filled into the trench and the via opening to create a metal line and a via, respectively. The conductive materials may include a diffusion barrier layer and a copper-containing metallic material over the diffusion barrier layer. The diffusion barrier layers may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0020] Guard rings 37 may be formed in the interconnect structure 32, enclosing each of the TSVs 26. The interconnect structure 32 may also include a passivation layer (not shown) disposed over and in contact with a lower upper dielectric layer 34. The passivation layer may be formed from a non-low-k dielectric material that may include silicon and one or more other elements, such as oxygen, nitrogen, carbon, and / or the like. For example, the passivation layer may be formed from or include SiON, SiN, SiOCN, SiCN, SiOC, SiC, or the like.

[0021] A bonding layer 38 is formed over the redistribution structure 32. The bonding layer 38 may be formed from a silicon-containing dielectric material selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, or the like, or combinations thereof. The bonding layer 38 is planarized using a CMP process or a machine grinding process so that its top surface is planar.

[0022] Bond pads 40 (including bond pads 40A and 40B) are formed in the bond layer 38. The active bond pads 40A in the bond pads 40 are electrically connected to underlying structures including the metal lines and vias 36, the integrated circuit devices, and the TSVs 26. The bond pads 40 may include copper and may be formed using a damascene process. The bond layer 38 and the bond pads 40 are planarized so that their upper surfaces are coplanar. The planarization may be performed using a CMP process performed during the formation of the bond pads 40. In some embodiments, the bond pads 40 include active bond pads 40A and dummy bond pads 40B. The active bond pads 40A are used for bonding to higher-level upper dies and are electrically connected to the conductive features 36 and, if applicable, to the TSVs 26.The dummy bond pads 40B can be used to reduce the structural charging effect during manufacturing, for example, in the CMP process. The dummy bond pads 40B can be electrically floating.

[0023] Let us stay with Fig. 1. Device dies 42 (also referred to as upper dies) are bonded to the device dies 20' (also referred to as lower dies) in the wafer 20. The corresponding process is indicated as a process 202 in the process flow 200 shown in Fig. 12. In some embodiments, the device dies 42 may each be a logic die, which may be a main processor die (CPU die), a microcontroller unit die (MCU die), an input / output die (I / O die), a baseband die (BB die), or the like. The device dies 42 may also be memory dies.

[0024] The device dies 42 may include semiconductor substrates 44 and interconnect structures 48 for connecting to active and passive devices within the device dies 42. According to some embodiments, each of the interconnect structures 48 includes a plurality of dielectric layers 45 and a plurality of conductive features 47, such as metal lines / metal pads, within the dielectric layers 45. The dielectric layers 45 may be low-k dielectric layers. Dielectric constants (k values) of the low-k dielectric layers may be, for example, less than about 3.5 or 3.0. The low-k dielectric layers may, in some embodiments, include a carbon-containing low-k dielectric material.

[0025] In some embodiments, fabricating device dies 42 includes fabricating a wafer and then sawing device dies 42 from the respective wafer. This exposes sidewalls of dielectric layers 45. Because dielectric layers 45 may be low-k dielectric layers that are porous, they tend to absorb moisture.

[0026] The device dies 42 each include a bond layer 52 (also referred to as a bond film) and bond pads 50 in the bond layer 52, wherein the bond layer 52 and the bond pads 50 are arranged on the illustrated bottom surface of the respective device die 42. The bottom surfaces of the bond pads 50 may be coplanar with the bottom surface of the bond layer 52. In some embodiments, the bond layer 52 may be formed from a silicon-containing dielectric material selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, or the like, or combinations thereof. The bond pads 50 may include copper and may be formed using a damascene process. The bond layer 52 and the bond pads 50 are planarized so that their surfaces are coplanar, which may be done using a CMP process during the formation of the bond pads 50.

[0027] The bonding may be realized by hybrid bonding. For example, the bond pads 50 are bonded to the bond pads 40A by metal-to-metal direct bonding. In some embodiments, the metal-to-metal direct bonding comprises a copper-to-copper direct bond. Furthermore, the bond layers 52 are bonded to the bond layer 38 by fusion bonding, for example, forming Si-O-Si bonds. Fig. 1 is hereinafter referred to as a reconfigured wafer 54, and in later processes, additional structural elements are fabricated to augment the reconfigured wafer 54.

[0028] In some embodiments, a backside grinding process may be performed to thin the semiconductor substrates 44 of the device dies 42. Thinning the semiconductor substrates 44 reduces the aspect ratio of gaps between adjacent device dies 42 to perform gap filling. Otherwise, the subsequent gap filling process may be difficult due to the otherwise high aspect ratio of the gaps.

[0029] In Fig. 2, a stress relief layer 56 is formed by a deposition or coating process. The corresponding process is indicated as a process 204 in the process flow 200 shown in Fig. 12. In some embodiments, the stress relief layer 56 is deposited by chemical vapor deposition (CVD). Alternatively, other deposition techniques capable of producing conformal or near-conformal layers may be used, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or the like.

[0030] In some embodiments, the stress relief layer 56 includes a silicon-containing dielectric material, such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon oxidecarbonitride, silicon carbide, or the like. In alternative embodiments, the stress relief layer 56 includes a metal-containing dielectric material, such as a metal oxide, a metal nitride, a metal oxynitride, or the like. For example, the stress relief layer 56 may include TiO, TiN, TiON, or the like.

[0031] In some embodiments, the process conditions for depositing the stress relief layer 56 are adjusted to have a reduced internal stress (residual stress) and a reduced density. For example, the internal stress of the stress relief layer 56 may be less than about 30 MPa in some embodiments. The density of the stress relief layer 56 may be less than about 2.2 g / cm 3 or less than about 2.0 g / cm 3 and can be about 1.8 g / cm 3 up to about 2.0 g / cm 3 be.

[0032] In addition, the stress relief layer 56 may have a reduced modulus of elasticity, for example, compared to an adhesive layer (adhesive coating) 60A ( Fig. 5) when manufactured, compared to gap-filling regions 60 when manufactured from molding compound. By reducing the density and elastic modulus of stress relief layer 56, stress relief layer 56 is assisted in absorbing stresses and buffering stresses originating from the higher-lying gap-filling regions 60.

[0033] Reducing the density and elastic modulus of the stress relief layer 56 can be achieved by adjusting the process conditions for depositing the stress relief layer 56. In some embodiments, reducing the density and elastic modulus of the stress relief layer 56 can be achieved by increasing the deposition rate of the stress relief layer 56. For example, when CVD is used, reducing the density and elastic modulus of the stress relief layer 56 can be achieved by decreasing the voltage source power and / or the bias power. In some embodiments, the voltage source power is less than about 800 W, and may be about 500 W to about 1200 W. The bias power may be less than about 1600 W and may be about 1200 W to about 2400 W.

[0034] In alternative embodiments, reducing the density and elastic modulus of the stress relief layer 56 can be achieved by increasing the gas flow rate of precursors for the stress relief layer 56. For example, when CVD is used and when the stress relief layer 56 contains silicon and nitrogen, reducing the density and elastic modulus of the stress relief layer 56 can be achieved by increasing the gas flow rate of precursors such as tetraethyl orthosilicate (TEOS) and O2. In some embodiments, the O2 flow rate can be higher than about 22,500 Ncm3 / min and can be about 15,000 Ncm 3 / min up to about 30,000 Ncm 3 / min. The throughput of TEOS can be higher than about 5.5 Ncm 3 / min and can be about 4 Ncm 3 / min up to about 6 Ncm 3 / min.

[0035] In some embodiments, a thickness of the stress relief layer 56 is selected to be within a certain range to maximize the stress relief effect. If the stress relief layer 56 is too thin, the stress relief effect is too small. Conversely, if the stress relief layer 56 is too thick, it occupies too much volume in the gap filling region. In some embodiments, the stress relief layer 56 has a thickness T1 that is less than about 10 µm and greater than about 0.5 µm. A thickness ratio T1 / T2 may be less than about 15, where T2 is the thickness of the bonding layer 52.

[0036] The stress relief layer 56 has a higher density than the low-k dielectric layers (portions of the dielectric layers 45) in the interconnect structure 48. Accordingly, in addition to the function of relieving stresses, the stress relief layer 56 also has the function of preventing moisture from the external environment from reaching the low-k dielectric layers in the interconnect structure 48. As will be explained with reference to later figures, the stress relief layer 56 may be unpatterned and remain as a protective layer in the final package. In alternative embodiments, the stress relief layer 56 is patterned, as will be explained with reference to the Fig. 3 and Fig. 4. Regardless of whether the stress relief layer 56 is patterned or remains unpatterned, it is formed on all sidewalls of the low-k dielectric layers in the interconnect structure 48 and protects these sidewalls.

[0037] Fig. 3 illustrates the patterning of the stress relief layer 56 according to some embodiments. During these patterning processes, an etch mask 58A may be formed. The corresponding process is indicated as a process 206 in the process flow 200 shown in Fig. 12. In some embodiments, the etch mask 58A is a photoresist or other organic or inorganic material. If the etch mask 58A is a photoresist or other organic material, it may be formed by spin coating and then cured. If the etch mask 58A includes an inorganic material (e.g., silicon nitride), it may be a hard mask formed using a deposition process and then planarized using a planarization process, such as a CMP process or a machine grinding process.

[0038] Then, a process is performed to thin the top surface of the etch mask 58A so that the top surface is lower than the top surfaces of the semiconductor substrates 44. The process may be an etch-back process. This exposes the semiconductor substrates 44 from the upper dies 42. The corresponding process is indicated as a process 208 in the process flow 200 shown in Fig. 12. In some embodiments, the top surface of the etch mask 58A is higher than the illustrated bottom surfaces of the semiconductor substrates 44. This ensures that when the stress relief layer 56 is later patterned, the remaining portions of the stress relief layer 56 have tops that are higher than the illustrated top surfaces of the interconnect structures 48, such that the sidewalls of the low-k dielectric layers in the interconnect structures 48 are protected. The illustrated top surfaces of the interconnect structures 48 also form interfaces with the respective upper-lying semiconductor substrates 44. In some embodiments, the top surfaces of the stress relief layer 56 are lower than the midpoint between the top surfaces and the corresponding bottom surfaces of the semiconductor substrates 44.

[0039] An etching process is then performed to remove the exposed portions of the stress relief layer 56 that are not protected by the etch mask 58A. The etching process may be an isotropic etching process, which may be a dry etching process. The portions of the stress relief layer 56 on the top dies 42 and the upper portions of the sidewalls of the semiconductor substrates 44 are removed. The lower portions of the stress relief layer 56 on the top side of the wafer 20 and the sidewalls of the dielectric layers 45 remain unetched. In a subsequent process, the etch mask 58A is removed.

[0040] Fig. 4 shows a patterning of the stress relief layer 56 according to alternative embodiments. In this patterning process, an etch mask 58B is formed. The corresponding process is indicated as a process 210 in the process flow 200 shown in Fig. 12. In some embodiments, the etch mask 58B is a photoresist patterned in a lithography process. The remaining portions of the etch mask 58B may fully protect the top dies 42, while leaving some portions of the stress relief layer 56 on the top side of the wafer 20 uncovered.

[0041] The remaining portions of the etch mask 58B may extend beyond edges of the upper dies 42 by a distance S2 that is greater than distances from adjacent bond pads 50. Keeping the distance S2 sufficiently large does not compromise the ability of the stress relief layer 56 to relieve stress. In some embodiments, a distance S1 is less than about 9 µm, and thus, the distance S2 is greater than about 10 µm.

[0042] Subsequently, an etching process is performed to remove the exposed portions of the stress relief layer 56 that are not protected by the etching mask 58B. The corresponding process is indicated as a process 212 in the process flow 200 shown in Fig. 12. The etching process may be an isotropic etching process, which may be a dry etching process or a wet etching process. In the resulting structure, some portions of the stress relief layer 56 have remained unetched, while portions of the stress relief layer 56 spaced from the upper dies 42 have been removed. The remaining portions of the stress relief layer 56 may form rings that enclose (and contact) the upper dies 42. In a subsequent process, the etch mask 58B is removed.

[0043] In some embodiments, the Fig. 3 is carried out, while the etching process shown in Fig. 4 is not performed. Accordingly, parts 56A of the stress relief layer 56 remain in the final package, while parts 56B ( Fig. 5) are removed. In alternative embodiments, the Fig. 4 shown etching process is carried out, while the one in Fig. 3 is not performed. Accordingly, the portions 56A of the stress relief layer 56 remain in the final package, while portions 56C ( Fig. 5) be removed.

[0044] In still further embodiments, both the Fig. 3 as well as the etching process shown in Fig. 4 is performed. Accordingly, the parts 56A of the stress relief layer 56 remain in the final package, while the parts 56B and 56C ( Fig. 5) are removed. If the Fig. 3 and Fig. 4 are both performed, the upper parts 56B can be removed before the parts 56C. Alternatively, the patterning process shown in the Fig. 3 and Fig. 4 may be reversed, and parts 56C may be removed before parts 56B. In subsequent figures, parts 56B and 56C are shown in phantom to indicate that these parts may be removed or may remain in place in various embodiments.

[0045] In some embodiments, after optionally covering the Fig. 4 has been carried out, the remaining parts 56A a dummy metal pad 40B. Alternatively, according to the process shown in Fig. 4, the dummy metal pad 40B is uncovered.

[0046] Fig. 5 shows the fabrication of the dielectric gap fill layers 60 over and in contact with the stress relief layer 56. The corresponding process is indicated as a process 214 in the process flow 200 shown in Fig. 12. In some embodiments, the entire dielectric gap fill layer 60 is a molding compound, which may include a base material and filler particles within the base material. The base material may be a polymer, a resin, and / or an epoxy. The filler particles may include silicon dioxide, alumina, silicon oxide, or the like. The manufacturing process may include dispensing the molding compound into a flowable form and curing the molding compound into a solid.

[0047] The dielectric gap fill layer 60 includes a dielectric coating 60A and a dielectric layer 60B over the dielectric coating 60A, wherein the dielectric coating 60A and the dielectric layer 60B are made of different materials. For example, the dielectric coating 60A may include a nitride (such as silicon nitride, silicon oxynitride, or the like), and the dielectric layer 60B may include an oxide (such as silicon oxide).

[0048] In these embodiments, the dielectric coating 60A and the stress relief layer 56 can be made of the same dielectric material (such as silicon nitride or silicon oxynitride) or of different materials, with the dielectric coating 60A still having a higher density and a higher elastic modulus (and a higher dielectric constant) than the stress relief layer 56. This can be achieved by adjusting the process conditions. For example, a source voltage and / or bias voltage for depositing the stress relief layer 56 can be set to be lower than the corresponding source voltage and / or bias voltage for depositing the dielectric coating 60A.The throughput of the precursors for depositing the dielectric coating 60A can also be set to be higher than the throughputs of the corresponding precursors for depositing the stress relief layer 56. This allows the stress relief layer 56 to have a higher deposition rate than the dielectric coating 60A if they are both made of the same material.

[0049] For example, the stress relief layer 56 and the dielectric coating 60A may be made of the same material (such as silicon nitride or silicon oxynitride), and they may have the same composition or different compositions. Throughout this specification, when two materials contain the same elements and the percentages of the elements are also the same, the two materials are referred to as materials having the same composition. Conversely, when two materials contain different elements and / or the percentages of the elements are different, the two materials are referred to as materials having different compositions. The stress relief layer 56 and the dielectric coating 60A may have the same or different compositions.Furthermore, the stress relief layer 56 and the dielectric coating 60A may contain the same elements but have different compositions, or they may contain different elements.

[0050] By reducing the throughputs of the precursors for forming the dielectric coating 60A (which may be the same precursors as those for forming the stress relief layer 56), the density and elastic modulus of the dielectric coating 60A may be higher than those of the stress relief layer 56, regardless of whether the dielectric coating 60A and the stress relief layer 56 have the same or different compositions.

[0051] In a non-inventive example, the dielectric coating 60A is not fabricated, and the entire dielectric gap fill layer 60 may be fabricated from a homogeneous material, such as silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbonitride, or the like. The dielectric gap fill layer 60 may have a higher density DS60 and a higher elastic modulus YM60 than a density DS56 and an elastic modulus YM56 of the stress relief layer 56, respectively. In these embodiments, a density ratio DS60 / DS56 is greater than about 1.05 or greater than about 1.1, and an elastic modulus ratio YM60 / YM56 may also be greater than about 1.05 or greater than about 1.1. However, when the dielectric coating 60A is manufactured, a corresponding density ratio DS60A / DS56 and a corresponding elastic modulus ratio YM60A / YM56 can be in similar ranges, where the values DS60A and YM60A represent the density and the elastic modulus, respectively.the elastic modulus of the dielectric coating is 60A.

[0052] In some embodiments, if the Fig. 3 has been performed, the dielectric gap filling layer 60 is in physical contact with the upper parts of the sidewalls of the semiconductor substrates 44. When the process shown in Fig. 4 has been performed, the dielectric gap fill layer 60 is in physical contact with the top side of the wafer 20, and it may or may not be in physical contact with the dummy bond pads 40B. Otherwise, the dielectric gap fill layer 60 is spaced from the semiconductor substrates 44 and / or from the top side of the wafer 20, depending on which of the Fig. 3 and Fig. 4 processes are not carried out.

[0053] In Fig. 6, a planarization process, such as a CMP process or a machine grinding process, is performed to thin the dielectric gap filling layer 60. The corresponding process is indicated as a process 216 in the process flow 200 shown in Fig. 12. In some embodiments, a portion of the dielectric gap fill layer 60 remains after the planarization process to overlap the upper dies 42. In alternative embodiments, the planarization process is performed until the semiconductor substrates 44 are exposed. The corresponding structure is shown in the Fig. 8B and Fig. 9B.

[0054] Fig. Fig. 7 shows a back grinding process for thinning the semiconductor substrate 22 from the back side. The corresponding process is indicated as a process 218 in the process flow 200 shown in Fig. 12. In some embodiments, the back grinding process is performed using a CMP process or a machine grinding process. The back grinding process exposes the TSVs 26.

[0055] Then, the semiconductor substrate 22 may be recessed in the device dies 20' to create recesses, and some parts (the lower parts shown) of the TSVs 26 protrude beyond the semiconductor substrate 22. Subsequently, a dielectric isolation layer 62 may be formed, as shown in Fig. 8. The corresponding process is indicated as a process 220 in the process flow 200 shown in Fig. 12. The formation of the dielectric isolation layer 62 may include a deposition process for depositing a dielectric layer in the recesses created by recessing the semiconductor substrate 22 so that the protruding portions of the TSVs 26 are located in the dielectric layer; and a subsequent planarization process. The portions of the dielectric layer outside the TSVs 26 are removed, and the remaining portions of the dielectric layer form the dielectric isolation layer 62, which becomes part of the device dies 20' and the wafer 20.

[0056] Fig. 8A shows the fabrication of a backside redistribution structure 64 comprising dielectric layers 68 and RDLs 66 in the dielectric layers 68. The corresponding process is indicated as a process 222 in the process flow 200 shown in Fig. 12. The backside redistribution structure 64 may be fabricated layer by layer. For example, fabricating a single layer of RDLs 66 may include forming a dielectric layer 68 and creating openings in the dielectric layer 68 with a patterning process. The dielectric layers 68 may be made of or include an organic material such as PBO, polyimide, BCB, or the like, or an inorganic material such as silicon oxide, silicon nitride, or the like.

[0057] A metallic seed layer (not shown) is then deposited, having some portions outside the dielectric layer 68 and some other portions extending into the dielectric layer 68. A patterned mask (not shown), such as a photoresist, is then formed over the metallic seed layer, followed by a metal plating process to deposit a metallic material on the exposed metallic seed layer. The patterned mask and the portions of the metallic seed layer covered by the patterned mask are then removed, leaving a layer of RDLs 66.

[0058] Fig. 8A further illustrates the fabrication of electrical interconnect elements 70 on the newly configured wafer 54. In some embodiments, the electrical interconnect elements 70 include solder regions, metal pillars, solder layers, and / or the like. Subsequently, the newly configured wafer 54 may be sawn to fabricate packages 54'. The corresponding process is indicated as a process 224 in the process flow 200 illustrated in Fig. 12 is shown.

[0059] In a subsequent process, which Fig. 9A, the package 54' is bonded to a package component 72. In some embodiments, the package component 72 is a package substrate, an interposer, another package, a printed circuit board, or the like. This creates a package 74.

[0060] The Fig. 8B and Fig. 9B illustrate the fabrication of the package 74 according to alternative embodiments. These embodiments are similar to those shown in Fig. 8A and Fig. 9A, except that the preceding planarization process is performed on the dielectric gap fill layer 60 until the semiconductor substrates 44 of the upper dies 42 have been exposed.

[0061] Fig. 10 shows a top view of the reconfigured wafer 54 prior to the dicing process. Two top dies 42 are shown as an exemplary group, but an actual reconfigured wafer 54 may include multiple groups of top dies 42 forming a matrix. In some embodiments, the stress relief layer 56 is a protective layer that covers the entire wafer 20 and extends to all edges of the reconfigured wafer 54. In alternative embodiments described in Fig. 10, the stress relief layer 56 is structured as a plurality of portions 56A, each disposed on one of the upper dies 42 and further including a ring portion extending outwardly from the corresponding upper die 42.

[0062] Fig. 11 shows a top view of one of the packages 54' that have been sawn from the reconfigured wafer 54 according to some embodiments. In some embodiments, the stress relief layer 56 is a protective layer that covers the entire die 20' and the upper dies 42 and extends to all edges of the package 54'. In alternative embodiments, the stress relief layer 56 is patterned, and the portions 56A of the stress relief layer 56 that extend out from different ones of the upper dies 42 may be separated from each other, or they may have a connecting portion 56C connecting them together.

[0063] Some processes and elements for fabricating a three-dimensional (3D) package according to some embodiments have been discussed above. Other processes and elements may also be used. For example, test structures may be used to assist in verification testing of a 3D package or 3D IC devices. The test structures may include, for example, test pads fabricated in a redistribution layer or on a substrate that enable testing of the 3D package or 3D IC devices, the use of probes and / or probe cards, and the like. Verification testing may be performed on intermediate structures as well as on the final structure. Furthermore, the structures and methods disclosed herein may be used in conjunction with test methodologies that include intermediate verification of proven good die to increase yield and reduce costs.

[0064] The embodiments of the present disclosure have several advantages. By forming the stress relief layer, which has the function of relieving stresses, the stresses introduced by the gap fill layer (encapsulation material) formed later are relieved. The stress relief layer also helps prevent moisture from reaching the low-k dielectric layers in the upper dies.

[0065] In some embodiments of the present disclosure, a method includes: bonding a top die over a bottom wafer; depositing a stress relief layer on the top die and on a top surface of the bottom wafer; forming a dielectric gap fill layer on the stress relief layer; performing a planarization process on the dielectric gap fill layer; and dicing the dielectric gap fill layer and the bottom wafer to fabricate a plurality of packages, one of the packages including the top die, a portion of the stress relief layer, and a bottom die in the bottom wafer.

[0066] In one embodiment, the method further comprises: forming an etch mask on the stress relief layer; recessing the etch mask until a first top surface of the etch mask is lower than a second top surface of the top die; performing an etch process to remove portions of the stress relief layer that are higher than the first top surface; and removing the etch mask. In one embodiment, one of the portions of the stress relief layer removed in the etch process is located on the second top surface of the top die. In one embodiment, the method further comprises: forming a patterned etch mask on the stress relief layer; performing an etch process to remove portions of the stress relief layer; and removing the patterned etch mask.

[0067] In one embodiment, one of the portions of the stress relief layer removed in the etch process is located on a top surface of the bottom die. In one embodiment, the dielectric gap fill layer comprises a molding compound, and the molding compound is in physical contact with the stress relief layer. The dielectric gap fill layer comprises a dielectric coating and a dielectric layer over the dielectric coating. In one embodiment, the stress relief layer and the dielectric coating are made of the same material, and the stress relief layer is formed at a higher deposition rate than the dielectric coating. In one embodiment, the stress relief layer and the dielectric coating are made of the same material, and the stress relief layer has a lower density than the dielectric coating.

[0068] According to some embodiments of the present disclosure, a structure comprises: a bottom die; an top die disposed over and connected to the bottom die; a stress relief layer having a first portion contacting a sidewall of the top die and a second portion contacting a top surface of the bottom die; and a dielectric gap fill region on the stress relief layer, wherein the stress relief layer is in physical contact with a top surface of the bottom die. In one embodiment, the dielectric gap fill region comprises a molding compound in physical contact with the stress relief layer. The dielectric gap fill region comprises: a dielectric coating; and a dielectric layer over and in contact with the dielectric coating, wherein the dielectric coating includes a different material than the dielectric layer.

[0069] In one embodiment, the dielectric coating and the stress relief layer contain the same material, and the stress relief layer has a lower density than the dielectric coating. In one embodiment, the upper die comprises a semiconductor substrate and an interconnect structure beneath the semiconductor substrate, wherein the stress relief layer has a top end that is higher than an interface between the semiconductor substrate and the interconnect structure and lower than another top surface of the upper die. In one embodiment, in a top view of the structure, the second portion forms a ring enclosing the first portion.

[0070] According to some embodiments of the present disclosure, a structure comprises: a lower die; an upper die disposed over and connected to the lower die, the upper die comprising a semiconductor substrate and an interconnect structure below the semiconductor substrate; a stress relief layer having a first portion contacting a first sidewall of the interconnect structure, wherein a top end of the stress relief layer is higher than an interface between the semiconductor substrate and the interconnect structure and lower than a top surface of the semiconductor substrate; and a dielectric gap fill region on the stress relief layer.

[0071] In one embodiment, the dielectric gap-filling region is further in physical contact with a second sidewall of the semiconductor substrate. In one embodiment, the dielectric gap-filling region is further in physical contact with another top surface of the bottom die.

Claims

[1] Method comprising: Bonding an upper die (42) over a lower wafer; Depositing a stress relief layer (56) on the upper die (42) and on a top surface of the lower wafer; Producing a dielectric gap filling layer (60) on the stress relief layer (56); performing a planarization process on the dielectric gap filling layer (60); and Dicing the dielectric gap fill layer (60) and the lower wafer to produce a plurality of packages, one of the packages comprising the upper die (42), a portion of the stress relief layer (56), and a lower die (20') in the lower wafer, the dielectric gap fill layer (60) comprising a dielectric coating (60A) and a dielectric layer (60B) over the dielectric coating (60A), the stress relief layer (56) being formed at a higher deposition rate than the dielectric coating (60A) and / or the stress relief layer (56) having a lower density than the dielectric coating (60A). [2] The method of claim 1, further comprising: Producing an etching mask (58A) on the stress relief layer (56); recessing the etch mask (58A) until a first top surface of the etch mask (58A) is lower than a second top surface of the upper die (42); Performing an etching process to remove portions of the stress relief layer (56) that are higher than the first top surface; and Removing the etching mask (58A). [3] A method according to claim 1 or 2, wherein: one of the parts of the stress relief layer (56) removed in the etching process is located on the second top side of the upper die (42). [4] The method of claim 1 or 2, further comprising: Producing a patterned etching mask (58B) on the stress relief layer (56); Performing an etching process to remove portions of the stress relief layer (56); and Removing the patterned etching mask (58B). [5] The method of claim 4, wherein: one of the parts of the stress relief layer (56) removed in the etching process is located on a top side of the lower die (20'). [6] Method according to one of the preceding claims, wherein: the stress relief layer (56) contains a metal-containing dielectric material. [7] Method according to one of the preceding claims, wherein: the dielectric gap fill layer (60) comprises a molding compound and the molding compound is in physical contact with the stress relief layer (56). [8] A method according to any one of claims 1 to 7, wherein: the stress relief layer (56) and the dielectric coating (60A) are made of the same material. [9] Structure with: a lower die (20'); an upper die (42) disposed above and connected to the lower die (20'); a stress relief layer (56) having a first portion contacting a sidewall of the upper die (42) and a second portion contacting a top surface of the lower die (20'); and a dielectric gap filling region (60) on the stress relief layer (56); wherein the dielectric gap filling region (60) comprises a dielectric coating (60A) and a dielectric layer (60B) over the dielectric coating (60A), the stress relief layer (56) having a lower density than the dielectric coating (60A). [10] Structure according to claim 9, wherein: the stress relief layer (56) further comprises a third portion contacting a top surface of the upper die (42). [11] Structure according to claim 9 or 10, wherein: the dielectric gap filling region (60) comprises a molding compound which is in contact with the stress relief layer (56). [12] The structure of any one of claims 9 to 11, wherein the dielectric layer (60B) is in contact with the dielectric coating (60A), and wherein the dielectric coating (60A) contains a different material than the dielectric layer (60B). [13] Structure according to claim 12, wherein: the dielectric coating (60A) and the stress relief layer (56) contain the same material. [14] Structure according to any one of claims 9 to 13, wherein: the upper die (42) comprises a semiconductor substrate (22) and an interconnect structure (48) under the semiconductor substrate (22), and the stress relief layer (56) has an upper end that is higher than an interface between the semiconductor substrate (22) and the interconnect structure (48) and lower than another upper surface of the upper die (42). [15] Structure according to any one of claims 9 to 14, wherein: in a plan view of the structure, the second part forms a ring enclosing the first part. [16] Structure with: a lower die (20'); an upper die (42) disposed above and connected to the lower die (20'), the upper die (42) comprising: a semiconductor substrate (22), and an interconnect structure (48) under the semiconductor substrate (22); a stress relief layer (56) having a first portion contacting a first sidewall of the interconnect structure (48), wherein an upper end of the stress relief layer (56) is higher than an interface between the semiconductor substrate (22) and the interconnect structure (48) and lower than a top surface of the semiconductor substrate (22); and a dielectric gap filling region (60) on the stress relief layer (56); wherein the dielectric gap filling region (60) comprises a dielectric coating (60A) and a dielectric layer (60B) over the dielectric coating (60A), the stress relief layer (56) having a lower density than the dielectric coating (60A). [17] Structure according to claim 16, wherein: the dielectric gap filling region (60) is further in physical contact with a second sidewall of the semiconductor substrate (22). [18] Structure according to claim 16 or 17, wherein: the dielectric gap filling region (60) is further in physical contact with another top side of the lower die (20').

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