Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device comprises: a semiconductor substrate having a device region and a singulation line region surrounding the device region; a front-side electrode provided on a front side of the semiconductor substrate in the device region; a back-side electrode formed of a metal and provided on a back side opposite to the front side of the semiconductor substrate; a first silicide layer provided between the back side and the back side electrode in the device region;and a second silicide layer provided between the back surface and the back surface electrode in the singulation line region, wherein a contact resistance between the first silicide layer and the semiconductor substrate is lower than a contact resistance between the second silicide layer and the semiconductor substrate, and wherein a hardness of the second silicide layer is lower than a hardness of the first silicide layer;

Description

Background of the inventionArea

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. background

[0002] A silicide layer is formed to reduce the contact resistance between a back surface of a semiconductor substrate and a back electrode. The silicide layer is formed on the entire back surface of the semiconductor substrate in a wafer state, including a singulation line region (see, for example, Patent Literature 1). Citation listPatent literature

[0003] Patent literature 1: JP 2021- 128 961 A SummaryTechnical problem

[0004] To reduce electrical resistance, it is necessary to form a silicide layer that forms excellent ohmic contact with a semiconductor substrate. However, such a silicide layer has high hardness and is thus resistant to mechanical stress. Therefore, if mechanical stress is applied to the silicide layer during a dicing process, the stress would propagate to the semiconductor substrate and a backside electrode in contact with the silicide layer, resulting in chipping or cracking in a region originating from a crystal defect or part of a structural stress concentration. This results in poor withstand voltage or appearance defects and is therefore problematic.

[0005] The present invention has been made to solve the above problem, and it is an object of the present invention to provide a semiconductor device which can achieve excellent ohmic characteristics and thus can suppress the generation of chipping and cracks during a dicing process, and a method for manufacturing a semiconductor device. Solution to the problem

[0006] The object underlying the invention is achieved in a semiconductor device according to the invention with the features of claim 1 and in a method for producing a semiconductor device according to the invention with the features of claim 10. Advantageous further developments are the subject of the respective dependent claims.

[0007] A semiconductor device comprises: a semiconductor substrate having a device region and a singulation line region surrounding the device region; a front-side electrode provided on a front side of the semiconductor substrate in the device region; a back-side electrode formed of a metal and provided on a back side opposite to the front side of the semiconductor substrate; a first silicide layer provided between the back side and the back side electrode in the device region;and a second silicide layer provided between the back surface and the back surface electrode in the singulation line region, wherein a contact resistance between the first silicide layer and the semiconductor substrate is lower than a contact resistance between the second silicide layer and the semiconductor substrate, and wherein a hardness of the second silicide layer is lower than a hardness of the first silicide layer;

[0008] A method of manufacturing a semiconductor device comprises: forming a front-side electrode on a front side of a semiconductor substrate in a device region, the semiconductor substrate having the device region and a singulation line region surrounding the device region; forming a metal layer on a back side opposite to the front side of the semiconductor substrate; and alloying the semiconductor substrate and the metal layer by a heat treatment to form a first silicide layer on the back side in the device region and to form a second silicide layer on the back side in the singulation line region, wherein a contact resistance between the first silicide layer and the semiconductor substrate is lower than a contact resistance between the second silicide layer and the semiconductor substrate, and wherein a hardness of the second silicide layer is lower than a hardness of the first silicide layer. Advantageous effects of the invention

[0009] In the present invention, the first silicide layer in the device region is formed to have low contact resistance with the semiconductor substrate. Accordingly, excellent ohmic characteristics can be obtained between the semiconductor substrate and the backside electrode in the device region. Meanwhile, the second silicide layer in the dicing line region is formed to have low hardness. This can reduce mechanical stress applied when the second silicide layer is cut during a dicing process and can therefore suppress propagation of the stress to the semiconductor substrate in contact with the second silicide layer. As a result, chipping and cracking during the dicing process can be suppressed. Short description of the characters Fig. 1 is a plan view illustrating a semiconductor wafer according to a first embodiment. Fig. 2 is a cross-sectional view illustrating the semiconductor device according to the first embodiment. Fig. 3 is a bottom view illustrating the silicide layers on the back side of the semiconductor wafer according to the first embodiment. Fig. 4 is a cross-sectional view illustrating the semiconductor device according to the first embodiment obtained by dicing in a dicing process. Fig. 5 is a plan view illustrating the semiconductor device according to the first embodiment obtained by dicing. Fig. 6 is a bottom view illustrating the semiconductor device according to the first embodiment obtained by dicing. Fig. 7 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment. Fig. 8 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment. Fig. 9 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment. Fig. 10 is a cross-sectional view illustrating a method of manufacturing the semiconductor device according to the first embodiment. Fig. 11 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment. Fig. 12 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment. Fig. 13 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment. Fig. 14 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment. Description of the embodiments

[0010] A semiconductor device and a method for manufacturing the same according to embodiments of the present invention will be described with reference to the reference numerals. Identical components are denoted by identical symbols, and repeated descriptions thereof may be omitted. First embodiment

[0011] Fig. Figure 1 is a plan view illustrating a semiconductor wafer according to a first embodiment. A plurality of device regions 2 are regularly arranged in a matrix of rows and columns on a semiconductor substrate 1 in a wafer state. A singulation line 3 surrounds each device region 2.

[0012] Fig. 2 is a cross-sectional view illustrating the semiconductor device according to the first embodiment. The semiconductor substrate 1 is formed of silicon or silicon carbide. The semiconductor substrate 1 has an n-type high-concentration layer 1a and an n-type drift layer 1b provided thereon. The n-type high-concentration layer 1a has a higher concentration of n-type impurities than the n-type drift layer 1b. Note that the n-type drift layer 1b may be provided on a single-crystal p-type high-concentration layer, or the n-type drift layer 1b, which is single-crystal, may be provided alone.

[0013] For example, a vertical MOSFET, a diode, or an IGBT is provided in each device region 2 of the semiconductor substrate 1. In such a case, p-type layers, n-type layers, and protrusions and recesses such as trenches are partially or entirely provided on the front side or the back side of the semiconductor substrate 1. Furthermore, the device region 2 includes, for example, an active region through which a current flows during device operation, a termination region provided around the active region to hold the withstand voltage, and a region in which a gate pad is formed. A diffusion layer such as a p-type base layer is formed in the active region.However, the diffusion layer does not necessarily have to be provided in the device region 2, since there may be a case where a Schottky diode is provided or where the semiconductor substrate 1 is used as a resistance element.

[0014] In the device region 2, an interlayer dielectric 4, a front-side electrode 5, and a protective layer 6 are provided on the front side of the semiconductor substrate 1. The front-side electrode 5 is connected to the front side of the semiconductor substrate 1 through an opening of the interlayer dielectric 4. The protective layer 6 protects the outer peripheral part of the front-side electrode 5 by covering it.

[0015] The front electrode 5 is formed from a metal layer made of one or more types of metals. For example, the front electrode 5 is formed from a metal layer including titanium (Ti) or aluminum (Al). A plating layer may be formed on the metal layer using electroless plating or electrolytic plating. The protective layer 6 is formed from, for example, at least one of silicon nitride (SiN), SiSiN (semi-insulating silicon nitride), or polyimide.

[0016] The interlayer dielectric 4, the front-side electrode 5, and the protective layer 6 are not provided in the dicing line region 3. Removing materials with a hardness different from the hardness of the semiconductor substrate 1 from the dicing line region 3 can reduce mechanical stress that would occur during the dicing process.

[0017] A backside electrode 7 formed of a metal is provided on the backside opposite to the frontside of the semiconductor substrate 1. The backside electrode 7 is formed of a metal layer made of one or more types of materials as in the frontside electrode 5, and a plating layer may be formed on the metal layer. In the device region 2, a first silicide layer 8 is provided between the backside of the semiconductor substrate 1 and the backside electrode 7. In the singulation line region 3, a second silicide layer 9 is provided between the backside of the semiconductor substrate 1 and the backside electrode 7. The first silicide layer 8 and the second silicide layer 9 are in contact with the backside of the semiconductor substrate 1.

[0018] Fig. 3 is a bottom view illustrating the silicide layers on the backside of the semiconductor wafer according to the first embodiment. The first silicide layer 8 is provided in each device region 2. The second silicide layer 9 is provided in each region other than the device regions 2, such as in each singulation line region 3.

[0019] Each of the first silicide layer 8 and the second silicide layer 9 is formed of a metal compound containing silicon (Si). Specifically, it is formed of one of a titanium silicide layer (Ti5Si3, TiSi, or TiSi2), a titanium silicon carbide layer (Ti3SiC2), a nickel silicide layer (Ni2Si, NiSi, or NiSi2), a molybdenum silicide layer (Mo3Si, Mo5Si3, or MoSi2), an aluminum silicide layer (AlSi), or a tungsten silicide layer (W5Si3 or WSi2). The materials of the first silicide layer 8 and the second silicide layer 9 can be a combination of compounds of different metal elements, or a combination of compounds of identical metal elements with different composition ratios.

[0020] The contact resistance between the first silicide layer 8 and the semiconductor substrate 1 is lower than the contact resistance between the second silicide layer 9 and the semiconductor substrate 1. Therefore, the first silicide layer 8 can achieve excellent ohmic characteristics. Meanwhile, although the second silicide layer 9 has a high contact resistance with the semiconductor substrate 1, it does not affect the electrical characteristics of the semiconductor device because the second silicide layer 9 is formed in the dicing line region 3. Furthermore, a metal interconnect with a high contact resistance tends to have low hardness. The second silicide layer 9 in the dicing line region 3 has a lower hardness than the first silicide layer 8 and is thinner than the first silicide layer 8.Therefore, a mechanical stress exerted while the second silicide layer 9 is cut during a dicing process can be reduced.

[0021] Fig. 4 is a cross-sectional view illustrating the semiconductor device according to the first embodiment obtained by dicing in a dicing process. Fig. 5 is a plan view illustrating the semiconductor device according to the first embodiment obtained by dicing. Fig. 6 is a bottom view illustrating the semiconductor device according to the first embodiment obtained by dicing. Note that the semiconductor substrate 1 in a wafer state is attached to a dicing foil (not illustrated) during the dicing process.

[0022] Each dicing line region 3 is divided into invalid regions 3a and a dicing cut region 3b by a dicing process. The invalid regions 3a are adjacent to the device regions 2. Each semiconductor device obtained by dicing at least partially includes the invalid regions 3a. The second silicide layer 9 is provided in the invalid regions 3a on the backside of the semiconductor substrate 1.

[0023] The cutting width of the dicing process performed by a blade is approximately 30 µm. Thus, it is preferable to set the width of the dicing line region 3 to 30 + α µm by adding the positional accuracy α of the blade. That is, the width of the dicing line region 3 is preferably equal to or greater than 30 µm. Accordingly, the silicide layer can be formed in the entire region through which the dicing blade is arranged to pass.

[0024] The Fig. 7 to 10 are cross-sectional views illustrating a method of manufacturing the semiconductor device according to the first embodiment. First, as shown in Fig. 7 illustrates, the semiconductor substrate 1 is formed by epitaxially growing the n-type drift layer 1b on a single-crystal n-type layer 1a with high concentration.

[0025] Next, as in Fig. As illustrated in Figure 8, the interlayer dielectric 4, the front-side electrode 5, and the protective layer 6 are partially formed on the front side of the semiconductor substrate 1 by a mask process. Note that p-type layers, n-type layers, and protrusions and recesses such as trenches can be partially or entirely formed on the front side or the back side of the semiconductor substrate 1 by ion implantation or etching. The thickness of the semiconductor substrate 1 can be reduced by processing.

[0026] Next, as in Fig. 9, a metal layer 10 is formed on the back surface of the semiconductor substrate 1 using a sputtering method or vapor deposition. A heat treatment is applied to the metal layer 10. Accordingly, the silicon of the semiconductor substrate 1 and metal atoms of the metal layer 10 are mutually diffused, so that the second silicide layer 9 is formed. The heat treatment method includes sintering, RTA (Rapid Thermal Treatment), FLA (Flash Lamp Heat Treatment), or laser heat treatment. The temperature of the heat treatment is set to a relatively low temperature of approximately 300 to 800°C. Accordingly, the second silicide layer 9, which has a high contact resistance with the semiconductor substrate 1 and is thin, is formed.

[0027] The second silicide layer 9 can be formed using the energy of metal ions deposited during the sputtering process. Furthermore, the temperature of the sputtering process can be adjusted to accelerate the alloying of the metal ions. Furthermore, performing etching (i.e., sputter etching) on the backside of the semiconductor substrate 1 during the sputtering process can induce crystal stress in the semiconductor substrate 1, which in turn can facilitate the formation of the second silicide layer 9 with high contact resistance. Forming the second silicide layer 9 by adjusting the sputtering process conditions in this way can reduce the number of heat treatment steps.

[0028] Next, as in Fig. As illustrated in Figure 10, the back surface of the semiconductor substrate 1 is irradiated with a laser beam only in the device region 2. This promotes the thermal reaction of the silicide in the device region 2, so that the first silicide layer 8 is formed. The heat treatment temperature here is set higher than the temperature for forming the second silicide layer 9, for example, to a temperature greater than or equal to 800°C. As a result, the first silicide layer 8 becomes thicker than the second silicide layer 9, and it has a higher composition ratio of silicon to a metal element than the second silicide layer 9.

[0029] Subsequently, the backside electrode 7 is formed on the backside of the semiconductor substrate 1 using, for example, a sputtering method, vapor deposition, electroless plating, or electrolytic plating. Note that the metal layer 10 may be entirely alloyed as the silicide layer, or the remaining part of the metal layer 10 may be used as the backside electrode 7. The semiconductor device according to the present embodiment is produced through the above steps.

[0030] As described above, in this embodiment, the first silicide layer 8 is formed in the device region 2 so as to have low contact resistance with the semiconductor substrate 1. Accordingly, excellent ohmic characteristics can be obtained between the semiconductor substrate 1 and the backside electrode 7 in the device region 2. Meanwhile, the second silicide layer 9 is formed in the dicing line region 3 so as to have low hardness. This can reduce mechanical stress exerted while the second silicide layer 9 is cut during a dicing process and thus can suppress propagation of the stress to the semiconductor substrate 1 in contact with the silicide layer 9. As a result, chipping and cracking during the dicing process can be suppressed.

[0031] Furthermore, the second silicide layer 9 is thinner than the first silicide layer 8. Accordingly, a mechanical stress exerted while the second silicide layer 9 is cut by the dicing process can be further reduced.

[0032] Furthermore, the first silicide layer 8 in the device region 2 has a higher composition ratio of silicon to the metal element than the second silicide layer 9 in the singulation line region 3. Accordingly, the first silicide layer 8 having excellent ohmic contact with the semiconductor substrate 1 can be obtained. For example, the first silicide layer 8 contains TiSi2, and the second silicide layer 9 contains Ti5Si3. Therefore, since the first silicide layer 8 has a high composition ratio of silicon, it has low contact resistance with the semiconductor substrate 1 and can therefore achieve excellent ohmic properties. Meanwhile, since the second silicide layer 9 has a high composition ratio of the metal element, it has high contact resistance with the semiconductor substrate 1. However, since the second silicide layer 9 has a sparse crystal lattice, it has low hardness.This can prevent the propagation of stress to the semiconductor substrate 1 while the second silicide layer 9 is being cut during a dicing process.

[0033] The first silicide layer 8 and the second silicide layer 9 may be silicide layers with different crystal structures. Note that the crystal structure of the first silicide layer 8 in the device region 2 has a lower resistivity than the crystal structure of the second silicide layer 9. Therefore, the on-state stress can be reduced. For example, the first silicide layer contains titanium silicide (TiSi2) with a C54 structure (i.e., face-centered orthorhombic), and the second silicide layer contains TiSi2 with a C49 structure (i.e., base-centered orthorhombic). Silicide with the C54 structure has a dense atom arrangement, and thus has excellent ohmic properties and high hardness. Titanium silicide with the C49 structure has a resistivity of approximately 60 µΩ·cm, and titanium silicide with the C54 structure has a resistivity of approximately 15 to 20 µΩ·cm.Thus, excellent electrical resistance can be obtained in the device region 2. The C49 structure is formed at a temperature approximately as low as 400°C, while the C54 structure is formed at a temperature approximately as high as 800°C. Therefore, it is possible to separately form the first silicide layer 8 and the second silicide layer 9 by adjusting the heat treatment conditions for forming the silicide.

[0034] The first silicide layer 8 and the second silicide layer 9 may be silicide layers with different types of crystallinity. For example, the second silicide layer 9 may be in a quasi-crystalline or an amorphous (i.e., non-crystalline) state. Amorphous titanium silicide has lower hardness than crystalline titanium silicide. Therefore, the propagation of stress to the semiconductor substrate 1 can be suppressed while the second silicide layer 9 is singulated. Meanwhile, the first silicide layer 8 is formed from a metal compound containing crystalline silicon to obtain excellent ohmic properties. Crystalline silicide has a dense atom arrangement and therefore has excellent ohmic properties and high hardness.It should be noted that crystal stress occurs in the semiconductor substrate 1 due to damage caused by a sputtering process performed thereon or when etching (i.e., sputter etching) is performed on the front surface of the semiconductor substrate 1. Subsequently, when a metal layer is formed, the metal elements enter the gap between the crystals, so that a layer in a quasi-crystalline or an amorphous state is formed. Subsequently, heat treatment is applied only to the device region 2, so that the first silicide layer 8 is formed in a crystalline state. Meanwhile, the layer in the dicing line region 3, which is not subjected to the heat treatment, remains as the second silicide layer 9 in a quasi-crystalline or amorphous state. Second embodiment

[0035] The Fig. 11 to 14 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment. First, the semiconductor substrate 1 is formed, and then the interlayer dielectric 4, the front-side electrode 5, and the protective layer 6 are partially formed on the front side of the semiconductor substrate 1 as in the first embodiment.

[0036] Next, as in Fig. As illustrated in Figure 11, a first metal layer 10a is formed on the back surface of the semiconductor substrate 1 using a sputtering method or vapor deposition. At this time, a predetermined silicide layer may be formed between the semiconductor substrate 1 and the first metal layer 10a.

[0037] Next, as in Fig. 12, a resist 11 is formed on the backside of the semiconductor substrate 1 in the device region 2. Subsequently, etching is performed using the resist 11 as a mask to remove the first metal layer 10a in the dicing line region 3. When the predetermined silicide layer is formed on the backside of the semiconductor substrate 1 in the dicing line region 3, such a silicide layer is removed at the same time. Subsequently, the resist 11 is removed.

[0038] Next, as in Fig. As illustrated in Fig. 13, a second metal layer 10b is formed on the exposed back surface of the semiconductor substrate 1 using a sputtering method or vapor deposition. At this time, a predetermined silicide layer may be formed between the semiconductor substrate 1 and the second metal layer 10b. Note that the first metal layer 10a and the second metal layer 10b may be formed of the same type of metal or different metals.

[0039] Next, as in Fig.14, a laser heat treatment is performed by irradiating the entire back surface of the semiconductor substrate 1 with a laser beam. Accordingly, the semiconductor substrate 1 and the first metal layer 10a thermally react to form the second silicide layer 9, and further, the semiconductor substrate 1 and the second metal layer 10b thermally react to form the first silicide layer 8.

[0040] As the first metal layer 10a, the type of metal with excellent ohmic properties is selected. For example, titanium is selected as the first metal layer 10a for the n-type semiconductor substrate 1. Meanwhile, aluminum is selected as the second metal layer 10b.

[0041] When a thick metal layer is formed, a silicide formed by heat treatment also becomes thick. Thus, the first metal layer 10a is formed thicker than the second metal layer 10b. Accordingly, the first silicide layer 8 in the device region 2 becomes thick.

[0042] The laser heat treatment conditions are adjusted to sufficiently perform the heat treatment for the thickness of the first metal layer 10a. Accordingly, the first silicide layer 8 can be formed thicker than the second silicide layer 9, and thus excellent ohmic contact with the semiconductor substrate 1 can be achieved. Note that if sufficient heat treatment is not performed, only a small difference in thickness will exist between the first silicide layer 8 and the second silicide layer 9.

[0043] In this embodiment, the second silicide layer 9 and the first silicide layer 8 can be formed from different metals. Furthermore, the first silicide layer 8 and the second silicide layer 9 can be formed simultaneously by irradiating the entire surface with a laser beam without performing pattern irradiation during laser annealing. The other configurations and advantageous effects of this embodiment are similar to those of the first embodiment.

[0044] Although the preferred embodiments and the like have been described in detail above, the present invention is not limited to the above-described embodiments and the like. Instead, the above-described embodiments and the like may be subjected to various modifications and substitutions without departing from the scope of the invention described in the claims. Aspects of the present invention are described collectively as supplementary notes. (Supplementary Note 1)

[0045] Semiconductor device comprising: a semiconductor substrate having a device region and a singulation line region surrounding the device region; a front side electrode provided on a front side of the semiconductor substrate in the device region; a backside electrode formed of a metal and formed on a backside opposite to the frontside of the semiconductor substrate; a first silicide layer provided between the back surface and the back surface electrode in the device region; and a second silicide layer provided between the back surface and the back surface electrode in the singulation line region, wherein a contact resistance between the first silicide layer and the semiconductor substrate is lower than a contact resistance between the second silicide layer and the semiconductor substrate, and a hardness of the second silicide layer is lower than a hardness of the first silicide layer. (Supplementary Note 2)

[0046] A semiconductor device according to supplementary note 1, wherein the second silicide layer is thinner than the first silicide layer. (Supplementary Note 3)

[0047] A semiconductor device according to supplementary note 1 or 2, wherein the first silicide layer has a higher composition ratio of silicon to a metal element than the second silicide layer. (Supplementary Note 4)

[0048] A semiconductor device according to supplementary note 1 or 2, wherein a crystal structure of the first silicide layer has a lower specific resistance than a crystal structure of the second silicide layer. (Supplementary Note 5)

[0049] A semiconductor device according to supplementary note 1 or 2, wherein the first silicide layer is in a crystalline state, and the second silicide layer is in a quasi-crystalline or amorphous state. (Supplementary Note 6)

[0050] A semiconductor device according to any one of supplementary notes 1 to 5, wherein a plurality of the device regions are formed in a matrix of rows and columns on the semiconductor substrate in a wafer state. (Supplementary Note 7)

[0051] The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein the front side electrode is not provided on the front side of the dicing line region. (Supplementary Note 8)

[0052] A semiconductor device according to any one of supplementary notes 1 to 7, wherein a width of the singulation line region is greater than 30 µm. (Supplementary Note 9)

[0053] A semiconductor device according to any one of supplementary notes 1 to 8, wherein the semiconductor substrate is formed of silicon or silicon carbide. (Supplementary Note 10)

[0054] A method for manufacturing a semiconductor device comprising: Forming a front-side electrode on a front side of a semiconductor substrate in a device region, the semiconductor substrate having the device region and a singulation line region surrounding the device region; Forming a metal layer on a back side opposite the front side of the semiconductor substrate; and Alloying the semiconductor substrate and the metal layer by a heat treatment to form a first silicide layer on the backside in the device region and to form a second silicide layer on the backside in the singulation line region, wherein a contact resistance between the first silicide layer and the semiconductor substrate is lower than a contact resistance between the second silicide layer and the semiconductor substrate, and a hardness of the second silicide layer is lower than a hardness of the first silicide layer. (Supplementary Note 11)

[0055] A method of manufacturing a semiconductor device according to Supplementary Note 10, wherein a heat treatment temperature for the device region is higher than a heat treatment temperature for the singulation line region. (Supplementary Note 12)

[0056] A method of manufacturing a semiconductor device according to supplementary note 10 or 11, wherein, as the metal layer, a first metal layer is formed in the device region, and a second metal layer different from the first metal layer is formed in the dicing line region. (Supplementary Note 13)

[0057] The method of manufacturing a semiconductor device according to Supplementary Note 12, wherein a laser heat treatment is performed on an entire back surface of the semiconductor substrate so that the semiconductor substrate and the first metal layer are alloyed to form the first silicide layer, and the semiconductor substrate and the second metal layer are alloyed to form the second silicide layer. List of reference symbols

[0058] 1 semiconductor substrate; 2 device region; 3 singulation line region; 5 front-side electrode; 7 back-side electrode; 8 first silicide layer; 9 second silicide layer; 10 metal layer; 10a first metal layer; 10b second metal layer

Claims

[1] Semiconductor device comprising: • a semiconductor substrate (1) having a device region (2) and a singulation line region (3) surrounding the device region (2); • a front side electrode (5) provided on a front side of the semiconductor substrate (1) in the device region (2); • a backside electrode (7) formed of a metal and provided on a backside opposite to the frontside of the semiconductor substrate (1); • a first silicide layer (8) provided between the back surface and the back surface electrode (7) in the device region (2); and • a second silicide layer (9) provided between the back side and the back side electrode (7) in the singulation line region (3), wherein • a contact resistance between the first silicide layer (8) and the semiconductor substrate (1) is lower than a contact resistance between the second silicide layer (9) and the semiconductor substrate (1), and • a hardness of the second silicide layer (9) is lower than a hardness of the first silicide layer (8). [2] A semiconductor device according to claim 1, wherein the second silicide layer (9) is thinner than the first silicide layer (8). [3] A semiconductor device according to claim 1 or 2, wherein the first silicide layer (8) has a higher composition ratio of silicon to a metal element than the second silicide layer (9). [4] A semiconductor device according to claim 1 or 2, wherein a crystal structure of the first silicide layer (8) has a lower specific resistance than a crystal structure of the second silicide layer (9). [5] A semiconductor device according to claim 1 or 2, wherein • the first silicide layer (8) is in a crystalline state, and • the second silicide layer (9) is in a quasi-crystalline or amorphous state. [6] A semiconductor device according to any one of claims 1 to 5, wherein a plurality of said device regions (2) are formed in a matrix of rows and columns on said semiconductor substrate (1) in a wafer state. [7] A semiconductor device according to any one of claims 1 to 6, wherein the front side electrode (5) is not provided on the front side in the dicing line region (3). [8] The semiconductor device according to any one of claims 1 to 7, wherein a width of the dicing line region (3) is greater than or equal to 30 µm. [9] A semiconductor device according to any one of claims 1 to 8, wherein the semiconductor substrate (1) is formed of silicon or silicon carbide. [10] A method of manufacturing a semiconductor device comprising: • forming a front side electrode (5) on a front side of a semiconductor substrate (1) in a device region (2), the semiconductor substrate (1) having the device region (2) and a singulation line region (3) surrounding the device region (2); • Forming a metal layer (10) on a back side opposite the front side of the semiconductor substrate (1); and • Alloying the semiconductor substrate (1) and the metal layer (10) by a heat treatment to form a first silicide layer (8) on the backside in the device region (2) and to form a second silicide layer (9) on the backside in the singulation line region (3), wherein • a contact resistance between the first silicide layer (8) and the semiconductor substrate (1) is lower than a contact resistance between the second silicide layer (9) and the semiconductor substrate (1), and • a hardness of the second silicide layer (9) is lower than a hardness of the first silicide layer (8). [11] A method of manufacturing a semiconductor device according to claim 10, wherein a heat treatment temperature for the device region (2) is higher than a heat treatment temperature for the dicing line region (3). [12] A method of manufacturing a semiconductor device according to claim 10 or 11, wherein, as the metal layer (10), a first metal layer (10a) is formed in the device region (2), and a second metal layer (10b) different from the first metal layer (10a) is formed in the dicing line region (3). [13] A method of manufacturing a semiconductor device according to claim 12, wherein a laser heat treatment is performed on an entire back surface of the semiconductor substrate (1) so that the semiconductor substrate (1) and the first metal layer (10a) are alloyed to form the first silicide layer (8), and the semiconductor substrate (1) and the second metal layer (10b) are alloyed to form the second silicide layer (9).

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