Semiconductor device with an embossed die pad

Abstract

A semiconductor device comprises a die pad with a top and a bottom surface, and a semiconductor die mounted on the top surface of the die pad. The bottom surface of the die pad includes at least two embossed edge regions and one unembossed region. The die pad includes an unembossed connecting ridge located between two embossed edge regions of the bottom surface. One area of ​​the top surface is larger than one area of ​​the unembossed region of the bottom surface.

Description

Technical area

[0001] The present disclosure relates to semiconductor devices with embossed die pads and associated manufacturing processes. background

[0002] Semiconductor devices can include die pads for mounting semiconductor dies, where the size of a die pad may be determined by the requirements for compatibility with the footprint. A die pad's mounting area may therefore be limited to a specific area, meaning that only semiconductor dies up to a certain size can be mounted on the die pad. In light of this, it may be desirable to provide die pads and semiconductor devices with a sufficient mounting area while simultaneously meeting existing footprint compatibility requirements. Additionally, it may be desirable to provide simple and cost-effective methods for manufacturing the die pads and semiconductor devices. Summary

[0003] One aspect of the present disclosure relates to a semiconductor device. The semiconductor device comprises a die pad having a top and a bottom surface. The semiconductor device further comprises a semiconductor die mounted on the top surface of the die pad. The bottom surface of the die pad comprises at least two embossed edge regions and one unembossed region. The die pad includes an unembossed tie bar located between two embossed edge regions of the bottom surface. One area of ​​the top surface is larger than one area of ​​the unembossed region of the bottom surface.

[0004] Another aspect of the present disclosure relates to a method. The method comprises a step of providing a metal panel. The method further comprises a step of forming several first openings in the metal panel to form a conductor frame panel comprising several die pads, the several die pads being arranged in a row, with two adjacent die pads being separated by two adjacent first openings and connected by a connecting bridge between the two first openings. The method further comprises a step of embossing edge regions of the underside of the die pads, wherein material of the die pads is pressed into a region of the first openings.The process further comprises a step of forming several second openings at the position of the several first openings in order to remove the material pressed into the area of ​​the first openings, wherein each second opening is wider than the first openings, with the two adjacent die pads still connected by the connecting bridge.

[0005] Another aspect of the present disclosure relates to a method. The method comprises a step of providing a conductor frame panel comprising several die pads arranged in multiple rows. Each die pad has a top and a bottom surface. The bottom surface of each die pad comprises an embossed border region and an unembossed area. One area of ​​the top surface is larger than one area of ​​the unembossed area of ​​the bottom surface. The method further comprises a step of mounting several semiconductor dies onto the top surfaces of the die pads. The method further comprises a step of attaching several clips to the top surfaces of the semiconductor dies. The method further comprises a step of performing an encapsulation process, forming several rods made of an encapsulation material, each rod encapsulating a series of die pads.The process also includes a step of singulating the multiple rods into multiple semiconductor packages. Brief description of the drawings

[0006] Devices and methods according to the disclosure are described in more detail below based on the drawings. The elements in the drawings are not necessarily to scale with respect to one another. Similar reference numerals may denote corresponding similar parts. The technical features of the various illustrated examples may be combined, provided they are not mutually exclusive, and / or they may be selectively omitted if they are not described as absolutely necessary. Fig. 1 contains the Fig. Figures 1A to 1C, the different views of a diepad 100, illustrate that may be contained in a semiconductor device according to the disclosure. Fig. 2 contains the Fig. 2A and Fig. 2B, which contain various views of a semiconductor device 200 according to the disclosure. Fig. 3 contains the Fig. 3A and Fig. 3B, which contain various views of a semiconductor device 300 according to the disclosure. Fig. Figure 4 illustrates a flowchart for a procedure according to the disclosure. Fig. 5 contains the Fig. 5A to 5E, which schematically illustrate a procedure according to the disclosure. Fig. Figure 6 illustrates a flowchart for a procedure according to the disclosure. Fig. 7 contains the Fig. Figures 7A to 7F, which schematically illustrate a method for manufacturing a semiconductor device 700 according to the disclosure. Detailed description

[0007] The following detailed description refers to the accompanying drawings, which illustrate certain aspects in which the disclosure can be put into practice. In this context, directional terms such as "top," "bottom," "front," "back," etc., may be used in relation to the orientation of the described figures. Since the components of the described devices can be arranged in various orientations, the directional terminology serves only for illustration and is in no way limited. Other aspects may also be used, and structural or logical modifications may be made without departing from the concept of the present disclosure. Therefore, the following detailed description is not to be understood in a limited sense, and the concept of the present disclosure is defined by the accompanying claims.

[0008] In the Fig. Figures 1A to 1C show different views of a diepad 100 that may be included in a semiconductor device according to the disclosure. It is noted that an exemplary method for manufacturing one or more such diepads, e.g., in conjunction with Fig. Figure 5 shows and describes the Diepad 100. The Diepad 100 may contain or be made of a metal or metal alloy. For example, the Diepad 100 may contain a core material comprising at least one of copper, a copper alloy, aluminum, an aluminum alloy, or the like. Optionally, the Diepad 100 may be coated with at least one coating material comprising, for example, at least one of nickel, nickel-phosphorus, nickel-nickel-phosphorus, copper, silver, or the like. The coating material may coat the entire Diepad 100 (or its core material) or only selected sections thereof. It is understood that the core material and the coating material of the Diepad 100 may depend on the type of semiconductor die to be mounted on the Diepad 100 and / or on the material of an electrical connecting element (e.g., wire, tape, clip, or the like) to be connected to the Diepad 100.

[0009] The diepad 100 can have a top surface 10 and an opposing bottom surface 12. The bottom surface 12 of the diepad 100 can have at least two embossed edge regions 14 and one unembossed region 16. Measured in a direction perpendicular to the top surface 10 or the bottom surface 12, i.e., in the z-direction, the thickness of the embossed edge regions 14 can be less than the thickness of the unembossed region 16. In the example shown, the bottom surface 12 can have an exemplary number of three embossed edge regions 14A to 14C. In other examples, the number of embossed edge regions 14 can be two or even more than three. In the Fig. In the exemplary top view of the underside 12 of the diepad 100 shown in Figure 1C, the underside 12 of the diepad 100 can include a first embossed edge region 14A, which is arranged on the underside of the diepad 100, and a second embossed edge region 14B, which is arranged on the top side of the diepad 100 opposite the underside. In the case shown, each of the embossed edge regions 14A and 14B can essentially have the shape of a rectangle. In other examples, the shape of the embossed edge regions 14 can be different. In one exemplary embodiment, the underside 12 can have only two embossed regions 14A and 14B, while the one shown in Figure 1C has two embossed regions 14A and 14B. Fig. The area shown in 1C may be an unmarked area, i.e., its thickness may be equal to that of the unmarked area 16.

[0010] The underside 12 of the diepad 100 may optionally contain a third embossed edge area 14C, located on the right side of the diepad 100. Fig. 1C is arranged and connects the underside and the top side of the diepad 100. In the illustrated example, the third embossed edge area 14C can extend across the entire right side of the diepad 100 and partially across the underside and top side of the diepad 100. The third embossed edge area 14C can thus have the shape of the letter "U" opening to the left. The embossed edge areas 14A to 14C can be separated by sections of the unembossed area 16.

[0011] Since the underside 12 of the diepad 100 can contain embossed edge regions 14A to 14C, but the top side 10 cannot, an area of ​​the top side 10 can be larger than an area of ​​the unembossed region 16 of the underside 12. In the illustrated example, the embossed edge regions 14A to 14C can surround the unembossed region 16 on three sides of the diepad 100. In another example, the diepad 100 need not necessarily contain the third embossed edge region 14C; that is, the embossed edge regions 14A and 14B can be located on two opposite sides of the diepad 100, while the other two sides of the diepad 100 can be free of embossed edge regions.

[0012] Measured in the z-direction, the thickness of the embossed edge regions 14A to 14C can be in a range of approximately 60% to approximately 90% (and in particular in a range of approximately 85% to approximately 90%) of the thickness of the unembossed region 16. In other words, the embossing depth can be in a range of approximately 10% to approximately 40% (and in particular in a range of approximately 10% to approximately 15%) of the thickness of the unembossed region 16 when measured in the z-direction. A dimension d measured in the y-direction A The dimension of the first embossed edge region 14A can range from approximately 0.2 mm to approximately 0.6 mm. A dimension d measured in the y-direction B of the second embossed edge area 14B can be similar to the dimension d A be. A dimension d measured in the x-direction cThe third embossed edge area 14C can range from approximately 0.4 mm to approximately 0.8 mm. All three of these dimensions can vary depending on the requirements for the base area and / or the embossing process. Optionally, a larger area of ​​regions 14A to 14C can improve the robustness of a mold joint positioned underneath.

[0013] The diepad 100 can contain at least one unembossed tie bar 18 arranged between two embossed edge regions 14 of the underside 12. In the manufacture of semiconductor devices, tie bars can be designed to mechanically connect adjacent diepads of a conductor frame panel, as is done, for example, in the process of Fig. Figure 5 shows that in the example shown, the diepad 100 can contain a first connecting rib 18A located between the first embossed edge region 14A and the third embossed edge region 14C, and a second connecting rib 18B located between the second embossed edge region 14B and the third embossed edge region 14C. The embossed edge regions 14A to 14C can surround the unembossed region 16 on three sides of the diepad 100, except at the locations of the unembossed connecting ribs 18A and 18B.

[0014] As from the in Fig. As can be seen in the exemplary view of the underside 12 shown in Figure 1C, each of the connecting webs 18A and 18B can contain a first section 20A with a first width w1 measured in the x-direction and a second section 20B with a second width w2 measured in the x-direction, which is smaller than the first width w1. The first section 20A of the respective connecting web 18 can be arranged within the area (or base) of the top surface 10, while the second section 20B of the respective connecting web 18 can extend beyond the area of ​​the top surface 10. Measured in the y-direction, a dimension d TB of the first section 20A of the first connecting web 18A, which is arranged between the two embossed edge regions 14A and 14C, of ​​dimension d A The same applies to the first section 20A of the second connecting web 18B and the dimension d. B apply.

[0015] The diepad 100 can optionally include an opening 22 that extends through the diepad 100 in the z-direction from the top 10 to the bottom 12. In the illustrated example, the opening 22 can be rectangular. In other examples, the shape of the opening 22 can vary and may be round, circular, elliptical, square, etc. The bottom 12 of the diepad 100 can include an embossed area 24 surrounding the opening 22.

[0016] In the Fig. 2A and Fig. Figure 2B shows various views of a semiconductor device 200 according to the disclosure. The semiconductor device 200 may include a diepad 100 that is similar to or identical with the diepad 100 of the Fig. The semiconductor device 200 may further comprise one or more semiconductor dies 26 mounted on the top surface 10 of the die pad 100, as well as one or more electrical connecting elements 28 connected to the semiconductor die 26.

[0017] In general, the semiconductor dies described herein can be fabricated from an elementary semiconductor material (e.g., Si), a wide-bandgap semiconductor material, or a compound semiconductor material (e.g., SiC, GaN, SiGe, GaAs). The semiconductor dies can be of any type and can contain integrated circuits with active and / or passive electronic components. The integrated circuits can be designed as integrated logic circuits, analog integrated circuits, integrated mixed-signal circuits, integrated power circuits, memory circuits, integrated passive devices, and so on. The terms "die," "semiconductor die," "chip," and "semiconductor chip" may be used interchangeably in this description.

[0018] The semiconductor die 26 may be a power semiconductor die. In this context, the term "power semiconductor die" can refer to a semiconductor die that provides at least one of the following capabilities: high voltage blocking or high current handling capabilities. A power semiconductor die may be designed to carry high currents with a maximum current rating of a few amperes, such as 10A, or a maximum current rating of up to 100A or more. Similarly, the voltages associated with such current ratings can range from a few volts to several tens, hundreds, or even thousands of volts, such as 1200V, 1600V, 2400V, or similar. Power semiconductor dies can be used in any type of power application, such as MOSFETs (metal-oxide-semiconductor field-effect transistors), half-bridge circuits, power modules with a gate driver, and so on.For example, semiconductor dies can contain or be part of a power device such as a power MOSFET, a low-voltage MOSFET, a power IGBT (Insulated Gate Bipolar Transistor), a power diode, a superjunction power MOSFET, etc.

[0019] In the illustrated example, the semiconductor device 200 can include an exemplary number of two electrical connecting elements 28A and 28B, implemented as clips. The clips 28A, 28B can contain or be made of a metal or metal alloy. A core material and / or a coating material of the clips 28A, 28B can be similar to or identical with the materials used in connection with the die pad 100 of the Fig. The first clip 28A can contact one or more electrical contacts of the semiconductor die 26, which are arranged on the top side of the semiconductor die 26, and can, for example, include a single lead or pin 30A. Similarly, the second clip 28B can contact one or more electrical contacts of the semiconductor die 26, which are arranged on the top side of the semiconductor die 26, and can, for example, include three leads or pins 30B.

[0020] In an unrestricted example, the semiconductor die 26 can contain, or correspond to, a power transistor, having a drain electrode located on the underside of the semiconductor die 26 facing the top surface 10 of the die pad 100, and a source electrode and a gate electrode located on the top surface of the semiconductor die 26 facing away from the top surface 10 of the die pad 100. In such a vertical power transistor, the drain electrode can be electrically connected to the die pad 100, the source electrode to the second clip 28B, and the gate electrode to the first clip 28A. The electrodes of the power transistor can thus be accessed via the die pad 100 and the terminals 30A and 30B.

[0021] In the Fig. 3A and Fig. Figure 3B shows various views of a semiconductor device 300 according to the disclosure. The semiconductor device 300 may have some or all of the features of the semiconductor device 200. Fig. 2. The device 300 can contain an encapsulation material 32 that at least partially encapsulates the die pad 100, the semiconductor die 26, and the clips 28A, 28B. For example, the encapsulation material 32 can contain or be made from at least an epoxy, a filled epoxy, a glass fiber-filled epoxy, an imide, a thermoplastic, a thermosetting polymer, a polymer mixture, a laminate, a mold compound, or the like. Various techniques can be used for encapsulating components in the encapsulation material 32, for example, at least one of the following processes: compression molding, injection molding, powder injection molding, liquid casting, map molding, or the like. In the illustrated example, the encapsulation material 32 can form an encapsulation body with a bottom surface 34, a opposite top surface 36, and side surfaces 38 that connect the bottom surface 34 and the top surface 36.The semiconductor device 300 can also be referred to as a semiconductor package.

[0022] The unembossed area 16 of the die pad 100 can be uncovered by the encapsulation material 32, while the embossed edge areas 14A to 14C of the die pad 100 can be at least partially covered by the encapsulation material 32. In the example shown, the embossed edge areas 14A to 14C can be completely covered by the encapsulation material 32 and are therefore visible in the view of Fig. 3B not visible. The unembossed area 16 of the die pad 100 and the bottom surface 34 of the encapsulation material 32 can be substantially coplanar, i.e., they can be arranged in a common plane. One or more of the side surfaces 38 of the encapsulation material 32 can be arranged substantially perpendicular to the bottom surface 34 and the top surface 36 of the encapsulation material 32. In the illustrative example, the side surfaces 38 of the encapsulation material 32 can be arranged in the xz-plane, while the bottom surface 34 and the top surface 36 of the encapsulation material 32 can be arranged in the xy-plane.

[0023] Each of the connecting webs 18A and 18B can be at least partially uncovered by the encapsulation material 32. In the illustrated example, a bottom surface 40 and a side surface 42 of each connecting web 18 can be uncovered by the encapsulation material 32. The side surface 38 of the encapsulation material 32 and the side surface 42 of the connecting web 18 can be substantially coplanar, i.e., they can be arranged in a common plane. In the illustrated example, the side surface 42 of each connecting web 18 can be arranged in the xz-plane.

[0024] The semiconductor device 300 and other semiconductor devices according to the disclosure described herein can outperform conventional semiconductor devices. Often, the area of ​​the underside of a die pad is determined by compatibility requirements with the base area. Furthermore, in many conventional semiconductor devices, the area of ​​the top side of the die pad can be equal to the area of ​​the underside of the die pad, thus limiting the mounting area of ​​the die pad to a specific mounting area. Accordingly, only semiconductor dies up to a certain size can be arranged on the die pad of a conventional semiconductor device. In contrast, the underside 12 of the die pad 100 can contain embossed edge regions 14A to 14C, so that the area of ​​the top side 10 can be larger than the area of ​​the unembossed region 16 of the underside 12.Thus, the semiconductor device can provide both a compatible footprint and a larger area for mounting the semiconductor die. In a non-restrictive example, a die pad of a conventional semiconductor device can only accommodate semiconductor dies with a chip size of up to approximately 6.39 mm. 2 accommodate, while a semiconductor device according to the disclosure has mounting surfaces of up to 10.5 mm 2 can provide approximately 64.3% more than conventional devices.

[0025] In Fig. Figure 4 illustrates a flowchart of a process according to the disclosure. The process is described in general terms to qualitatively specify aspects of the disclosure. The process can be used in the fabrication of semiconductor devices according to the disclosure. In particular, the process can be applied to fabricate one or more die pads, as e.g., in Fig. 1 shown. It is understood that the procedure may include further aspects. For example, the procedure may be extended to include any of the aspects described in connection with other examples provided herein. For example, the procedure may be extended to include any of the aspects related to the procedure of Fig. 5 are described.

[0026] In step 44, a metal panel can be provided. In step 46, multiple first openings can be formed in the metal panel to create a ladder frame panel containing multiple die pads. The multiple die pads can be arranged in a row, with two adjacent die pads separated by two adjacent first openings and connected by a connecting rib between the two first openings. In step 48, edge regions of the undersides of the die pads can be embossed, with material from the die pads being pressed into a region of the first openings. In step 50, multiple second openings can be formed at the location of the multiple first openings to remove the material pressed into the area of ​​the first openings, with each second opening being wider than the first openings, and the two adjacent die pads still being connected by the connecting rib.

[0027] With reference to the Fig. Sections 5A to 5E now describe a further procedure according to the disclosure. The procedure of Fig. 5 can at least in part be considered a more detailed version of the procedure of Fig. 4 can be viewed. For example, the procedure of Fig. 5 for the production of the diepad 100 of the Fig. 1 can be used.

[0028] In Fig. 5A A metal panel (or metal sheet) 52 can be provided. The metal panel 52 can contain or consist of a metal or metal alloy. For example, the metal panel 52 can contain a core material that includes at least one of copper, a copper alloy, aluminum, an aluminum alloy, or the like. Optionally, the metal panel 52 can be coated with at least one coating material that includes, for example, at least one of the following materials: nickel, nickel-phosphorus, nickel-nickel-phosphorus, copper, silver, or the like. The step of Fig. 5A can be followed by step 44 of the Fig. 4 correspond.

[0029] In Fig. 5B Several initial openings 56 can be formed in the metal panel 52 to create a conductor frame panel 54. For example, the material at the location of the initial openings 56 can be removed by a cutting process. In the illustrated example, the initial openings 56 are indicated by hatched areas. The resulting conductor frame panel 54 can contain a peripheral frame 60 and several rows of die pads 58 connected to opposite sides of the peripheral frame 60. For simplicity, only one row of die pads 58 is shown, extending in the y-direction and containing an exemplary number of three die pads 58. In practice, the conductor frame panel 54 can contain several rows of parallel die pads 58, with the number of die pads in a row being greater than three, for example, up to several dozen.

[0030] Diepads 58 arranged in the same row can be connected via connecting webs 18. In this context, adjacent diepads 58 can be separated by two adjacent first openings 56A, 56B and connected by a connecting web 18 between the two first openings 56A, 56B. A diepad 58 in a row can contain two connecting webs 18 arranged on opposite sides of the diepad 58. The innermost and outermost diepad 58 can be connected to the peripheral frame 60 via a connecting web 18 and to an adjacent diepad 58 via an opposite connecting web 38. The other diepads 58 in a row can be connected to two adjacent diepads 58 in the row via two opposite connecting webs 18. The step of the Fig. 5B can be followed by step 46 of the Fig. 4 correspond.

[0031] In Fig. 5C, the conductor frame panel 54 can be embossed using an embossing tool. During the embossing process, a punch of the embossing tool can be moved in the z-direction towards the conductor frame panel 54 and emboss the conductor frame panel 54 at least partially. The material 62 of the die pads 58 can be pressed into one or more surfaces of the first openings 56A to 56C. In the illustrated example, the material 62 pressed into the first openings 56 and the surfaces of the die pads 58 from which this material originates are indicated by hatched areas. After the embossing process, each of the die pads 58 can have embossed edge regions 14A to 14C and an unembossed region 16 on its underside 12. The embossed and unembossed regions of the die pads 58 can be similar to the respective regions previously associated with Fig. 1 were described. The step of Fig. 5C can be added to step 48 of the Fig. 4 correspond.

[0032] In Fig. In 5D, several second openings 64 can be formed at the position of the several first openings 56A to 56C in order to remove the material 62 pressed into the area of ​​the first openings 56A to 56C. For example, the material 62 can be removed by a cutting process similar to that described in Fig. 5B are processed. In particular, every second opening 64 can be wider than an associated opening 56A to 56C. It should be noted that at least a section of the embossed edge areas 14A to 14C remains when the material 62 is removed by the cutting operation. Furthermore, the cutting operation does not necessarily affect the connecting webs 18, as two adjacent die pads 58 are still connected by the connecting web 18 after the cutting operation has been carried out. The step of Fig. 5D can be used in step 50 of the Fig. 4 correspond.

[0033] In Fig. 5E shows the arrangement after the cutting process of Fig. 5D was performed. The die pads 58 can still be connected by the connecting bridges 18. The side walls of each die pad 58 can be substantially perpendicular to the bottom 12 of the respective die pad 58, and the side walls can be free of the material 62. Each of the manufactured die pads 58 can be connected to the die pad 100 of the Fig. 1. The connecting ribs may be similar to and include some or all of the features of the diepad 100 as previously described. In particular, the connecting ribs 18 may be unembossed and arranged between two embossed edge regions of the bottom surface 12. Viewed in the z-direction, the connecting ribs 18 may comprise a first section with a first width and a second section with a second width that is smaller than the first width. The first section of each connecting rib 18 may be located within the area of ​​the top surface 10 of the diepad 18, and the second section of the connecting rib 18 may extend beyond the area of ​​the top surface 10.

[0034] In Fig. Figure 6 illustrates a flowchart of a process according to the disclosure. The process is described in general terms to qualitatively specify aspects of the disclosure. The process can be used in the fabrication of semiconductor devices according to the disclosure as described above. It is understood that the process may include further aspects. For example, the process may be extended to include any of the aspects described in connection with other examples herein.

[0035] In step 66, a conductor frame panel can be provided containing multiple die pads arranged in multiple rows. Each die pad can have a top and a bottom surface. The bottom surface of each die pad can have an embossed border area and an unembossed area. An area of ​​the top surface can be larger than an area of ​​the unembossed bottom surface. In step 68, multiple semiconductor dies can be mounted on the top surfaces of the die pads. In step 70, multiple clips can be attached to the top surface of the semiconductor dies. In step 72, an encapsulation process can be performed, whereby multiple rods can be formed from an encapsulation material, with each rod capable of encapsulating a series of die pads. In step 74, the multiple rods can be singulated into multiple semiconductor packages.

[0036] In the Fig. Sections 7A to 7F describe a further process according to the disclosure, which is at least partly the same as the process of Fig. 6 may resemble. For example, the procedure of Fig. 7 for the manufacture of one or more of the semiconductor devices 200 and 300 of the Fig. 2 and Fig. 3 can be used.

[0037] In Fig. 7A A conductor frame panel 54 with multiple die pads 58 arranged in multiple rows can be provided. The semiconductor dies 26 can be arranged on mounting surfaces of the die pads 58. The conductor frame panel 54 can include a peripheral frame 60, wherein the rows of die pads 58 can be connected to opposite sides of the peripheral frame 60. The rows of die pads 58 can be partially separated by columns 76. An enlarged detail of the conductor frame panel 54 is shown in a dashed rectangle. As can be seen from this detail, the rows of die pads 58 can be connected to opposite sides of the peripheral frame 60. Fig. 7A den in Fig. The rows of diepads shown in 5E may be similar to 58. Associated features have already been discussed in connection with Fig. 5 described, to which reference is hereby made. In particular, each diepad 58 can contain a top surface 10 and a bottom surface 12, the bottom surface 12 being able to contain embossed edge areas 14A to 14C and an unembossed area 16. An area of ​​the top surface 10 can be larger than an area of ​​the unembossed area 16 of the bottom surface 12. The step of Fig. 7A can follow steps 66 and 68 of the Fig. 6 correspond.

[0038] In a further step (not illustrated), clips can be attached and electrically connected to the semiconductor dies 26. This step can be compared to step 70 of the Fig. 6 correspond. For example, the clips can be similar to clips 28A and 28B, which are associated with the Fig. 2A and Fig. 2B were described. In particular, the clips can be configured as a batch-clip frame containing a plurality of clips 28A, 28B. Such batch-clip frames can be arranged in the columns 76, and the contained clips can be attached to the semiconductor dies 26 arranged on both sides of the respective column 76. In the illustrated example, four batch-clip frames can be arranged in the four columns 76, so that all semiconductor dies 26 can be electrically coupled to clips, similar to, for example, in Fig. 2.

[0039] In a further step (not illustrated), a reflow process can be performed to bond the batch clip frames or clips to the semiconductor dies 26. Additionally, optional processes such as flux cleaning and plasma cleaning can be performed.

[0040] In a further step (not illustrated), an encapsulation process can be carried out. This step can be compared to step 72 of the Fig. 6. For example, several rods can be formed from an encapsulation material in a molding process, with each molded rod capable of encapsulating a series of die pads. Additionally, post-mold curing (PMC) can be performed after the molding process.

[0041] In a further step (not illustrated), one or more connecting bridges of the assembly can be cut. Connecting bridges can be used in conductor frame designs to facilitate a molding or encapsulation process and also to provide support for connecting conductors. In this context, the connecting bridges can be positioned between adjacent connecting conductors. During the encapsulation process, the connecting bridge can be designed to act as a clamping surface for the edges of the molding tool and as a barrier to prevent the molding material from leaking or overflowing from the molding tool onto the connecting conductors. After encapsulation, the connecting bridge can be removed, allowing the connecting conductors to be physically and / or electrically customized depending on their specific function.

[0042] In a further step (not illustrated), at least one deflashing or coating process can be carried out.

[0043] In a further step (not illustrated) the connecting conductors of clips 28A, 28B can be trimmed and / or shaped.

[0044] In Fig. Figure 7B shows the assembly processed in the previously described steps, but rotated 180 degrees. The assembly can contain a variety of encapsulated elements arranged in rows, each element potentially containing a die pad, a semiconductor die, and clips. The assembly, which contains multiple rods of encapsulation material, can be singulated into multiple semiconductor devices (or semiconductor packages). An example of singulating the assembly is indicated by dashed lines.

[0045] In the Fig. Figures 7C to 7F show different views of a semiconductor device 700 produced by the singulation method of the Fig. 7B was obtained. In particular, the semiconductor device 700 can have some or all of the features of the semiconductor device 300 from Fig. 3 included. These features have already been mentioned in connection with Fig. 3 described, to which reference is hereby made. Examples

[0046] The following describes semiconductor devices and methods according to the disclosure by means of examples.

[0047] Example 1 is a semiconductor device comprising: a die pad with a top and a bottom; and a semiconductor die mounted on the top of the die pad, wherein the bottom of the die pad comprises at least two embossed edge regions and one non-embossed region, wherein the die pad comprises a non-embossed connecting rib arranged between two embossed edge regions of the bottom, and wherein an area of ​​the top is larger than an area of ​​the non-embossed region of the bottom.

[0048] Example 2 is a semiconductor device according to Example 1, wherein, in a top view of the underside, the connecting web comprises a first section with a first width and a second section with a second width that is smaller than the first width.

[0049] Example 3 is a semiconductor device according to Example 2, wherein, in the top view of the bottom side: the first section of the connecting bridge is arranged within the surface of the top side and the second section of the connecting bridge extends beyond the surface of the top side.

[0050] Example 4 is a semiconductor device according to any of the preceding examples, further comprising: an encapsulation material that at least partially encapsulates the die pad and the semiconductor die, wherein the unprinted area of ​​the underside is uncovered by the encapsulation material.

[0051] Example 5 is a semiconductor device according to Example 4, wherein: the embossed edge region of the underside is at least partially covered by the encapsulation material and the connecting bridge is at least partially uncovered by the encapsulation material.

[0052] Example 6 is a semiconductor device according to Example 4 or 5, wherein the unprinted area of ​​the underside and an underside of the encapsulation material are substantially coplanar.

[0053] Example 7 is a semiconductor device according to any one of Examples 4 to 6, wherein a side surface of the encapsulation material is arranged substantially perpendicular to a bottom surface of the encapsulation material and a top surface of the encapsulation material.

[0054] Example 8 is a semiconductor device according to any one of Examples 4 to 7, wherein a side face of the encapsulation material and the connecting bridge are substantially coplanar.

[0055] Example 9 is a semiconductor device according to one of the preceding examples, wherein the at least two embossed edge regions surround the unembossed region on two or more sides of the die pad.

[0056] Example 10 is a semiconductor device according to one of the preceding examples, wherein the at least two embossed edge regions surround the unembossed region on two or more sides of the die pad, except at the location of the connecting bridge.

[0057] Example 11 is a semiconductor device according to any of the preceding examples, wherein the underside of the diepad comprises a first embossed edge region arranged on a first side of the diepad and a second embossed edge region arranged on a second side of the diepad opposite the first side.

[0058] Example 12 is a semiconductor device according to Example 11, wherein the underside of the diepad includes a third embossed edge region arranged on a third side of the diepad connecting the first side and the second side of the diepad.

[0059] Example 13 is a semiconductor device according to any one of Examples 2 to 12, wherein a dimension of the first section of the connecting bridge arranged between the two embossed edge regions is equal to a dimension of the two embossed edge regions.

[0060] Example 14 is a semiconductor device according to one of the preceding examples, wherein the thickness of the embossed edge region is in a range of 60% to 90% of the thickness of the unembossed region.

[0061] Example 15 is a method comprising: providing a metal panel; forming multiple first openings in the metal panel to form a conductor frame panel comprising multiple die pads, the multiple die pads being arranged in a row, with two adjacent die pads separated by two adjacent first openings and connected by a connecting rib between the two first openings; embossing edge regions of the undersides of the die pads, with material of the die pads being pressed into a region of the first openings; and forming multiple second openings at the position of the multiple first openings to remove the material pressed into the region of the first openings, each second opening being wider than the first openings, with the two adjacent die pads still connected by the connecting rib.

[0062] Example 16 is a method according to Example 15, wherein the connecting web is unembossed and is arranged between two embossed edge areas of the underside.

[0063] Example 17 is a method according to Example 15 or 16, wherein at least one section of the embossed edge areas remains when the material pressed into the area of ​​the first openings is removed.

[0064] Example 18 is a method according to one of Examples 15 to 17, wherein, after forming the multiple second openings: a side wall of each die pad is substantially perpendicular to the underside of the respective die pad and the side wall is free of material that is pressed into the surface of the first openings.

[0065] Example 19 is a method according to any one of Examples 15 to 18, wherein: the conductor frame panel comprises a peripheral frame and several rows of diepads, the rows of diepads being connected to opposite sides of the peripheral frame and the diepads arranged in the same row of diepads being connected via connecting bridges.

[0066] Example 20 is a method according to Example 19, wherein: a diepad in a series of diepads comprises two connecting ribs arranged on opposite sides of the diepad and the diepad is connected to two adjacent diepads of the series of diepads via the two connecting ribs.

[0067] Example 21 is a method according to any of Examples 15 to 20, wherein, in a top view of the underside of the connecting web, a first section has a first width and a second section has a second width which is smaller than the first width.

[0068] Example 22 is a method according to Example 21, wherein, in the top view of the underside, the first section of the connecting web is arranged within the surface of the top side and the second section of the connecting web extends beyond the surface of the top side.

[0069] Example 23 is a method comprising: providing a conductor frame panel comprising multiple die pads arranged in multiple rows, each die pad comprising a top and a bottom, the bottom of each die pad comprising an embossed border region and an unembossed region, and an area of ​​the top being larger than an area of ​​the unembossed region of the bottom; mounting multiple semiconductor dies onto the tops of the die pads; attaching multiple clips to the top of the semiconductor dies; performing an encapsulation process in which multiple rods are formed from an encapsulation material, each rod encapsulating a series of die pads; and singulating the multiple rods into multiple semiconductor packages.

[0070] The terms "connected," "coupled," "electrically connected," and / or "electrically coupled" used in this description do not necessarily mean that the elements must be directly connected or coupled to each other. Intermediate elements may be provided between the "connected," "coupled," "electrically connected," or "electrically coupled" elements.

[0071] Furthermore, the words "over" and "on" can be used herein, in reference to, for example, a layer of material formed or arranged "over" or "on" a surface of an object, to mean that the layer of material can be arranged (e.g., formed, deposited, etc.) "directly on," i.e., in direct contact with the surface in question. The words "over" and "on," used herein, for example, in reference to a layer of material formed or arranged "over" or "on" a surface, can also mean that the layer of material can be arranged (e.g., formed, deposited, etc.) "indirectly on" the surface in question, with, for example, one or more additional layers arranged between the surface in question and the layer of material.

[0072] Where the terms “having”, “containing”, “including”, “with”, or variations thereof are used in the detailed description or claims, these terms are to be understood in a similarly comprehensive way as the term “comprising”. That is to say, as used herein, the terms “having”, “containing”, “including”, “with”, “comprising”, or similar are open terms that indicate the presence of specified elements or features but do not exclude additional elements or features. The articles “a”, “an”, and “the” are to include both the plural and the singular unless the context clearly indicates otherwise.

[0073] Furthermore, the word "exemplary" is used herein to serve as an example, instance, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be understood as advantageous over other aspects or designs. Rather, the use of the word "exemplary" is intended to illustrate concepts in a concrete way. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is to say, unless otherwise specified or evident from the context, "X uses A or B" means any of the natural, inclusive permutations. That is, if X uses A, X uses B, or X uses both A and B, then the condition "X uses A or B" is satisfied in each of the preceding instances.In addition, the articles “a” and “an”, as used in this application and the attached claims, can generally be interpreted as meaning “one or more”, unless otherwise indicated or the context suggests a singular form. Furthermore, “at least one of A and B” or similar generally means A or B or both A and B.

[0074] This document describes devices and methods for manufacturing devices. Remarks made in connection with a described device may also apply to a corresponding method, and vice versa. For example, if a particular component of a device is described, a corresponding method for manufacturing the device may include a step for providing the component in a suitable manner, even if such a step is not explicitly described or illustrated in the figures.

[0075] Although the disclosure has been shown and described with respect to one or more embodiments, other skilled persons will make equivalent changes and modifications, at least in part, based on reading and understanding this description and the accompanying drawings. The disclosure contains all such modifications and variations and is limited only by the concept of the following claims. In particular, with regard to the various functions performed by the components described above (e.g., elements, resources, etc.), the terms used to describe such components, unless otherwise specified, are intended to correspond to each component that performs the specified function of the described component (i.e.,which is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary embodiments of the disclosure illustrated herein. Additionally, although a particular feature of the disclosure may have been disclosed only in respect of one of several embodiments, such a feature may be combined with one or more other features of the other embodiments, as may be desirable and advantageous for a given or particular application.

Claims

[1] Semiconductor device comprising: a diepad (58, 100) having a top (10) and a bottom (12); and a semiconductor die (26) mounted on the top (10) of the die pad (58, 100), wherein the underside (12) of the die pad (58, 100) comprises at least two embossed edge areas (14) and one unembossed area (16), wherein the diepad (58, 100) comprises an unembossed connecting rib (18) arranged between two embossed edge areas (14) of the underside (12), and wherein an area of ​​the top (10) is larger than an area of ​​the unembossed area (16) of the bottom (12). [2] Semiconductor device according to claim 1, wherein in a top view of the underside (12) the connecting bridge (18) has a first section (20A) with a first width and a second section (20B) with a second width which is smaller than the first width. [3] Semiconductor device according to claim 2, wherein in the top view of the underside: the first section (20A) of the connecting web (18) is arranged within the surface of the top (10), and the second section (20B) of the connecting bridge (18) extends beyond the surface of the top (10). [4] Semiconductor device according to any one of the preceding claims, further comprising: an encapsulation material (32) which at least partially encapsulates the die pad (58, 100) and the semiconductor die (26), wherein the unembossed area (16) of the underside (12) is not covered by the encapsulation material (32). [5] Semiconductor device according to claim 4, wherein: the embossed edge area (14) of the underside (12) is at least partially covered by the encapsulation material (32), and the connecting bridge (18) is at least partially uncovered by the encapsulation material (32). [6] Semiconductor device according to claim 4 or 5, wherein the unprinted area (16) of the underside (12) and an underside (34) of the encapsulation material (32) are substantially coplanar. [7] Semiconductor device according to one of claims 4 to 6, wherein a side surface (38) of the encapsulation material (32) is arranged substantially perpendicular to a bottom surface (34) of the encapsulation material (32) and a top surface (36) of the encapsulation material (32). [8] Semiconductor device according to any one of claims 4 to 7, wherein a side surface (38) of the encapsulation material (32) and the connecting bridge (18) are substantially coplanar. [9] Semiconductor device according to one of the preceding claims, wherein the at least two embossed edge regions (14) surround the unembossed region (16) on two or more sides of the die pad (58, 100). [10] Semiconductor device according to one of the preceding claims, wherein the at least two embossed edge regions (14) surround the unembossed region (16) on two or more sides of the die pad (58, 100), except at the location of the connecting bridge (18). [11] Semiconductor device according to one of the preceding claims, wherein the underside (12) of the die pad (58, 100) comprises a first embossed edge region (14A) arranged at a first side of the die pad (58, 100) and a second embossed edge region (14B) arranged at a second side of the die pad (58, 100) opposite the first side. [12] Semiconductor device according to claim 11, wherein the underside (12) of the diepad (58, 100) comprises a third embossed edge area (14C) arranged at a third side of the diepad (58, 100) which connects the first side and the second side of the diepad (58, 100). [13] Semiconductor device according to one of claims 2 to 12, wherein a dimension of the first section (20A) of the connecting bridge (18) arranged between the two embossed edge regions (14) is equal to a dimension of the two embossed edge regions (14). [14] Semiconductor device according to one of the preceding claims, wherein the thickness of the embossed edge region (14) is in a range of 60% to 90% of the thickness of the unembossed region (16). [15] Procedure, encompassing: Providing a metal panel (52); Forming several first openings (56) in the metal panel (52) to form a conductor frame panel (54) comprising several die pads (58), the several die pads (58) being arranged in a row, with two adjacent die pads (58) being separated by two adjacent first openings (56) and connected by a connecting web (18) between the two first openings (56); Embossing of edge areas (14) of undersides (12) of the die pads (58), wherein material (62) of the die pads (58) is pressed into an area of ​​the first openings (56); and Forming several second openings (64) at the position of the several first openings (56) in order to remove the material (62) pressed into the area of ​​the first openings (56), wherein each second opening (64) is wider than the first openings (56), wherein the two adjacent die pads (58) are still connected by the connecting bridge (18). [16] Method according to claim 15, wherein the connecting web (18) is unembossed and arranged between two embossed edge areas (14) of the underside (12). [17] Method according to claim 15 or 16, wherein at least one section of the embossed edge areas (14) remains when the material (62) pressed into the area of ​​the first openings (56) is removed. [18] Method according to any one of claims 15 to 17, wherein after forming the multiple second openings (64): a side wall of each die pad (58) is substantially perpendicular to the underside (12) of the respective die pad (58) and the side wall is free of material (62) that is pressed into the area of ​​the first openings (56). [19] Method according to any one of claims 15 to 18, wherein: the ladder frame panel (54) comprises a peripheral frame (60) and several rows of die pads (58), the rows of die pads (58) being connected to opposite sides of the peripheral frame (60), and Die pads (58) arranged in the same row of die pads (58) are connected via connecting bridges (18). [20] Method according to claim 19, wherein: a diepad (58) in a series of diepads (58) comprises two connecting bridges (18) arranged on opposite sides of the diepad (58), and the diepad (58) is connected to two adjacent diepads (58) of the row of diepads (58) via the two connecting bridges (18). [21] Method according to any one of claims 15 to 20, wherein in a top view of the underside (12) the connecting web (18) comprises a first section (20A) having a first width and a second section (20B) having a second width which is smaller than the first width. [22] Method according to claim 21, wherein in the top view of the underside (12): the first section (20A) of the connecting web (18) is arranged within the surface of the top (10), and the second section (20B) of the connecting bridge (18) extends beyond the surface of the top (10). [23] Procedures, comprehensive: Providing a ladder frame panel (54) comprising several die pads (58) arranged in multiple rows, wherein: Each diepad (58) has a top (10) and a bottom (12), the underside (12) of each die pad (58) has an embossed edge area (14) and an unembossed area (16), and an area of ​​the top (10) is larger than an area of ​​the unembossed area (16) of the bottom (12); Mounting multiple semiconductor dies (26) on the top surfaces (10) of the die pads (58); Attaching several clips (28) to the semiconductor dies (26); Performing an encapsulation process, forming several rods made from an encapsulation material (32), each rod encapsulating a series of die pads (58); and Separating the multiple rods into multiple semiconductor packages.

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