Profiles of gate structures in semiconductor devices

Abstract

A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device comprises: a substrate; a semiconductor layer disposed on the substrate; a source / drain region disposed adjacent to the semiconductor layer; a gate structure disposed on the semiconductor layer; an interfacial spacer layer having a triangular cross-sectional profile disposed along a sidewall of the gate structure; and a gate spacer. The gate spacer comprises: a first spacer portion having a first bottom surface with a substantially straight profile and disposed on the semiconductor layer; and a second spacer portion having a second bottom surface with an inclined profile and disposed on the interfacial spacer layer.

Description

Cross-reference to related application

[0001] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 609,616, filed December 13, 2023, entitled "Metal Gate Profiles in Semiconductor Devices," which is incorporated by reference into this application. background

[0002] With advances in semiconductor technology, a growing demand for higher storage capacity, faster processing systems, higher performance, and lower costs has emerged. To meet this demand, the semiconductor industry is further shrinking the dimensions of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), which include planar MOSFETs, fin field-effect transistors (FinFETs), and gate-all-around field-effect transistors (GAA-FETs). This shrinking has increased the complexity of semiconductor manufacturing processes. Short description of the drawings

[0003] Aspects of the present disclosure can best be understood from the following detailed description taken in conjunction with the accompanying drawings. Fig. 1A shows an isometric view of a semiconductor device according to some embodiments. The Fig. 1B to 1E and 2 show various cross-sectional views of a semiconductor device with interfacial spacer layers according to some embodiments. Fig. 3 is a flow diagram of a method of manufacturing a semiconductor device with interfacial spacer layers according to some embodiments. The Fig. 4 to 20 show cross-sectional views of a semiconductor device having interfacial spacer layers at various stages of its manufacturing process according to some embodiments.

[0004] Illustrative embodiments are described below with reference to the accompanying drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. Detailed description

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the process for manufacturing a first element over a second element in the description may include embodiments in which the first and second elements are manufactured in direct contact, and may also include embodiments in which additional elements may be manufactured between the first and second elements such that the first and second elements are not in direct contact. Here, manufacturing a first element on a second element means manufacturing the first element in direct contact with the second element.Furthermore, reference numbers and / or letters may be repeated throughout the various examples in the present disclosure. This repetition does not, in itself, dictate any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structural element to one or more other elements or structural elements illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90° or in another orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0007] It should be noted that in the specification, references to "one embodiment," "an exemplary embodiment," "exemplary," etc., mean that the described embodiment may have a particular element, structure, or characteristic, but not every embodiment has the particular element, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. If a particular element, structure, or characteristic is described in connection with one embodiment, one skilled in the art will know how to implement the particular element, structure, or characteristic in connection with other embodiments, regardless of whether it is explicitly described.

[0008] It is to be understood that the phraseology or terminology used herein is for the purpose of description rather than limitation, and it is intended that the phraseology or terminology used in this specification be interpreted by those skilled in the art in light of the principles.

[0009] In some embodiments, the terms "about" and "substantially" may indicate a value of a given quantity that varies within 5% to 20% of the value (e.g., by ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±10 to ±15%, ±15 to ±20% of the value). These values ​​are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of the values ​​as interpreted by those skilled in the art in light of the principles used herein.

[0010] GAA transistor structures can be patterned using a suitable method. For example, the structures can be patterned using one or more photolithography processes, such as double or multiple patterning processes. Double or multiple patterning processes can combine photolithography and self-aligned processes, which can create structures that, for example, have pitches smaller than those otherwise achievable with a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, which is then patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA transistor structure.

[0011] The fin structures disclosed herein may be patterned using any suitable method. For example, the fin structures may be patterned using one or more photolithography processes, such as double or multiple patterning processes. Double or multiple patterning processes may combine photolithography and self-aligned processes, which may create structures having, for example, pitches smaller than those otherwise achievable with a single direct photolithography process. For example, a sacrificial layer is formed over a substrate, which is then patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. Subsequently, the sacrificial layer is removed, and the remaining spacers may then be used to pattern the fin structures.

[0012] The present disclosure provides example structures and methods for improving bottom corner profiles of gate structures in FETs to avoid leakage between gate structures and source / drain (S / D) regions in the FETs. In some embodiments, a FET may include: nanostructured channel regions disposed on a substrate; a gate structure disposed around the nanostructured channel regions; S / D regions disposed adjacent to the nanostructured channel regions; and outer gate spacers disposed along sidewalls of the gate structure to electrically isolate the gate structure from adjacent S / D regions. In some embodiments, interface gaps may be present between the outer gate spacers and the topmost nanostructured channel regions.The interface gaps can be filled with interface spacer layers containing an insulating material. The interface spacer layers can prevent bottom corner portions of the gate structure from forming in the interface gaps during gate structure fabrication. By preventing bottom corner portions of the gate structure from extending below the outer gate spacers, the distance between the gate structure and adjacent S / D regions can be increased, current leakage between the gate structure and adjacent S / D regions can be avoided or minimized, and device performance can be improved. Thus, by using the interface spacer layers, the bottom corner profiles of the gate structure can be controlled.Depending on the sidewall profiles of the interface spacer layers, the gate structure may have a U-shaped cross-sectional profile with bottom corners having right-angled, obtuse-angled, or rounded corner profiles.

[0013] Fig. 1A shows an isometric view of a semiconductor device 100 that may embody a GAA-FET 100, according to some embodiments. Fig. 1B shows a cross-sectional view of the GAA-FET 100 according to some embodiments, taken along line A-A of Fig. 1A, with further structures, which for the sake of simplicity are Fig. 1A are not shown. The Fig. 1C to 1E show various enlarged sectional views of an area 101 of Fig. 1B according to some embodiments, with further details shown for convenience in Fig. 1B are not shown. Unless otherwise stated, the discussions of the elements in the Fig. 1A to 1E, which have the same reference symbols, for each other.

[0014] In the Fig. 1A to 1E, in some embodiments, the GAA-FET 100 may include: (I) a substrate 102; (II) shallow trench isolation (STI) regions 104 disposed on the substrate 102; (III) fin-shaped base structures 106 (also referred to as a “layer base 106” or a “fin base 106”) disposed on the substrate 102; (IV) nanostructured channel regions 108 disposed on the base structure 106; (V) S / D regions 110 disposed adjacent to the nanostructured channel regions 108; (VI) gate structures 112 enclosing the nanostructured channel regions 108; (VII) outer gate spacers 114; (VIII) interface spacer layers 116; (IX) inner gate spacers 118; (X) etch stop layers (ESLs) 120 disposed directly on the S / D regions 110; (XI) interlayer dielectric (ILD) layers 122 disposed directly on the ESLs 120;and (XII) contact structures 124 arranged on the S / D regions 110;

[0015] In some embodiments, the substrate 102 may be a semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), a semiconductor-on-insulator (SOI) structure, or a combination thereof. In addition, the substrate 102 may be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic). In some embodiments, the STI regions 104 may include an insulating material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide carbide (SiOC), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), or silicon germanium oxide (SiGeO x). In some embodiments, the base structures 106 may include a similar material as the substrate 102. The base structures 106 may have elongated sides extending along an x-axis.

[0016] In some embodiments, the nanostructured channel regions 108 may be in the form of nanosheets, nanowires, nanorods, or nanotubes, or other suitable nanostructure shapes. The term "nanostructure" as used herein defines a structure, layer, and / or region that has a horizontal dimension (e.g., along an x- and / or y-axis) and / or a vertical dimension (e.g., along a z-axis) that is less than about 100 nm, for example, about 90 nm, about 50 nm, or about 10 nm, or has other values ​​that are less than about 100 nm. The nanostructured channel regions 108 may include semiconductor materials similar to or different from those of the substrate 102.In some embodiments, the nanostructured channel regions 108 may include Si, silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon carbon phosphide (SiCP), silicon germanium (SiGe), silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), a III-V semiconductor compound, or other suitable semiconductor materials. In some embodiments, each of the nanostructured channel regions 108 may have a thickness of about 3 nm to about 15 nm along the z-axis. While two nanostructured channel regions 108 are shown below the gate structure 112, the GAA-FET 100 may include any number of nanostructured channel regions 108. Although nanostructured channel regions 108 are shown with rectangular cross-sections, the nanostructured channel regions 108 may also have cross-sections with other geometric shapes (e.g., round, elliptical, triangular, or polygonal shapes).

[0017] In some embodiments, the S / D regions 110 may include an epitaxially grown semiconductor material such as Si, as well as n-type dopants such as phosphorus and other suitable n-type dopants for an n-GAA FET 100. The S / D regions 110 may include an epitaxially grown semiconductor material such as Si and SiGe, as well as p-type dopants such as boron and other suitable p-type dopants for a p-GAA FET 100. Each of the S / D regions 110 may individually or collectively denote a source or a drain, depending on the context.

[0018] In some embodiments, each gate structure 112 may have an outer gate portion 113A and inner gate portions 113B. In some embodiments, the outer gate portions 113A may be disposed on top of and in physical contact with the uppermost nanostructured channel regions 108. In some embodiments, the inner gate portions 113B may be disposed between adjacent nanostructured channel regions 108 and between adjacent inner gate spacers 118.

[0019] Each gate structure may be a multi-level gate structure and may include: (I) an interfacial oxide (IL) layer 112A; (II) a high-k gate dielectric (HK) layer 112B; a conductive layer 112C; and (IV) a gate cap layer 112D. In some embodiments, the IL layer 112A may be disposed directly on the topmost nanostructured channel regions 108. The IL layer 112A may, in some embodiments, comprise SiO2, SiGeO x or germanium oxide (GeO x) and may have a thickness H1 of about 0.5 nm to about 1 nm. In some embodiments, the HK gate dielectric layer 112B may be disposed directly on the IL layer 112A and may include a high-k dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), or zirconium silicate (ZrSiO2). In some embodiments, sidewalls of the HK gate dielectric layer 112B may be in contact with sidewalls of the outer gate spacers 114.

[0020] In some embodiments, the conductive layer 112C may be disposed on the HK gate dielectric layer 112B and may be a multi-layer structure. The different layers of the conductive layer 112C are not shown for simplicity. In some embodiments, the conductive layer 112C may include a work function metal (WFM) layer disposed on the HK gate dielectric layer 112B and a gate metal fill layer disposed on the WFM layer. In some embodiments, the WFM layer may include substantially Al-free (i.e., without Al) Ti- or Ta-based nitrides or alloys, such as titanium nitride (TiN), titanium silicon nitride (TiSiN), a titanium gold alloy (Ti-Au alloy), a titanium copper alloy (Ti-Cu alloy), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), a tantalum gold alloy (Ta-Au alloy), and tantalum copper (Ta-Cu).In some embodiments, the WFM layer may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, or other suitable Al-based materials. In some embodiments, the gate metal fill layer may include a suitable conductive material, such as tungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys, or a combination thereof.

[0021] In some embodiments, the gate cap layer 112D may be disposed directly on the HK gate dielectric layer 112B and the conductive layer 112C. The gate cap layer 112D may protect the underlying layers from structural and / or compositional degradation during later processing of the GAA-FET 100. In some embodiments, the gate cap layer 112D may include a nitride material such as SiN and may have a thickness of about 5 nm to about 10 nm to adequately protect the underlying layers.

[0022] The outer gate spacers 114 may electrically isolate the outer gate portions 113A from adjacent S / D regions 110 and adjacent contact structures 124. In some embodiments, each outer gate spacer 114 may include a horizontal spacer portion 114h and a sloped spacer portion 114s. The horizontal spacer portion 114h may have a bottom surface 114hb with a substantially straight profile and in direct contact with a top surface of the uppermost nanostructured channel region 108. The sloped spacer portion 114s may have a bottom surface 114sb with a sloped profile and in direct contact with the interfacial spacer layer 116. The interfaces between the sloped spacer portions 114s and the interfacial spacer layers 116 may have sloped profiles.In some embodiments, the outer gate spacers 114 may comprise an undoped dielectric layer, such as an undoped SiO2 layer, an undoped SiN layer, an undoped SiON layer, an undoped SiOC layer, an undoped SiCN layer, an undoped SiOCN layer, or another suitable undoped dielectric layer.

[0023] In some embodiments, each interfacial spacer layer 116 may include a dielectric material such as SiO2, SiN, SiON, SiCN, and SiOCN. In some embodiments, each interfacial spacer layer 116 may be an oxide layer (e.g., SiO2) with a semiconductor element (e.g., Si) in the outer gate spacer 114 and / or in the nanostructured channel region 108. The interfacial spacer layers 116 may be disposed between the inclined spacer portions 114s and the uppermost nanostructured channel regions 108. By arranging the interfacial spacer layers 116 in this manner, interfacial gaps 1316 (in the Fig. 1A to 1E not shown; see Fig. 13) that are formed between the inclined spacer portions 114s and the uppermost nanostructured channel regions 108 during the formation of the gate structures 112, as will be explained in more detail later. This can prevent lower corner regions 112cr of the outer gate portions 113A from extending into the interface gaps 1316 and being formed under the outer gate spacers 114 during the formation of the gate structures 112. By preventing the outer gate portions 113A from extending under the outer gate spacers 114, the distance between the outer gate portions 113A and adjacent S / D regions 110 can be increased, current leakage between the outer gate portions 113A and adjacent S / D regions 110 can be avoided or minimized, and device performance can be improved.Thus, by using the interface spacer layers 116, the bottom corner profiles of the outer gate portions 113A can be controlled. Depending on the sidewall profiles of the interface spacer layers 116, the outer gate portions 113A can each have a U-shaped cross-sectional profile with different bottom corner profiles, as described below with reference to FIG. Fig. 1C, Fig. 1D and Fig. 1E.

[0024] In Fig. 1C, in some embodiments, each interface spacer layer 116 on both sides of the outer gate portion 113A may include: (I) a triangular cross-sectional profile; (II) a substantially vertical sidewall 116s1 having a height H2 of about 2 nm to about 5 nm, facing and contacting the outer gate portion 113A; (III) a sidewall 116s1 substantially aligned with a sidewall 114sw of the outer gate spacer 114; (IV) a sloped sidewall facing and contacting the outer gate spacer 114; (V) a substantially right-angled corner (e.g., from about 85° to about 90°) between the sidewall 116s1 and a bottom surface of the interfacial spacer layer 116; and (VI) an acute-angled corner (e.g., from about 35° to about 75°) between the sloped sidewall and the bottom surface of the interfacial spacer layer 116.

[0025] In some embodiments, due to these structural profiles of the interface spacer layers 116 on both sides of the outer gate portion 113A of Fig. 1C, the following are possible: (I) the outer gate portion 113A may be formed with a U-shaped cross-sectional profile; (II) the lower corner regions 112cr may be formed with substantially rectangular corner profiles (e.g., from about 90° to about 95°); (III) sidewalls 112s of the outer gate portion 113A may form angles A and B of about 90° to about 95° with a bottom surface 112b of the outer gate portion 113A; (IV) sidewalls of the IL layer 112A may form angles of about 90° to about 95° with a bottom surface of the IL layer 112A; (V) sidewalls of the HK gate dielectric layer 112B may form angles of about 90° to about 95° with a bottom surface of the HK gate dielectric layer 112B; and (VI) sidewalls of the conductive layer 112C may form angles of about 90° to about 95° with a bottom surface of the conductive layer 112C.

[0026] In some embodiments, a ratio between the dimension H1 and the dimension H2 may be about 0.1 to about 0.5. In some embodiments, the interfaces between the interfacial spacer layers 116 and the IL layer 112A, as well as between the interfacial spacer layers 116 and the HK gate dielectric layer 112B, may have straight profiles. The structural profiles and dimensions of the interfacial spacer layers 116 and the outer gate portions 113A of Fig. 1C can prevent or minimize the likelihood of current leakage between the outer gate portions 113A and adjacent S / D regions 110, thereby improving device performance.

[0027] In some embodiments, the interface spacer layers 116 may be formed of a Fig. 1C shown structural profiles have structural profiles as shown in Fig. 1D. In Fig. 1D, in some embodiments, each interfacial spacer layer 116 on both sides of the outer gate portion 113A may have: (I) a triangular cross-sectional profile; (II) a first inclined sidewall 116s2 facing and contacting the outer gate portion 113A; (III) a second inclined sidewall facing and contacting the outer gate spacer 114; and (IV) an acute-angled corner (e.g., from about 45° to about 85°) between the sidewall 116s2 and the bottom surface of the interfacial spacer layer 116. In some embodiments, due to these structural profiles of the interfacial spacer layers 116 on both sides of the outer gate portion 113A of Fig. 1D, the following are possible: (I) the outer gate part 113A can be formed with a U-shaped cross-sectional profile; (II) the lower corner regions 112cr can be formed with obtuse-angled corner profiles; (III) the sidewalls of the IL layer 112A can be formed with inclined profiles; (IV) the lower corners of the HK gate dielectric layer 112B can be formed with obtuse-angled corner profiles; and (V) the lower corners of the conductive layer 112C can be formed with obtuse-angled corner profiles. In some embodiments, the interfaces between the interface spacer layers 116 and the IL layer 112A, and between the interface spacer layers 116 and the HK gate dielectric layer 112B, can have inclined profiles. The structural profiles and dimensions of the interface spacer layers 116 and the outer gate portions 113A of Fig. 1D can prevent or minimize the likelihood of current leakage between the outer gate portions 113A and adjacent S / D regions 110, thereby improving device performance.

[0028] In some embodiments, the interface spacer layers 116 may be formed of a Fig. 1C or Fig. 1D have structural profiles as shown in Fig. 1E. In Fig. 1E, in some embodiments, each interface spacer layer 116 on both sides of the outer gate portion 113A may include: (I) a triangular cross-sectional profile; (II) a curved sidewall 116s3 facing and contacting the outer gate portion 113A; (III) a sloped sidewall facing and contacting the outer gate spacer 114; and (IV) an acute-angled corner (e.g., from about 35° to about 75°) between the sloped sidewall and the bottom surface of the interfacial spacer layer 116. In some embodiments, due to these structural profiles of the interfacial spacer layers 116 on both sides of the outer gate portion 113A of Fig. 1E, the following are possible: (I) the outer gate portion 113A can be fabricated with a U-shaped cross-sectional profile; (II) the lower corner regions 112cr can be fabricated with rounded corner profiles; (III) the sidewalls of the IL layer 112A can be fabricated with curved profiles; (IV) the lower corners of the HK gate dielectric layer 112B can be fabricated with rounded corner profiles; and (V) the lower corners of the conductive layer 112C can be fabricated with rounded corner profiles. In some embodiments, the interfaces between the interface spacer layers 116 and the IL layer 112A, as well as between the interface spacer layers 116 and the HK gate dielectric layer 112B, can have curved profiles. The structural profiles and dimensions of the interface spacer layers 116 and the outer gate portions 113A of Fig. 1E can prevent or minimize the likelihood of current leakage between the outer gate portions 113A and adjacent S / D regions 110, thereby improving device performance.

[0029] In the Fig. 1A and Fig. 1B, the inner gate spacers 118 may electrically isolate the inner gate portions 113B from adjacent S / D regions 110. In some embodiments, each inner gate spacer 118 may have a height of about 3 nm to about 20 nm and a thickness of about 1 nm to about 10 nm. Within these height and thickness ranges, the inner gate spacers 118 may sufficiently electrically isolate the inner gate portions 113B from adjacent S / D regions 110 without impacting device size and manufacturing costs.

[0030] In some embodiments, the ESLs 120 may be disposed directly on the S / D regions 110. In some embodiments, the ESLs 120 may have a dielectric constant of about 4 to about 7 and may include a dielectric material such as lanthanum oxide (LaO), alumina (Al2O3), yttrium oxide (Y2O3), tantalum carbon nitride (TaCN), zirconium silicide (ZrSi), SiOCN, SiOC, SiCN, zirconium nitride (ZrN), zirconium alumina (ZrAlO), TiO2, Ta2O3, ZrO2, HfO2, SiN, hafnium silicide (HfSi), alumina nitride (AlON), SiO2, SiC, SiN, and zinc oxide (ZnO). In some embodiments, the ILD layers 122 may include an insulating material such as SiO2, SiN, SiON, SiCN, or SiOCN.

[0031] In some embodiments, each contact structure 124 may include (I) a silicide layer 124A and (II) contact studs 124B disposed on the silicide layer 124A. In some embodiments, the silicide layer 124A in the n-GAA FET 100 may comprise titanium silicide (Ti x Si y ), tantalum silicide (Ta x Si y ), molybdenum silicide (Mo x Si y ), zirconium silicide (Zr x Si y ), hafnium silicide (Hf x Si y ), scandium silicide (Sc x Si y ), yttrium silicide (Y x Si y ), terbium silicide (Tb x Si y ), lutetium silicide (Lu x Si y ), erbium silicide (Er x Si y ), ytterbium silicide (Yb x Si y ), europium silicide (Eu x Si y ), thorium silicide (Th x Si y), other suitable metal silicide materials, or a combination thereof. In some embodiments, the silicide layer 124A in the p-GAA FET 100 may comprise nickel silicide (Ni x Si y ), cobalt silicide (Co x Si y ), manganese silicide (Mn x Si y ), tungsten silicide (W x Si y ), iron silicide (Fe x Si y ), rhodium silicide (Rh x Si y ), palladium silicide (Pd x Si y ), ruthenium silicide (Ru x Si y ), platinum (Pt x Si y ), iridium silicide (Ir x Si y ), osmium silicide (Os x Si y ), other suitable metal silicide materials, or a combination thereof. In some embodiments, contact pin 124B may include conductive materials such as Co, W, Ru, Al, Mo, Ir, Ni, osmium (Os), rhodium (Rh), other suitable conductive materials, or a combination thereof.

[0032] In some embodiments, the semiconductor device 100 may embody a FinFET 100 instead of the GAA-FET 100, which is a cross-sectional view of Fig. 2 along the line A - A from Fig. 1A. Unless otherwise stated, the discussions of the elements in the Fig. 1A to 1E and 2, which have the same reference symbols, for each other. Unless otherwise stated, the discussion of the outer gate portion 113A of the GAA-FET 100 in the Fig. 1B to 1E also for the gate structure 112 of the FinFET 100 of Fig. 2. In Fig. 2, in contrast to the GAA-FET 100, the FinFET 100 may include: (I) fin structures 106 instead of the nanostructured channel regions 108 and the base structures 106; (II) gate structures 112 disposed directly on the fin structures 106; (III) fin regions of the fin structures 106 functioning as channel regions, which are disposed below the gate structures 112 and adjacent to the S / D regions 110; (IV) horizontal spacer portions 114h of the outer gate spacers 114 disposed directly on the fin structures 106; and (V) interface spacer layers 116 disposed directly on the fin regions of the fin structures 106 below the outer gate spacers 114.

[0033] Fig. 3 is a flow diagram of an exemplary method 300 for manufacturing a GAA-FET 100 with the cross-sectional views of the Fig. 1B to 1E according to some embodiments. For illustrative purposes, the Fig. 3 operations are described using the exemplary manufacturing process for the GAA-FET 100 shown in the Fig. 4 to 20. The Fig. 4 to 20 are sectional views of the GAA-FET 100 along the line A - A of Fig. 1A at various stages of fabrication for the GAA-FET 100, according to some embodiments. Depending on specific applications, operations may also be performed in a different order or not at all. It should be noted that the method 300 may not be able to fabricate a complete GAA-FET 100. It should therefore be understood that additional processes may be provided before, during, and after the method 300, and that some other processes may only be briefly described herein. Unless otherwise noted, the discussions of the elements in the Fig. 1A to 1E, 2 and 11 to 16, which have the same reference symbols, for each other.

[0034] In Fig. 3, in an operation 305, a superlattice structure with a nanostructured layer and a nanostructured sacrificial layer is fabricated on a base structure. As in Fig. For example, as shown in Figure 4, a superlattice structure 111 (also referred to as a "nanosheet stack 111") is fabricated on a fin-shaped base structure 106 fabricated on a substrate 102. The superlattice structure 111 may include nanostructured layers 108 and nanostructured sacrificial layers 109 arranged in an alternating configuration. In some embodiments, the nanostructured layers 108 may include Si, and the nanostructured sacrificial layers 109 may include SiGe.

[0035] In Fig. 3, in an operation 310, an oxide layer is formed on the superlattice structure, and a polysilicon structure is formed on the oxide layer. As described with reference to Fig. 4 and Fig. 5, an oxide layer 516 is formed on the top nanostructured layer 108 of the superlattice structure 111, and a polysilicon structure 512 is formed on the oxide layer 516. In some embodiments, the formation of the oxide layer 516 may include: (I) performing an oxidation process on the superlattice structure 111 to form a thermal oxide layer 416 that is Fig. 4; and (II) performing an etching process on the thermal oxide layer 416 after the formation of the polysilicon structure 512 to form the oxide layer 516 shown in Fig. 5. In these embodiments, the oxide layer 516 may include an oxide (e.g., SiO2) of the material (e.g., Si) of the topmost nanostructured layer 108 of the superlattice structure 111. In some embodiments, the formation of the oxide layer 516 may include contacting the topmost nanostructured layer 108 of the superlattice structure 111 with a precursor, such as tetraethyl orthosilicate (TEOS), in a CVD (chemical vapor deposition) process at a temperature of about 650°C to about 750°C to deposit a chemical oxide layer 416 (e.g., SiO2), as shown in Fig. 4; and (II) performing an etching process on the chemical oxide layer 416 after the formation of the polysilicon structure 512 to form the oxide layer 516, as shown in Fig. 5 is shown.

[0036] In some embodiments, the fabrication of the polysilicon structure 512 may include the following sequential operations: (I) depositing an amorphous, polycrystalline, or monocrystalline polysilicon layer 412 on the thermal or chemical oxide layer 416, as in Fig. 4; and (II) performing a patterning process (e.g., a lithography process) and an etching process on the polysilicon layer 412 to form the polysilicon structure 512, as shown in Fig. 5. In some embodiments, the same etch process may be used to etch the oxide layer 416 and the polysilicon layer 412. This may result in the oxide layer 516 being formed with sloped sidewalls and enlarged oxide regions 516ex extending laterally above sidewalls of the polysilicon structure 512 due to the difference in etch selectivity between the materials of the oxide layer 416 and the polysilicon layer 412. These enlarged oxide regions 516ex may lead to the formation of interface gaps between the outer gate spacers 114 and the topmost nanostructured layer 108 during the replacement of the polysilicon structure 512 and the oxide layer 516 with the gate structure 112.To prevent the gate structure 112 from extending into these interface gaps and being fabricated under the outer gate spacers 114, which may result in current leakage between the gate structure 112 and the S / D region 110, the interface gaps are filled with the interface spacer layers 116, as described below with reference to FIG. Fig. 9 to 17.

[0037] In Fig. 3, outer gate spacers and inner gate spacers are fabricated on the superlattice structure in an operation 315. As described with reference to the Fig. 6 and Fig. 7, for example, outer gate spacers 614 and inner gate spacers 118 are fabricated on the superlattice structure 111. In some embodiments, the fabrication of the outer gate spacers 614 may include the following sequential operations: (I) depositing a dielectric material layer (not shown) on the structure of Fig. 5; (II) performing an annealing process to densify the dielectric material layer; and (III) etching horizontal portions of the densified material layer on the superlattice structure 111 to produce outer gate spacers 614 having a thickness T1, as shown in Fig. 6. In subsequent operations, the gate spacers 614 are thinned to a thickness T7 to fabricate the outer gate spacers 114, as shown in Fig. 17 is shown.

[0038] The fabrication of the inner gate spacers 118 may include the following sequential operations: (I) performing an etching process on the structure of Fig. 6, to etch the parts of the superlattice structure 111 that are not covered by the polysilicon structure 512 and the outer gate spacers 614, and to create openings 710, as shown in Fig. 7; (II) performing an etching process on sidewalls of nanostructured sacrificial layers 109 facing the openings 710 to create inner gate spacer openings (not shown); (III) depositing a dielectric material layer (not shown) on sidewalls of the outer gate spacers 614 and the nanostructured layers 108 and on top surfaces of the polysilicon structure 512, the outer gate spacers 614, and the base structure 106 to fill the inner gate spacer openings; and (IV) performing an etching process on the dielectric material layer to create the structure of Fig. 7 to produce.

[0039] In some embodiments, etching the superlattice structure 111 to create the openings 710 may include a plasma-based dry etching process using etching gases such as carbon tetrafluoride (CF4), sulfur dioxide (SO2), hexafluoroethane (C2F6), chlorine (Cl2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), and hydrogen bromide (HBr), with gas mixtures such as hydrogen (H2), oxygen (O2), nitrogen (N2), and argon (Ar). The etching may be performed at a temperature of about 25°C to about 200°C at a pressure of about 5 mTorr to about 50 mTorr. The throughput for the etching gases may be about 5 Ncm 3 / min up to about 100 Ncm 3 / min. The plasma power can be approximately 50 W to approximately 200 W at a bias voltage of approximately 30 V to approximately 200 V.

[0040] In some embodiments, the etching of the sidewalls of the nanostructured sacrificial layers 109 may be performed using a dry etching process that has a higher etch selectivity for the SiGe of the nanostructured sacrificial layers 109 than for the Si of the nanostructured layers 108. For example, halogen-based chemicals may exhibit an etch selectivity that is higher for Ge than for Si. Therefore, halogen gases may etch SiGe faster than Si. In some embodiments, the halogen-based chemicals may be fluorine-based and / or chlorine-based gases. Alternatively, the etching of the nanostructured sacrificial layers 109 may be performed using a wet etching process with a higher selectivity for SiGe than for Si. For example, a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) and / or a mixture of ammonium hydrate (NH4OH) with H2O2 and deionized water (DI water) may be used for the wet etching process.

[0041] In some embodiments, an anisotropic dry etching process may be used to etch the dielectric material layer to form the inner gate spacers 118, which may have a higher etch rate along the z-axis than along the x-axis or the y-axis. This allows the portions of the dielectric material layer on the sidewalls of the outer gate spacers 614 and the nanostructured layers 108, and on the top surfaces of the polysilicon structure 512, the outer gate spacers 614, and the base structure 106 to be etched without etching the portions of the dielectric material layer in the inner gate spacer openings.

[0042] In Fig. 3, 320 S / D regions are generated in the superlattice structure in one operation. As in Fig. 8, for example, S / D regions 110 are created in a superlattice structure 111. In some embodiments, creating the S / D regions 110 may comprise epitaxial growth of a semiconductor material (e.g., Si or SiGe) with n- or p-dopants in openings 710, as shown in Fig. 8. The creation of the S / D regions 110 may be followed by the fabrication of the ESLs 120 and the ILD layers 122, as shown in Fig. 8 is shown.

[0043] In Fig. 3, in an operation 325, interface spacer layers are formed between the outer gate spacers and the superlattice structure. As described with reference to the Fig. 9 to 17, for example, interfacial spacer layers 116 are formed between outer gate spacers 114 and the topmost nanostructured layer 108 of the superlattice structure 111. The formation of the interfacial spacer layers 116 may include the following sequential operations: (I) Removing the polysilicon structure 512 to create a gate opening 912 having a width W1, as shown in Fig. 9; (II) performing a first oxidation process on the outer gate spacers 614 of Fig. 9 to produce an oxide layer 1015 as shown in Fig. 10; (III) performing a first oxide etching process on the structure of Fig. 10, to reduce the thickness of the oxide layer 1015 from the thickness T3 to a thickness T4 and to increase the width of the gate opening 912 from the width W1 to a width W2, as in Fig. 11; (IV) performing a second oxidation process on the outer gate spacers 614 of Fig. 11 to further oxidize sidewall portions of the outer gate spacers 614 to form an oxide layer 1215, as shown in Fig. 12; (V) performing a second oxide etching process on the structure of Fig. 12 to remove the oxide layers 516 and 1215, as in Fig. 13; (VI) performing a third oxidation process on the structure of Fig. 13 to produce an oxide layer 1415 as shown in Fig. 14; and (VII) performing a third oxide etching process on the structure of Fig. 14 to etch the oxide layer 1415 and to form interface spacer layers 116 and outer gate spacers 114, as shown in Fig. 15, Fig. 16 or Fig. 17. In some embodiments, depending on the etch parameters of the third oxide etch process, interface spacer layers 116 having the structural profiles of Fig. 15, Fig. 16 or Fig. 17 are produced.

[0044] In some embodiments, the first oxidation process may remove sidewall portions of the outer gate spacers 614 from Fig. 9 to produce an oxide layer 1015 having a thickness T3 of about 4 nm to about 10 nm, as shown in Fig. 10. In some embodiments, the outer gate spacers 614 may include SiOCN, SiOC, or SiON, and through the first oxidation process, the SiOCN, SiOC, or SiON of the sidewall portions may be converted to SiO2 to form the oxide layer 1015. By forming the oxide layer 1015, the thickness of the outer gate spacers 614 may be reduced from thickness T1 to thickness T2, as shown in Fig. 10. In some embodiments, the first oxidation process may be a high-temperature plasma oxidation process. In the high-temperature plasma oxidation process, the outer gate spacers 614 may be contacted with oxygen radicals in a plasma having a high temperature of about 400°C to about 900°C at a chamber pressure of about 0.003 Torr to about 3.0 Torr. The plasma may be generated using a gas mixture of oxygen with a flow rate of about 6000 Ncm 3 / min up to about 6500 Ncm 3 / min, nitrogen with a throughput of about 3800 Ncm 3 / min up to about 4000 Ncm 3 / min and hydrogen with a throughput of about 160 Ncm 3 / min up to about 200 Ncm 3 / min in the plasma chamber.

[0045] In some embodiments, the first oxide etching process may be a wet etching process. In the wet etching process, the oxide layer 1015 may be contacted with a hydrofluoric acid (HF acid) solution in deionized water (DI water). A volume ratio between the HF acid and DI water (HF:DI) may be about 1:100 to about 1:500.

[0046] In some embodiments, the second oxidation process may be used to remove the sidewall portions of the outer gate spacers 614 from Fig. 11 may be further oxidized to produce an oxide layer 1215 having a thickness T6 of about 4 nm to about 10 nm, as shown in Fig. 12. In some embodiments, the second oxidation process may be similar to the first oxidation process, and may convert the SiOCN, SiOC, or SiON in the layers of the sidewall portions of the outer gate spacers 614 into SiO2 to form the oxide layer 1215. By forming the oxide layer 1215, the thickness of the outer gate spacers 614 may be reduced from the thickness T2 to a thickness T5, as shown in Fig. 12 is shown.

[0047] In some embodiments, the second oxidation process may be a dry etching process. In the dry etching process, the oxide layers 516 and 1215 may be contacted with a gas mixture of HF gas and ammonia gas (NH3 gas) at a chamber pressure of about 0.1 Torr to about 1.0 Torr. A gas ratio of HF to NH3 may be about 1:4 to about 1:5. Removing the oxide layer 516 with the second oxide etching process creates interface gaps 1316 between the outer gate spacers 614 and the topmost nanostructured layer 108, as shown in Fig. 13. By removing the oxide layer 1215 with the second oxide etching process, the width of the gate opening 912 is increased from the width W2 to a width W3, as shown in Fig. 13 is shown.

[0048] In some embodiments, the third oxidation process may oxidize sidewall portions of the outer gate spacers 614 exposed in the gate opening 912 to form vertical portions of the oxide layer 1415 having a thickness T8, as shown in Fig. 14. At the same time, with the third oxidation process, the top surface of the nanostructured layer 108 exposed in the gate opening 912 may be oxidized to produce a horizontal portion of the oxide layer 1415, as shown in Fig. 14. The horizontal portion of the oxide layer 1415 extends to fill the interface gaps 1316 and is formed with a thickness T9 that is greater than the thickness T8. In some embodiments, the third oxidation process may be similar to the first oxidation process and may convert the SiOCN, SiOC, or SiON in the layers of the sidewall portions of the outer gate spacers 614 to SiO2 to form the vertical portions of the oxide layer 1415. In some embodiments, the third oxidation process may also convert a layer of Si of an upper portion of the nanostructured layer 108 to SiO2 to form the horizontal portion of the oxide layer 1415. By forming the oxide layer 1415, the thickness of the outer gate spacers 614 may be reduced from a thickness T5 to a thickness T7, as shown in Fig. 14 is shown.

[0049] In some embodiments, the third oxide etch process may be similar to the second oxide etch process, except that the duration of the third oxide etch process is shorter than that of the second oxide etch process. The duration of the third oxide etch process is shorter because the oxide layer 1415 is only partially removed to leave portions of the oxide layer 1415 in the interface gaps 1316, as opposed to the complete removal of the oxide layer 1415 during the second oxide etch process. By removing the vertical portions of the oxide layer 1415 with the third oxide etch process, the width of the gate opening 912 is increased from the width W3 to a width W4, as shown in FIGS. Fig. 15, Fig. 16 and Fig. 17 is shown.

[0050] In some embodiments, the oxide layer 1415 may be formed by depositing a layer of an insulating oxide material, such as SiO2, SiON, SiCN, or SiOCN, using a CVD process or an ALD (atomic layer deposition) process instead of performing the third oxidation process. In these embodiments, the thickness of the outer gate spacers 614 remains the thickness T5, and their thickness is not reduced from the thickness T5 to the thickness T7. Since the thickness T5 of the outer gate spacers 614 remains, the width of the gate opening 912 remains the width W3, and its width does not increase from the width W3 to the width W4 after the third oxide etch process.

[0051] As explained above, the first, second, and third oxidation processes and the first, second, and third oxide etching processes may be used to form the interface spacer layers 116, and they may simultaneously be used to adjust the width of the gate opening 912, if necessary. Thus, the width of the gate opening 912, which defines the gate length of the later-fabricated gate structure 112, may not be limited by the width of the polysilicon structure 512.

[0052] In some embodiments, the first and second oxidation processes and the first and second oxide etching processes may not be performed, and the formation of the interface spacer layers 116 may include the following sequential operations: (I) removing the polysilicon structure 512 to create a gate opening 912 having a width W1, as shown in Fig. 9; (II) removing the oxide layer 516 with a dry etching process similar to the second oxide etching process to create interfacial oxide gaps 1316; (III) performing the third oxidation process or the CVD or ALD process on the outer gate spacers 614 of Fig. 9 to produce an oxide layer 1415 as shown in Fig. 14; and (IV) performing a third oxide etching process on the structure of Fig. 14 to etch the oxide layer 1415 to form the interface spacer layers 116 and the outer gate spacers 114, as shown in Fig. 15, Fig. 16 or Fig. 17 is shown.

[0053] In Fig. 3, a gate structure is formed around the nanostructured layers in an operation 330. As described with reference to the Fig. 18 to 20, for example, a gate structure 112 is formed around the nanostructured layers 108. The formation of the gate structure 112 may include the following sequential operations: (I) Removing the nanostructured sacrificial layers 109 from the structure of Fig. 15, Fig. 16 or Fig. 17 to create gate openings 1812; (II) performing an oxidation process on the exposed areas of the nanostructured layers 108 in the gate openings 912 and 1812 to create ILD layers 112A, as in Fig. 18; (III) forming HK gate dielectric layers 112B on the ILD layers 112A as shown in Fig. 19; (IV) forming conductive layers 112C on the HK gate dielectric layers 112B as shown in Fig. 19; (V) etching the HK gate dielectric layer 112B and the conductive layer 112C in the outer gate part 113A; and (VI) forming a gate capping layer 112D on the HK gate dielectric layer 112B and the conductive layer 112C, as shown in Fig. 20. In some embodiments, the formation of the gate structure 112 may be followed by the formation of contact structures 124 on the S / D regions 110, as shown in Fig. 20 is shown.

[0054] The present disclosure provides example structures and methods for improving bottom corner profiles of gate structures in FETs to avoid current leakage between gate structures and S / D regions in the FETs. In some embodiments, a FET (e.g., GAA-FET 100) may include: nanostructured channel regions (e.g., nanostructured channel regions 108) disposed on a substrate; a gate structure (e.g., gate structure 112) disposed around the nanostructured channel regions; S / D regions (e.g., S / D regions 110) disposed adjacent to the nanostructured channel regions; and outer gate spacers (e.g., outer gate spacers 114) disposed along sidewalls of the gate structure to electrically isolate the gate structure from adjacent source / drain regions. In some embodiments, interface gaps (e.g.,Interfacial gaps (e.g., the interfacial gaps 1316) may be present between the outer gate spacers and the uppermost nanostructured channel regions. These interfacial gaps may be filled with interfacial spacer layers (e.g., the interfacial spacer layers 116) containing an insulating material. The interfacial spacer layers may prevent lower corner portions (e.g., a lower corner region 112cr) of the gate structure from forming in the interfacial gaps during gate structure fabrication. By preventing the lower corner portions of the gate structure from extending below the outer gate spacers, the distance between the gate structure and adjacent S / D regions may be increased, current leakage between the gate structure and adjacent S / D regions may be avoided or minimized, and device performance may be improved.Thus, by using the interfacial spacer layers, the bottom corner profiles of the gate structure can be controlled. Depending on the sidewall profiles (e.g., the rectangular profiles of sidewalls 116s1, the inclined profiles of sidewalls 116s2, and the curved profiles of sidewalls 116s3) of the interfacial spacer layers, the gate structure can have a U-shaped cross-sectional profile with bottom corners that have rectangular, obtuse, or rounded corner profiles.

[0055] In some embodiments, a semiconductor device comprises: a substrate; a semiconductor layer disposed on the substrate; an S / D region disposed adjacent to the semiconductor layer; a gate structure disposed on the semiconductor layer; an interface spacer layer having a triangular cross-sectional profile disposed along a sidewall of the gate structure; and a gate spacer. The gate spacer comprises: a first spacer portion having a first bottom surface with a substantially straight profile and disposed on the semiconductor layer; and a second spacer portion having a second bottom surface with an inclined profile and disposed on the interface spacer layer.

[0056] In some embodiments, a semiconductor device comprises: a substrate; a fin structure disposed on the substrate; a gate structure disposed on the fin structure; a gate spacer disposed along a sidewall of the gate structure; and an interface spacer layer. The interface spacer layer comprises: a first sidewall with an inclined profile facing a bottom surface of the gate spacer; a second sidewall facing the sidewall of the gate structure; and a bottom surface facing a top surface of the fin structure.

[0057] In some embodiments, a method comprises: forming an oxide layer on a semiconductor layer; forming a polysilicon structure on the oxide layer; forming a gate spacer on the oxide layer and the polysilicon structure; creating a gate opening by removing the polysilicon structure; forming an interfacial spacer layer between a bottom surface of the gate spacer and a top surface of the semiconductor layer; and forming a gate structure in the gate opening and in contact with the interfacial spacer layer and the gate spacer.

[0058] Features of various embodiments have been described above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other methods and structures for achieving the same objectives and / or obtaining the same benefits as the embodiments presented herein. Those skilled in the art will also appreciate that such equivalent interpretations do not depart from the spirit and scope of the present disclosure and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 609,616

[0001]

Claims

[1] Semiconductor device comprising: a substrate; a semiconductor layer disposed on the substrate; a source / drain region disposed adjacent to the semiconductor layer; a gate structure arranged on the semiconductor layer; an interface spacer layer having a triangular cross-sectional profile disposed along a sidewall of the gate structure; and a gate spacer comprising: a first spacer part having a first bottom surface with a substantially straight profile and arranged on the semiconductor layer, and a second spacer portion having a second bottom surface with an inclined profile and disposed on the interface spacer layer. [2] The semiconductor device of claim 1, wherein the interface spacer layer has a sidewall with a substantially straight profile facing the gate structure. [3] The semiconductor device according to claim 1 or 2, wherein the interface spacer layer has a sidewall with an inclined profile facing the gate structure. [4] A semiconductor device according to any one of the preceding claims, wherein the interface spacer layer has a sidewall with a curved profile facing the gate structure. [5] A semiconductor device according to any one of the preceding claims, wherein the interface spacer layer is disposed between the gate spacer and the semiconductor layer. [6] A semiconductor device according to any preceding claim, wherein the interface spacer layer contains an oxide of a material of the gate spacer. [7] A semiconductor device according to any one of the preceding claims, wherein the interface spacer layer contains an oxide of a material of the semiconductor layer. [8] A semiconductor device according to any preceding claim, wherein a lower corner of the gate structure has an obtuse-angled corner profile and is in contact with the interface spacer layer. [9] A semiconductor device according to any preceding claim, wherein a lower corner of the gate structure has a rounded corner profile and is in contact with the interface spacer layer. [10] A semiconductor device according to any one of the preceding claims, wherein the gate structure comprises: a gate oxide layer in contact with the interface spacer layer; and a gate dielectric layer in contact with the interface spacer layer. [11] Semiconductor device comprising: a substrate; a fin structure arranged on the substrate; a gate structure arranged on the fin structure; a gate spacer disposed along a sidewall of the gate structure; and an interfacial spacer layer comprising: a first side wall with an inclined profile facing the gate spacer, a second sidewall facing the sidewall of the gate structure, and a bottom side facing a top side of the fin structure. [12] The semiconductor device according to claim 11, wherein the interface spacer layer is disposed between the gate spacer and the fin structure. [13] The semiconductor device according to claim 11 or 12, wherein the second sidewall has a substantially straight profile. [14] The semiconductor device according to any one of claims 11 to 13, wherein the second side wall has an inclined profile. [15] The semiconductor device according to any one of claims 11 to 14, wherein the second sidewall has a curved profile. [16] A semiconductor device according to any one of claims 11 to 15, wherein the gate structure comprises: a gate oxide layer in contact with the interface spacer layer; and a gate dielectric layer in contact with the interface spacer layer. [17] Method comprising: Forming an oxide layer on a semiconductor layer; forming a polysilicon structure on the oxide layer; Forming a gate spacer on the oxide layer and the polysilicon structure; Creating a gate opening by removing the polysilicon structure; Forming an interface spacer layer between a bottom surface of the gate spacer and a top surface of the semiconductor layer; and Forming a gate structure in the gate opening and in contact with the interface spacer layer and the gate spacer. [18] The method of claim 17, wherein forming the interface spacer layer comprises oxidizing a sidewall of the gate spacer and the top surface of the semiconductor layer. [19] The method of claim 17 or 18, wherein forming the interface spacer layer comprises exposing an interface gap between a bottom surface of the gate spacer and a top surface of the semiconductor layer. [20] The method of claim 19, wherein exposing the interface gap comprises etching the oxide layer.

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