Semiconductor device

Abstract

A transistor that can be miniaturized is provided. The semiconductor device comprises an oxide semiconductor layer, first through fourth conductive layers, and first through fourth insulating layers. Above the first conductive layer, which includes a recessed section, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer, which includes a first opening section overlapping the recessed section, are provided in that order. The third insulating layer is in contact with at least the side face of the second conductive layer in the first opening section. The oxide semiconductor layer is in contact with the top surface of the third conductive layer, as well as the bottom surface and side face of the recessed section, and is in contact with the third insulating layer in the first opening section.The fourth insulating layer is located further inward than the oxide semiconductor layer in the first opening section. The fourth conductive layer is located further inward than the fourth insulating layer in the first opening section. In a cross-sectional view, the oxide semiconductor layer includes an area that overlaps with the second conductive layer, with the third insulating layer in between, and overlaps with the fourth conductive layer, with the fourth insulating layer in between.

Description

Background of the invention 1. Field of the invention

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. One embodiment of the present invention also relates to a method for manufacturing the semiconductor device.

[0002] An embodiment of the present invention is not limited to the above technical field. Examples of the technical field of an embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input / output device (e.g., a touch screen), operating methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device refers to a device utilizing semiconductor properties, and refers to a circuit including a semiconductor element (e.g., a transistor, a diode, or a photodiode), a device including the circuit, and the like. The semiconductor device also refers to devices that can operate by utilizing semiconductor properties. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component including a chip in a package are examples of the semiconductor device. In some cases, a memory device, a display device, a light-emitting device, a lighting device, and an electronic appliance are semiconductor devices per se and also include a semiconductor device. 2. Description of the state of the art

[0004] In recent years, semiconductor devices have been developed; an LSI, a central processing unit (CPU), a memory, and the like are mainly used for semiconductor devices. A CPU is an aggregate of semiconductor elements; the CPU includes a semiconductor integrated circuit (including at least one transistor and a memory) formed into a chip by processing a semiconductor wafer and provided with an electrode that serves as a connection terminal.

[0005] A semiconductor circuit (IC chip) of an LSI, a CPU, a memory, or the like is mounted on a circuit board, such as a printed circuit board, to be used as one of the components of various electronic devices.

[0006] A technique in which a transistor is formed using a semiconductor thin film formed over a substrate with an insulating surface has attracted attention. The transistor is used in a wide range of electronic devices, such as integrated circuits (ICs) and display devices. Silicon-based semiconductor materials are widely used as semiconductor materials for the transistor, but oxide semiconductors are also attracting attention as alternative materials.

[0007] It is known that a transistor containing an oxide semiconductor has a very low leakage current in the off state. For example, Patent Document 1 discloses a low-power CPU that utilizes a low leakage current characteristic of the transistor containing an oxide semiconductor. Furthermore, Patent Document 2, for example, discloses a memory device that can retain stored data for a long time by utilizing a low leakage current characteristic of the transistor containing an oxide semiconductor.

[0008] In recent years, demand for a higher-density integrated circuit has increased with the reduction in size and weight of electronic devices. Furthermore, the productivity of a semiconductor device including an integrated circuit is to be improved. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique that achieves a higher-density integrated circuit by overlapping a plurality of memory cells by stacking a first transistor including an oxide semiconductor film and a second transistor including an oxide semiconductor film. Patent Document 4 discloses a technique that achieves a higher-density integrated circuit by forming a channel of a transistor including an oxide semiconductor film in the vertical direction. [References][Patent Documents] [Patent Document 1] Japanese Patent Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Laid-Open No. 2011-151383 [Patent Document 3] PCT International Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Laid-Open No. 2013-211537 [Non-patent document]

[0009] [Non-Patent Document 1] M. Oota, et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72 nm,” IEDM Tech. Dig., 2019, pp.50-53 Summary of the invention

[0010] An object of an embodiment of the present invention is to provide a transistor with advantageous electrical properties. Another object of an embodiment of the present invention is to provide a transistor with high forward current. An object of an embodiment of the present invention is to provide a transistor with low parasitic capacitance. Another object of an embodiment of the present invention is to provide a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated. Another object of an embodiment of the present invention is to provide a display device with high resolution or high aperture ratio.Another object of an embodiment of the present invention is to provide a transistor, a semiconductor device, a display device, or a memory device with high reliability. Another object of an embodiment of the present invention is to provide a semiconductor device, a display device, or a memory device with low power consumption. Another object of an embodiment of the present invention is to provide a memory device that operates at high speed. Another object of an embodiment of the present invention is to provide a method for manufacturing the transistor, the semiconductor device, the display device, or the memory device.

[0011] It should be noted that the description of these objects does not preclude the existence of further objects. An embodiment of the present invention does not necessarily have to fulfill all of these objects. Further objects may be derived from the explanation of the description, the drawings, the claims, and the like.

[0012] One embodiment of the present invention is a semiconductor device comprising an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. The first insulating layer overlies the first conductive layer. The second conductive layer overlies the first insulating layer. The second insulating layer overlies the second conductive layer. The third conductive layer overlies the second insulating layer. The first conductive layer includes a first recessed portion. The first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer include a first opening portion in a position overlapping with the first recessed portion.The third insulating layer is in contact with at least one side surface of the second conductive layer in the first opening portion. The oxide semiconductor layer is in contact with a top surface of the third conductive layer and a bottom surface and a side surface of the first recessed portion, and is in contact with the third insulating layer in the first opening portion. The fourth insulating layer is located further inside the first opening portion than the oxide semiconductor layer. The fourth conductive layer is located further inside the first opening portion than the fourth insulating layer. In a cross-sectional view, the oxide semiconductor layer includes a region that overlaps with the second conductive layer with the third insulating layer therebetween and overlaps with the fourth conductive layer with the fourth insulating layer therebetween.

[0013] The semiconductor device preferably further comprises a fifth insulating layer. In this case, the first conductive layer and the second insulating layer are preferably located above the fifth insulating layer, and the shortest distance from a top surface of the fifth insulating layer to a top surface of the first conductive layer in contact with the first insulating layer is preferably longer than the shortest distance from the top surface of the fifth insulating layer to a bottom surface of the fourth insulating layer. Alternatively, the first conductive layer and the fourth conductive layer are preferably located above the fifth insulating layer, and the shortest distance from the top surface of the fifth insulating layer to the top surface of the first conductive layer in contact with the first insulating layer is preferably longer than or equal to the shortest distance from the top surface of the fifth insulating layer to a bottom surface of the fourth conductive layer.

[0014] The first conductive layer preferably comprises a fifth conductive layer and a sixth conductive layer over the fifth conductive layer. The sixth conductive layer preferably comprises a second recessed portion. The first opening portion preferably overlaps with the second recessed portion. The oxide semiconductor layer is preferably in contact with a bottom surface and a side surface of the second recessed portion.

[0015] The semiconductor device preferably further comprises a sixth insulating layer. In this case, the fourth insulating layer preferably covers a top surface and a side surface of the oxide semiconductor layer over the second insulating layer. It is preferable that the sixth insulating layer overlies the fourth insulating layer and includes a second opening portion in a position overlapping with the first opening portion. The fourth conductive layer preferably includes a portion overlapping with the oxide semiconductor layer in the first opening portion with the fourth insulating layer therebetween, and a portion positioned in the second opening portion.Alternatively, it is preferable that the sixth insulating layer overlies the second insulating layer, covers the top and side surfaces of the oxide semiconductor layer over the second insulating layer, and includes the second opening portion in a position overlapping with the first opening portion. The fourth insulating layer preferably includes a portion positioned within the second opening portion. The fourth conductive layer is preferably located further inside the second opening portion than the fourth insulating layer.

[0016] Another embodiment of the present invention is a semiconductor device comprising an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer. The first insulating layer overlies the first conductive layer. The second conductive layer overlies the first insulating layer. The second insulating layer overlies the second conductive layer. The third conductive layer overlies the second insulating layer. The first conductive layer includes a first recessed portion. The first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer include a first opening portion in a position overlapping with the first recessed portion.The third insulating layer is in contact with at least one side surface of the second conductive layer in the first opening portion. The oxide semiconductor layer is in contact with a top surface of the third conductive layer and a bottom surface and a side surface of the first recessed portion, and is in contact with the third insulating layer in the first opening portion. The fourth insulating layer is located further inside the first opening portion than the oxide semiconductor layer. The fourth conductive layer is located further inside the first opening portion than the fourth insulating layer. The fifth insulating layer is located over the fourth insulating layer and includes a second opening portion that reaches the fourth conductive layer at a position overlapping with the first opening portion. The fifth conductive layer is in contact with the fourth conductive layer in the second opening portion.In a cross-sectional view, the oxide semiconductor layer includes a region overlapping with the second conductive layer with the third insulating layer therebetween and overlapping with the fourth conductive layer with the fourth insulating layer therebetween.

[0017] The semiconductor device preferably further comprises a sixth insulating layer. In this case, the first conductive layer and the second insulating layer are preferably located above the sixth insulating layer, and the shortest distance from a top surface of the sixth insulating layer to a top surface of the first conductive layer in contact with the first insulating layer is preferably longer than the shortest distance from the top surface of the sixth insulating layer to a bottom surface of the fourth insulating layer. Alternatively, the first conductive layer and the fourth conductive layer are preferably located above the sixth insulating layer, and the shortest distance from the top surface of the sixth insulating layer to the top surface of the first conductive layer in contact with the first insulating layer is preferably longer than or equal to the shortest distance from the top surface of the sixth insulating layer to a bottom surface of the fourth conductive layer.

[0018] The first conductive layer preferably comprises a sixth insulating layer and a seventh conductive layer over the sixth conductive layer. The seventh conductive layer preferably comprises a second recessed portion. The first opening portion preferably overlaps with the second recessed portion. The oxide semiconductor layer is preferably in contact with a bottom surface and a side surface of the second recessed portion.

[0019] In each of the above semiconductor devices, the third insulating layer preferably includes a seventh insulating layer in contact with the oxide semiconductor layer and an eighth insulating layer positioned further outward than the seventh insulating layer in the first opening portion. It is preferable that one of the seventh insulating layer and the eighth insulating layer is an oxide insulating layer, and the other is a nitride insulating layer.

[0020] Another embodiment of the present invention is a semiconductor device comprising a first layer and a second layer over the first layer. The second layer comprises a first memory cell array and a second memory cell array. The first memory cell array comprises a plurality of first memory cells. The second memory cell array comprises a plurality of second memory cells. The first layer comprises a transistor including silicon in a channel formation region. The first memory cell and the second memory cell each comprise a vertical transistor. The vertical transistor includes an oxide semiconductor in a channel formation region. The first memory cell and the second memory cell have different structures.

[0021] Another embodiment of the present invention is a semiconductor device comprising a first layer, a second layer over the first layer, and a third layer over the second layer. The second layer comprises a first memory cell array. The third layer comprises a second memory cell array. The first memory cell array comprises a plurality of first memory cells. The second memory cell array comprises a plurality of second memory cells. The first layer comprises a transistor including silicon in a channel formation region. The first memory cell and the second memory cell each comprise a vertical transistor. The vertical transistor includes an oxide semiconductor in a channel formation region. The first memory cell and the second memory cell have different structures.

[0022] One of the first memory cell and the second memory cell preferably holds data for a longer time than the other without power supply to the memory cell.

[0023] Another embodiment of the present invention is a semiconductor device comprising a first layer and a second layer over the first layer. The second layer comprises a first memory cell array and a second memory cell array. The first memory cell array comprises a plurality of first memory cells. The second memory cell array comprises a plurality of second memory cells. The first layer comprises a transistor including silicon in a channel formation region. The first memory cell consists of a vertical transistor and a capacitor. The second memory cell consists of two vertical transistors. The vertical transistors included in the first memory cell and the second memory cell each include an oxide semiconductor in a channel formation region.

[0024] Another embodiment of the present invention is a semiconductor device comprising a first layer, a second layer over the first layer, and a third layer over the second layer. The second layer comprises a first memory cell array. The third layer comprises a second memory cell array. The first memory cell array comprises a plurality of first memory cells. The second memory cell array comprises a plurality of second memory cells. The first layer comprises a transistor including silicon in a channel formation region. One of the first memory cell and the second memory cell consists of a vertical transistor and a capacitor, and the other consists of two vertical transistors. The vertical transistors included in the first memory cell and the second memory cell each include an oxide semiconductor in a channel formation region.

[0025] One embodiment of the present invention may provide a transistor with advantageous electrical properties. Another embodiment of the present invention may provide a transistor with high forward current. Another embodiment of the present invention may provide a transistor with low parasitic capacitance. Another embodiment of the present invention may provide a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated. Another embodiment of the present invention may provide a display device with high resolution or high aperture ratio. Another embodiment of the present invention may provide a transistor, a semiconductor device, a display device, or a memory device with high reliability.Another embodiment of the present invention may provide a semiconductor device, a display device, or a memory device with low power consumption. Another embodiment of the present invention may provide a memory device that operates at high speed. Another embodiment of the present invention may provide a method for manufacturing the transistor, the semiconductor device, the display device, or the memory device.

[0026] It should be noted that the description of these effects does not preclude the existence of further effects. An embodiment of the present invention does not necessarily have to have all of these effects. Further effects can be derived from the explanation of the description, the drawings, the claims, and the like. Short description of the drawings

[0027] In the accompanying drawings: Fig. 1A to Fig. 1F are perspective views illustrating structural examples of a semiconductor device; Fig. 2A1 and Fig. 2A2 are plan views showing examples of a semiconductor device, and Fig. 2B to Fig. 2E are cross-sectional views illustrating the example of a semiconductor device; Fig. 3 is a cross-sectional view illustrating an example of a semiconductor device; Fig. 4A and Fig. 4B are cross-sectional views illustrating examples of a semiconductor device; Fig. 5A and Fig. 5B are cross-sectional views illustrating examples of a semiconductor device; Fig. 6A to Fig. 6D are cross-sectional views illustrating examples of a semiconductor device; Fig. 7A to Fig. 7C are cross-sectional views illustrating examples of a semiconductor device; Fig. 8A is a plan view showing an example of a semiconductor device, and Fig. 8B to Fig. 8E are cross-sectional views illustrating the example of a semiconductor device; Fig. 9A and Fig. 9B are cross-sectional views illustrating examples of a semiconductor device; Fig. 10A is a plan view showing an example of a semiconductor device, and Fig. 10B to Fig. 10E are cross-sectional views illustrating the example of a semiconductor device; Fig. 11A and Fig. 11B are cross-sectional views illustrating examples of a semiconductor device; Fig. 12A is a plan view showing an example of a semiconductor device, and Fig. 12B to Fig. 12E are cross-sectional views illustrating the example of a semiconductor device; Fig. 13A and Fig. 13B are cross-sectional views illustrating examples of a semiconductor device; Fig. 14A to Fig. 14C2 are cross-sectional views illustrating examples of a semiconductor device; Fig. 15A1 to Fig. 15E are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device; Fig. 16A to Fig. 16C are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device; Fig. 17A to Fig. 17F are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device; Fig. 18A to Fig. 18F are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device; Fig. 19A to Fig. 19D are cross-sectional views illustrating the example of a method for manufacturing a semiconductor device; Fig. 20A to Fig. 20D are cross-sectional views illustrating a method for forming a metal oxide of one embodiment of the present invention; Fig. 21A to Fig. 21D are cross-sectional views illustrating the method for forming a metal oxide of one embodiment of the present invention; Fig. 22A is a plan view illustrating an example of a storage device, and Fig. 22B and Fig. 22C are cross-sectional views illustrating the example of a memory device; Fig. 23A and Fig. 23B are cross-sectional views illustrating an example of a memory device; Fig. 24A and Fig. 24B are cross-sectional views illustrating an example of a memory device; Fig. 25A is a plan view showing an example of a storage device, and Fig. 25B and Fig. 25C are cross-sectional views illustrating the example of a memory device; Fig. 26A and Fig. 26B are cross-sectional views illustrating an example of a memory device; Fig. 27A and Fig. 27B are cross-sectional views illustrating examples of a memory device; Fig. 28 is a cross-sectional view illustrating an example of a memory device; Fig. 29 is a cross-sectional view illustrating an example of a memory device; Fig. 30 is a cross-sectional view illustrating an example of a memory device; Fig. 31 is a cross-sectional view illustrating an example of a memory device; Fig. 32 is a cross-sectional view illustrating an example of a memory device; Fig. 33A is a plan view illustrating an example of a storage device, and Fig. 33B is a cross-sectional view illustrating the example of a memory device; Fig. 34 is a cross-sectional view illustrating an example of a memory device; Fig. 35 is a cross-sectional view illustrating an example of a memory device; Fig. 36A is a plan view illustrating an example of a storage device, and Fig. 36B is a cross-sectional view illustrating the example of a memory device; Fig. 37 is a cross-sectional view illustrating an example of a memory device; Fig. 38 is a cross-sectional view illustrating an example of a memory device; Fig. 39 is a block diagram showing a structural example of a semiconductor device; Fig. 40A to Fig. 40G each illustrates an example of a circuit structure of a memory cell; Fig. 41A and Fig. 41B are perspective views illustrating structural examples of a semiconductor device; Fig. 42 is a block diagram illustrating a CPU; Fig. 43A and Fig. 43B are perspective views illustrating a structural example of a semiconductor device; Fig. 44A and Fig. 44B are perspective views of a semiconductor device; Fig. 45A and Fig. 45B each represent a hierarchy of different types of storage devices; Fig. 46A and Fig. 46B are perspective views illustrating an example of a display device. Fig. 47 is a cross-sectional view showing an example of a display device; Fig. 48 is a cross-sectional view showing an example of a display device; Fig. 49 is a cross-sectional view showing an example of a display device; Fig. 50 is a cross-sectional view showing an example of a display device; Fig. 51A to Fig. 51 C illustrate structural examples of a display device; Fig. 52A and Fig. 52B represent examples of electronic components; Fig. 53A to Fig. 53C are examples of a large computer, Fig. 53D shows an example of a room interior, and Fig. Figure 53E illustrates an example of a storage system that may be used in a data center; Fig. 54A to Fig. 54F are examples of electronic devices; Fig. 55A to Fig. 55G are examples of electronic devices; Fig. 56A to Fig. 56F represent examples of electronic devices; Fig. 57A is a circuit diagram of an example, and Fig. 57B is a timing diagram of the example; and Fig. 58A and Fig. 58B shows measurement results of read currents in an example; Detailed description of the invention

[0028] Embodiments will be described in detail with reference to the drawings. It should be noted that the embodiments of the present invention are not limited to the following description, and it will be readily apparent to those skilled in the art that modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as limited to the description of the following embodiments.

[0029] It should be noted that in the structures of the invention described below, the same sections or sections with similar functions are designated by the same reference numerals in different drawings, and descriptions of such sections will not be repeated. The same hatching pattern is used for sections with similar functions, and in some cases, the sections are not designated by specific reference numerals.

[0030] The position, size, range, or the like of each component illustrated in drawings may not accurately represent the position, size, range, or the like in some cases for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like disclosed in the drawings.

[0031] It should be noted that ordinal numbers such as "first" and "second" are used in this specification and the like for convenience and do not limit the number or order (e.g., the order of steps or the order of arrangement) of components. The ordinal number assigned to a component in one part of this specification may be different from the ordinal number assigned to the component in another part of this specification or the scope of the claims.

[0032] A transistor is a type of semiconductor device that enables amplification of current or voltage, switching to control conduction or non-conduction, and the like. A transistor in this description includes an insulated-gate field-effect transistor (IGFET) and a thin-film transistor (TFT).

[0033] In this specification and the like, in some cases, a transistor containing an oxide semiconductor or a metal oxide in its semiconductor layer and a transistor containing an oxide semiconductor or a metal oxide in its channel formation region are each referred to as an OS transistor. Furthermore, in some cases, a transistor containing silicon in its channel formation region is referred to as an Si transistor.

[0034] In this specification and the like, a transistor is an element that includes at least three terminals, namely a gate, a drain, and a source. The transistor includes a region where a channel is formed (also called a channel formation region) between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode), and a current can flow through the channel formation region between the source and the drain. Note that in this specification and the like, a channel formation region refers to a region through which a current mainly flows.

[0035] For example, when a transistor with a different polarity is used or when the current flow direction is changed during circuit operation, the functions of a "source" and a "drain" are sometimes interchanged. Therefore, the terms "source" and "drain" can be used interchangeably in this description.

[0036] It should be noted that, for example, impurities in a semiconductor refer to elements that are different from the main components of the semiconductor. For example, an element whose concentration is lower than 0.1 atomic% is an impurity. If a semiconductor contains an impurity, it could, for example, cause an increase in the density of defect states or a decrease in the crystallinity of the semiconductor. In the case where the semiconductor is an oxide semiconductor, examples of an impurity that changes the properties of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals that are different from the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.It should be noted that water also serves as a contaminant in some cases. The ingress of a contaminant could, for example, cause oxygen vacancies (also known as V. o (called) in an oxide semiconductor.

[0037] It should be noted that in this specification and the like, an oxynitride refers to a material in which the oxygen content is higher than the nitrogen content. A nitride oxide refers to a material in which the nitrogen content is higher than the oxygen content.

[0038] The contents of elements such as hydrogen, oxygen, carbon, and nitrogen in a film can be analyzed, for example, by secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). Note that XPS is suitable when the percentage content of a target element is high (e.g., 0.5 atomic% or higher, or 1 atomic% or higher). In contrast, SIMS is suitable when the percentage content of a target element is low (e.g., 0.5 atomic% or lower, or 1 atomic% or lower). To compare element contents, analysis by a combination of SIMS and XPS is preferably used.

[0039] It should be noted that the terms "film" and "layer" can be used interchangeably depending on the situation or circumstances. For example, the term "conductive layer" can be replaced with the term "conductive film." As another example, the term "insulating film" can be replaced with the term "insulating layer."

[0040] In this specification and the like, the term "parallel" indicates that the angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°. Therefore, the case where the angle is greater than or equal to -5° and less than or equal to 5° is also included. The term "substantially parallel" indicates that the angle formed between two straight lines is greater than or equal to -20° and less than or equal to 20°. The term "perpendicular" indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°. Therefore, the case where the angle is greater than or equal to 85° and less than or equal to 95° is also included.Furthermore, the term “substantially perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 70° and less than or equal to 110°.

[0041] In this specification and the like, the term "electrically connected" includes the case where components are connected to each other via "an object having any electrical function." There is no particular limitation on an "object having any electrical function" as long as electrical signals can be sent and received between components connected via the object. Examples of the "object having any electrical function" include a switching element such as a transistor, a resistor, a coil, a capacitor, and an element with various functions, as well as an electrode and a wire.

[0042] Unless otherwise stated, a reverse current in this specification and the like refers to a leakage current between a source and a drain generated when a transistor is in a reverse state (also called a non-conductive state or cutoff state). Unless otherwise stated, the reverse state of an n-channel transistor means that a gate-source voltage V gs is lower than a threshold voltage Vt h , and the off state of a p-channel transistor means that V gs is higher than V th .

[0043] Note that in this specification and the like, "normally on" refers to a state in which a channel exists even when no voltage is applied to a gate and a current flows through a transistor. Furthermore, "normally off" refers to a state in which no current flows through a transistor when no potential or a ground potential is applied to a gate.

[0044] In this specification and the like, a tapered shape refers to a shape in which at least a part of a side surface of a component is inclined with respect to a substrate surface or a formation surface of the component. For example, a tapered shape preferably includes a range in which the angle between the inclined side surface and the substrate surface or the formation surface (such an angle is also referred to as a taper angle) is greater than 0° and less than 90°. Note that the side surface of the component, the substrate surface, and the formation surface are not necessarily completely flat and may be substantially flat with a slight curvature or with slight unevenness.

[0045] In this specification and the like, when the expression “A is positioned over B” is used, at least a part of A is positioned over B. In other words, A includes, for example, an area positioned over B. Similarly, when the expression “A is in contact with B” or “A overlaps with B” is used, at least a part of A is in contact with or overlaps with B. In other words, A includes, for example, an area in contact with B or A includes an area overlapping with B. Similarly, in this specification and the like, when the expression “A covers B” is used, a part of A covers B. In other words, A includes, for example, an area covering B.

[0046] In this specification and the like, a device formed using a metal mask or a fine metal mask (FMM) may be referred to as a device having a metal mask (MM) structure. In this specification and the like, a device formed without using a metal mask or an FMM may be referred to as a device having a metal maskless (MML) structure.

[0047] In this specification and the like, a structure in which light-emitting layers of light-emitting elements (also referred to as light-emitting devices) with different emission wavelengths are separately formed may be referred to as a side-by-side (SBS) structure. The SBS structure can optimize the materials and structures of light-emitting elements and thus increase the degree of freedom of choice of materials and structures, thereby easily improving luminance and reliability.

[0048] In this specification and the like, a hole or an electron is referred to as a carrier in some cases. Specifically, a hole injection layer or an electron injection layer may be referred to as a carrier injection layer, a hole transport layer or an electron transport layer may be referred to as a carrier transport layer, and a hole blocking layer or an electron blocking layer may be referred to as a carrier blocking layer. Note that the carrier injection layer, the carrier transport layer, and the carrier blocking layer mentioned above may not be different from each other in some cases. One layer may have two or three functions of the carrier injection layer, the carrier transport layer, and the carrier blocking layer in some cases.

[0049] In this specification and the like, a light-emitting element includes an EL layer between a pair of electrodes. The EL layer includes at least one light-emitting layer. Examples of layers (also referred to as functional layers) in the EL layer include a light-emitting layer, charge injection layers (a hole injection layer and an electron injection layer), charge transport layers (a hole transport layer and an electron transport layer), and charge blocking layers (a hole blocking layer and an electron blocking layer). In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other may be referred to as a common electrode.

[0050] In this specification and the like, a sacrificial layer (which may also be referred to as a mask layer) refers to a layer positioned at least above a light-emitting layer (particularly, a layer processed into an island shape among layers included in an EL layer) and having a function of protecting the light-emitting layer in the manufacturing process.

[0051] In this specification and the like, separation refers to a phenomenon in which a layer, film, or electrode is split due to the shape of its formation surface (e.g., a step).

[0052] In the drawings for this specification and the like, in some cases, arrows are shown representing an X direction, a Y direction, and a Z direction. In this specification and the like, the "X direction" is a direction along the X axis, and unless otherwise specified, the forward direction and the reverse direction are not distinguished in some cases. The same applies to the "Y direction" and the "Z direction." The X direction, the Y direction, and the Z direction are directions that intersect each other. For example, the X direction, the Y direction, and the Z direction are directions that are perpendicular to each other. (Embodiment 1)

[0053] In this embodiment, semiconductor devices of embodiments of the present invention are described with reference to Fig. 1A to Fig. 1F. The semiconductor devices of this embodiment can each serve as a memory device.

[0054] Fig. 1A to Fig. 1F are schematic perspective views illustrating the semiconductor devices. The Fig. 1A to Fig. 1F each comprise a layer 91 and one or more layers 92 over layer 91.

[0055] The layer 91 may, for example, be a structure suitable for a driver circuit 910 ( Fig. 39) described later, or have a structure suitable for an arithmetic device 960 ( Fig. 42), which will be described later. In particular, layer 91 includes, for example, a read circuit. Layer 91 preferably includes a transistor containing silicon in its channel formation region.

[0056] A layer 92 includes at least one type of memory cell array 93. The following description assumes that a memory cell array 93 includes one type of memory cell. The memory cell array 93 includes one or more memory cells. For example, the memory cell array 93 includes a plurality of memory cells arranged in a matrix. In the memory cell array 93, a plurality of memory cells can be arranged in at least one of the X direction, the Y direction, and the Z direction.

[0057] The semiconductor device of one embodiment of the present invention includes at least two types of memory cell arrays 93. Examples of a memory cell that can be used for each memory cell array 93 include a memory cell consisting of one transistor and one capacitor (hereinafter referred to as a 1Tr1C memory cell), a memory cell consisting of two transistors and one capacitor (hereinafter referred to as a 2Tr1C memory cell), and a memory cell consisting of two transistors (hereinafter referred to as a 2Tr0C memory cell). Note that the structure of the memory cell is not limited to this; two or more transistors (typically two to six transistors) and one or more capacitors (typically one to five capacitors) can be used in combination.

[0058] When the semiconductor device includes two or more types of memory cells, a memory cell to be used can be selected depending on the purpose. This allows the memory device to achieve all of the features of high-speed writing, high-speed reading, and low power consumption.

[0059] For example, in a 1Tr1C memory cell, stored data is erased upon reading (also referred to as destructive reading). On the other hand, in 2Tr0C and 2Tr1C memory cells, stored data is not erased upon reading (also referred to as non-destructive reading). The semiconductor device of one embodiment of the present invention preferably includes a plurality of types of such memory cells that perform different operations.

[0060] The semiconductor device of an embodiment of the present invention preferably comprises at least one of the Fig. 40A to Fig. 40G memory cells. Here is one in Fig. 40A, the memory cell 951 is an example of the 1Tr1 C memory cell. Fig. 40C shown memory cell 953 and one in Fig. 40D are examples of the 2Tr1 C memory cell. Fig. 40E shown memory cell 955 and one in Fig. The memory cell 956 shown in Figure 40F are examples of the 2Tr0C memory cell. The details of the memory cells are described below.

[0061] Layer 92 preferably comprises a transistor that includes an oxide semiconductor in its channel formation region. The transistor of one embodiment of the present invention that includes an oxide semiconductor in its channel formation region and has a low off-state current is suitable for a memory cell. Therefore, the memory cell is substantially non-volatile. In addition, the transistor of one embodiment of the present invention has a high on-state current and a low off-state current, thus enabling high-speed writing and non-destructive reading. The details of the transistor that includes an oxide semiconductor in its channel formation region are described below (see Fig. 2A1 to Fig. 2E, Fig. 3, Fig. 4A and Fig. 4B, Fig. 5A and Fig. 5B, Fig. 6A to Fig. 6D, Fig. 7A to Fig. 7C, Fig. 8A to Fig. 8E, Fig. 9A and Fig. 9B, Fig. 10A to Fig. 10E, Fig. 11A and Fig. 11B, Fig. 12A to Fig. 12E, Fig. 13A and Fig. 13B, Fig. 14A to Fig. 14C2, Fig. 15A1 to Fig. 15E, Fig. 16A to Fig. 16C, Fig. 17A to Fig. 17F, Fig. 18A to Fig. 18F, Fig. 19A to Fig. 19D and the like).

[0062] Note that in this specification and the like, a non-volatile memory refers to a memory that can retain stored data at 85°C for at least 1 day, preferably 1 month or more, more preferably 1 year or more, and even more preferably 10 years or more without power being supplied to the memory. In this specification and the like, a volatile memory refers to a memory other than the non-volatile memory.

[0063] For specific cross-sectional structure examples of the memory cell comprising the transistor of an embodiment of the present invention, Fig. 22A to Fig. 22C, Fig. 23A and Fig. 23B, Fig. 24A and Fig. 24B, Fig. 25A to Fig. 25C, Fig. 26A and Fig. 26B, Fig. 27A and Fig. 27B, Fig. 28, Fig. 29, Fig. 30, Fig. 31, Fig. 32 and the like. Here, memory cells that are Fig. 22A to Fig. 22C and Fig. 25A to Fig. 25C are examples of the 1Tr1 C memory cell. Memory cells used in Fig. 23A and Fig. 23B, Fig. 24A and Fig. 24B, Fig. 26A and Fig. 26B, Fig. 27A and Fig. 27B, Fig. 28, Fig. 29, Fig. 30 and Fig. 31 are examples of the 2Tr0C memory cell. The 2Tr0C memory cell can be used, for example, as a high-speed write memory or write-mostly memory. Fig. The memory cell shown in Figure 32 is an example of the 2Tr1C memory cell. When OS transistors are used for the 2Tr1C memory cell, a non-volatile function can be imparted to, for example, a dynamic random access memory (DRAM) or a static random access memory (SRAM). Note that the 1Tr1C and 2Tr1C memory cells can each be used as random access memory (RAM). The details of these cross-sectional structures are described below.

[0064] The Fig. 22A to Fig. The memory cells shown in Figure 32 each comprise a vertical transistor containing an oxide semiconductor in its semiconductor layer. The vertical transistor has high forward current characteristics, high frequency characteristics, and low reverse current characteristics, thus enabling the memory cell to have a substantially non-volatile function and perform high-speed writing and non-destructive reading.

[0065] It should be noted that the semiconductor device of one embodiment of the present invention has a function for reading and writing data from and to a storage (typically a large-capacity non-volatile memory device such as a 3D NAND memory device) in which data that needs to be stored for a long time, programs used in an arithmetic processing device, or the like are held (see Embodiment 6 and Fig. 45, described below, for details.) The 3D NAND memory device serves as a read-mostly memory due to its characteristics.

[0066] A semiconductor device 81 which is in Fig. 1A, and a semiconductor device 82 shown in Fig. 1B, each comprise a layer 92 above layer 91. Layer 92 of semiconductor device 81 comprises a memory cell array 93A and a memory cell array 93B. Layer 92 of semiconductor device 82 comprises memory cell array 93A, memory cell array 93B, and memory cell array 93C.

[0067] Memory cell arrays 93A and 93B preferably include memory cells with different circuit structures. For example, memory cell array 93A preferably includes one of the 1Tr1C, 2Tr0C, and 2Tr1C memory cells, and memory cell array 93B preferably includes another of the 1Tr1C, 2Tr0C, and 2Tr1C memory cells. Specifically, the 1Tr1C memory cell is preferably used for one of the memory cell arrays 93A and 93B, and the 2Tr0C memory cell is preferably used for the other.

[0068] Memory cell arrays 93A, 93B, and 93C preferably include memory cells with different circuit structures. For example, memory cell array 93A preferably includes one of the 1Tr1C, 2Tr0C, and 2Tr1C memory cells, memory cell array 93B preferably includes another of the 1Tr1C, 2Tr0C, and 2Tr1C memory cells, and memory cell array 93C preferably includes the remaining one of the 1Tr1C, 2Tr0C, and 2Tr1C memory cells.

[0069] Alternatively, two or more of the memory cell arrays 93A, 93B, and 93C may include memory cells having the same circuit structure. For example, two or more of the memory cell arrays 93A, 93B, and 93C may include memory cells having the same circuit structure (1Tr1C, 2Tr0C, 2Tr1C, or the like), and the number, size, and the like of the memory cells may differ from each other. By using a plurality of memory cell arrays differing in performance, specifications, and the like in this way, a multifunctional semiconductor device can be achieved even if the memory cells have the same circuit structure.

[0070] By providing two or more types of memory cell arrays 93 in one layer 92 in this way, a semiconductor device with a combination of a plurality of types of memory cells can be obtained. The combination of a plurality of types of memory cells enables the semiconductor device to have a function between a write-mostly memory and a read-mostly memory.

[0071] Note that the semiconductor device of one embodiment of the present invention is suitable for an arithmetic processing device, typically a CPU, a graphics processing unit (GPU), or the like. A CPU, a GPU, a memory, and the like are required to have higher performance with the advancement of artificial intelligence (AI) technology. On the other hand, in AI technology, the same data or similar data is used repeatedly in some cases. Therefore, a memory to be used is selected depending on the data to be stored. For example, important data that should not be deleted is stored in a memory that has a long data retention time, and the same data, similar data, or data that should be temporarily retained is stored in a memory that has a relatively short data retention time.As described above, in the semiconductor device of one embodiment of the present invention, different memory cells can be used depending on the purpose.

[0072] As a method for stacking layer 92 including the memory cell array and layer 91, a method in which layer 92 is disposed directly above layer 91 (also called a monolithic stacking method) may be used. The monolithic stacking method is suitable for miniaturization because alignment or fixing of layers 91 and 92 for connecting the layers is unnecessary. Note that, when the monolithic stacking method is used, assuming that layer 91 is a processor and layer 92 is a memory, for example, a so-called on-chip memory structure in which a memory is formed directly above a processor can be obtained. The on-chip memory structure enables an interface portion between the processor and the memory to operate at high speed.With the on-chip memory structure, the size of an interconnect line and the like can be small, thus increasing the number of interconnect pins. Increasing the number of interconnect pins enables parallel operations, which can improve memory bandwidth (also called memory bandwidth).

[0073] Alternatively, a mounting method or a bonding method may be used in which the layers 91 and 92 are formed over different substrates, and the different substrates are mounted and electrically connected to each other using a through-electrode technique such as a through-silicon via (TSV) or a bonding method using a conductive film (Cu-Cu interconnection or the like). The memory cell arrays 93A and 93B may be formed over the same substrate or different substrates. The same applies to the case where three or more types of memory cell arrays 93 are provided.

[0074] In the case where a plurality of types of memory cell arrays 93 are provided in one layer 92, the memory cell arrays 93 have the Fig. 1A and the like, the memory cell arrays 93A and 93B have uniformly divided regions; however, the present invention is not limited thereto. For example, one of the memory cell arrays 93A and 93B may occupy a larger area on top of the layer 91 than the other. The same applies to the case where three or more types of memory cell arrays 93 are provided. The outer shapes of the layers 91 and 92 may be the same or different from each other.

[0075] One in Fig. The semiconductor device 83 illustrated in Figure 1C includes two layers 92 above layer 91. Specifically, the semiconductor device 83 includes layer 91, a layer 92a above layer 91, and a layer 92b above layer 92a. Layer 92a includes memory cell array 93A, and layer 92b includes memory cell array 93B.

[0076] One in Fig. The semiconductor device 84 illustrated in Figure 1D includes three layers 92 above layer 91. Specifically, the semiconductor device 84 includes layer 91, layer 92a above layer 91, layer 92b above layer 92a, and a layer 92c above layer 92b. Layer 92a includes memory cell array 93A, layer 92b includes memory cell array 93B, and layer 92c includes memory cell array 93C.

[0077] With such a layer arrangement of the layers 92 comprising different memory cell arrays 93, a semiconductor device having a combination of a plurality of types of memory cells can be obtained.

[0078] One in Fig. 1E and a semiconductor device 85 shown in Fig. 1F each comprise two layers 92 above layer 91. In particular, semiconductor devices 85 and 86 each comprise layer 91, layer 92a above layer 91, and layer 92b above layer 92a. In semiconductor device 85, layer 92a comprises memory cell array 93A, and layer 92b comprises memory cell arrays 93B and 93C. In semiconductor device 86, layer 92a comprises memory cell arrays 93A and 93B, and layer 92b comprises memory cell array 93C.

[0079] It should be noted that in the semiconductor devices 83, 85 and 86 shown in Fig. 1C, Fig. 1E and Fig. 1F, the layers can be stacked by various methods. For example, layer 92a can be formed over layer 91 by the monolithic stacking method, and layer 92b can be formed over layer 92a by an attachment method. It should be noted that the present invention is not limited to this example, and layers 91, 92a, and 92b can be formed by the same stacking method. It should be noted that the above structure is also applicable to the layers shown in Fig. 1D may be used. In particular, layers 91, 92a, 92b, and 92c may be formed by the same stacking method or different stacking methods.

[0080] In this way, two or more types of memory cell arrays 93 are provided in one layer 92, and a plurality of layers 92 including different memory cell arrays 93 are stacked one on top of the other, whereby a semiconductor device with a combination of a plurality of types of memory cells can be obtained. Using the memory cell structure of one embodiment of the present invention, it is expected that power consumption will be reduced to 1 / 1000 of that of a conventional memory cell (e.g., DRAM).

[0081] This embodiment can be combined with any of the other embodiments as needed. In this description, where a plurality of structural examples are shown in one embodiment, the structural examples can be combined as needed. (Embodiment 2)

[0082] In this embodiment, semiconductor devices of embodiments of the present invention and a manufacturing method thereof are described with reference to Fig. 2A1 to Fig. 2E, Fig. 3, Fig. 4A and Fig. 4B, Fig. 5A and Fig. 5B, Fig. 6A to Fig. 6D, Fig. 7A to Fig. 7C, Fig. 8A to Fig. 8E, Fig. 9A and Fig. 9B, Fig. 10A to Fig. 10E, Fig. 11A and Fig. 11B, Fig. 12A to Fig. 12E, Fig. 13A and Fig. 13B, Fig. 14A to Fig. 14C2, Fig. 15A1 to Fig. 15E, Fig. 16A to Fig. 16C, Fig. 17A to Fig. 17F, Fig. 18A to Fig. 18F and Fig. 19A to Fig. 19D described.

[0083] The semiconductor device of one embodiment of the present invention includes an oxide semiconductor layer, first to fourth conductive layers, and first to fourth insulating layers.

[0084] The oxide semiconductor layer serves as the semiconductor layer of a transistor. The first conductive layer serves as one of the source electrode and the drain electrode of the transistor, the third conductive layer serves as the other of the source electrode and the drain electrode of the transistor, and the fourth conductive layer serves as the first gate electrode of the transistor. The fourth insulating layer serves as the first gate insulating layer of the transistor. The second conductive layer serves as the second gate electrode, and the third insulating layer serves as the second gate insulating layer.

[0085] The first insulating layer is positioned over the first conductive layer. The second conductive layer is positioned over the first insulating layer. The second insulating layer is positioned over the second conductive layer. The third conductive layer is positioned over the second insulating layer. The first conductive layer includes a first recessed portion. The first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer include a first opening portion in a position overlapping with the first recessed portion. The third insulating layer is in contact with the first conductive layer and in contact with at least the side surface of the first insulating layer, the side surface of the second conductive layer, and the side surface of the second insulating layer in the first opening portion.The oxide semiconductor layer is in contact with the top surface of the third conductive layer and the bottom and side surfaces of the first recessed portion, and is in contact with the third insulating layer in the first opening portion. The fourth insulating layer is positioned further inside the first opening portion than the oxide semiconductor layer. The fourth conductive layer is positioned further inside the first opening portion than the fourth insulating layer.

[0086] In the transistor of one embodiment of the present invention, the first recessed portion is provided in the first conductive layer. Therefore, compared with the case where the first recessed portion is not provided, the heights of the bottom surfaces of the fourth insulating layer and the fourth conductive layer in the first opening portion can be made low. Consequently, an electric field of a gate is easily applied to the oxide semiconductor layer, resulting in favorable electrical characteristics of the transistor. Here, the heights of the surfaces can be determined, for example, using a formation surface of the transistor as a reference.

[0087] In a cross-sectional view, the oxide semiconductor layer included in the transistor of one embodiment of the present invention includes a region that overlaps with the second conductive layer with the third insulating layer therebetween, and overlaps with the fourth conductive layer with the fourth insulating layer therebetween. One of the second conductive layer and the fourth conductive layer serves as a gate, and the other serves as a back gate. When the transistor includes the back gate, the threshold voltage can be easily controlled, and a change in the threshold voltage can be prevented, so that the electrical characteristics and reliability of the transistor can be improved.

[0088] A high capacitance generated between a gate line and the source electrode or the drain electrode could slow down the operation of the transistor and degrade the frequency characteristics of a circuit including the transistor.

[0089] In view of the above, in the transistor of one embodiment of the present invention, the parasitic capacitance generated between the third conductive layer and the fourth conductive layer is preferably reduced. In this case, high-speed operation of the transistor can be achieved. A semiconductor device with advantageous electrical characteristics can also be provided.

[0090] For example, the semiconductor device of one embodiment of the present invention preferably further comprises a fifth insulating layer. In this case, it is preferable that the fourth insulating layer covers the top and side surfaces of the oxide semiconductor layer over the second insulating layer, that the fifth insulating layer is positioned over the fourth insulating layer and includes a second opening portion in a position overlapping with the first opening portion, and that the fourth conductive layer includes a portion overlapping with the oxide semiconductor layer in the first opening portion with the fourth insulating layer interposed therebetween, and a portion positioned in the second opening portion.Alternatively, it is preferable that the fifth insulating layer is positioned over the second insulating layer, covers the top and side surfaces of the oxide semiconductor layer over the second insulating layer, and includes the second opening portion in a position overlapping with the first opening portion. It is preferable that the fourth insulating layer includes a portion positioned in the second opening portion, and the fourth conductive layer is positioned further inside the second opening portion than the fourth insulating layer.

[0091] The fourth conductive layer includes a portion overlapping the oxide semiconductor layer in the first opening portion with the fourth insulating layer therebetween, and a portion positioned in the second opening portion. In this case, a gate line is placed over the fifth insulating layer, so that the physical distance between the third conductive layer and the gate line can be increased. Therefore, the parasitic capacitance generated between the third conductive layer and the gate line can be reduced. Note that a part of the fourth conductive layer (a portion positioned over the fifth insulating layer) may serve as a gate line, and another gate line may be provided separately from the fourth conductive layer over the fifth insulating layer.

[0092] Alternatively, in the transistor of one embodiment of the present invention, the parasitic capacitance generated between the third conductive layer and the gate line is preferably reduced. In this case, high-speed operation of the transistor can be achieved. A semiconductor device with advantageous electrical properties can also be provided.

[0093] For example, the semiconductor device of one embodiment of the present invention preferably includes a fifth conductive layer and a sixth insulating layer in addition to the oxide semiconductor layer, the first to fourth conductive layers, and the first to fourth insulating layers described above. In this case, it is preferable that the sixth insulating layer is positioned over the fourth insulating layer and includes the second opening portion reaching the fourth conductive layer in a position overlapping with the first opening portion, and that the fifth conductive layer is in contact with the fourth conductive layer in the second opening portion.

[0094] The fifth conductive layer serves as the gate line. Because the fifth conductive layer is placed above the sixth insulating layer, the physical distance between the third conductive layer and the gate line can be increased. Therefore, the parasitic capacitance generated between the third conductive layer and the gate line can be reduced.

[0095] It should be noted that a groove (slot) may be provided instead of the opening portion.

[0096] In the transistor of one embodiment of the present invention, the source electrode and the drain electrode are positioned at different heights, so that a current flows in the semiconductor layer in the height direction. In other words, the channel longitudinal direction includes a height (vertical) component, so the transistor of one embodiment of the present invention can also be referred to as a vertical field-effect transistor (VFET), vertical transistor, vertical-channel transistor, or the like.

[0097] In the transistor of one embodiment of the present invention, the source electrode, the semiconductor layer, and the drain electrode can be provided so as to overlap each other. Therefore, the area occupied by the transistor can be significantly smaller than that of a so-called planar transistor in which a planar semiconductor layer is provided.

[0098] The channel length of the transistor of one embodiment of the present invention can be controlled by the thicknesses of the first insulating layer, the second conductive layer, the second insulating layer, and the like. Therefore, a transistor with a very small channel length, which is difficult to achieve in a planar transistor, can be achieved. Consequently, a transistor with a small occupied area and high forward current can be provided.

[0099] When a transistor has a short channel length, the transistor is likely to exhibit normally-on behavior due to the influence of the so-called short-channel effect (SCE). In contrast, as described above, the transistor of one embodiment of the present invention includes a backgate. Therefore, by controlling the threshold voltage, a normally-off transistor is easily achieved. This means that even when miniaturized, the transistor of one embodiment of the present invention can exhibit high on-state current, normally-off characteristics, and high reliability.

[0100] The transistor containing an oxide semiconductor has a low off-state current, thus enabling long-term retention of stored contents when used for a memory device, for example. In other words, in such a memory device, a refresh operation is unnecessary or the refresh operation frequency is extremely low, resulting in sufficiently reduced power consumption. When the transistor of one embodiment of the present invention is used for a memory device, the memory device can be highly integrated, and the power consumption of the memory device can be reduced. <Strukturbeispiel 1 einer Halbleitervorrichtung>

[0101] A structure of the semiconductor device of an embodiment of the present invention will be described with reference to Fig. 2A1 to Fig. 2E and Fig. 3 described. [Transistor 200]

[0102] Fig. 2A1 is a plan view of a semiconductor device including a transistor 200. Fig. 2A2 is a plan view illustrating an example in which a plurality of transistors 200 are arranged. Fig. 2B and Fig. 3 are each a cross-sectional view along the dash-dotted line A1-A2 in Fig. 2A. Fig. 3 corresponds to an example of an enlarged view of Fig. 2B and shows further details of the structural example of each layer. Fig. Figure 2C is a cross-sectional view along the dotted line A3-A4 in Fig. 2A. Fig. 2D is a cross-sectional view along the dotted line A5-A6 in Fig. 2B and Fig. 2C. Fig. 2D can also be viewed as a cross-sectional view along an XY plane including an insulating layer 280a. Fig. 2E is a cross-sectional view along the dashed line A7-A8 in Fig. 2B and Fig. 2C. Fig. Figure 2E can also be viewed as a cross-sectional view along the XY plane, including a conductive layer 255. It should be noted that for simplicity, some components in the plan view are shown in Fig. 2A1 are not shown. Some components are also omitted in some cases in the following plan views.

[0103] The Fig. 2A1, Fig. 2B to Fig. 2E and Fig. The semiconductor device shown in Figure 3 includes an insulating layer 210 over a substrate (not shown), the transistor 200 over the insulating layer 210, the insulating layer 280a over the insulating layer 210, and an insulating layer 280b over the insulating layer 280a. The insulating layer 210, the insulating layer 280a, and the insulating layer 280b serve as interlayer films.

[0104] The transistor 200 includes a conductive layer 220a, a conductive layer 220b over the conductive layer 220a, the conductive layer 255 over the insulating layer 280a, a conductive layer 240a over the insulating layer 280b, a conductive layer 240b over the conductive layer 240a, an insulating layer 235, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, a conductive layer 265a over the insulating layer 250, and a conductive layer 265b over the conductive layer 265a.

[0105] Hereinafter, the conductive layer 220a and the conductive layer 220b are collectively referred to as the conductive layer 220 in some cases. Furthermore, the conductive layer 240a and the conductive layer 240b are collectively referred to as the conductive layer 240 in some cases. Furthermore, the conductive layer 265a and the conductive layer 265b are collectively referred to as the conductive layer 265 in some cases.

[0106] In the transistor 200, the oxide semiconductor layer 230 serves as a semiconductor layer, the conductive layer 265 serves as a first gate electrode, the insulating layer 250 serves as a first gate insulating layer, the conductive layer 220 serves as one of a source electrode and a drain electrode, the conductive layer 240 serves as the other of the source electrode and the drain electrode, the conductive layer 255 serves as a second gate electrode, and the insulating layer 235 serves as a second gate insulating layer. The conductive layer 265 serves as a gate line. As shown in Fig. 2A2, the conductive layer 240 and the conductive layer 255 may each serve as a line.

[0107] Conductive layer 265 preferably serves as the gate electrode, and conductive layer 255 preferably serves as the backgate electrode. In this case, insulating layer 250 serves as the gate insulating layer, and insulating layer 235 serves as the backgate insulating layer. Note that conductive layer 265 may serve as the backgate electrode, and conductive layer 255 may serve as the gate electrode.

[0108] The oxide semiconductor layer 230 includes a region that overlaps with the conductive layer 255 with the insulating layer 235 therebetween, and overlaps with the conductive layer 265a with the insulating layer 250 therebetween. At least a portion of the region serves as a channel formation region of the transistor 200. One of a region of the oxide semiconductor layer 230 that is in contact with the conductive layer 220 and a region of the oxide semiconductor layer 230 that is in contact with the conductive layer 240 serves as a source region, and the other serves as a drain region. That is, the channel formation region is located between the source region and the drain region.

[0109] As in Fig. 2B and Fig. 2C, an opening portion 290 reaching the conductive layer 220 is provided in the insulating layer 280a, the conductive layer 255, the insulating layer 280b, the conductive layer 240a, and the conductive layer 240b.

[0110] The conductive layer 220 includes the conductive layer 220a and the conductive layer 220b above the conductive layer 220a, and a recessed portion is provided in the conductive layer 220b. In other words, the conductive layer 220 includes a recessed portion, the bottom surface of the recessed portion corresponds to the bottom surface of the recessed portion of the conductive layer 220b, and the side surface of the recessed portion corresponds to the side surface of the recessed portion of the conductive layer 220b. Specifically, the conductive layer 220b includes a first recessed portion and a second recessed portion positioned further outward than the first recessed portion. The depth of the first recessed portion is greater than that of the second recessed portion.The second recessed portion is provided in the conductive layer 220b when forming the opening portion 290, and then the first recessed portion is provided in the conductive layer 220b when processing the insulating layer 235. Therefore, in . Fig. 2B and the like, the side surface of the first recessed portion is aligned with a surface of the insulating layer 235 on the oxide semiconductor layer 230 side, and the side surface of the second recessed portion is aligned with surfaces of the insulating layer 280a and the like on the opening portion 290 side. Hereinafter, the first recessed portion and the second recessed portion are collectively referred to as a recessed portion in some cases.

[0111] The opening portion 290 overlaps with the recessed portion of the conductive layer 220b. Here, the bottom of the opening portion 290 includes the bottom surface of the recessed portion of the conductive layer 220b, and the side wall of the opening portion 290 includes the side surface of the recessed portion of the conductive layer 220b, the side surface of the insulating layer 280a, the side surface of the conductive layer 255, the side surface of the insulating layer 280b, the side surface of the conductive layer 240a, and the side surface of the conductive layer 240b.

[0112] The opening portion 290 includes an opening portion included in the insulating layer 280a, an opening portion included in the conductive layer 255, an opening portion included in the conductive layer 280b, an opening portion included in the conductive layer 240a, and an opening portion included in the conductive layer 240b.In other words, the opening portion in a region where the insulating layer 280a overlaps with the conductive layer 220a is one part of the opening portion 290, the opening portion in a region where the conductive layer 255 overlaps with the conductive layer 220a is another part of the opening portion 290, the opening portion in a region where the insulating layer 280b overlaps with the conductive layer 220a is another part of the opening portion 290, the opening portion in a region where the conductive layer 240a overlaps with the conductive layer 220a is another part of the opening portion 290, and the opening portion in a region where the conductive layer 240b overlaps with the conductive layer 220a is another part of the opening portion 290. The shape and size of the opening section 290 in the plan view may vary depending on the layer.When the opening portion 290 has a circular top shape, the opening portions in the layers may be arranged concentrically, but not necessarily.

[0113] At least some of the components of transistor 200 are placed in opening portion 290. Specifically, insulating layer 235, oxide semiconductor layer 230, insulating layer 250, and conductive layer 265 are positioned such that they are at least partially positioned in opening portion 290.

[0114] The insulating layer 235 includes at least a region positioned between the oxide semiconductor layer 230 and the conductive layer 255. The oxide semiconductor layer 230 is in contact with the insulating layer 235 in the opening portion 290.

[0115] In Fig. 2B and the like, the insulating layer 235 is in contact with the bottom and side surfaces of the recessed portion (specifically, the second recessed portion) of the conductive layer 220, and is in contact with the side surfaces of the insulating layer 280a, the conductive layer 255, the insulating layer 280b, the conductive layer 240a, and the conductive layer 240b in the opening portion 290. The oxide semiconductor layer 230 is in contact with the bottom and side surfaces of the recessed portion (specifically, the first recessed portion) of the conductive layer 220, the insulating layer 235, and the top surface of the conductive layer 240b. The insulating layer 250 is positioned further inside the opening portion 290 than the oxide semiconductor layer 230, and the conductive layer 265a is positioned further inside the opening portion 290 than the insulating layer 250.

[0116] The insulating layer 235 is provided along at least a portion of the sidewall of the opening portion 290. Portions of the oxide semiconductor layer 230 and the insulating layer 250 placed in the opening portion 290 reflect the shape of the opening portion 290. Specifically, the oxide semiconductor layer 230 is provided to cover the bottom and sidewall of the opening portion 290, and the insulating layer 250 is provided to cover the oxide semiconductor layer 230. Then, the conductive layer 265a is provided to fill at least a portion of a recessed portion of the insulating layer 250 that reflects the shape of the opening portion 290.

[0117] In the transistor of one embodiment of the present invention, at least one layer included in the conductive layer 265 is provided in the opening portion 290. In the case where the conductive layer 265 has a multi-layer structure, it becomes more difficult to place all the layers included in the conductive layer 265 in the opening portion 290 as the diameter of the opening portion 290 becomes smaller with the progress of miniaturization of the transistor 200. Fig. 2B and Fig. 2C illustrates an example in which the conductive layer 265 has a two-layer structure, only the conductive layer 265a is provided in the opening portion 290, and the conductive layer 265b is provided over the conductive layer 265a in a position overlapping with the opening portion 290. Note that in some cases, both the conductive layer 265a and the conductive layer 265b are positioned in the opening portion 290 depending on the diameter of the opening portion 290, the thickness of the conductive layer 265a, and the like.

[0118] When the conductive layer 220b includes the recessed portion in a position overlapping with the opening portion 290, unlike the case where the recessed portion is not provided, the heights of the bottom surfaces of the insulating layer 250 and the conductive layer 265a in the opening portion 290 may be lower than the height of the top surface of the conductive layer 220b in contact with the insulating layer 280a, using the top surface of the insulating layer 210 as a reference. Here, the heights of the surfaces may be determined using the formation surface of the transistor as a reference. Here, the top surface of the insulating layer 210 is used as a reference. The surface used as a reference is not limited to the formation surface of the transistor. For example, the top surface of the substrate over which the transistor or semiconductor device is provided may be used as a reference.

[0119] As in Fig. 3, a shortest distance Tc from the top surface of the insulating layer 210 to the top surface of the conductive layer 220b in contact with the insulating layer 280a is preferably longer than a shortest distance Ta from the top surface of the insulating layer 210 to the bottom surface of the insulating layer 250. Accordingly, the contact area between the side surface of the conductive layer 220b and the oxide semiconductor layer 230 can be increased, so that the contact resistance therebetween can be reduced. This can prevent a decrease in the on-state current of the transistor 200 due to the contact resistance between the conductive layer 220b and the oxide semiconductor layer 230. Note that the shortest distance Ta can be determined based on the bottom surface of the insulating layer 250 in the opening portion 290.

[0120] As in Fig. 3, the shortest distance Tc is preferably longer than or equal to a shortest distance Tb from the top surface of the insulating layer 210 to the bottom surface of the conductive layer 265a, more preferably longer than the shortest distance Tb. Therefore, a gate electric field is easily applied to the channel formation region of the oxide semiconductor layer 230, so that the electrical characteristics of the transistor 200 can be improved. Furthermore, a gate electric field is easily applied to a region of the oxide semiconductor layer 230 that is in contact with the conductive layer 220b, so that the on-state current of the transistor 200 can be increased. When the conductive layer 220 or the conductive layer 240 is used as a drain electrode, the electrical characteristics of the transistor 200 can be improved. Note that the shortest distance Tb can be determined based on the bottom surface of the conductive layer 265a in the opening portion 290.

[0121] The oxide semiconductor layer 230 is in contact with the bottom and side surfaces of the recessed portion of the conductive layer 220b and the top surface of the conductive layer 240b. When the conductive layer 220b includes a recessed portion, the contact area between the oxide semiconductor layer 230 and the conductive layer 220b can be increased. Therefore, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220b can be reduced.

[0122] A conductive material containing oxygen is preferably used for the conductive layer 220b. Accordingly, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220b can be reduced.

[0123] In the case where the conductive layer 220 and the conductive layer 240 each have a multilayer structure, a conductive material containing oxygen is preferably used for a layer having the largest contact area with the oxide semiconductor layer 230 in the multilayer structure, in which case the contact resistance with the oxide semiconductor layer 230 can be reduced. Therefore, for example, a conductive material containing oxygen is preferably used for the conductive layer 220b and the conductive layer 240b.

[0124] Alternatively, in the case where the conductive layer 220 and the conductive layer 240 each have a multilayer structure, using a conductive material containing oxygen for the layer closest to the channel formation region in the multilayer structure can reduce the contact resistance with the oxide semiconductor layer 230, enabling a short current path between the source and drain, and thus increasing the on-state current of the transistor. Therefore, it is preferable to use a conductive material containing oxygen, for example, for the conductive layer 220b and the conductive layer 240a.

[0125] As a conductive material containing oxygen, a metal oxide with conductivity (also called oxide conductor) is preferably used.

[0126] Fig. 2B illustrates a structure in which an end portion of the conductive layer 240a, an end portion of the conductive layer 240b, and an end portion of the oxide semiconductor layer 230 outside the opening portion 290 are aligned with each other. As in an example of a manufacturing method described below, the conductive layer 240a, the conductive layer 240b, and the oxide semiconductor layer 230 can be formed by processing using the same mask. This is preferable because the number of masks required to manufacture the semiconductor device can be reduced. Note that the present invention is not limited to this. For example, in the X direction or the Y direction, one of the end portion of the oxide semiconductor layer 230, the end portion of the conductive layer 240a, and the end portion of the conductive layer 240b may be positioned further inward or outward than the others.

[0127] The conductive layer 240 includes the opening portion 290 in a region overlapping with the conductive layer 220. The conductive layer 240 is preferably not positioned in the opening portion 290 included in the insulating layer 280b and the like. That is, the conductive layer 240 preferably does not include a region in the opening portion 290 that is in contact with the side surface of the insulating layer 280b. With such a structure, the opening portion 290 can be formed in the conductive layer 240, the insulating layer 280b, the conductive layer 255, and the insulating layer 280a all at once.Furthermore, when the side surfaces of the conductive layer 240, the insulating layer 280b, the conductive layer 255, and the insulating layer 280a are aligned with each other in the opening portion 290, the thickness distributions of the insulating layer 235, the oxide semiconductor layer 230, and the like provided in the opening portion 290 can be uniform. Furthermore, the insulating layer 235, the oxide semiconductor layer 230, and the like can be prevented from being divided by a step formed by, for example, the conductive layer 240 and the insulating layer 280b.

[0128] Although Fig. 2B and Fig. 2C illustrates the structure in which the side surface of the conductive layer 240 in the opening portion 290 and the side surface of the insulating layer 280b in the opening portion 290 are on the same plane (also referred to as aligned with each other or substantially aligned with each other), the present invention is not limited thereto. For example, the side surface of the conductive layer 240 in the opening portion 290 and the side surface of the insulating layer 280b in the opening portion 290 may not be continuous. The inclination of the side surface of the conductive layer 240 in the opening portion 290 and the inclination of the side surface of the insulating layer 280b in the opening portion 290 may be different from each other. For example, the taper angle of the side surface of the conductive layer 240 in the opening portion 290 is preferably smaller than that of the side surface of the insulating layer 280b in the opening portion 290.With such a structure, the coverage of the side surface of the conductive layer 240 with the oxide semiconductor layer 230 in the opening portion 290 is improved, so that defects such as voids can be reduced. In the case where the insulating layers 280a and 280b each have a multilayer structure, the inclinations of the side surfaces of the layers in the opening portion 290 may differ from each other. Similarly, in the case where the conductive layer 240 has a multilayer structure, the inclinations of the side surfaces of the layers in the opening portion 290 may differ from each other.

[0129] Transistor 200 includes a metal oxide serving as a semiconductor (also referred to as an oxide semiconductor) in oxide semiconductor layer 230, which includes a channel formation region. This means that transistor 200 can be considered an OS transistor.

[0130] If oxygen deficiencies (V o ) and impurities are present in a channel formation region of an oxide semiconductor in an OS transistor, the electrical characteristics of the OS transistor vary slightly, and its reliability may deteriorate. In some cases, hydrogen forms a defect in the vicinity of an oxygen vacancy, which is an oxygen vacancy into which hydrogen penetrates (hereinafter referred to as V in some cases). oH), which generates an electron serving as a charge carrier. Therefore, if the channel formation region of the oxide semiconductor includes oxygen vacancies, the OS transistor is likely to exhibit normal conduction. Therefore, the oxygen vacancies and impurities in the channel formation region of the oxide semiconductor are preferably reduced as much as possible. In other words, the oxide semiconductor preferably includes an i-type (intrinsic) or substantially i-type channel formation region with a low charge carrier concentration.

[0131] In contrast, it is preferred that the source region and drain region of the OS transistor have more oxygen vacancies, more V oH or a higher concentration of an impurity, such as hydrogen, nitrogen, or a metal element, than the channel formation region and are therefore low-resistance regions with high carrier concentrations. In other words, the source and drain regions of the OS transistor are preferably n-type regions, which have higher carrier concentrations and lower resistances than the channel formation region.

[0132] As described above, the oxide semiconductor layer 230 is provided in the opening portion 290. The transistor 200 has a structure in which one of the source electrode and the drain electrode (here, the conductive layer 220) is located at a lower position, and the other of the source electrode and the drain electrode (here, the conductive layer 240) is located at an upper position, and therefore, a current flows in the vertical direction. That is, a channel is formed along the side surface of the opening portion 290.

[0133] The positional relationship of the layers in the opening portion 290 is determined by Fig. 2D and Fig. 2E. The insulating layer 235 is in contact with the outside of the oxide semiconductor layer 230. The conductive layer 255 surrounds the entire periphery of the oxide semiconductor layer 230, with the insulating layer 235 interposed therebetween. The insulating layer 250 is in contact with the outside of the conductive layer 265a. The oxide semiconductor layer 230 surrounds the entire periphery of the conductive layer 265a, with the insulating layer 250 interposed therebetween. Therefore, the channel formation region of the transistor 200 can be formed in a region of the oxide semiconductor layer 230 along its entire surface on the insulating layer 235 side in the opening portion 290 (the entire region in contact with the insulating layer 235). Note that Fig. 2E can be viewed as a cross-sectional view along the XY plane including the channel formation region of the oxide semiconductor layer 230.

[0134] The channel length of transistor 200 can be considered the distance between the source region and the drain region. That is, the channel length of transistor 200 is determined by the thicknesses of insulating layer 280a, conductive layer 255, insulating layer 280b, and the like above conductive layer 220.

[0135] Since the transistor 200 includes the conductive layer 255 serving as a backgate, the threshold voltage of the transistor 200 can be controlled by a potential supplied to the conductive layer 255. In this case, a portion of the oxide semiconductor layer 230 that overlaps with the conductive layer 255, with the insulating layer 235 therebetween, is most likely to be influenced by the conductive layer 255. Therefore, Fig. 3 the oxide semiconductor layer 230 is divided into three regions: a region 230n + , an area 230n -and a region 230i. Region 230i corresponds to the portion of oxide semiconductor layer 230 that overlaps with conductive layer 255, with insulating layer 235 interposed therebetween.

[0136] The area 230n + is formed in a region of the oxide semiconductor layer 230 that is in contact with the conductive layer 240b or the conductive layer 220b and its surroundings and may be referred to as a source region or a drain region. The source and drain regions are n-type (low-resistance) regions that have a higher carrier concentration than the channel formation region.

[0137] Region 230i is a region of the oxide semiconductor layer 230 that overlaps with the conductive layer 255 with the insulating layer 235 therebetween, and overlaps with the conductive layer 265a with the insulating layer 250 therebetween, and may be referred to as a channel formation region. The channel formation region is preferably controlled to an i-type (intrinsic) or substantially i-type region with a potential supplied to the conductive layer 255.

[0138] The area 230n - is preferably an area that has a higher resistance than the area 230n + and has a lower resistance than the 230i region. If there is a high-resistance region between the 230i region and the 230n region + the forward current of transistor 200 could be reduced. If the area 230n -has a relatively low resistance, in some cases the forward current of the transistor 200 can be increased. It should be noted that the region 230n - in some cases also serves as a channel formation area.

[0139] As described above, in the case where the channel length of the transistor 200 is regarded as the distance between the source region and the drain region, the channel length of the transistor 200 can be referred to as length L1. On the other hand, since the region 230n -has a lower resistance than region 230i, the channel formation region of transistor 200 can be considered region 230i, which is controlled by conductive layer 255 to become a high-resistance region. In this case, the channel length of transistor 200 can be considered length L0 of region 230i, which is shorter than length L1. Length L0 can also be referred to as the effective channel length of transistor 200.

[0140] If the range 230n -has a low resistance and the effective channel length of the transistor is small, the transistor is likely to exhibit normally-on behavior. On the other hand, the transistor of one embodiment of the present invention includes a backgate. When a potential lower than or equal to a source potential or a potential lower than or equal to 0 V (preferably a negative potential) is applied to the backgate, the threshold voltage of the transistor can be positively shifted, and the transistor can exhibit normally-off behavior. Consequently, the transistor of one embodiment of the present invention can exhibit both high forward current and normally-off characteristics.

[0141] Note that in the transistor of one embodiment of the present invention, one of the conductive layer 255 and the conductive layer 265 may be used as a gate, and the other may be used as a back gate. In the transistor of one embodiment of the present invention, in some cases, it is particularly appropriate to use the conductive layer 265 as a gate and the conductive layer 255 as a back gate. When the conductive layer 265, whose area facing the oxide semiconductor layer 230 is larger than that of the conductive layer 255, is used as a gate, an electric field of the gate is more effectively applied to the oxide semiconductor layer 230, and therefore, the electrical characteristics of the transistor can be improved in some cases.

[0142] In a planar transistor, the channel length is determined by the photolithography exposure limit. In one embodiment of the present invention, the channel length may be determined by the thicknesses of the insulating layer 280a and the insulating layer 280b. Therefore, the transistor 200 may have a very small channel length of less than or equal to the photolithography exposure limit (e.g., less than or equal to 60 nm, less than or equal to 50 nm, less than or equal to 40 nm, less than or equal to 30 nm, less than or equal to 20 nm, or less than or equal to 10 nm, and greater than or equal to 0.1 nm, greater than or equal to 1 nm, or greater than or equal to 5 nm). Accordingly, the transistor 200 may have higher forward current and higher frequency characteristics.

[0143] Furthermore, as described above, the channel formation region, the source region, and the drain region can be formed in the opening portion 290. Therefore, the area occupied by the transistor 200 can be reduced compared to a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. Therefore, the semiconductor device can be highly integrated. In the case where the semiconductor device of one embodiment of the present invention is used for a memory device, the storage capacity per unit area can be increased.

[0144] Fig. 2A2 illustrates an example in which a plurality of transistors 200 are arranged in a matrix. In particular, Fig. 2A2 shows an example in which 5 × 5 transistors are arranged in the X-direction and the Y-direction. As in Fig. 2A2, the transistor 200 is provided in a crossing portion of the conductive layer 265 extending in the X direction and the conductive layer 240 extending in the Y direction. As shown in Fig. 2A2, the opening portion 290 may have a diameter smaller than the widths of the short sides of the conductive layers 240, 255, and 265. Therefore, it can be said that the transistor 200 can be highly integrated and miniaturized.

[0145] As in Fig. As shown in FIG. 2D, the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 265a are provided concentrically. Therefore, the side surface of the conductive layer 265a provided at the center faces the side surface of the oxide semiconductor layer 230, with the insulating layer 250 interposed therebetween. That is, the entire circumference of the oxide semiconductor layer 230 in the plan view serves as a channel formation region. In this case, for example, the channel width of the transistor 200 is determined by the length of the circumference of the oxide semiconductor layer 230. In other words, the channel width of the transistor 200 is determined by the width of the opening portion 290 (the diameter in the case where the opening portion 290 is circular in the plan view). Fig. 2B to Fig. 2E each show a width D of the opening portion 290, and Fig. 2E shows a channel width W of the transistor 200. By increasing the width D of the opening portion 290, the channel width per unit area can be increased and the forward current can be increased.

[0146] Note that the width D of the opening portion 290 varies in the depth direction in some cases. Specifically, here, the shortest distance between two side surfaces of the conductive layer 255 on the opening portion 290 side in a cross-sectional view is used as the width D. In other words, the minimum width of the opening portion 290 in the conductive layer 255 is used as the width D of the opening portion 290. The width of the opening portion 290 at the highest position, the width of the opening portion 290 at the lowest position, or the width of the opening portion 290 at the midpoint therebetween in the conductive layer 255, or the average value of these three widths can be used as the width D.Although the example in which the width D is determined using the width of the opening portion 290 in the conductive layer 255 is described here, there is no particular limitation on the method for determining the width D. For example, the shortest distance between two side surfaces of the insulating layer 280a, the insulating layer 280b, the conductive layer 240a, or the conductive layer 240b on the opening portion 290 side can be used as the width D. Alternatively, the width of the opening portion 290 at the highest position, the width of the opening portion 290 at the lowest position, or the width of the opening portion 290 at the midpoint therebetween in the insulating layer 280a, the insulating layer 280b, the conductive layer 240a, or the conductive layer 240b, or the average value of these three widths can be used as the width D.

[0147] In the case where the opening portion 290 is formed by a photolithography process, the width D of the opening portion 290 is determined by the exposure limit of the photolithography. Furthermore, the width D of the opening portion 290 is determined by the thicknesses of the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 265a provided in the opening portion 290. The width D of the opening portion 290 is preferably, for example, greater than or equal to 5 nm, greater than or equal to 10 nm, or greater than or equal to 20 nm, and less than or equal to 100 nm, less than or equal to 60 nm, less than or equal to 50 nm, less than or equal to 40 nm, or less than or equal to 30 nm. In the case where the opening portion 290 is circular in the plan view, the width D of the opening portion 290 corresponds to the diameter of the opening portion 290, and the channel width W may be “D × π”.

[0148] The channel length L of the transistor 200 is preferably less than at least the channel width W of the transistor 200. The channel length L of the transistor 200 is preferably greater than or equal to 0.1 times and less than or equal to 0.99 times, more preferably greater than or equal to 0.5 times and less than or equal to 0.8 times the channel width W of the transistor 200. This structure enables the transistor to have advantageous electrical properties and high reliability.

[0149] As described above, when the opening portion 290 is formed to be substantially circular in plan view, the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 265a are formed concentrically. This makes each of the distance between the conductive layer 255 and the oxide semiconductor layer 230 and the distance between the conductive layer 265a and the oxide semiconductor layer 230 substantially uniform, so that a gate electric field can be substantially uniformly applied to the oxide semiconductor layer 230.

[0150] Although this embodiment describes the example in which the opening portion 290 has a circular shape in plan view, the present invention is not limited thereto. The opening portion 290 in plan view may, for example, have a circular shape, a substantially circular shape such as an elliptical shape, a polygonal shape such as a triangular shape, a quadrilateral shape (including a rectangular shape, a rhombic shape, and a square), a pentagonal shape, or a star polygonal shape, or any of these polygonal shapes whose corners are rounded. Note that the polygonal shape may be a concave polygonal shape (a polygonal shape at least one of whose interior angles is greater than 180°) or a convex polygonal shape (a polygonal shape all of whose interior angles are less than or equal to 180°). As shown in Fig. 2A1 and the like, the opening portion 290 preferably has a circular shape in plan view. When the opening portion has a circular shape in plan view, the processing accuracy in forming the opening portions can be high, thereby allowing the opening portions to be formed to have very small sizes. Note that in this description and the like, a circular shape is not necessarily a perfect circular shape. <Materialien für eine Halbleitervorrichtung>

[0151] Materials that can be used for the semiconductor device of this embodiment will be described below. Note that the layers included in the semiconductor device of this embodiment may each have a single-layer structure or a multi-layer structure. Fig. 2B and Fig. 2C illustrates an example in which the conductive layer 220a has a single-layer structure. Fig. 3 illustrates an example in which the conductive layer 220a has a multilayer structure. [Oxide semiconductor layer 230]

[0152] As described above, the oxide semiconductor layer 230 includes the channel formation region. The oxide semiconductor layer 230 further includes the source region and the drain region. The source and drain regions are n-type (low-resistance) regions that have a higher carrier concentration than the channel formation region. The oxide semiconductor layer 230 may have a multilayer structure composed of two or more layers.

[0153] There is no particular limitation on the crystallinity of the semiconductor material used for the oxide semiconductor layer 230, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor with crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor partially including crystal regions) can be used. Preferably, a single-crystal semiconductor or a semiconductor with crystallinity is used, in which case, deterioration of the transistor characteristics can be prevented.

[0154] The band gap of the metal oxide serving as a semiconductor is preferably greater than or equal to 2.0 eV, more preferably greater than or equal to 2.5 eV. Using such a wide-band gap metal oxide can reduce the off-state current of the transistor. The off-state current of the OS transistor is small, so the power consumption of the semiconductor device can be sufficiently reduced. The OS transistor has high frequency characteristics, enabling the semiconductor device to operate at high speed.

[0155] For the oxide semiconductor layer that can be used as the semiconductor layer of the transistor of one embodiment of the present invention, reference can be made to the description of Embodiment 3. The details will not be described here.

[0156] Note that a transistor containing another semiconductor material in a channel formation region can also be used for the semiconductor device of this embodiment. Examples of another semiconductor material include a single-element semiconductor and a compound semiconductor. Examples of the single-element semiconductor include silicon and germanium. Examples of the compound semiconductor include gallium arsenide and silicon germanium. Other examples of the compound semiconductor include an organic semiconductor and a nitride semiconductor. Note that the oxide semiconductor described above is also a type of compound semiconductor. These semiconductor materials may contain an impurity as a dopant.

[0157] Examples of silicon that can be used as a semiconductor material for a transistor include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS).

[0158] Alternatively, a semiconductor layer of a transistor may include a layered material serving as a semiconductor. The layered material generally refers to a group of materials having a layered crystal structure. In the layered crystal structure, layers formed by a covalent bond or an ionic bond are stacked one on top of the other with a bond, such as the van der Waals bond, which is weaker than a covalent bond or an ionic bond. The layered material has high electrical conductivity in a unit layer, that is, high two-dimensional electrical conductivity. When a material serving as a semiconductor and having high two-dimensional electrical conductivity is used for a channel formation region, the transistor can have a high on-state current.

[0159] Examples of layered materials include graphene, silicene, and chalcogenide. Chalcogenide is a compound containing chalcogen (a group 16 element). Examples of chalcogenide include a transition metal chalcogenide and a chalcogenide of Group 13 elements. Specific examples of the transition metal chalcogenide that can be used for a semiconductor layer of a transistor include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2). [Insulating layer]

[0160] An inorganic insulating film is preferably used for each of the insulating layers (insulating layer 210, insulating layer 250, insulating layer 235, insulating layer 280a, insulating layer 280b, and the like) included in the semiconductor device. Examples of the inorganic insulating film include an insulating oxide film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of the insulating oxide film include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of the insulating nitride film include a silicon nitride film and an aluminum nitride film.Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An organic insulating film can also be used for the insulating layer included in the semiconductor device.

[0161] With miniaturization and higher integration of a transistor, for example, a problem such as leakage current generation may arise due to a thin gate insulating layer. If a high-k material is used for the gate insulating layer, the voltage at the time of transistor operation can be reduced while maintaining the physical thickness. Furthermore, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. In contrast, if a low-dielectric constant material is used for an insulating layer serving as an interlayer film, the parasitic capacitance generated between lines can be reduced. Therefore, a material is preferably selected depending on the function of an insulating layer. Note that a low-dielectric constant material is a material with high dielectric strength.

[0162] Examples of a high dielectric constant material (a high-k material) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0163] Examples of low-dielectric-constant materials include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (e.g., nylon and aramid), polyimide, polycarbonate, and acrylic resin. Other examples of low-dielectric-constant inorganic insulating materials include fluorine-added silicon oxide, carbon-added silicon oxide, and carbon-nitrogen-added silicon oxide. Another example is porous silicon oxide. Note that these silicon oxides may contain nitrogen.

[0164] A material capable of exhibiting ferroelectricity can be used for the insulating layer included in the semiconductor device. Examples of the material capable of exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrOx (X is a real number greater than 0). Examples of the material capable of exhibiting ferroelectricity also include a material in which an element J1 (here, the element J1 is one or more of zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, and the like) is added to hafnium oxide. Here, the atomic ratio of hafnium to the element J1 can be appropriately adjusted; for example, the atomic ratio of hafnium to the element J1 can be 1:1 or close to it.Examples of the material capable of exhibiting ferroelectricity also include a material in which a J2 element (here, the J2 element is one or more of hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, and the like) is added to zirconium oxide. The atomic ratio of zirconium to the J2 element can be appropriately adjusted; for example, the atomic ratio of zirconium to the J2 element can be 1:1 or close to it. As a material capable of exhibiting ferroelectricity, a piezoelectric ceramic having a perovskite structure, such as lead titanate (PbTiOx), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, can be used.

[0165] Examples of the material capable of exhibiting ferroelectricity also include a metal nitride containing an M1 element, an M2 element, and nitrogen. Here, the M1 element is one or more of aluminum, gallium, indium, and the like. The M2 element is one or more of boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, and the like. Note that the atomic ratio of the M1 element to the M2 element can be appropriately adjusted. A metal oxide containing the M1 element and nitrogen exhibits ferroelectricity in some cases even if the metal oxide does not contain the M2 element. Examples of the material capable of exhibiting ferroelectricity also include the above metal nitride to which an M3 element is added. Note that the M3 element is one or more of magnesium, calcium, strontium, zinc, cadmium, and the like.The atomic ratio between element M1, element M2 and element M3 can be adjusted appropriately.

[0166] Examples of the material that can exhibit ferroelectricity also include perovskite-type oxynitrides, such as SrTaO2N and BaTaO2N, as well as GaFeO3 with a κ-alumina-type structure.

[0167] Although metal oxides and metal nitrides have been described above as examples, an embodiment of the present invention is not limited thereto. For example, a metal oxynitride in which nitrogen is added to one of the above metal oxides, a metal nitride oxide in which oxygen is added to one of the above metal nitrides, or the like can be used.

[0168] As a material capable of exhibiting ferroelectricity, for example, a mixture or compound containing a plurality of materials selected from the above-mentioned materials can be used. Alternatively, an insulating layer may have a multilayer structure composed of a plurality of materials selected from the above-mentioned materials. Since the above-mentioned materials and the like may change their crystal structures (properties) according to various processes and the like as well as film formation conditions, a material capable of exhibiting ferroelectricity is referred to in this specification and the like not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0169] A metal oxide containing hafnium and / or zirconium is preferred because the metal oxide can exhibit ferroelectricity even if it is a thin film of a few nanometers. A metal oxide containing hafnium and / or zirconium is preferred because the metal oxide can exhibit ferroelectricity even with a very small area. The use of a metal oxide containing hafnium and / or zirconium therefore enables miniaturization of the semiconductor device.

[0170] Note that in this specification and the like, the material capable of exhibiting ferroelectricity and processed into a layered form is sometimes referred to as a ferroelectric layer, metal oxide film, or metal nitride film. Furthermore, in this specification and the like, a device comprising such a ferroelectric layer, metal oxide film, or metal nitride film is sometimes referred to as a ferroelectric device.

[0171] It should be noted that ferroelectricity is exhibited by the dislocation of oxygen or nitrogen of a crystal contained in a ferroelectric layer due to an external electric field. Ferroelectricity is presumably exhibited depending on a crystal structure of a crystal contained in a ferroelectric layer. Therefore, for the insulating layer to exhibit ferroelectricity, the insulating layer must comprise a crystal. It is particularly preferable that the insulating layer comprise a crystal having an orthorhombic crystal structure, in which case ferroelectricity is exhibited. A crystal contained in the insulating layer may have one or more of a cubic, tetragonal, orthorhombic, monoclinic, and hexagonal crystal structure. Alternatively, the insulating layer may have an amorphous structure.In this case, the insulating layer may have a composite structure including an amorphous structure and a crystal structure.

[0172] Adding a Group 3 element (also called a IIIa element) in the periodic table to an oxide containing hafnium and / or zirconium increases the concentration of oxygen vacancies in the oxide and facilitates the formation of a crystal with an orthorhombic crystal structure. This is preferred because the proportion of the crystal with an orthorhombic crystal structure is increased and the amount of remanent polarization can be increased. On the other hand, excessive addition of the Group 3 element could reduce the crystallinity of the oxide and hinder the occurrence of ferroelectricity. Therefore, the percentage of the Group 3 element in the oxide containing hafnium and / or zirconium is preferably higher than or equal to 0.1 atomic% and lower than or equal to 10 atomic%, more preferably higher than or equal to 0.1 atomic% and lower than or equal to 5 atomic%, even more preferably higher than or equal to 0.1 atomic% and lower than or equal to 3 atomic%.Here, the percentage of the Group 3 element refers to the proportion of the number of atoms of the Group 3 element to the number of all atoms of the metal element contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, more preferably lanthanum and / or yttrium.

[0173] A transistor containing a metal oxide can exhibit stable electrical properties when enclosed by an insulating layer having a function of preventing the passage of impurities and oxygen. The insulating layer having a function of preventing the passage of impurities and oxygen can have, for example, a single-layer structure or a multi-layer structure of an insulating layer containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. As the material for the insulating layer having a function of preventing the passage of impurities and oxygen, a metal oxide such as, for example,Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide, or a metal nitride such as aluminum nitride, silicon nitride oxide or silicon nitride may be used.

[0174] As an insulating layer having a function of preventing the passage of oxygen and impurities such as water and hydrogen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide can be used. Other examples of the insulating layer having a function of preventing the passage of oxygen and impurities such as water and hydrogen include oxides containing aluminum and hafnium (hafnium aluminate). Other examples of the insulating layer having a function of preventing the passage of oxygen and impurities such as water and hydrogen include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.

[0175] Furthermore, an insulating layer in contact with an oxide semiconductor layer, such as a gate insulating layer, or an insulating layer provided in the vicinity of the oxide semiconductor layer, preferably includes a region containing oxygen (hereinafter referred to as excess oxygen in some cases) that is released by heating. For example, when an insulating layer having an excess oxygen region is in contact with an oxide semiconductor layer or is positioned in the vicinity of the oxide semiconductor layer, the number of oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of an insulating layer in which an excess oxygen region is easily formed include silicon oxide, silicon oxynitride, and porous silicon oxide.

[0176] The insulating layer 210 serves as an interlayer film and preferably has a low dielectric constant. Using a material with a low dielectric constant for the interlayer film can reduce the parasitic capacitance generated between lines. Silicon oxide and silicon oxynitride are thermally stable and thus suitable for the insulating layer 210.

[0177] The concentration of impurities such as water and hydrogen in the insulating layer 210 is preferably reduced. This can prevent impurities such as water and hydrogen from penetrating the channel formation region of the oxide semiconductor layer 230.

[0178] A hydrogen barrier insulating layer is preferably used as the insulating layer 210. If the insulating layer 210, which is provided outside the oxide semiconductor layer 230, has a hydrogen barrier property, hydrogen can be prevented from diffusing into the oxide semiconductor layer 230.

[0179] Examples of a hydrogen insulating barrier material include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0180] It should be noted that in this specification and the like, an insulating barrier layer refers to an insulating layer that has a barrier property. In addition, the barrier property refers to a property that does not easily allow diffusion of a target substance (also referred to as a property that does not easily allow passage of a target substance, a low-permeability property of a target substance, or a function of preventing diffusion of a target substance). It should be noted that hydrogen described as a target substance may include at least one of a hydrogen atom, a hydrogen molecule, substances bonded to hydrogen, such as a hydrogen molecule and OH. -, and the like. Unless otherwise specified, an impurity described as a target substance refers to an impurity in a channel formation region or a semiconductor layer, and refers, for example, to at least one of a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (e.g., N2O, NO, or NO2), and a copper atom. Oxygen described as a target substance refers, for example, to at least one of an oxygen atom, an oxygen molecule, and the like.

[0181] For example, a silicon nitride film is preferably used for the insulating layer 210.

[0182] The insulating layer 280a and the insulating layer 280b each preferably include the above-described hydrogen barrier insulating layer. The insulating layer 280a and the insulating layer 280b are provided to surround the oxide semiconductor layer 230. If the insulating layer 280a and the insulating layer 280b, which are provided outside the oxide semiconductor layer 230, have a hydrogen barrier property, hydrogen can be prevented from diffusing into the oxide semiconductor layer 230. For example, the insulating layer 280a and the insulating layer 280b each preferably include an aluminum oxide film and / or a silicon nitride film.

[0183] It should be noted that silicon nitride also has a barrier property against oxygen. Therefore, the use of silicon nitride for the insulating layer 280a and the insulating layer 280b can prevent the extraction of oxygen from the oxide semiconductor layer 230 and can therefore prevent the formation of an excessive amount of oxygen vacancies in the oxide semiconductor layer 230.

[0184] Furthermore, when silicon nitride is used for the insulating layer 280a and the insulating layer 280b, excess oxygen can be prevented from being supplied to the oxide semiconductor layer 230. Therefore, the channel formation region of the oxide semiconductor layer 230 can be prevented from containing excess oxygen, thereby improving the reliability of the transistor 200.

[0185] The insulating layer 280a and the insulating layer 280b each preferably comprise any one of an insulating oxide film, an oxynitride film, and an insulating layer including an excess oxygen region, which have been described above.

[0186] For example, the insulating layer including a region with excess oxygen may be formed by deposition using a sputtering method in an oxygen-containing atmosphere. Since no hydrogen-containing molecule is used as a deposition gas in the sputtering method, the hydrogen concentration in the insulating layer 280a and the insulating layer 280b can be reduced. When at least one layer in each of the insulating layers 280a and 280b is formed in this way, oxygen can be supplied from the insulating layer 280a and the insulating layer 280b to the channel formation region of the oxide semiconductor layer 230, so that oxygen vacancies and V O H can be reduced therein.

[0187] The concentration of impurities such as water and hydrogen in the insulating layer 280a and the insulating layer 280b is preferably reduced. This can prevent impurities such as water and hydrogen from penetrating the channel formation region of the oxide semiconductor layer 230.

[0188] Since the thicknesses of the insulating layers 280a and 280b above the conductive layer 220 affect the channel length of the transistor 200, the thicknesses of the insulating layers 280a and 280b are appropriately adjusted depending on a designed channel length of the transistor 200.

[0189] For example, a single-layer structure of a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film is preferably used for each of the insulating layers 280a and 280b. Alternatively, for example, a three-layer structure in which a silicon nitride film, a silicon oxide film, and a silicon nitride film are stacked in this order is preferably used for each of the insulating layers 280a and 280b. For example, a three-layer structure in which an aluminum oxide film, a silicon oxide film, and an aluminum oxide film are stacked in this order is preferably used for each of the insulating layers 280a and 280b.

[0190] The insulating layer 250 preferably has a function of capturing and fixing hydrogen. In this case, the hydrogen concentration in the oxide semiconductor layer 230 (especially the hydrogen concentration in the channel formation region of the transistor) can be reduced. Accordingly, V O H in the channel formation region, so that the channel formation region may be an i-type region or a substantially i-type region.

[0191] Examples of an insulating layer material having a hydrogen trapping or fixing function include metal oxides such as an oxide containing hafnium, an oxide containing magnesium, an oxide containing aluminum, and an oxide containing aluminum and hafnium (hafnium aluminate). Furthermore, these metal oxides may further contain zirconium, and an example of such a metal oxide is an oxide containing hafnium and zirconium. Note that in a metal oxide having an amorphous structure, some oxygen atoms have an open bond, which enables the metal oxide to have a high hydrogen trapping or fixing property. Therefore, these metal oxides each preferably have an amorphous structure. For example, these oxides may have an amorphous structure by containing silicon. For example, an oxide containing hafnium and silicon (hafnium silicate) is preferably used.It should be noted that the metal oxide may partially comprise a crystal region and / or a crystal grain boundary.

[0192] It should be noted that a function for capturing or fixing a target substance can also be referred to as a property that does not easily allow diffusion of a target substance. Therefore, a function for capturing or fixing a target substance can be reformulated as a barrier property.

[0193] In the case where the gate insulating layer has a multilayer structure, a layer in contact with the oxide semiconductor layer 230 preferably has a hydrogen trapping or fixing function. In this case, hydrogen contained in the oxide semiconductor layer 230 can be more effectively trapped or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. For a layer in the insulating layer 250 that is in contact with the oxide semiconductor layer 230, hafnium silicate or the like is preferably used. The layer preferably has an amorphous structure.

[0194] If the layer has an amorphous structure, the formation of a crystal grain boundary can be prevented. Preventing the formation of a crystal grain boundary can increase the flatness of the layer. This allows the insulating layer 250 to have a uniform thickness distribution and a reduced number of very thin portions, so that the withstand voltage of the insulating layer 250 can be increased. Furthermore, the thickness distribution of the film provided over the insulating layer 250 can be uniform.

[0195] Furthermore, by preventing the formation of a crystal grain boundary in the layer, leakage current due to defect states in the crystal grain boundary can be reduced. Therefore, the insulating layer 250 can serve as a low-leakage insulating film.

[0196] Since hafnium oxide is a high-dielectric constant (high-k) material, hafnium silicate becomes a high-dielectric constant (high-k) material depending on the silicon content. Therefore, when hafnium oxide or hafnium silicate is used for the gate insulating layer, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulating layer. Furthermore, the equivalent oxide film thickness (EOT) of the gate insulating layer can be reduced.

[0197] As described above, for the insulating layer 250, an oxide containing aluminum and / or hafnium is preferably used, more preferably an oxide containing aluminum and / or hafnium and having an amorphous structure, even more preferably aluminum oxide having an amorphous structure is used.

[0198] The above-described hydrogen barrier insulating layer is preferably used as the insulating layer 250. Using a hydrogen barrier insulating layer as the insulating layer 250 can prevent impurities contained in the conductive layer 265 from diffusing into the oxide semiconductor layer 230. For example, silicon nitride is suitable for the insulating layer 250 because it has a high hydrogen barrier property. Furthermore, the insulating layer 250 may comprise a thermally stable insulating layer, such as silicon oxide or silicon oxynitride.

[0199] With such a structure, a semiconductor device with favorable electrical characteristics can be provided. A semiconductor device with high reliability can be provided. A semiconductor device with low fluctuations in the electrical characteristics of the transistor can be provided. A semiconductor device with high forward current can be provided.

[0200] Furthermore, the insulating layer 250 may comprise a thermally stable insulating layer, such as silicon oxide or silicon oxynitride.

[0201] The insulating layer 250 may comprise a thermally stable insulating layer between a pair of insulating layers having a function of trapping and fixing hydrogen.

[0202] The insulating layer 250 preferably includes an oxygen insulating barrier. In this case, oxidation of the conductive layer 240, the conductive layer 265, and the like can be prevented. In the case where the insulating layer 250 has a multilayer structure, a layer in contact with the conductive layer 240 or the conductive layer 265 is preferably an oxygen insulating barrier. Specifically, the layer in contact with the conductive layer 240 and a layer in contact with the conductive layer 265 included in the insulating layer 250 are preferably oxygen insulating barriers.

[0203] When an insulating barrier layer against hydrogen and oxygen is used as a layer in the insulating layer 250 that is in contact with the conductive layer 265, oxidation of the conductive layer 265 can be prevented. Furthermore, oxygen contained in the oxide semiconductor layer 230 can be prevented from diffusing into the conductive layer 265, thus preventing the formation of oxygen vacancies in the oxide semiconductor layer 230.

[0204] Examples of an insulating barrier layer against oxygen include an oxide containing aluminum and / or hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of the oxide containing aluminum and / or hafnium include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate).

[0205] The layer in the insulating layer 250 that is in contact with the conductive layer 240 is preferably less likely to transmit oxygen than at least the insulating layer 280b. If the layer has an oxygen barrier property, oxidation of the side surface of the conductive layer 240 can be prevented, and accordingly, the formation of an oxide film on the side surface can be prevented. This can prevent a reduction in the forward current or the field-effect mobility of the transistor 200.

[0206] Each layer included in the insulating layer 250 is preferably a thin film. For example, if the insulating layer 250 has a thickness of greater than or equal to 1 nm and less than or equal to 20 nm, preferably greater than or equal to 3 nm and less than or equal to 10 nm, the subthreshold swing value (also referred to as S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in the gate voltage in the subthreshold region when the drain voltage is constant and the drain current is changed by one order of magnitude.

[0207] The thickness of each layer included in the insulating layer 250 is preferably greater than or equal to 0.1 nm and less than or equal to 10 nm, more preferably greater than or equal to 0.1 nm and less than or equal to 5.0 nm, even more preferably greater than or equal to 0.5 nm and less than or equal to 5.0 nm, even more preferably greater than or equal to 1.0 nm and less than 5.0 nm, even more preferably greater than or equal to 1.0 nm and less than or equal to 3.0 nm. It should be noted that each layer included in the insulating layer 250 at least partially includes a region having the above thickness.

[0208] The insulating layer 250 preferably has a three-layer structure in which a first insulating layer containing a low-dielectric constant material, a second insulating layer having a hydrogen trapping or fixing function, and a third insulating layer having a hydrogen and oxygen barrier property are stacked in this order from the oxide semiconductor layer 230 side. Silicon oxide or silicon oxynitride is preferably used as the low-dielectric constant material contained in the first insulating layer. The first insulating layer is in contact with the oxide semiconductor layer 230. When an oxide is used for the first insulating layer, oxygen may be supplied to the oxide semiconductor layer 230.By providing the third insulating layer, oxygen contained in the first insulating layer can be prevented from diffusing into the conductive layer 265 and oxidizing the conductive layer 265. Furthermore, the amount of oxygen supplied to the oxide semiconductor layer 230 from the first insulating layer can be prevented from decreasing.

[0209] The insulating layer 250 preferably has a four-layer structure in which a fourth insulating layer having an oxygen barrier property, a first insulating layer containing a low dielectric constant material, a second insulating layer having a hydrogen trapping or fixing function, and a third insulating layer having a hydrogen and oxygen barrier property are stacked in this order from the oxide semiconductor layer 230 side. The first to third insulating layers may have a structure similar to that of the layers used in the above three-layer structure. The fourth insulating layer is in contact with the oxide semiconductor layer 230. When the fourth insulating layer has an oxygen barrier property, oxygen release from the oxide semiconductor layer 230 can be prevented.For the fourth insulating layer, aluminum oxide, for example, is preferably used. Aluminum oxide has a hydrogen trapping or fixing function and is therefore suitably used for the fourth insulating layer in contact with the oxide semiconductor layer 230. Specifically, a four-layer structure is preferably used in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the oxide semiconductor layer 230 side.

[0210] Typically, the thicknesses of the fourth, first, second, and third insulating layers are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. Such a structure enables a transistor to have favorable electrical properties even when the transistor is miniaturized or highly integrated.

[0211] Alternatively, the insulating layer 250 preferably has a three-layer structure in which a fourth insulating layer having an oxygen barrier property, a first insulating layer containing a low dielectric constant material, and a second insulating layer having a hydrogen trapping or fixing function are stacked in this order from the oxide semiconductor layer 230 side. Specifically, a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the oxide semiconductor layer 230 side is preferably employed.

[0212] The silicon oxide film included in the insulating layer 250 is preferably formed by a PEALD method. The thickness of the silicon oxide film included in the insulating layer 250 is preferably greater than or equal to 0.7 nm and less than or equal to 3.0 nm. With an ALD method, one atomic layer can be formed at a time, and the ALD method has various advantages, such as the formation of an extremely thin film, deposition on a component with a high aspect ratio or a surface with a large step, formation of a film with few defects such as pinholes, deposition with excellent coverage, and low-temperature deposition.Therefore, an ALD process can increase the coverage of the sidewall and the bottom surface of the opening portion 290 with the insulating layer 250 in the transistor of one embodiment of the present invention, allowing the insulating layer 250 to be formed with a uniform thickness. A PEALD process using plasma is preferable because deposition at a lower temperature is possible. Furthermore, when plasma is used, the deposition rate can be increased, and productivity can be improved.

[0213] The insulating layer 250 is preferably formed from two or more types of films. When the insulating layer 250 is formed from two or more types of films, the insulating layer 250 can have a variety of functions. Examples of the functions of the insulating layer 250 include a function of extracting hydrogen from the oxide semiconductor layer 230 and a function of preventing hydrogen from diffusing into the oxide semiconductor layer 230. Note that in the formation of the insulating layer 250, an ALD process is preferably used two or more times. For example, the insulating layer 250 preferably has a multilayer structure composed of a plurality of insulating films, and two or more of the plurality of insulating films are preferably formed by an ALD process.When at least two insulating films are formed by an ALD process, the coverage of the insulating layer 250 and the uniformity of the thickness of the insulating layer 250 can be improved. When two or more types of films, for example, two or more types of insulating films, are successively formed by an ALD process, productivity can be increased.

[0214] As the insulating layer 210, the above-described insulating layer having a hydrogen trapping or fixing function can be used. Consequently, hydrogen diffused into the insulating layer 210 via the conductive layers 220a and 220b can be trapped or fixed in the oxide semiconductor layer 230. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. For example, the insulating layer 210 may have a two-layer structure of a silicon nitride film and a hafnium silicate film over the silicon nitride film.

[0215] The insulating layer 235 may be referred to as a sidewall, sidewall insulating layer, sidewall protective layer, or the like.

[0216] The insulating layer 235 preferably comprises an insulating layer that includes a region containing oxygen that is released upon heating. Accordingly, oxygen can be supplied from the insulating layer 235 to the oxide semiconductor layer 230. For example, silicon oxide or silicon oxynitride is preferably used for the insulating layer 235.

[0217] The insulating layer 235 preferably includes a hydrogen barrier insulating layer. Consequently, hydrogen can be prevented from diffusing into the oxide semiconductor layer 230, and the reliability of the transistor 200 can be improved. For example, aluminum oxide, hafnium oxide, silicon nitride, or silicon nitride oxide is preferably used for the insulating layer 235.

[0218] A silicon nitride film included in the insulating layer 235 is preferably formed by a PEALD method. This can improve the coverage of the sidewall of the opening portion 290 with the insulating layer 235, so that the insulating layer 235 can be formed with a uniform thickness.

[0219] Alternatively, it is also possible to use any of the materials described above that can exhibit ferroelectricity for the insulating layer 235.

[0220] For example, the insulating layer 235 may have a single-layer structure of a silicon oxide film, a single-layer structure of a silicon nitride film, a two-layer structure of a silicon oxide film and a silicon nitride film, a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film, or a three-layer structure of a silicon nitride film, a silicon oxide film, and a silicon nitride film. For example, in the case of the two-layer structure of a silicon oxide film and a silicon nitride film, it is preferable that the silicon oxide film is provided on the oxide semiconductor layer 230 side and the silicon nitride film is provided on the conductive layer 255 side. Consequently, oxygen can be efficiently supplied to the oxide semiconductor layer 230, and the diffusion of impurities such as hydrogen into the oxide semiconductor layer 230 can be prevented.Alternatively, the silicon nitride film may be provided on the oxide semiconductor layer 230 side, and the silicon oxide film may be provided on the conductive layer 255 side. [Senior Layer]

[0221] For each of the conductive layers (the conductive layer 220, the conductive layer 240, the conductive layer 255, the conductive layer 265, and the like) included in the semiconductor device, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, and the like, an alloy containing any of the above metal elements, an alloy containing a combination of the above metal elements, or the like is preferably used. As the alloy containing any of the above metal elements, a nitride of the alloy or an oxide of the alloy can be used.For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like are preferably used. Alternatively, a semiconductor with high electrical conductivity, typically polycrystalline silicon, containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0222] A conductive material containing nitrogen, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing ruthenium, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum, a conductive material containing oxygen, such as ruthenium oxide, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel, or a material containing a metal element such as titanium, tantalum, or ruthenium, is preferred because it is a conductive material that is not easily oxidized, a conductive material with a function of preventing oxygen diffusion, or a material that maintains conductivity even after absorbing oxygen.Examples of the conductive material containing oxygen include an indium oxide containing tungsten oxide, an indium oxide containing titanium oxide, an indium tin oxide (also referred to as ITO), an indium tin oxide containing titanium oxide, an indium tin oxide with silicon added (also referred to as ITSO), an indium zinc oxide (also referred to as IZO (registered trademark)), and an indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using the conductive material containing oxygen may be referred to as an oxide conductor film.

[0223] A conductive material containing tungsten, copper or aluminum as the main component is preferred because it has high conductivity.

[0224] Conductive layers formed using any of the above materials can be stacked. For example, a multilayer structure combining a material containing any of the above metal elements and an oxygen-containing conductive material may be used. Alternatively, a multilayer structure combining a material containing any of the above metal elements and a nitrogen-containing conductive material may be used. Alternatively, a multilayer structure combining a material containing any of the above metal elements, an oxygen-containing conductive material, and a nitrogen-containing conductive material may also be used.

[0225] In the case where a metal oxide is used for the channel formation region of the transistor, the conductive layer serving as the gate electrode will preferably have a multilayer structure combining a material containing the above metal element and an oxygen-containing conductive material. In this case, the oxygen-containing conductive material is preferably provided on the channel formation region side. When the oxygen-containing conductive material is provided on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0226] Each of the conductive layers 220 and 240 is in contact with the oxide semiconductor layer 230 and is therefore preferably formed using a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even after oxidation, a metal oxide that has conductivity (also referred to as an oxide conductor), or a conductive material that has a function of preventing oxygen diffusion. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. Therefore, a reduction in the conductivity of the conductive layer 220 and the conductive layer 240 can be prevented.

[0227] When an oxygen-containing conductive material is used for the conductive layer 220 or the conductive layer 240, the conductive layer 220 or the conductive layer 240 can maintain its conductivity even after absorbing oxygen. It is also preferable that an insulating layer containing oxygen, such as hafnium oxide, be used as the insulating layer 210 because the conductive layer 220 can maintain its conductivity. For each of the conductive layers 220 and 240, for example, ITO, ITSO, IZO (registered trademark), or the like is preferably used.

[0228] Fig. 3 illustrates an example in which the conductive layer 220 has a three-layer structure of a conductive layer 220a1, a conductive layer 220a2 above the conductive layer 220a1, and the conductive layer 220b above the conductive layer 220a2. In this case, for example, a conductive material that is not easily oxidized or a conductive material that has a function of preventing oxygen diffusion is preferably used for the conductive layer 220a1, a conductive material that has high conductivity is preferably used for the conductive layer 220a2, and a conductive material containing oxygen (preferably an oxide conductor) is preferably used for the conductive layer 220b. Specifically, titanium nitride is preferably used for the conductive layer 220a1, tungsten is preferably used for the conductive layer 220a2, and an oxide conductor (e.g.,ITO, ITSO, or IZO (registered trademark) is preferably used for the conductive layer 220b. In this case, the titanium nitride is in contact with the insulating layer 210, and the oxide conductor is in contact with the oxide semiconductor layer 230. In addition, the oxide conductor is used for the layer closest to the channel formation region of the oxide semiconductor layer 230. Since the oxide conductor has a lower contact resistance with the oxide semiconductor layer 230 than tungsten, the current path between the source and drain can be shortened, and the on-state current of the transistor can be increased. With such a structure, the conductive layer 220 can maintain its conductivity even when it is in contact with the oxide semiconductor layer 230. When an insulating oxide layer is used as the insulating layer 210, the conductive layer 220 can be prevented from being excessively oxidized by the insulating layer 210.When a metal material (here, tungsten) having a higher conductivity than an oxide conductor and titanium nitride is used for the conductive layer 220a2, the conductivity of the conductive layer 220 can be increased.

[0229] Fig. 3 illustrates the example in which the conductive layer 240 has a two-layer structure of the conductive layer 240a and the conductive layer 240b above the conductive layer 240a. In this case, for example, an oxygen-containing conductive material is preferably used for the conductive layer 240b, and a material having a higher conductivity than the material for the conductive layer 240b is preferably used for the conductive layer 240a. Specifically, for example, an oxide conductor (e.g., ITO, ITSO, or IZO (registered trademark)) is preferably used for the conductive layer 240b, and tungsten is preferably used for the conductive layer 240a. Alternatively, ruthenium, titanium nitride, tantalum nitride, or the like may be used for the conductive layer 240a.

[0230] In the conductive layer 240, the conductive layer 240b is mainly in contact with the oxide semiconductor layer 230. Using an oxide conductor for the conductive layer 240b is preferable because the contact resistance with the oxide semiconductor layer 230 can be reduced. Using a material with a higher conductivity than the oxide conductor for the layer included in the conductive layer 240 is preferable because the conductivity of the conductive layer 240 can be increased.

[0231] Note that an oxygen-containing conductive material may be used for the conductive layer 240a, and a material having a higher conductivity than the material for the conductive layer 240a may be used for the conductive layer 240b. In this case, the oxide conductor is used for the layer of the conductive layer 240 closest to the channel formation region of the oxide semiconductor layer 230. Therefore, the current path between the source and drain can be shortened, so that the forward current of the transistor can be increased.

[0232] The conductive layers 255 and 265 are each preferably formed using a material with high conductivity, such as tungsten. Furthermore, a conductive material that is not easily oxidized, a conductive material having a function of preventing oxygen diffusion, or the like is preferably used for each of the conductive layers 255 and 265. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). Therefore, a reduction in the conductivity of the conductive layers 255 and 265 can be prevented.

[0233] In particular, a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed is preferably used for the conductive layer 265. Alternatively, a conductive material containing the above metal element and nitrogen (e.g., titanium nitride or tantalum nitride) may be used. One or more of an indium tin oxide, an indium oxide containing tungsten oxide, an indium zinc oxide containing tungsten oxide, an indium oxide containing titanium oxide, an indium tin oxide containing titanium oxide, an indium zinc oxide, and an indium tin oxide to which silicon is added may be used. An indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed can be trapped in some cases.Hydrogen penetrating from a surrounding insulating layer or the like can also be trapped in some cases.

[0234] Fig. 3 illustrates an example in which the conductive layer 265 has a two-layer structure consisting of the conductive layer 265a and the conductive layer 265b above the conductive layer 265a. In this case, for example, titanium nitride is preferably used for the conductive layer 265a and tungsten for the conductive layer 265b. Alternatively, tantalum nitride is preferably used for the conductive layer 265a and copper for the conductive layer 265b. With such a structure, the conductivity of the conductive layer 265 can be increased.

[0235] The conductive layer 265 may have a multilayer structure consisting of three or more layers. For example, the conductive layer 265 may have a three-layer structure consisting of tantalum nitride, titanium nitride over the tantalum nitride, and tungsten over the titanium nitride.

[0236] The conductive layer 265 serves as a gate line and therefore preferably has a high conductivity. The conductive layer 265 is preferably formed using tungsten. For example, a two-layer structure of titanium nitride and tungsten can be used.

[0237] The conductive layer 255 is preferably formed using, for example, tungsten or tantalum nitride. [Substrate]

[0238] As a substrate over which a transistor is formed, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttrium-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Another example is one of the above semiconductor substrates provided with an insulator region, such as a silicon-on-insulator (SOI) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.Other examples include a substrate containing a nitride of a metal and a substrate containing an oxide of a metal. Other examples include an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductor substrate provided with a semiconductor or an insulator. Alternatively, these substrates provided with elements may be used. Examples of the element provided above the substrate include a capacitor, a resistor, a switching element, a light-emitting element, and a memory element. <Strukturbeispiel 2 einer Halbleitervorrichtung>

[0239] Structures of semiconductor devices of further embodiments of the present invention are described with reference to Fig. 4A and Fig. 4B, Fig. 5A and Fig. 5B, Fig. 6A to Fig. 6D, Fig. 7A to Fig. 7C, Fig. 8A to Fig. 8E, Fig. 9A and Fig. 9B, Fig. 10A to Fig. 10E, Fig. 11A and Fig. 11B, Fig. 12A to Fig. 12E, Fig. 13A and Fig. 13B and Fig. 14A to Fig. 14C2 described. [Transistor 200A]

[0240] Fig. 4A is a cross-sectional view of a semiconductor device including a transistor 200A.

[0241] Fig. 4A illustrates an example in which the sidewall of the opening portion 290 has a tapered shape. When the sidewall of the opening portion 290 has a tapered shape, the coverage with the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250, and the like can be improved, so that defects such as voids can be reduced. For example, in the case where the sidewall of the opening portion 290 has a tapered shape, a taper angle θ280 of the side surface of the insulating layer 280a in the opening portion 290 is preferably greater than or equal to 45° and less than 90°. Specifically, the taper angle θ280 is preferably greater than or equal to 80° and less than 90°, in which case the semiconductor device can be miniaturized or highly integrated as described above.Alternatively, the taper angle θ280 is preferably greater than or equal to 45°, or greater than or equal to 50° and less than 80°, less than or equal to 75°, less than or equal to 70°, less than or equal to 65°, or less than or equal to 60°, in which case, the coverage with a film formed in the opening portion 290 is improved.

[0242] Alternatively, for example, the side wall of the opening portion 290 may have a downwardly tapered shape. In other words, the taper angle θ280 of the side surface of the insulating layer 280a in the opening portion 290 may be greater than 90°. [Transistors 200B, 200C and 200D]

[0243] Fig. 4B is a cross-sectional view of a semiconductor device including a transistor 200B. Fig. 5A is a cross-sectional view of a semiconductor device including a transistor 200C. Fig. 5B is a cross-sectional view of a semiconductor device including a transistor 200D.

[0244] The transistors 200B, 200C, and 200D differ from the transistor 200 mainly in that the insulating layer 235 has a two-layer structure and that an insulating layer 280c and an insulating layer 280d are provided.

[0245] Transistors 200B, 200C, and 200D each include an insulating layer 235a and an insulating layer 235b over insulating layer 235a. Insulating layers 235a and 235b each serve as the second gate insulating layer of the transistor.

[0246] One of the insulating layers 235a and 235b preferably comprises an insulating layer that includes a region containing oxygen that is released upon heating. The other of the insulating layers 235a and 235b preferably comprises a hydrogen insulating barrier layer.

[0247] Consequently, oxygen can be supplied from the insulating layer 235a or the insulating layer 235b to the oxide semiconductor layer 230, and the diffusion of hydrogen into the oxide semiconductor layer 230 can be prevented, resulting in higher reliability of the transistor.

[0248] For example, one of the insulating layers 235a and 235b is preferably an insulating oxide layer, and the other is preferably an insulating nitride layer. Specifically, it is preferable that a silicon nitride film be used as the insulating layer 235a, and a silicon oxide film be used as the insulating layer 235b. Alternatively, it is preferable that a silicon oxide film be used as the insulating layer 235a, and a silicon nitride film be used as the insulating layer 235b.

[0249] The insulating layer 235 preferably comprises a silicon oxide film with a thickness greater than 0 nm and less than or equal to 5 nm. The insulating layer 235 preferably comprises a silicon nitride film with a thickness greater than 0 nm and less than or equal to 5 nm. The silicon oxide film and the silicon nitride film are each preferably formed by a PEALD method. With such a structure, a gate leakage current from the conductive layer 255 in the transistor 200B can be prevented. When the insulating layer 235 comprises a silicon nitride film, the insulating layer 235 can have a hydrogen blocking function.

[0250] In the example of transistor 200B, the insulating layer 235a is provided in contact with the bottom and side surfaces of the recessed portion of the conductive layer 220b, and the insulating layer 235b is provided over the insulating layer 235a. For example, an insulating film that will become the insulating layer 235a and an insulating film that will become the insulating layer 235b are superimposed on each other, and then the two insulating films are processed, whereby the insulating layer 235a and the insulating layer 235b can be formed, as shown in FIG. Fig. 4B. Therefore, it can be said that the structure can be formed relatively easily.

[0251] In the example of the transistor 200C, the insulating layer 235a is provided in contact with the bottom and side surfaces of the recessed portion of the conductive layer 220b, and the insulating layer 235b is provided in the opening portion further inside than the insulating layer 235a in contact with the bottom of the recessed portion of the conductive layer 220b.

[0252] In the transistor 200D, the conductive layer 220b includes a first recessed portion, a second recessed portion positioned further outward than the first recessed portion, and a third recessed portion positioned further outward than the second recessed portion. The depth of the first recessed portion is greater than that of the second recessed portion, and the depth of the second recessed portion is greater than that of the third recessed portion. The third recessed portion is provided in the conductive layer 220b when forming the opening portion 290, the second recessed portion is provided in the conductive layer 220b when processing the insulating layer 235a, and then the first recessed portion is provided in the conductive layer 220b when processing the insulating layer 235b. Therefore, in Fig. 5B, the side surface of the first recessed portion is aligned with a surface of the insulating layer 235b on the oxide semiconductor layer 230 side, the side surface of the second recessed portion is aligned with a surface of the insulating layer 235a on the insulating layer 235b side, and the side surface of the third recessed portion is aligned with surfaces of the insulating layer 280a and the like on the opening portion 290 side.

[0253] In the example of the transistor 200D, the insulating layer 235a is provided in contact with the bottom and side surfaces of the third recessed portion of the conductive layer 220b, and the insulating layer 235b is provided in contact with the bottom and side surfaces of the second recessed portion of the conductive layer 220b.

[0254] For example, after the insulating layer 235a is provided on the side wall of the opening portion, an insulating film to become the insulating layer 235b is formed and processing is performed, whereby the insulating layer 235a and the insulating layer 235b can be formed, as shown in Fig. 5A or Fig. 5B. The contact area between the insulating layer 235a and the oxide semiconductor layer 230 may be smaller than that in the transistor 200B, and the insulating layer 235b may be in contact with the oxide semiconductor layer 230.

[0255] In transistors 200B, 200C, and 200D, insulating layers 280a and 280b are located closer to the channel formation region of oxide semiconductor layer 230 than insulating layers 280c and 280d. When an insulating layer containing oxygen is used as each of insulating layers 280a and 280b, oxygen can be supplied to oxide semiconductor layer 230.

[0256] The insulating layers 280a and 280b each preferably include a region having a higher oxygen content than at least one of the insulating layers 280c and 280d. When the insulating layers 280a and 280b each have a high oxygen content, an i-type region can be easily formed in the oxide semiconductor layer 230.

[0257] It is further preferable that a film from which oxygen is released upon heating is used for each of the insulating layers 280a and 280b. When the insulating layers 280a and 280b release oxygen upon heating during the transistor manufacturing process, the oxygen can be supplied to the oxide semiconductor layer 230. The oxygen supply from the insulating layers 280a and 280b to the oxide semiconductor layer 230, particularly to the channel formation region of the oxide semiconductor layer 230, can reduce the amount of oxygen vacancies and V OH in the oxide semiconductor layer 230, so that the transistor can have advantageous electrical properties and high reliability.

[0258] In order to improve the electrical characteristics and reliability of the OS transistor, it is important to optimize the amount of oxygen supplied to the oxide semiconductor after the hydrogen concentration in the oxide semiconductor has been sufficiently reduced.

[0259] In particular, when the channel length of the transistor is small, the influence of oxygen vacancies and V OH in the channel formation region on the electrical characteristics and reliability of the channel formation region is particularly large. Accordingly, if the amount of oxygen supplied to the oxide semiconductor layer 230 is optimized after the hydrogen concentration in the oxide semiconductor layer 230 has been sufficiently reduced, a transistor with a short channel length, favorable electrical characteristics, and high reliability can be provided.

[0260] The insulating layers 280a and 280b are each preferably formed by a film formation method such as a sputtering method or a plasma-enhanced chemical vapor deposition (PECVD) method. It is particularly preferable to use a sputtering method, which does not necessarily use hydrogen gas as the deposition gas, to form a film with a very low hydrogen content. Accordingly, the supply of hydrogen to the oxide semiconductor layer 230 is prevented, and the electrical characteristics of the transistor can be stabilized.

[0261] In the case where a large amount of oxygen is supplied to the oxide semiconductor layer 230, it is preferable to perform, for example, a heat treatment in an oxygen-containing atmosphere or a plasma treatment in an oxygen-containing atmosphere after the formation of the insulating layer 280a or 280b. Alternatively, an oxide film may be formed over the top of the insulating layer 280a or 280b by a sputtering method in an oxygen atmosphere to supply oxygen. Thereafter, the oxide film may be removed. Such a treatment can supply oxygen to the insulating layer 280a or 280b and increase the amount of oxygen supplied to the oxide semiconductor layer 230.

[0262] An insulating layer suitable for insulating layers 280a and 280b is preferably used as insulating layer 235 (particularly insulating layer 235b in contact with oxide semiconductor layer 230). Therefore, oxygen can be efficiently supplied to oxide semiconductor layer 230.

[0263] A material with a low dielectric constant is preferably used for each of the insulating layers 280a and 280b. In this case, parasitic capacitance generated between lines can be reduced. For example, silicon oxide or silicon oxynitride can be suitably used for each of the insulating layers 280a and 280b.

[0264] For each of the insulating layers 280c and 280d, an insulating barrier layer against oxygen is preferably used. This can prevent the conductive layers 220 and 240 from being oxidized and exhibiting increased resistance.

[0265] As each of the insulating layers 280c and 280d, a hydrogen barrier insulating layer may preferably be used. This structure is preferable because the diffusion of impurities such as hydrogen into the oxide semiconductor layer 230 can be prevented.

[0266] In the transistors 200B, 200C, and 200D, a silicon oxide film is preferably used as each of the insulating layers 280a and 280b, and a silicon nitride film or an aluminum oxide film is preferably used as each of the insulating layers 280c and 280d. [Transistor 200E]

[0267] Fig. 6A is a cross-sectional view of a semiconductor device including a transistor 200E.

[0268] The transistor 200E differs from the transistor 200 mainly in that only one recessed portion is provided in the conductive layer 220b.

[0269] A recessed portion may be formed in the conductive layer 220b in a step of forming the opening portion 290 and / or a step of forming the insulating layer 235. In the example of the transistor 200, a recessed portion is formed in the conductive layer 220b in both steps; in contrast, in the example of the transistor 200E, a recessed portion is formed in the conductive layer 220b not in the step of forming the opening portion 290, but in the step of forming the insulating layer 235.

[0270] In transistor 200E, the insulating layer 235 in the opening portion 290 is in contact with the side surface of the insulating layer 280a, the side surface of the conductive layer 255, the side surface of the insulating layer 280b, the side surface of the conductive layer 240a, the side surface of the conductive layer 240b, and the top surface of the conductive layer 220b. The oxide semiconductor layer 230 is in contact with the bottom surface and the side surface of the recessed portion of the conductive layer 220b.

[0271] When a recessed portion is formed in the conductive layer 220b in at least one of the step of forming the opening portion 290 and the step of forming the insulating layer 235, the height of the bottom surface of the conductive layer 265a in the opening portion 290 can be made low; consequently, a gate electric field can be easily applied to the channel formation region of the oxide semiconductor layer 230, and the electrical characteristics of the transistor 200 can be improved.

[0272] A recessed portion is preferably formed in the conductive layer 220b in the step of forming the insulating layer 235, in which case the oxide semiconductor layer 230 may be in contact with the bottom surface and the side surface of the recessed portion of the conductive layer 220b, so that the contact area between the oxide semiconductor layer 230 and the conductive layer 220b is increased and consequently the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220b can be reduced. [Transistor 200F]

[0273] Fig. 6B is a cross-sectional view of a semiconductor device including a transistor 200F.

[0274] The transistor 200F differs from the transistor 200 mainly in that the insulating layer 235 does not cover the side surface of the conductive layer 240b.

[0275] The Fig. The insulating layer 235 shown in FIG. 6B is in contact with the bottom surface and the side surface of the recessed portion of the conductive layer 220, and is in contact with the side surfaces of the insulating layer 280a, the conductive layer 255, and the insulating layer 280b in the opening portion 290. The insulating layer 235 is in contact with a part of the side surface of the conductive layer 240a and is not in contact with the side surface of the conductive layer 240b. The insulating layer 235 serves as a second gate insulating layer. Therefore, the insulating layer 235 covers at least the entire side surface of the conductive layer 255 in the opening portion 290 to electrically isolate the conductive layer 255 and the oxide semiconductor layer 230 from each other.The insulating layer 235 may be in contact with one or more of the side surfaces of the insulating layer 280a, the insulating layer 280b, the conductive layer 240a, and the conductive layer 240b in the opening portion 290, or may cover part or all of each side surface.

[0276] In the case where at least a part of the side surface of the conductive layer 240b is not covered with the insulating layer 235, the uncovered part is in contact with the oxide semiconductor layer 230. This is preferable because the contact area between the oxide semiconductor layer 230 and the conductive layer 240 can be increased and the contact resistance therebetween can be reduced. Similarly, in the case where the insulating layer 235 does not cover the side surface of the conductive layer 240b and at least a part of the side surface of the conductive layer 240a, the uncovered part is in contact with the oxide semiconductor layer 230. This is preferable because the contact area between the oxide semiconductor layer 230 and the conductive layer 240 can be increased and the contact resistance therebetween can be reduced. [Transistor 200G]

[0277] Fig. 6C is a cross-sectional view of a semiconductor device including a transistor 200G.

[0278] The transistor 200G differs from the transistor 200 primarily in that the transistor 200G includes the insulating layer 280c, the insulating layer 280d, an insulating layer 280e, and an insulating layer 280f.

[0279] In the transistor 200G, a silicon oxide film is preferably used as each of the insulating layers 280a and 280b, and a silicon nitride film or an aluminum oxide film is preferably used as each of the insulating layers 280c, 280d, 280e, and 280f. A hydrogen barrier insulating layer is preferably provided as each of the insulating layer 280c in contact with the upper surface of the conductive layer 220, the insulating layer 280d in contact with the lower surface of the conductive layer 240, the insulating layer 280e in contact with the lower surface of the conductive layer 255, and the insulating layer 280f in contact with the upper surface of the conductive layer 255. In this case, diffusion of impurities such as hydrogen into the oxide semiconductor layer 230 can be prevented.

[0280] For example, in the case where tungsten, tantalum nitride, or the like is used for the conductive layer 255, the conductive layer 255 may be oxidized if an insulating oxide film is used as an insulating layer in contact with the conductive layer 255. Therefore, a silicon nitride film is preferably used for each of the insulating layers 280e and 280f above and below the conductive layer 255. Accordingly, oxidation of the conductive layer 255 can be prevented, and an insulating barrier against hydrogen can be provided. [Transistor 200H]

[0281] Fig. 6D is a cross-sectional view of a semiconductor device including a transistor 200H.

[0282] The transistor 200H differs from the transistor 200 mainly in that the side surface of the conductive layer 220 in the opening portion 290 is aligned with the side surfaces of the conductive layer 240, the insulating layer 280b, the conductive layer 255, and the insulating layer 280a.

[0283] The width of the conductive layer 220 in the cross-sectional view corresponds to the width of the opening portion 290. Such a structure is preferable because the parasitic capacitance generated between the conductive layer 220 and the conductive layer 240 can be reduced. [Transistor 200I]

[0284] Fig. 7A is a cross-sectional view of a semiconductor device including a transistor 2001.

[0285] The transistor 200I differs from the transistor 200 mainly in that the insulating layer 235 has a three-layer structure.

[0286] Transistor 200I includes insulating layer 235a, insulating layer 235b over insulating layer 235a, and an insulating layer 235c over insulating layer 235b. Insulating layer 235a, insulating layer 235b, and insulating layer 235c serve as the second gate insulating layer of transistor 200I.

[0287] At least one of the insulating layers 235a, 235b, and 235c preferably comprises an insulating layer that includes a region containing oxygen that is released upon heating. At least one of the insulating layers 235a, 235b, and 235c preferably comprises a hydrogen insulating barrier layer.

[0288] Consequently, oxygen can be supplied from at least one of the insulating layers 235a, 235b, and 235c to the oxide semiconductor layer 230, and the diffusion of hydrogen into the oxide semiconductor layer 230 can be prevented, resulting in higher reliability of the transistor.

[0289] For example, it is preferable that a silicon nitride film be used as each of the insulating layers 235a and 235c, and a silicon oxide film be used as the insulating layer 235b. Alternatively, it is preferable that a silicon oxide film be used as each of the insulating layers 235a and 235c, and a silicon nitride film be used as the insulating layer 235b.

[0290] It should be noted that the insulating layer 235 having a three-layer structure in the transistor 200B is used as a variation example of the insulating layer 235 having a two-layer structure in the transistor 200B ( Fig. 4B). In the case where the insulating layer 235 has a three-layer structure, the structure is not limited to that shown in the transistor 2001. For example, the insulating layer 235 may have a two-layer structure in the transistor 200C ( Fig. 5A) or the transistor 200D ( Fig. 5B) have a three-layer structure. [Transistors 200K and 200J]

[0291] Fig. 7B is a cross-sectional view of a semiconductor device including a transistor 200J. Fig. Figure 7C is a cross-sectional view of a semiconductor device including a 200K transistor.

[0292] The transistor 200J differs from the transistor 200 mainly in that it does not include the conductive layer 265a or 265b, but includes the conductive layer 265 with a single-layer structure.

[0293] Like the conductive layer 265 included in transistor 200J, the conductive layer serving as the gate electrode may have a single-layer structure. The conductive layer 265 is preferably provided to fill the opening portion 290.

[0294] Transistor 200K differs from transistor 200 primarily in that both conductive layer 265a and conductive layer 265b are positioned in opening portion 290.

[0295] In the transistor 200K, the conductive layer 265b is positioned in the opening portion 290. As described above, depending on the diameter of the opening portion 290, the thickness of the conductive layer 265a, and the like, not only the conductive layer 265a but also the conductive layer 265b are provided in the opening portion 290 in some cases. [Transistor 201]

[0296] Fig. 8A is a plan view of a semiconductor device including a transistor 201. Fig. 8B is a cross-sectional view taken along the dot-dash line A1-A2 in Fig. 8A. Fig. Figure 8C is a cross-sectional view along the dotted line A3-A4 in Fig. 8A. Fig. Figure 8D is a cross-sectional view along the dotted line A5-A6 in Fig. 8B and Fig. 8C. Fig. Figure 8E is a cross-sectional view along the dotted line A7-A8 in Fig. 8B and Fig. 8C. Since the structures in Fig. 8D and Fig. 8E those in Fig. 2D and Fig. 2E are similar, the details of which are not described.

[0297] The Fig. 8A to Fig. The semiconductor device shown in Figure 8E includes the insulating layer 210 over a substrate (not shown), the transistor 201 over the insulating layer 210, the insulating layer 280a over the insulating layer 210, the insulating layer 280b over the insulating layer 280a, an insulating layer 283 over the insulating layer 250, and an insulating layer 285 over the insulating layer 283. The insulating layer 210, the insulating layer 280a, the insulating layer 280b, the insulating layer 283, and the insulating layer 285 serve as interlayer films.

[0298] The transistor 201 includes the conductive layer 220a, the conductive layer 220b over the conductive layer 220a, the conductive layer 255 over the insulating layer 280a, the conductive layer 240a over the insulating layer 280b, the conductive layer 240b over the conductive layer 240a, the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250 over the oxide semiconductor layer 230, the conductive layer 265a over the insulating layers 250 and 285, and the conductive layer 265b over the conductive layer 265a.

[0299] Since the multilayer structure from the conductive layer 220a to the insulating layer 250 in the transistor 201 is similar to that in the transistor 200, the details thereof will not be described.

[0300] As in Fig. 8B and Fig. As shown in Figure 8C, an opening portion 270 reaching the insulating layer 250 is provided in the insulating layer 283 at a position overlapping with the opening portion 290. The conductive layer 265a is placed so as to be at least partially positioned in the opening portion 270. Furthermore, the conductive layer 265b may be placed so as to be at least partially positioned in the opening portion 270. The conductive layer 265a is in contact with the insulating layer 250 in the opening portion 270.

[0301] The conductive layer 265a is provided to fill at least a part of the opening portion 290 and the opening portion 270.

[0302] In the transistor of one embodiment of the present invention, at least one layer included in the conductive layer 265 is provided in the opening portions 290 and 270. In the case where the conductive layer 265 has a multi-layer structure, it becomes more difficult to place all the layers included in the conductive layer 265 in the opening portions 290 and 270 as the diameters of the opening portions 290 and 270 become smaller with the progress of miniaturization of the transistor. Fig. 8B and Fig. 8C illustrates an example in which the conductive layer 265 has a two-layer structure, only the conductive layer 265a is provided in the opening portion 290, and the conductive layers 265a and 265b are provided in the opening portion 270. Note that in some cases, both the conductive layer 265a and the conductive layer 265b are positioned in the opening portion 290 depending on the diameter of the opening portion 290, the thickness of the conductive layer 265a, and the like. In some cases, only the conductive layer 265a is positioned in the opening portion 270 depending on the diameter of the opening portion 270, the thickness of the conductive layer 265a, the thickness of the conductive layer 265b, and the like.

[0303] Portions of the conductive layers 265a and 265b that do not overlap with the opening portion 290 are positioned primarily over the insulating layer 285. Therefore, the conductive layer 265 primarily overlaps with the conductive layer 240, with the insulating layers 283 and 285 interposed therebetween. This can increase the physical distance between the conductive layers 265 and 240 and reduce the parasitic capacitance generated therebetween. Note that the conductive layers 240 and 265 may include a portion where they overlap with each other without the insulating layer 285 interposed therebetween.

[0304] Fig. 8B and Fig. 8C illustrates an example in which the width of the opening portion 270 is smaller than the width D of the opening portion 290. The width of the opening portion 270 is preferably as small as possible because the area where the conductive layers 240 and 265 overlap with each other without the insulating layer 285 intervening can be narrowed and the parasitic capacitance generated between the conductive layers 240 and 265 can be reduced. For example, the width of the opening portion 270 is preferably smaller than or equal to that of the opening portion 290.

[0305] It should be noted that the width of the opening portion 270 may be larger than that of the opening portion 290. For example, the width of the opening portion 270 is preferably smaller than that of the width of the short side of the conductive layer 265 (the maximum width of the conductive layer 265a and the conductive layer 265b in Fig. 8C). For example, the maximum width of the conductive layer 265 is preferably less than or equal to the width of the short side of the conductive layer 255 (the maximum width of the conductive layer 255 in the Y direction in Fig. 8E). Accordingly, the area of ​​the portion where the conductive layers 240 and 265 overlap with each other without the insulating layer 285 interposed therebetween can be sufficiently smaller than the area of ​​the portion where the conductive layers 240 and 265 overlap with each other with the insulating layer 285 interposed therebetween, so that the parasitic capacitance generated between the conductive layers 240 and 265 can be reduced.

[0306] That is, transistor 201 has a structure that reduces the parasitic capacitance generated between the source and drain electrodes and the gate line. Consequently, the frequency characteristics of a circuit including the transistor can be improved.

[0307] Although this embodiment describes the example in which the opening portion 270 has a circular shape in plan view, the present invention is not limited thereto. The shape that can be used for the opening portion 270 is similar to the shape that can be used for the opening portion 290 described above.

[0308] In some cases, the width of the opening portion 270 varies in the depth direction. Here, specifically, the maximum width of the opening portion 270 provided in the insulating layer 283 in a cross-sectional view is used as the width of the opening portion 270.

[0309] A hydrogen barrier insulating layer is preferably used as the insulating layer 283. In this case, hydrogen can be prevented from diffusing from above the insulating layer 283 into the oxide semiconductor layer 230. A silicon nitride film and a silicon nitride oxide film are suitable for the insulating layer 283 because they release few impurities (e.g., water and hydrogen) and are less likely to transmit oxygen and hydrogen.

[0310] As the insulating layer 283, it is particularly preferable to use a silicon nitride film formed by a sputtering method. A deposition gas in a sputtering method does not need to contain hydrogen-containing molecules; therefore, the hydrogen concentration in the insulating layer 283 can be reduced. When the insulating layer 283 is formed by a sputtering method, a high-density silicon nitride film can be obtained.

[0311] As the insulating layer 283, an insulating layer having a hydrogen trapping or fixing function can be used. With such a structure, hydrogen can be prevented from diffusing from above the insulating layer 283 into the oxide semiconductor layer 230, and hydrogen contained in the oxide semiconductor layer 230 can be trapped or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. Alumina, hafnium oxide, hafnium silicate, or the like can be used for the insulating layer 283.

[0312] The insulating layer 283 may have a multilayer structure consisting of an insulating layer with a hydrogen trapping or fixing function and a hydrogen insulating barrier layer. For example, a multilayer film of aluminum oxide and silicon nitride over the aluminum oxide may be used for the insulating layer 283.

[0313] The insulating layer 285 serves as an interlayer film and is therefore preferably formed using the low dielectric constant material described above. For example, the insulating layer 285 preferably comprises a silicon oxide film. [Transistor 201A]

[0314] Fig. 9A is a cross-sectional view of a semiconductor device including a transistor 201A.

[0315] Fig. 9A illustrates an example in which the sidewall of the opening portion 290 has a tapered shape. For the details of the case in which the sidewall of the opening portion 290 has a tapered shape, reference may be made to the description of the transistor 200A ( Fig. 4A) may be referred to. [Transistor 201B]

[0316] Fig. 9B is a cross-sectional view of a semiconductor device including a transistor 201B.

[0317] Transistor 201B differs from transistor 201 mainly in that insulating layer 235 has a two-layer structure. For details of the case where insulating layer 235 has a two-layer structure, refer to the description of transistor 200B ( Fig. 4B) may be referred to.

[0318] The mode and details of transistor 201 may be modified as in the case of transistor 200. In particular, transistor 201 may have a structure similar to that of any of transistors 200C to 200K. [Transistor 202]

[0319] Fig. 10A is a plan view of a semiconductor device including a transistor 202. Fig. 10B is a cross-sectional view taken along the dot-dash line A1-A2 in Fig. 10A. Fig. 10C is a cross-sectional view along the dotted line A3-A4 in Fig. 10A. Fig. 10D is a cross-sectional view along the dotted line A5-A6 in Fig. 10B and Fig. 10C. Fig. 10E is a cross-sectional view along the dashed line A7-A8 in Fig. 10B and Fig. 10C. Since the structures in Fig. 10D and Fig. 10E those in Fig. 2D and Fig. 2E, except that the conductive layer 265a is not provided but the conductive layer 260 is provided, the details thereof will not be described.

[0320] The Fig. 10A to Fig. The semiconductor device illustrated in Figure 10E includes the insulating layer 210 over a substrate (not shown), the transistor 202 over the insulating layer 210, the insulating layer 280a over the insulating layer 210, the insulating layer 280b over the insulating layer 280a, the insulating layer 283 over the insulating layer 250, the insulating layer 285 over the insulating layer 283, and the conductive layer 265 over the insulating layer 285. The insulating layer 210, the insulating layer 280a, the insulating layer 280b, the insulating layer 283, and the insulating layer 285 serve as interlayer films.

[0321] The transistor 202 includes the conductive layer 220a, the conductive layer 220b over the conductive layer 220a, the conductive layer 255 over the insulating layer 280a, the conductive layer 240a over the insulating layer 280b, the conductive layer 240b over the conductive layer 240a, the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250 over the oxide semiconductor layer 230, and the conductive layer 260 over the insulating layer 250. It should be noted that the conductive layer 265 can be considered a component of the transistor 202.

[0322] Conductive layer 260 serves as the gate electrode (first gate electrode) of transistor 202, and conductive layer 265 serves as the gate line. Conductive layer 260 can be formed using a material that can be used for conductive layer 265.

[0323] Since the multilayer structure from the conductive layer 220a to the insulating layer 230 in the transistor 202 is similar to that in the transistor 200, the details thereof will not be described.

[0324] As in Fig. 10B and Fig. As shown in Figure 10C, the opening portion 270 reaching the oxide semiconductor layer 230 is provided in the insulating layer 283 in a position overlapping with the opening portion 290. At least a portion of the components of the transistor 202 is placed in the opening portion 270. Specifically, the insulating layer 250 and the conductive layer 260 are at least partially placed in the opening portion 270. The insulating layer 250 is in contact with the oxide semiconductor layer 230 and the insulating layer 283 in the opening portion 270.

[0325] A portion of the insulating layer 250 placed in the opening portion 270 reflects the shape of the opening portion 270. Specifically, the insulating layer 250 is provided to cover the side wall of the opening portion 270 (the side surface of the insulating layer 283). Then, the conductive layer 260 is provided to fill at least a portion of a recessed portion of the insulating layer 250 that reflects the shape of the opening portion 270.

[0326] Since the conductive layer 260 does not overlap with the top surface of the conductive layer 240 in the transistor 202, the parasitic capacitance generated between the conductive layer 240 and the conductive layer 260 can be reduced. As shown in Fig. 10B and Fig. 10C, the maximum width of the conductive layer 260 is smaller than the width D of the opening portion 290 in the cross-sectional view. As described above, the maximum width of the conductive layer 260 is preferably smaller than the width D of the opening portion 290, in which case the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240 can be reduced. It should be noted that, for example, as shown in Fig. 10B or Fig. 10C, the relationship between the two widths in the semiconductor device of one embodiment of the present invention can be determined in a cross section parallel to the Z direction.

[0327] Fig. 10B and Fig. 10C illustrates an example in which the width of the opening portion 270 is equal to that of the opening portion 290 (equal to the width D). The width of the opening portion 270 is preferably less than or equal to that of the opening portion 290. This is preferable because the conductive layer 260 does not overlap with the top surface of the conductive layer 240, and therefore the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240 can be reduced.

[0328] Although this embodiment mainly describes the example in which the conductive layer 260 does not overlap with the upper surface of the conductive layer 240, the conductive layer 260 may include a portion that overlaps with the upper surface of the conductive layer 240. The overlap portion is preferably as small as possible because the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240 can be reduced. For example, the width of the opening portion 270 is preferably smaller than the width of the short side of the conductive layer 265 (the maximum width of the conductive layer 265 in Fig. 10C). For example, the maximum width of the conductive layer 265 is preferably less than or equal to the width of the short side of the conductive layer 255 (the maximum width of the conductive layer 255 in the Y direction in Fig. 10E).

[0329] The top surface of the conductive layer 260 is preferably at the same height or substantially at the same height as the top surface of the insulating layer 285. The conductive layer 265 is provided above the insulating layer 285, the insulating layer 283, and the conductive layer 260 and is in contact with the top surface of the conductive layer 260. The conductive layer 260 and the conductive layer 265 can be said to be electrically connected to each other. The insulating layer 283 and the insulating layer 285 are positioned between the conductive layer 265 and the conductive layer 240. This can increase the physical distance between the conductive layer 265 and the conductive layer 240 and reduce the parasitic capacitance generated therebetween.

[0330] That is, transistor 202 has a structure that reduces the parasitic capacitance generated between the source electrode, the drain electrode, and the gate electrode, and the parasitic capacitance generated between the source electrode, the drain electrode, and the gate line. Consequently, the frequency characteristics of a circuit using the transistor can be improved. [Transistor 202A]

[0331] Fig. 11A is a cross-sectional view of a semiconductor device including a transistor 202A.

[0332] Fig. 11A illustrates an example in which the sidewall of the opening portion 290 has a tapered shape. For the details of the case in which the sidewall of the opening portion 290 has a tapered shape, reference may be made to the description of the transistor 200A ( Fig. 4A) may be referred to. [Transistor 202B]

[0333] Fig. 11B is a cross-sectional view of a semiconductor device including a transistor 202B.

[0334] Transistor 202B differs from transistor 202 mainly in that insulating layer 235 has a two-layer structure. For details of the case where insulating layer 235 has a two-layer structure, refer to the description of transistor 200B ( Fig. 4B) may be referred to.

[0335] The mode and details of transistor 202 may be modified as in the case of transistor 200. In particular, transistor 202 may have a structure similar to that of any of transistors 200C to 200K. [Transistor 203]

[0336] Fig. 12A is a plan view of a semiconductor device including a transistor 203. Fig. 12B is a cross-sectional view taken along the dot-dash line A1-A2 in Fig. 12A. Fig. 12C is a cross-sectional view along the dotted line A3-A4 in Fig. 12A. Fig. 12D is a cross-sectional view along the dotted line A5-A6 in Fig. 12B and Fig. 12C. Fig. 12E is a cross-sectional view along the dashed line A7-A8 in Fig. 12B and Fig. 12C. Since the structures in Fig. 12D and Fig. 12E those in Fig. 2D and Fig. 2E, except that the conductive layer 265a is not provided but the conductive layer 260 is provided, the details thereof will not be described.

[0337] The Fig. 12A to Fig. The semiconductor device illustrated in Figure 12E includes the insulating layer 210 over a substrate (not shown), the transistor 203 over the insulating layer 210, the insulating layer 280a over the insulating layer 210, the insulating layer 280b over the insulating layer 280a, the insulating layer 285 over the insulating layer 250, the conductive layer 265a over the insulating layer 285, and the conductive layer 265b over the conductive layer 265a. The insulating layer 210, the insulating layer 280a, the insulating layer 280b, and the insulating layer 285 serve as interlayer films.

[0338] The transistor 203 includes the conductive layer 220a, the conductive layer 220b over the conductive layer 220a, the conductive layer 255 over the insulating layer 280a, the conductive layer 240a over the insulating layer 280b, the conductive layer 240b over the conductive layer 240a, the insulating layer 235, the oxide semiconductor layer 230, the insulating layer 250 over the oxide semiconductor layer 230, and the conductive layer 260 over the insulating layer 250. Note that the conductive layer 265a and the conductive layer 265b can each be considered a component of the transistor 203.

[0339] The conductive layer 260 serves as the gate electrode (first gate electrode) of the transistor 203, and the conductive layer 265a and the conductive layer 265b serve as the gate line. The conductive layer 260 can be formed using a material that can be used for the conductive layer 265.

[0340] Since the multilayer structure from the conductive layer 220a to the insulating layer 250 in the transistor 203 is similar to that in the transistor 200, the details thereof will not be described.

[0341] As in Fig. 12B and Fig. 12C, the transistor 203 includes the conductive layer 260 over the insulating layer 250. The conductive layer 260 is provided to fill the opening portion 290. The conductive layer 260 included in the transistor 203 may be referred to as a conductive layer having a shape different from that of the conductive layer 265a included in the transistor 200. The conductive layer 260 extends neither in the X direction nor in the Y direction. The width of the conductive layer 260 is preferably small in both the X direction and the Y direction. Therefore, the area of ​​a portion of the conductive layer 260 that overlaps with the top surface of the conductive layer 240 can be reduced, so that the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240 can be reduced.

[0342] Fig. 12B and Fig. 12C illustrates an example in which the maximum width of the conductive layer 260 is smaller than the width D of the opening portion 290. In this way, the maximum width of the conductive layer 260 is preferably less than or equal to the width of the opening portion 290.

[0343] It should be noted that the maximum width of the conductive layer 260 may be greater than the width of the opening portion 290. For example, the maximum width of the conductive layer 260 is preferably less than or equal to the width of the short side of the conductive layer 265 (the maximum width of the conductive layer 265a and the conductive layer 265b in Fig. 12C). For example, the maximum width of the conductive layer 260 is preferably less than or equal to the width of the short side of the conductive layer 255 (the maximum width of the conductive layer 255 in the Y direction in Fig. 12E). Therefore, the area of ​​the portion where the conductive layer 260 and the conductive layer 240 overlap with each other can be sufficiently small, and accordingly, the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240 can be reduced.

[0344] As in Fig. 12B and Fig. As shown in Fig. 12C, the opening portion 270 reaching the conductive layer 260 is provided in the insulating layer 285 at a position overlapping with the opening portion 290. The conductive layer 265a is placed so as to be at least partially positioned in the opening portion 270. Furthermore, the conductive layer 265b may be placed so as to be at least partially positioned in the opening portion 270. The conductive layer 265a is in contact with the conductive layer 260 in the opening portion 270. It can be said that the conductive layer 260 and the conductive layer 265 are electrically connected to each other.

[0345] The conductive layer 265a is provided to fill at least a portion of the opening portion 270. The conductive layer 265b may be provided to fill a portion of the opening portion 270.

[0346] In the transistor of one embodiment of the present invention, at least one layer included in the conductive layer 265 is provided in the opening portion 270. In the case where the conductive layer 265 has a multi-layer structure, it becomes more difficult to place all the layers included in the conductive layer 265 in the opening portion 270 as the diameter of the opening portion 270 becomes smaller with the progress of miniaturization of the transistor. Fig. 12B and Fig. 12C illustrates an example in which the conductive layer 265 has a two-layer structure, and the conductive layer 265a and the conductive layer 265b are provided in the opening portion 270. Note that in some cases, only the conductive layer 265a is positioned in the opening portion 270 depending on the diameter of the opening portion 270, the thickness of the conductive layer 265a, the thickness of the conductive layer 265b, and the like.

[0347] Portions of the conductive layers 265a and 265b that do not overlap with the opening portion 290 are positioned primarily over the insulating layer 285. Therefore, the conductive layer 265 primarily overlaps with the conductive layer 240, with the insulating layer 285 interposed therebetween. This can increase the physical distance between the conductive layers 265 and 240 and reduce the parasitic capacitance generated therebetween. Note that the conductive layers 240 and 265 may include a portion where they overlap with each other without the insulating layer 285 interposed therebetween.

[0348] Fig. 12B and Fig. 12C illustrates an example in which the width of the opening portion 270 is smaller than the width D of the opening portion 290. The width of the opening portion 270 is preferably as small as possible because the area where the conductive layers 240 and 265 overlap with each other without the insulating layer 285 intervening can be narrowed and the parasitic capacitance generated between the conductive layers 240 and 265 can be reduced. For example, the width of the opening portion 270 is preferably smaller than or equal to that of the opening portion 290.

[0349] It should be noted that the width of the opening portion 270 may be larger than that of the opening portion 290. For example, the width of the opening portion 270 is preferably smaller than the width of the short side of the conductive layer 265 (the maximum width of the conductive layer 265a and the conductive layer 265b in Fig. 12C). For example, the maximum width of the conductive layer 265 is preferably less than or equal to the width of the short side of the conductive layer 255 (the maximum width of the conductive layer 255 in the Y direction in Fig. 12E). Accordingly, the area of ​​the portion where the conductive layers 240 and 265 overlap with each other without the insulating layer 285 interposed therebetween can be sufficiently smaller than the area of ​​the portion where the conductive layers 240 and 265 overlap with each other with the insulating layer 285 interposed therebetween, so that the parasitic capacitance generated between the conductive layers 240 and 265 can be reduced.

[0350] That is, transistor 203 has a structure that reduces the parasitic capacitance generated between the source and drain electrodes and the gate line. Consequently, the frequency characteristics of a circuit using the transistor can be improved. [Transistor 203A]

[0351] Fig. 13A is a cross-sectional view of a semiconductor device including a transistor 203A.

[0352] Fig. 13A illustrates an example in which the sidewall of the opening portion 290 has a tapered shape. For the details of the case in which the sidewall of the opening portion 290 has a tapered shape, reference may be made to the description of the transistor 200A ( Fig. 4A) may be referred to. [Transistor 203B]

[0353] Fig. 13B is a cross-sectional view of a semiconductor device including a transistor 203B.

[0354] Transistor 203B differs from transistor 203 mainly in that insulating layer 235 has a two-layer structure. For details of the case where insulating layer 235 has a two-layer structure, refer to the description of transistor 200B ( Fig. 4B) may be referred to.

[0355] The mode and details of transistor 203 may be modified as in the case of transistor 200. In particular, transistor 203 may have a structure similar to that of any of transistors 200C to 200K. [Transistors 203C and 203D]

[0356] Fig. 14A is a cross-sectional view of a semiconductor device including a transistor 203C. Fig. 14B is a cross-sectional view of a semiconductor device including a transistor 203D.

[0357] The transistor 203C differs from the transistor 203 mainly in that an insulating layer 285a and an insulating layer 285b are provided instead of the insulating layer 285.

[0358] Transistor 203C and transistor 203D differ from transistor 203 primarily in that the top surface of conductive layer 260 is flat.

[0359] As described above, the top surface of the conductive layer 260 may be planarized. The top surface of the conductive layer 260 is preferably at the same height or substantially at the same height as the top surface of the insulating layer 285a. [Transistor 203E]

[0360] Fig. 14C1 and Fig. 14C2 are cross-sectional views of a semiconductor device including a transistor 203E.

[0361] Transistor 203E differs from transistor 203 primarily in that conductive layer 260 includes a portion that overlaps the top surface of conductive layer 240b.

[0362] As described above, the conductive layer 260 may include a portion overlapping with the conductive layer 240. On the other hand, it is preferable that the conductive layer 265 serving as a gate line is additionally provided, and the insulating layer 285 is provided between the conductive layers 265 and 240. This can increase the physical distance between the conductive layers 265 and 240 and reduce the parasitic capacitance generated between the gate line and the conductive layer 240. [Region containing a halogen element and region containing a first element]

[0363] In the semiconductor device of one embodiment of the present invention, at least one of the side surface of the insulating layer 280a on the opening portion 290 side and its vicinity, the side surface of the insulating layer 280b on the opening portion 290 side and its vicinity, the insulating layer 235, and the oxide semiconductor layer 230 may include a region containing a halogen element.

[0364] The halogen element is preferably one or more selected from chlorine, fluorine, bromine, and iodine, and more preferably chlorine or fluorine. Regarding the substitution of oxygen, fluorine, which has a higher electronegativity than oxygen, is preferably used.

[0365] When the insulating layer 280a, the insulating layer 280b, or the insulating layer 235 contains a halogen element, the halogen element can be supplied to the oxide semiconductor layer 230. The halogen element (X) has a function of generating an electron serving as a charge carrier by converting the halogen element into an oxygen vacancy (V O ) in the oxide semiconductor layer 230 to form a defect (V O X). For example, in the case where chlorine (Cl) is used as a halogen element, Cl exists stably in a state of V O Cl in the oxide semiconductor layer 230 (particularly at and near the interface between the insulating layer 235 and the oxide semiconductor layer 230). Cl may be in the state of V O Cl by not only inserting it into an existing V O occurs, but also substitutes oxygen.

[0366] In contrast, oxygen substituted by Cl (also called excess oxygen) has an electron-capturing function. Furthermore, the capture of charge carriers by oxygen takes precedence over the generation of charge carriers by V. O Cl. Therefore, a negative charge (also referred to as a negative fixed charge) is formed at and near the interface between the insulating layer 235 and the oxide semiconductor layer 230. When a negative charge is present in the channel formation region, the threshold voltage of the transistor can be positively shifted. Therefore, even if the transistor has a fine structure or a very short channel length, the transistor can exhibit normally off behavior.

[0367] As described above, the transistor of one embodiment of the present invention can exhibit a normally off behavior not only by controlling the threshold voltage with a back gate but also by using a halogen element.

[0368] In the semiconductor device of one embodiment of the present invention, the source region and the drain region of the oxide semiconductor layer 230 preferably contain an impurity element. A first element is preferably used as the impurity element. Alternatively, the first element and hydrogen are each preferably used as the impurity element. It is particularly preferable that the oxide semiconductor layer 230 contains the impurity element in the above-described region 230n. + contains (see Fig. 3).

[0369] It should be noted that at least one of the conductive layers 240a, 240b, 220a and 220b may also contain the impurity element.

[0370] As the first element, one or more of boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium and a noble gas (helium, neon, argon, krypton, xenon and the like) is preferably used.

[0371] The first element is not limited to the above elements, and one or more of first transition elements (3d transition elements or 3d transition metals), second transition elements (4d transition elements or 4d transition metals), third transition elements (5d transition elements or 5d transition metals), alkaline earth metal elements, and rare earth elements may be used.

[0372] When the first element is supplied to the source region and the drain region, the first element, for example, removes oxygen from these regions and therefore creates an oxygen vacancy therein. The oxygen vacancy is then bonded to hydrogen in the film, so that a charge carrier is generated, and the resistances of the source region and the drain region can be reduced. As a result, the sheet resistance of the oxide semiconductor layer 230, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced. As a result, the on-state current of the transistor can be increased. The increased on-state current can lower the operating voltage of the transistor. This can reduce the power consumption of the semiconductor device.

[0373] In the case where an element that is easily bonded to oxygen is used as the first element, the first element is in a state where it is bonded to oxygen in the semiconductor layer. Further, when an element stabilized by bonding to oxygen is used as the first element, the first element is stably in an oxidized state in the semiconductor layer and is therefore not easily released by heat or the like applied during the manufacturing process of the semiconductor device, thereby enabling a low-resistance region that is stable in a low electrical resistance state. Therefore, an element whose oxide can exist as a solid at 25°C and under a pressure of 1 atmosphere is preferably used as the first element.As the first element, a typical non-metallic element other than hydrogen, a typical metallic element, and a transition element (transition metal) are particularly preferred, and as the first element, boron, phosphorus, magnesium, aluminum, and silicon are particularly preferred.

[0374] Therefore, boron, phosphorus, magnesium, aluminum, or silicon is preferably used as the first element. In particular, boron or phosphorus is preferably used as the first element.

[0375] Furthermore, hydrogen, in addition to the function of generating an oxygen vacancy, has a function of being bonded to an oxygen vacancy, and therefore it is suitable as an impurity element.

[0376] When the first element and hydrogen are each used as an impurity element, the electrical resistances of the source and drain regions of the oxide semiconductor layer 230 are slightly reduced, and a low electrical resistance state can be stably maintained.

[0377] Both the first element and hydrogen are preferably added because ions generated from the source gases can be added without mass separation, thus increasing productivity. For example, when a B2H6 gas is used, boron and hydrogen can be added as impurity elements. As another example, when a PH3 gas is used, phosphorus and hydrogen can be added as impurity elements. Note that the method for adding the impurity element is not limited to this. For example, a specific element can be added by ionizing a source gas and then subjecting the ion to mass separation. For example, boron can be added after mass separation of an ionized B2H6 gas.

[0378] It should be noted that in some cases, the impurity element is also supplied to the channel formation region of the oxide semiconductor layer 230. Alternatively, the above impurity element diffused in the region 230n + or area 230 - contained, in some cases, for example, as a result of the influence of heat applied during the manufacturing process, partially into the channel formation region (the region 230i).

[0379] In manufacturing the semiconductor device of one embodiment of the present invention, an impurity element is preferably added more easily to the source and drain regions of the oxide semiconductor layer 230 than to the channel formation region. Therefore, the impurity element is preferably added from a direction perpendicular or substantially perpendicular to the upper surface of the substrate. At this time, in the oxide semiconductor layer 230, the amount of the added impurity element is smaller in a surface inclined to the upper surface of the substrate than in a surface parallel or substantially parallel to the upper surface of the substrate. That is, in the oxide semiconductor layer 230, the amount of the added impurity element is larger in the source and drain regions than in the channel formation region. Thus, the resistances of the source and drain regions can be primarily reduced. <Beispiel für ein Herstellungsverfahren der Halbleitervorrichtung>

[0380] Next, a method of manufacturing the semiconductor device of an embodiment of the present invention will be described with reference to Fig. 15A1 to Fig. 15E, Fig. 16A to Fig. 16C, Fig. 17A to Fig. 17F, Fig. 18A to Fig. 18F and Fig. 19A to Fig. 19D. Note that, with respect to a material and a forming method of each component, portions similar to those described in the above embodiment will not be described in some cases.

[0381] It should be noted that thin films included in the semiconductor device (e.g., insulating films, semiconductor films, and conductive films) can be formed by any of the following methods: a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, and the like.

[0382] Examples of the sputtering method include an RF sputtering method in which a high-frequency power source is used as the sputtering power source, a DC sputtering method in which a DC power source is used, and a pulsed DC sputtering method in which a voltage is applied to an electrode while changing it in a pulsed manner. The RF sputtering method is mainly used in the case where an insulating film is formed, and the DC sputtering method is mainly used in the case where a conductive metal film is formed. The pulsed DC sputtering method is mainly used in the case where a film of a compound such as an oxide, a nitride, or a carbide is formed by a reactive sputtering method.

[0383] It should be noted that CVD processes can be divided into plasma-enhanced CVD (PECVD) processes that use plasma, thermal CVD (TCVD) processes that use heat, photo-CVD processes that use light, and the like. Furthermore, depending on the source gas, CVD processes can be divided into metal-organic CVD (MCVD) processes and metal-organic CVD (MOCVD).

[0384] A PECVD process can produce a high-quality film at a relatively low temperature. A thermal CVD process does not use plasma and therefore causes less plasma damage to a subject. For example, a wire, electrode, element (e.g., a transistor or capacitor), or the like included in a semiconductor device may become charged by receiving charges from the plasma. In this case, the accumulated charges could damage the wire, electrode, element, or the like included in the semiconductor device. A thermal CVD process that does not use plasma causes no such damage and can therefore increase the yield of the semiconductor device. A thermal CVD process produces a film with few defects because there is no plasma damage during deposition.

[0385] As the ALD method, a thermal ALD method in which a precursor and a reactant react with each other only by thermal energy, a PEALD method in which a reactant excited by plasma is used, or the like can be used.

[0386] It should be noted that some precursors used in the ALD process contain an element such as carbon or chlorine. Therefore, in some cases, a film formed by the ALD process contains a larger amount of an element such as carbon or chlorine than a film formed by a different film formation method. It should be noted that these elements can be quantified by XPS or SIMS. The metal oxide formation method of one embodiment of the present invention, which uses an ALD process and a high substrate temperature deposition condition and / or an impurity removal treatment, could form a film with smaller amounts of carbon and chlorine than a method using an ALD process and neither the condition nor the treatment.

[0387] Unlike a film formation method that deposits particles emitted from a target or the like, an ALD method forms a film by a reaction on the surface of an object to be processed. Therefore, an ALD method is less likely to be affected by the shape of an object, and thus enables favorable step coverage. In particular, an ALD method enables excellent step coverage and excellent thickness uniformity, and can be suitably used, for example, to cover the surface of an opening portion with a high aspect ratio.

[0388] A CVD method and an ALD method are different from a sputtering method, which deposits particles emitted from a target or the like. Therefore, a CVD method and an ALD method are less likely to be affected by the shape of an object and therefore enable favorable step coverage. In particular, for example, an ALD method can provide excellent step coverage and excellent thickness uniformity and can therefore be suitably used for covering a surface of an opening portion with a high aspect ratio. Note that an ALD method has a relatively low deposition rate, so in some cases, an ALD method is preferably combined with another high-rate deposition method, such as a CVD method.

[0389] By a CVD method, a film with a specific composition can be formed by regulating the flow rate ratio of the source gases. For example, by a CVD method, a film whose composition gradually changes can be formed by changing the flow rate ratio of the source gases during deposition. In the case where a film is formed while changing the flow rate ratio of the source gases, the deposition time can be reduced compared to the case where a film is formed using a plurality of deposition chambers because the time for transferring and regulating pressure is omitted. Therefore, the productivity of the semiconductor device can be improved in some cases.

[0390] An ALD process in which a plurality of different types of precursors are introduced simultaneously enables the formation of a film with the desired composition. In the case where a plurality of different types of precursors are introduced, the number of cycles of precursor deposition is controlled, allowing the formation of a film with the desired composition.

[0391] Alternatively, thin films included in the semiconductor device (e.g., insulating films, semiconductor films, and conductive films) may be formed by a wet method such as a spin coating method, a dip coating method, a spray coating method, an inkjet method, dispensing, screen printing, offset printing, doctor blade coating, gap coating, roll coating, curtain coating, or doctor blade coating.

[0392] When processing thin films included in the semiconductor device, a photolithography method or the like can be used. Alternatively, the thin films can be processed by a nanoimprinting method, a sandblasting method, a lift-off method, or the like. Alternatively, island-shaped thin films can be directly formed by a film formation method using a shielding mask, such as a metal mask.

[0393] There are two typical examples of photolithography processes. In one of the processes, a photoresist mask is formed over a thin film to be processed, the thin film is processed by etching or the like, and then the photoresist mask is removed. In the other process, a photosensitive thin film is formed and then processed into a desired shape by exposure and development.

[0394] For exposure light in a photolithography process, i-line light (wavelength: 365 nm), g-line light (wavelength: 436 nm), h-line light (wavelength: 405 nm), or light in which the i-line, g-line, and h-line are mixed can be used. Alternatively, ultraviolet light, KrF laser light, ArF laser light, or the like can be used. Exposure can be performed by a liquid immersion exposure technique. Extreme ultraviolet (EUV) light or X-rays can also be used as exposure light. Furthermore, an electron beam can be used instead of exposure light. It is preferable to use EUV, X-rays, or an electron beam because very fine processing can be performed. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0395] To etch thin films, a dry etching method, a wet etching method, a sandblasting method, or the like can be used. [Example of a manufacturing process of the transistor 200]

[0396] An example of a method for manufacturing the semiconductor device including the transistor 200 (see Fig. 2A1 to Fig. 2E and Fig. 3), is based on Fig. 15A1 to Fig. 15E and Fig. 16A to Fig. 16C described.

[0397] First, as in Fig. 15A1 and Fig. 15A2, the insulating layer 210 is formed over a substrate (not shown), the conductive layer 220a is formed over the insulating layer 210, the conductive layer 220b is formed over the conductive layer 220a, the insulating layer 280a is formed over the conductive layer 220b, and the conductive layer 255 is formed over the insulating layer 280a.

[0398] Note that a planarization treatment is preferably performed after the formation of the insulating layer 280a to planarize the upper surface of the insulating layer 280a. As the planarization treatment, a planarization treatment using a chemical mechanical polishing (CMP) method (also referred to as CMP treatment) is suitable. Alternatively, a planarization treatment using etching (also referred to as etch-back treatment) may be performed. The planarization treatment performed on the insulating layer 280a can planarize the formation surface of the conductive layer 255, thereby preventing separation of the conductive layer 255. Note that the planarization treatment is not necessarily performed, in which case, the manufacturing cost can be reduced.

[0399] Next, as in Fig. 15B, the insulating layer 280b is formed over the conductive layer 255, the conductive layer 240a is formed over the insulating layer 280b, and the conductive layer 240b is formed over the conductive layer 240a.

[0400] Next, as in Fig. 15C, the opening portion 290 is formed in the conductive layer 240b, the conductive layer 240a, the insulating layer 280b, the conductive layer 255, and the insulating layer 280a at a position overlapping with the conductive layer 220a. At this time, a recessed portion is preferably provided in the conductive layer 220b at a position overlapping with the opening portion 290. By forming the opening portion 290, the bottom surface and the side surface of the recessed portion of the conductive layer 220b are preferably exposed.

[0401] For microstructuring and a small size of the transistor, when forming the opening portion 290, a part of the conductive layer 220b, a part of the conductive layer 240a, a part of the conductive layer 240b, a part of the conductive layer 255, a part of the insulating layer 280a, and a part of the insulating layer 280b are preferably processed using anisotropic etching. It is particularly preferable to use a dry etching method because it is suitable for microstructuring. The opening portion 290 can be formed under processing conditions that differ between layers.Note that the side surface of the recessed portion of the conductive layer 220b and the side surfaces of the conductive layer 240a, the conductive layer 240b, the conductive layer 255, the insulating layer 280a, and the insulating layer 280b in the opening portion 290 may have different inclinations depending on the materials, processing conditions, and the like for the conductive layer 220b, the conductive layer 240a, the conductive layer 240b, the conductive layer 255, the insulating layer 280a, and the insulating layer 280b.

[0402] In the step of forming the opening portion 290 or the like, a region containing a halogen element is provided in some cases in at least one of the bottom surface and the side surface of the recessed portion of the conductive layer 220b, the side surface of the insulating layer 280a, the side surface of the insulating layer 280b, the side surface of the insulating layer 255, the side surface of the conductive layer 240a, and the top surface and the side surface of the conductive layer 240b. Examples of the region include a region containing fluorine, a region containing chlorine, and a region containing fluorine and chlorine. In some cases, for example, a halogen element derived from an etching gas used in dry etching remains in the region.

[0403] Next, a heat treatment can be performed. The heat treatment is performed, for example, at temperatures greater than or equal to 250°C and less than or equal to 650°C, preferably greater than or equal to 300°C and less than or equal to 500°C, more preferably greater than or equal to 320°C and less than or equal to 450°C.

[0404] It should be noted that the heat treatment is carried out in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. For example, in the case where the heat treatment is carried out in a mixed atmosphere of a nitrogen gas and an oxygen gas, the proportion of the oxygen gas is preferably about 20%. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out in the following manner: A heat treatment is carried out in an atmosphere of a nitrogen gas or an inert gas, and then another heat treatment is carried out in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more to compensate for released oxygen. By the above-described heat treatment, impurities such aswater contained in the insulating layer 280a, the insulating layer 280b and the like, before the semiconductor layer 230 is formed.

[0405] The gas used in the above heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the above heat treatment is preferably less than or equal to 1 ppb, more preferably less than or equal to 0.1 ppb, and even more preferably less than or equal to 0.05 ppb. For example, heat treatment using a highly purified gas can prevent moisture from penetrating the insulating layer 280a, the insulating layer 280b, and the like as much as possible.

[0406] Next, as in Fig. 15D, the insulating layer 235 is formed to cover the opening portion 290. The insulating layer 235 is provided in contact with the bottom and side surfaces of the recessed portion of the conductive layer 220b, the side surfaces of the insulating layer 280a, the side surfaces of the conductive layer 255, the side surfaces of the insulating layer 280b, the side surfaces of the conductive layer 240a, and the top and side surfaces of the conductive layer 240b.

[0407] The insulating layer 235 is provided in the opening portion 290 and is therefore preferably formed by a CVD method or an ALD method, more preferably by an ALD method. In such a case, the insulating layer 235 can be provided with good coverage.

[0408] Next, as in Fig. 15E, the insulating layer 235 is processed such that the top surface of the conductive layer 240b is exposed and the conductive layer 220b is exposed in the opening portion 290. Preferably, the bottom surface of the recessed portion of the conductive layer 220b is exposed in the opening portion 290.

[0409] When the insulating layer 235 is processed by anisotropic etching, a portion of the insulating layer 235 positioned at the top of the conductive layer 240b and a portion of the insulating layer 235 positioned at the bottom of the opening portion 290 are removed, so that the insulating layer 235 can remain only on the side surface of the opening portion 290. The insulating layer 235 is preferably processed by anisotropic etching using a dry etching method.

[0410] It should be noted that, as in Fig. 15E, a portion of the conductive layer 220b may be removed during processing of the insulating layer 235 to provide a recessed portion in the conductive layer 220b.

[0411] Next, as in Fig. 16A, the oxide semiconductor layer 230 is formed to cover the opening portion 290. The oxide semiconductor layer 230 is provided in contact with the bottom surface and the side surface of the recessed portion of the conductive layer 220b, the insulating layer 235, and the top surface of the conductive layer 240b.

[0412] The oxide semiconductor layer 230 can be formed, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0413] The formed oxide semiconductor layer 230 is preferably a film with a thickness as uniform as possible along the bottom and side surfaces of the recessed portion of the conductive layer 220b, the insulating layer 235, and the top surface of the conductive layer 240b. Using an ALD method enables the formation of a thin film with high controllability. Therefore, the oxide semiconductor layer 230 is preferably formed by an ALD method.

[0414] Furthermore, when the oxide semiconductor layer 230 has high crystallinity, diffusion of impurities in the oxide semiconductor layer 230 is prevented, resulting in low fluctuations in electrical properties and high reliability of the transistor. The oxide semiconductor layer 230 is preferably formed by a sputtering method, in which case a layer with high crystallinity can be easily obtained compared to the case of using an ALD method.

[0415] In the case where the oxide semiconductor layer 230 is formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen in the sputtering gas, the amount of excess oxygen contained in the oxide films to be formed can be increased. Furthermore, when the oxide films are formed by a sputtering method, a target made of In-M-Zn oxide, for example, can be used.

[0416] In the case where the oxide semiconductor layer 230 is formed by a sputtering method, and the oxygen content in the sputtering gas is higher than 30% and lower than or equal to 100%, preferably higher than or equal to 70% and lower than or equal to 100%, an oxygen-excessive oxide semiconductor is formed. A transistor containing an oxygen-excessive oxide semiconductor in a channel formation region can have relatively high reliability. However, an embodiment of the present invention is not limited thereto. When the oxygen content in the sputtering gas is higher than or equal to 1% and lower than or equal to 30%, preferably higher than or equal to 5% and lower than or equal to 20%, an oxygen-deficient oxide semiconductor is formed. A transistor containing an oxygen-deficient oxide semiconductor in a channel formation region can have relatively high field-effect mobility.In addition, if the oxide semiconductor layer is formed while heating the substrate, the crystallinity of the oxide semiconductor layer can be increased.

[0417] For a manufacturing method of the oxide semiconductor layer, reference may be made to the description in Embodiment 3.

[0418] Next, a heat treatment is preferably performed. The heat treatment is preferably performed in a temperature range in which the oxide semiconductor layer 230 does not become a polycrystal. For example, the heat treatment temperature is preferably higher than or equal to 100°C and lower than or equal to 650°C, more preferably higher than or equal to 250°C and lower than or equal to 600°C, and even more preferably higher than or equal to 350°C and lower than or equal to 550°C. For details of the heat treatment, reference can be made to the above description.

[0419] The gas used in the above heat treatment is preferably highly purified. When the heat treatment is performed using a highly purified gas, for example, the penetration of moisture or the like into the oxide semiconductor layer 230 can be prevented as much as possible.

[0420] In this embodiment, heat treatment is performed at 450°C for one hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. By performing the heat treatment using the above-described oxygen gas, impurities such as carbon, water, and hydrogen in the oxide semiconductor layer 230 can be reduced. Impurities in the film are reduced in the above manner, whereby the crystallinity of the oxide semiconductor layer 230 can be improved and a dense structure can be obtained. Consequently, the crystal area in the oxide semiconductor layer 230 can be expanded, and the in-plane deviation of the crystal area in the oxide semiconductor layer 230 can be reduced. Therefore, the in-plane deviation of the electrical characteristics of the transistor can be reduced.

[0421] In the case where at least one of the insulating layers 280a, 280b, and 235 contains oxygen, oxygen is preferably supplied from the insulating layer containing oxygen to the channel formation region of the oxide semiconductor layer 230 through the heat treatment. Thus, oxygen vacancies and V O H can be reduced.

[0422] In this way, oxygen (also referred to as excess oxygen) released by heating from the insulating layer in contact with or around the oxide semiconductor layer 230 is sometimes supplied to the oxide semiconductor layer 230. Since excess oxygen has a function of trapping electrons, a negative charge is likely to be generated. Consequently, the threshold voltage of the transistor can be positively shifted to achieve a normally-off transistor.

[0423] Next, as in Fig. 16B, the oxide semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b are processed into island shapes, exposing a portion of the upper surface of the insulating layer 280b. The oxide semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b can be processed using the same mask. This is preferred because the number of masks required to manufacture the semiconductor device can be reduced.

[0424] Next, as in Fig. 16C, the insulating layer 250 is formed to cover the opening portion 290, and the conductive layer 265a is formed over the insulating layer 250. Further, the conductive layer 265b is formed over the conductive layer 265a. The insulating layer 250 is provided in contact with the oxide semiconductor layer 230. The conductive layer 265a is preferably provided to fill the opening portion 290. Note that in some cases, the conductive layer 265b is also provided in the opening portion 290 depending on the diameter of the opening portion 290, the thickness of the conductive layer 265a, and the like.

[0425] The insulating layer 250 and the conductive layer 265a are each formed in the opening portion 290 with a high aspect ratio. Therefore, the insulating layer 250 and the conductive layer 265a are preferably formed by a film formation method with a favorable coverage, more preferably by a CVD method, an ALD method, or the like.

[0426] In this way, the transistor 200 can be manufactured. [Example of a manufacturing process of transistor 201]

[0427] An example of a method for manufacturing the semiconductor device including the transistor 201 (see Fig. 8A to Fig. 8E), is based on Fig. 17A to Fig. 17F. Detailed descriptions of steps similar to those of the example of the manufacturing method of the transistor 200 are omitted.

[0428] First, the steps in Fig. 15A1 to Fig. 16B as in the example of the manufacturing method of the transistor 200. Next, as in Fig. 17A, the insulating layer 250 is formed to cover the insulating layer 280b, the conductive layer 240a, the conductive layer 240b, and the oxide semiconductor layer 230.

[0429] A sacrificial layer 262 is then formed over the insulating layer 250. A spin-on carbon (SOC) film and a spin-on glass (SOG) film are suitable as the sacrificial layer 262. For example, the sacrificial layer 262 preferably has a two-layer structure consisting of an SOC film and an SOG film over the SOC film.

[0430] The sacrificial layer 262 is preferably provided over and in contact with the insulating layer 250, in which case, damage to the oxide semiconductor layer 230 in the manufacturing process of the semiconductor device can be reduced compared to the case where the sacrificial layer 262 is provided over and in contact with the oxide semiconductor layer 230. In contrast, in the case where, as in a manufacturing method of the transistor 202 to be described below, the sacrificial layer 262 is provided over and in contact with the oxide semiconductor layer 230, damage to the insulating layer 250 in the manufacturing process of the semiconductor device can be reduced, which is preferable.It should be noted that in the case where the insulating layer 250 has a multi-layer structure, some of the layers included in the insulating layer 250 may be formed before the formation of the sacrificial layer 262, and the other layer(s) may be formed after the removal of the sacrificial layer 262.

[0431] Next, as in Fig. 17B, ​​a portion of the sacrificial layer 262 is removed. A gate electrode (the conductive layer 265a and the conductive layer 265b) is provided in a later step in a region where the sacrificial layer 262 remains. Therefore, it is preferable that only a small area of ​​the sacrificial layer 262 overlaps with the top surface of the conductive layer 240b, and it is more preferable that the sacrificial layer 262 does not overlap with the top surface of the conductive layer 240b. As shown in Fig. 17B, ​​the maximum width of the sacrificial layer 262 is preferably smaller than the width D of the opening portion 290 in a cross-sectional view.

[0432] Next, as in Fig. 17C, the insulating layer 283 is formed to cover the insulating layer 250 and the sacrificial layer 262, and the insulating layer 285 is formed over the insulating layer 283.

[0433] When the insulating layer 285 is formed thick, the distance between the conductive layer 240b and the conductive layer 265a can be increased, so that the parasitic capacitance generated between the conductive layer 240b and the gate electrode (or gate line) can be reduced.

[0434] For example, as the insulating layer 285, a silicon oxide film is preferably formed by a sputtering method.

[0435] Here, in the case where the insulating layer 283 is not provided, the sacrificial layer 262 is exposed to an oxygen-containing plasma when forming a silicon oxide film as the insulating layer 285 by a sputtering method, so that in some cases, part or all of the sacrificial layer 262 is etched. As described above, the sacrificial layer 262 may shrink or disappear depending on the formation method of the insulating layer 285. For this reason, the insulating layer formed over the sacrificial layer 262 preferably has not a single-layer structure of the insulating layer 285, but a multi-layer structure of the insulating layer 283 and the insulating layer 285.Thereby, the following effects can be achieved: selection options of materials for the sacrificial layer 262 and the insulating layer 285 can be increased, the difficulty in manufacturing the semiconductor device can be reduced, and the like.

[0436] In the case where an oxide film is used as the insulating layer 283, the oxide film is preferably formed by a method other than a sputtering method, such as an ALD method. For example, an aluminum oxide film or a hafnium oxide film is preferably formed as the insulating layer 283 by an ALD method. Alternatively, a nitride film (e.g., a silicon nitride film) is preferably used as the insulating layer 283. Therefore, the sacrificial layer 262 can be prevented from being inadvertently processed during the formation of the insulating layer 283 and the insulating layer 285.

[0437] The insulating layer 283 is preferably formed by a CVD method or an ALD method, more preferably by an ALD method. In such a case, the insulating layer 283 can be provided, for example, on the side surface of the sacrificial layer 262 with good coverage.

[0438] Then, as in Fig. 17D, a planarization treatment is performed to expose the top surface of the sacrificial layer 262 and to planarize the top surfaces of the sacrificial layer 262, the insulating layer 283, and the insulating layer 285. A CMP treatment is suitable as the planarization treatment. At least a portion of the insulating layer 283 and a portion of the insulating layer 285 are removed by the planarization treatment. A portion of the sacrificial layer 262 may also be removed.

[0439] Then, as in Fig. 17E, the sacrificial layer 262 is removed. There is no particular limitation on the method for removing the sacrificial layer 262. For example, the sacrificial layer 262 may be removed by dry etching. In this case, as shown in Fig. 17E, it can be assumed that the insulating layer 283 encompasses the opening portion 270 in a position overlapping with the opening portion 290.

[0440] Next, as in Fig. 17F, the conductive layer 265a is formed to cover the opening portion 270 and the opening portion 290. The conductive layer 265a is provided in contact with the insulating layer 250 and the insulating layer 283 in the opening portion 270 and the opening portion 290. The conductive layer 265a is preferably provided to fill the opening portion 290. Furthermore, the conductive layer 265b is formed over the conductive layer 265a. Here, an example is shown in which the conductive layer 265b is provided in the opening portion 270.

[0441] The conductive layer 265a and the conductive layer 265b are each formed in the opening portion 290 and / or the opening portion 270, which has a high aspect ratio. Therefore, the conductive layer 265a and the conductive layer 265b are preferably formed by a film formation method with a favorable coverage, and are more preferably formed by a CVD method, an ALD method, or the like.

[0442] Note that in some cases, the conductive layer 265b is also provided in the opening portion 290 depending on the diameter of the opening portion 270, the diameter of the opening portion 290, the thickness of the conductive layer 265a, the thickness of the conductive layer 265b, and the like. In another case, the conductive layer 265a fills the opening portion 270, and the conductive layer 265b is not provided in the opening portion 270.

[0443] In this way, the transistor 201 can be manufactured. [Example of a manufacturing process of transistor 202]

[0444] An example of a method for manufacturing the semiconductor device including the transistor 202 described above (see Fig. 10A to Fig. 10E), is based on Fig. 18A to Fig. 18F. Detailed descriptions of steps similar to those of the examples of the manufacturing method of transistors 200 and 201 are omitted.

[0445] First, the steps in Fig. 15A1 to Fig. 16B as in the example of the manufacturing method of the transistor 200. Next, as in Fig. 18A, the sacrificial layer 262 is formed to cover the insulating layer 280b, the conductive layer 240a, the conductive layer 240b, and the oxide semiconductor layer 230.

[0446] Next, as in Fig. 18B, a part of the sacrificial layer 262 is removed. In a region where the sacrificial layer 262 remains, a gate insulating layer and a gate electrode (the insulating layer 250 and the conductive layer 260) are provided in a later step. Therefore, it is preferable that only a small area of ​​the sacrificial layer 262 overlaps with the upper surface of the conductive layer 240b, and it is more preferable that the sacrificial layer 262 does not overlap with the upper surface of the conductive layer 240b. In a cross-sectional view, the width of the sacrificial layer 262 is preferably smaller than the sum of the width D of the opening portion 290 and twice the thickness of the insulating layer 250 that will be formed later. Fig. 18B illustrates an example in which the width of the sacrificial layer 262 corresponds to the width D of the opening portion 290.

[0447] Next, as in Fig. 18C, the insulating layer 283 is formed to cover the insulating layer 280b, the conductive layer 240a, the conductive layer 240b, the oxide semiconductor layer 230, and the sacrificial layer 262, and the insulating layer 285 is formed over the insulating layer 283.

[0448] When the insulating layer 285 is formed thick, the distance between the conductive layer 240b and the gate line (the conductive layer 265) can be increased, so that the parasitic capacitance generated therebetween can be reduced.

[0449] Then, as in Fig. 18D, a planarization treatment is performed to expose the top surface of the sacrificial layer 262 and to planarize the top surfaces of the sacrificial layer 262, the insulating layer 283, and the insulating layer 285.

[0450] Then, as in Fig. 18E, the sacrificial layer 262 is removed.

[0451] Next, as in Fig. 18F, the insulating layer 250 is formed to cover the opening portion 270 and the opening portion 290, and the conductive layer 260 is formed over the insulating layer 250. Next, a planarization treatment is performed to expose the top surfaces of the insulating layers 283 and 285 and to planarize the top surfaces of the conductive layer 260, the insulating layer 250, the insulating layer 283, and the insulating layer 285.

[0452] The insulating layer 250 is provided in contact with the oxide semiconductor layer 230 and the insulating layer 283.

[0453] The insulating layer 250 and the conductive layer 260 are formed in the opening portion 290 and the opening portion 270, respectively, with a high aspect ratio. Therefore, the insulating layer 250 and the conductive layer 260 are preferably formed by a film formation method with a favorable coverage, more preferably by a CVD method, an ALD method, or the like.

[0454] A CMP treatment is suitable as a planarization treatment. During the planarization treatment, at least portions of the conductive layer 260 and the insulating layer 250 that overlap with the upper surface of the insulating layer 285 are removed. Therefore, a portion of the conductive layer 260 that overlaps with the upper surface of the conductive layer 240 can be removed, so that the generation of parasitic capacitance between the conductive layer 260 and the conductive layer 240 can be prevented.

[0455] For example, by removing the portion of the conductive layer 260 overlapping with the top surface of the conductive layer 240 by the CMP treatment, an increase in the number of masks can be suppressed compared with the case of using dry etching.

[0456] As in Fig. As shown in Figure 18F, the top surface of the insulating layer 285 and the top surface of the conductive layer 260 preferably have the same height. Alternatively, one of the insulating layer 285 and the conductive layer 260 may be higher than the other. Thanks to the difference between the polishing speeds of the materials for the insulating layer 285 and the conductive layer 260, the heights of the top surfaces of the two layers can be controlled.

[0457] Next, as in Fig. 18F, the conductive layer 265 is formed over the insulating layer 250, the insulating layer 283, the insulating layer 285 and the conductive layer 260.

[0458] The insulating layer 283 and the insulating layer 285 are positioned between the conductive layer 265 and the conductive layer 240b. This can increase the physical distance between the conductive layer 265 and the conductive layer 240b and reduce the parasitic capacitance generated therebetween.

[0459] Through the above steps, the semiconductor device of one embodiment of the present invention can be manufactured. [Example of a manufacturing process of transistor 203]

[0460] An example of a method for manufacturing the semiconductor device including the transistor 203 described above (see Fig. 12A and Fig. 12E), is based on Fig. 19A to Fig. 19D. Detailed descriptions of steps similar to those of the example of the manufacturing method of the transistor 200 are omitted.

[0461] First, the steps in Fig. 15A1 to Fig. 16B as in the example of the manufacturing method of the transistor 200. Next, as in Fig. 19A, the insulating layer 250 is formed to cover the insulating layer 280b, the conductive layer 240a, the conductive layer 240b, and the oxide semiconductor layer 230, and the conductive layer 260 is formed over the insulating layer 250.

[0462] The insulating layer 250 and the conductive layer 260 are each formed in the opening portion 290 with a high aspect ratio. Therefore, the insulating layer 250 and the conductive layer 260 are preferably formed by a film formation method with a favorable coverage, more preferably by a CVD method, an ALD method, or the like.

[0463] It is preferable that only a small area of ​​the conductive layer 260 overlaps with the top surface of the conductive layer 240b, and it is more preferable that the conductive layer 260 does not overlap with the top surface of the conductive layer 240b. Therefore, the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240b can be reduced. Note that, as in the transistor 203E (see Fig. 14C1 and Fig. 14C2) the conductive layer 260 may include a portion that overlaps with the top surface of the conductive layer 240b.

[0464] Next, as in Fig. 19B, the insulating layer 285 is formed to cover the insulating layer 250 and the conductive layer 260.

[0465] When the insulating layer 285 is formed thick, the distance between the conductive layer 240b and the conductive layer 265a can be increased, so that the parasitic capacitance generated between the conductive layer 240b and the gate line can be reduced.

[0466] For example, as the insulating layer 285, a silicon oxide film is preferably formed by a sputtering method.

[0467] Next, as in Fig. 19C, the opening portion 270 reaching the conductive layer 260 is formed in the insulating layer 285.

[0468] Next, as in Fig. 19D, the conductive layer 265a is formed to cover the opening portion 270, and the conductive layer 265b is formed over the conductive layer 265a. The conductive layer 265a is provided in the opening portion 270 in contact with the conductive layer 260. The conductive layer 265a and the conductive layer 265b are preferably provided to fill the opening portion 270.

[0469] The conductive layer 265a and the conductive layer 265b are formed in the opening portion 270 with a high aspect ratio. Therefore, the conductive layer 265a and the conductive layer 265b are preferably formed by a film formation method with a favorable coverage, and are more preferably formed by a CVD method, an ALD method, or the like.

[0470] It should be noted that in some cases, depending on the diameter of the opening portion 270, the thickness of the conductive layer 265a, and the like, the conductive layer 265a fills the opening portion 270 and the conductive layer 265b is not provided in the opening portion 270.

[0471] In this way, the transistor 203 can be manufactured. [Method for adding an element]

[0472] As described above, a region containing a halogen element may be provided in at least one of the insulating layer 280a, the insulating layer 280b, the insulating layer 235, and the oxide semiconductor layer 230. A region containing the above-described first element may be provided in the oxide semiconductor layer 230. A region containing the first element may be provided in at least one of the conductive layers 220a, 220b, 240a, and 240b.

[0473] For example, a halogen element may be supplied to the side surfaces of the insulating layers 280a and 280b in the opening portion 290 after the Fig. 15C has been formed. Note that the halogen element may also be supplied to one or more of the conductive layers 240a, 240b, 255, 220a, and 220b.

[0474] Here Fig. 15C illustrates an example in which the sidewall of the opening portion 290 is perpendicular to the top surface of the substrate. In the semiconductor device of one embodiment of the present invention, the sidewall of the opening portion 290 is perpendicular or substantially perpendicular to the top surface of the substrate, or it has a tapered shape. Consequently, when a halogen element is added perpendicularly or substantially perpendicular to the top surface of the substrate, it is sometimes difficult to uniformly supply the halogen element to a desired area.

[0475] Therefore, a halogen element is preferably added in a direction that is inclined by more than 0° and less than 90° with respect to the top surface of the substrate. Therefore, the halogen element can be easily added to the side surfaces of the insulating layers 280a and 280b in the opening portion 290. The addition direction is not limited to one direction; the halogen element is preferably added stepwise at different angles, in which case the halogen element can be more evenly supplied to a desired area.

[0476] An element that can be used as a halogen element is the one described above.

[0477] A plasma ion doping method or an ion implantation method can be suitably used for the supply of the halogen element. In the above methods, the concentration profile in the depth direction can be controlled with high precision, for example, by the acceleration voltage and the ion dose.

[0478] It should be noted that, for example, when the substrate to be processed and / or the ion irradiation section of the apparatus are inclined, the angle at which the halogen element is added may be within the above range.

[0479] By using an ion implantation method, in which a source gas is ionized, the ion is subjected to mass separation, and then added, the purity of the halogen element to be supplied can be increased. Furthermore, by using a plasma ion doping method, in which the source gas is ionized and the ion is added without mass separation, productivity can be increased.

[0480] An ion implantation device or an ion doping device used to supply the halogen element is also used in the manufacture of a Si transistor, such as an LTPS transistor. This is preferable because one device can be used for an existing LTPS production line and no new investment is required. This can reduce the investment for manufacturing the semiconductor device.

[0481] As the source gas of the halogen element, a gas containing the above-described halogen element can be used. A gas of only halogen or a halide gas can also be used as the gas. In the case where fluorine is supplied, an F2 gas, a BF3 gas, a C4F6 gas, a C5F6 gas, a C4F8 gas, a CF4 gas, an SF6 gas, a CHF3 gas, a CH2F2 gas, a CH3F gas, or the like can typically be used. In the case where chlorine is supplied, a Cl2 gas, a BCl3 gas, a SiCl4 gas, or a CCl4 gas can typically be used. A mixed gas in which the above source gas is diluted with hydrogen or a rare gas can be used. The ion source is not limited to a gas, and a solid or a liquid can be vaporized by heating.

[0482] The supply of the halogen element can be controlled by adjusting the conditions such as the acceleration voltage and the dose, taking into account the composition, density, thickness, and the like of the insulating layers 280a and 280b.

[0483] Note that there is no limitation on the method for supplying the halogen element. For example, plasma treatment, treatment using thermal diffusion by heating, or the like can be used. In the case of a plasma treatment method, a halogen element can be supplied in such a way that a plasma is generated in a gas atmosphere containing the halogen element to be supplied, and plasma treatment is performed. A dry etching device, an ashing device, a plasma CVD device, a high-density plasma CVD device, or the like can be used to generate the plasma.

[0484] The step of adding the halogen element can be performed while heating the substrate. Therefore, damage caused to the insulating layers 280a and 280b during the addition of the halogen element can be repaired. That is, the addition of the halogen element and the repair of damage to the insulating layers 280a and 280b due to the addition can be performed in parallel.

[0485] The substrate temperature in the step of supplying the halogen element is preferably higher than or equal to 150°C and lower than the stress relief limit of the substrate, more preferably higher than or equal to 200°C and lower than or equal to 500°C, still more preferably higher than or equal to 200°C and lower than or equal to 450°C, even more preferably higher than or equal to 250°C and lower than or equal to 400°C, even more preferably higher than or equal to 250°C and lower than or equal to 350°C, or higher than or equal to 300°C and lower than or equal to 400°C, even more preferably higher than or equal to 300°C and lower than or equal to 350°C.

[0486] Alternatively, after the Fig. 15D or Fig. 15E has been formed, the halogen element is supplied to the insulating layer 235 positioned in the opening portion 290.

[0487] Thereafter, the oxide semiconductor layer 230 is formed while heating the substrate, so that the halogen element can be supplied from the insulating layer 280a, 280b, or 235 to the oxide semiconductor layer 230 in some cases. During the heat treatment performed after the formation of the oxide semiconductor layer 230, the halogen element can be supplied from the insulating layer 280a, 280b, or 235 to the oxide semiconductor layer 230 in some cases.

[0488] As described above, in the semiconductor device of one embodiment of the present invention, the halogen element is added to the insulating layer in contact with or in the vicinity of the oxide semiconductor layer 230 and then supplied to the oxide semiconductor layer 230 from the insulating layer. Therefore, damage to the channel formation region of the oxide semiconductor layer 230 due to the element addition, a reduction in the crystallinity of the channel formation region due to the element addition, and the like can be prevented. As a result, the reliability of the transistor can be increased.

[0489] Alternatively, the side surface of the oxide semiconductor layer 230 positioned in the opening portion 290 may be supplied with the halogen element after the Fig. 16A or Fig. 16B has been formed.

[0490] After the Fig. 15C has been formed, an impurity element may be supplied to the upper surface of the conductive layer 220b and the upper surface of the conductive layer 240b.

[0491] Thereafter, the oxide semiconductor layer 230 is formed and a heat treatment or the like is performed, whereby the impurity element can be supplied from the conductive layers 220b and 240b to the source and drain regions of the oxide semiconductor layer 230.

[0492] When the impurity element is supplied to the oxide semiconductor layer 230 via the conductive layer 220 or the conductive layer 240, a reduction in the crystallinity of the oxide semiconductor layer 230 can be prevented compared to the case where the impurity element is directly added to the oxide semiconductor layer 230. Therefore, an increase in electrical resistance due to a reduction in crystallinity can be prevented.

[0493] It should be noted that the step of supplying the impurity element is preferably carried out after the step in Fig. 15C, but before the step of forming the conductive layer 265a in Fig. 16C. That is, after the formation of the oxide semiconductor layer 230, the impurity element may be added to the oxide semiconductor layer 230. Alternatively, the impurity element may be added to the oxide semiconductor layer 230 via the insulating layer 250.

[0494] When the impurity element is added to the oxide semiconductor layer 230, the sheet resistance of the oxide semiconductor layer 230, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced.

[0495] The insulating layer 250 is formed over the oxide semiconductor layer 230 after the impurity element is directly added to the oxide semiconductor layer 230, whereby the insulating layer 250 can be prevented from being damaged by the addition of the impurity element.

[0496] When the impurity element is supplied to the oxide semiconductor layer 230 via the insulating layer 250, a reduction in the crystallinity of the oxide semiconductor layer 230 can be prevented compared to the case where the impurity element is directly added to the oxide semiconductor layer 230. Therefore, an increase in electrical resistance due to a reduction in crystallinity can be prevented.

[0497] If the insulating layer 250 is formed after the addition of the impurity element, the deposition chamber of the insulating layer 250 may be contaminated. Therefore, it is preferable to add the impurity element after the formation of the insulating layer 250.

[0498] Here, the thickness of the insulating layer 250 in the direction in which the impurity element is added is greater in a region along the side surface of the insulating layer 235 than in a region along the top surface of the conductive layer 220b or the top surface of the conductive layer 240b. Therefore, in the oxide semiconductor layer 230, the amount of the added impurity element is greater in the region along the top surface of the conductive layer 220b or the top surface of the conductive layer 240b than in the region along the side surface of the insulating layer 235. In this way, the impurity element can be prevented from penetrating into the channel formation region of the oxide semiconductor layer 230, so that the resistances of the source and drain regions can be primarily reduced.

[0499] The impurity element is preferably added from a direction perpendicular or substantially perpendicular to the upper surface of the substrate. In the oxide semiconductor layer 230, the amount of added impurity element is smaller in a surface inclined to the upper surface of the substrate than in a surface parallel or substantially parallel to the upper surface of the substrate. That is, in the oxide semiconductor layer 230, the amount of added impurity element is greater in the source and drain regions than in the channel formation region. Thus, the resistances of the source and drain regions can be preferentially reduced.

[0500] An element that can be used as an impurity element is the one described above.

[0501] A plasma ion doping method or an ion implantation method can be suitably used for the supply of the impurity element. In the above methods, the concentration profile in the depth direction can be controlled with high precision, for example, by the acceleration voltage and the ion dose.

[0502] By using an ion implantation method in which the source gas is ionized and the ion is subjected to mass separation and then added, the purity of an impurity element to be added can be increased. When using an ion implantation method, it is preferable that the above-described first element be used as the impurity element, and it is more preferable that boron or phosphorus be used. When an element stabilized by bonding with oxygen is used as the impurity element, a low-resistance region stable in a low electrical resistance state can be obtained.

[0503] Furthermore, productivity can be increased by using a plasma ion doping method in which the source gas is ionized and the ion is added without mass separation. When using a plasma ion doping method, it is preferable to use the first element and hydrogen as the impurity element, and it is more preferable to use hydrogen and boron or phosphorus. When hydrogen and an element stabilized by bonding with oxygen are each used as the impurity element, the electrical resistance of the low-resistance region is slightly reduced, and the low electrical resistance state can be maintained stably.

[0504] An ion implantation device or an ion doping device used to supply the impurity element is also preferably used in the manufacture of a Si transistor, such as an LTPS transistor. In this case, a device for an existing LTPS production line can be used, and no new investment is required. This can reduce the investment for manufacturing the semiconductor device.

[0505] During the impurity element supply treatment, the treatment conditions are preferably controlled such that the concentration of the impurity element in the oxide semiconductor layer 230 is higher in a portion overlapping with the upper surface of the conductive layer 220b or the upper surface of the conductive layer 240b than in other regions. Consequently, the impurity element can be supplied to the source and drain regions of the oxide semiconductor layer 230 at an optimal concentration.

[0506] A gas containing the above impurity element can be used as the source gas of the impurity element. In the case where boron is supplied, a B2H6 gas, a BF3 gas, or the like can typically be used. In the case where phosphorus is supplied, a PH3 gas can typically be used. A mixed gas in which the above source gas is diluted with hydrogen or a rare gas can be used.

[0507] Alternatively, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, a noble gas, or the like can be used as the source gas. The ion source is not limited to a gas, and a solid or liquid can be vaporized by heating.

[0508] For example, as the impurity element, boron and hydrogen are preferably added using a gas containing boron and hydrogen. This is preferable because the impurity element can be added without mass separation and the resistance of the oxide semiconductor layer 230 can be easily reduced, thereby improving both the productivity and the characteristics of the semiconductor device.

[0509] Furthermore, the same source gas is preferably used in the halogen element supply step and the impurity element supply step, in which case, manufacturing costs can be reduced. For example, by ionizing a BF3 gas and mass separating the ions, fluorine can be supplied as a halogen element, and boron can be supplied as an impurity element.

[0510] The supply of the impurity element can be controlled by adjusting the conditions such as the acceleration voltage and the dose, taking into account the composition, density, thickness, and the like of the oxide semiconductor layer 230.

[0511] Note that there is no limitation on the method for supplying the impurity element. For example, plasma treatment, treatment using thermal diffusion by heating, or the like can be used. In the case of a plasma treatment method, an impurity element can be supplied by generating plasma in a gas atmosphere containing the impurity element to be supplied, and plasma treatment can be performed. A dry etching device, an ashing device, a plasma CVD device, a high-density plasma CVD device, or the like can be used to generate the plasma.

[0512] The step of adding the impurity element is preferably performed while heating the substrate. Therefore, damage caused to the oxide semiconductor layer 230 during the addition of the impurity element can be repaired. That is, the addition of the impurity element and the repair of damage to the oxide semiconductor layer 230 due to the addition can be performed in parallel.

[0513] The substrate temperature in the step of supplying the impurity element is preferably higher than or equal to 150°C and lower than the stress relief limit of the substrate, more preferably higher than or equal to 200°C and lower than or equal to 500°C, still more preferably higher than or equal to 200°C and lower than or equal to 450°C, even more preferably higher than or equal to 250°C and lower than or equal to 400°C, even more preferably higher than or equal to 250°C and lower than or equal to 350°C, even more preferably higher than or equal to 300°C and lower than or equal to 400°C, even more preferably higher than or equal to 300°C and lower than or equal to 350°C.

[0514] A heat treatment may be performed after the impurity element has been added. The heat treatment can repair damage to the oxide semiconductor layer 230 in the step of adding the impurity element.

[0515] When an element stabilized by bonding with oxygen is used as the impurity element, the impurity element can be prevented from being released by heat or the like applied during the manufacturing process of the semiconductor device. Therefore, even if a heat treatment or a film formation step or the like is performed while heating the substrate after the addition of the impurity element, the impurity element is not released, and the low electrical resistance state can be maintained.

[0516] As described above, the semiconductor device of one embodiment of the present invention has a structure in which an electric field of a gate is easily applied to the oxide semiconductor. As a result, the transistor can have favorable electrical characteristics.

[0517] The semiconductor device of one embodiment of the present invention has a structure in which the parasitic capacitance generated between the gate electrode and the source electrode or the drain electrode, and the parasitic capacitance generated between the gate line and the source electrode or the drain electrode are reduced. Consequently, the frequency characteristics of a circuit in which the semiconductor device is used can be improved.

[0518] The transistor of one embodiment of the present invention includes a backgate. Therefore, even when miniaturized, the transistor of one embodiment of the present invention can still exhibit all of high conduction characteristics, normally-off characteristics, and high reliability.

[0519] This embodiment can be combined with any of the other embodiments as required. (Embodiment 3)

[0520] In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor is described. [Oxide semiconductor layer]

[0521] An oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide layer having crystallinity. Examples of the structure of a metal oxide having crystallinity include a c-axis aligned crystalline structure (CAAC (c-axis aligned crystalline) structure), a polycrystalline structure, and a nanocrystalline (nano-crystal, nc) structure. By using a metal oxide having crystallinity for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. This can improve the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention, thereby improving the reliability of a semiconductor device including the transistor.

[0522] It is particularly preferable that the oxide semiconductor layer of one embodiment of the present invention contains a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have an alignment with respect to the c-axis and are connected to each other in the ab plane without alignment. Furthermore, according to a cross-sectional image of an oxide semiconductor layer having the CAAC structure observed with a high-resolution transmission electron microscope (TEM), metal atoms are arranged layer by layer in a crystal part. Therefore, the oxide semiconductor layer having the CAAC structure can be said to include a layered crystal part. The metal atoms arranged layer by layer can be observed as bright spots in the cross-sectional TEM image of the oxide semiconductor layer.

[0523] The CAAC structure is formed, for example, such that the c-axis is perpendicular or substantially perpendicular to a formation surface. In the CAAC structure, metal atoms are layered in a direction parallel or substantially parallel to the formation surface. In a region having the CAAC structure, an angle formed by the c-axis and the formation surface is preferably within 90° ± 20° (greater than or equal to 70° and less than or equal to 110°), more preferably within 90° ± 15° (greater than or equal to 75° and less than or equal to 105°), even more preferably within 90° ± 10° (greater than or equal to 80° and less than or equal to 100°), and even more preferably within 90° ± 5° (greater than or equal to 85° and less than or equal to 95°).

[0524] The crystallinity of the oxide semiconductor layer can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, these methods can be combined as needed for analysis.

[0525] When the oxide semiconductor layer with the CAAC structure is subjected to electron diffraction, spots indicating c-axis alignment (bright spots) are observed in the electron diffraction pattern. The c-axes of the CAAC structure are preferably aligned in a direction parallel to the normal vector of the formation surface of the oxide semiconductor layer or the normal vector of a surface of the oxide semiconductor layer.

[0526] A fast Fourier transform (FFT) pattern obtained by FFT processing on a TEM image reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0527] When a cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is obtained and each region of the cross-sectional TEM image is subjected to FFT processing to form an FFT pattern, the crystal axis direction in each region can be calculated from the obtained FFT pattern. Specifically, the direction of a line segment connecting two points having high luminance and substantially the same distance from the center among points observed in the obtained FFT pattern is referred to as the crystal axis direction.A region in which an angle formed by the crystal axis direction calculated from the FFT pattern and the formation surface is preferably within 90° ± 20° (greater than or equal to 70° and less than or equal to 110°), more preferably within 90° ± 15° (greater than or equal to 75° and less than or equal to 105°), even more preferably within 90° ± 10° (greater than or equal to 80° and less than or equal to 100°), and even more preferably within 90° ± 5° (greater than or equal to 85° and less than or equal to 95°) can be regarded as having a CAAC structure.

[0528] When the oxide semiconductor layer with the CAAC structure is observed from the direction perpendicular to the formation surface using the TEM image, a triangular or hexagonal atom arrangement and crystallinity in the ab plane are observed. In a Voronoi diagram formed by analyzing the TEM image of the oxide semiconductor layer with the CAAC structure observed from the direction perpendicular to the formation surface, mainly pentagonal, hexagonal, and heptagonal Voronoi regions are observed, with a hexagonal Voronoi region being typically observed. For example, the proportion of the hexagonal Voronoi region is greater than or equal to 30% and less than 100% of the Voronoi regions observed in the Voronoi diagram.

[0529] A method for forming a Voronoi diagram is described. First, FFT processing is performed on a TEM image analysis, only information within a specific region is retained by filtering, and then an inverse fast Fourier transform is performed to obtain an FFT filtered image. Grid points are extracted from the obtained FFT filtered image, and perpendicular bisectors of line segments connecting adjacent grid points are formed. A point where three perpendicular bisectors intersect is called a Voronoi point, and a polygonal region enclosed by line segments connecting the Voronoi points is called a Voronoi region. In the above manner, a Voronoi diagram can be formed.

[0530] Note that, for example, a rectangular area 50 nm wide and 50 nm long can be observed as the TEM observation area for forming a Voronoi diagram. Note that the observation area is not limited to this.

[0531] Furthermore, when analyzing the distribution of hexagonal lattice orientations using lattice points extracted by analyzing a plan-view TEM image, at a boundary between two structures with different hexagonal lattice orientations, the difference in hexagonal lattice orientation is small, the boundary is blurred, and the two structures are connected to each other in such a way that they become entangled. This means that no clear boundary section is observed in the CAAC structure.

[0532] It should be noted that the hexagonal lattice orientation can be calculated as the orientation of a hexagon formed by six lattice points that are closest to each other.

[0533] Note that there is no particular limitation on the crystallinity of a semiconductor material included in the oxide semiconductor layer. For example, in some cases, the oxide semiconductor layer contains one or more of an amorphous semiconductor (a semiconductor with an amorphous structure), a single-crystal semiconductor (a semiconductor with a single-crystal structure), and a semiconductor with crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor partially including a crystal region). If the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be prevented in some cases.

[0534] The metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), more preferably indium as the main component. Here, the metal oxide contains indium as the main component and may further contain an element M. The metal oxide preferably contains two or three elements selected from indium, the element M, and zinc, and more preferably contains indium and zinc as the main components. Here, the metal oxide contains indium and zinc as the main components and may further contain the element M. The element M is a metal element or a semimetal element having a high binding energy to oxygen, such as a metal element or a semimetal element whose binding energy to oxygen is higher than that of In.Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide of one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. In this specification and the like, a metal element and a semi-metal element may be collectively referred to as a "metal element," and a "metal element" in this specification and the like may refer to a semi-metal element.

[0535] In the cross-section of the oxide semiconductor layer observed using the TEM image, metal atoms are observed to be layered in a direction parallel or substantially parallel to the formation surface. In a TEM image, a metal atom is observed as a bright spot. For example, in a metal oxide containing indium, indium atoms are observed to be layered. As another example, in a metal oxide containing indium and zinc, indium atoms and zinc atoms are observed to be layered.

[0536] As a metal oxide of an embodiment of the present invention, for example, an indium zinc oxide (In-Zn oxide), an indium tin oxide (In-Sn oxide), an indium titanium oxide (In-Ti oxide), an indium gallium oxide (In-Ga oxide), an indium gallium aluminum oxide (In-Ga-Al oxide), an indium gallium tin oxide (also referred to as In-Ga-Sn oxide or IGTO), a gallium zinc oxide (also referred to as Ga-Zn oxide or GZO), an aluminum zinc oxide (also referred to as Al-Zn oxide or AZO), an indium aluminum zinc oxide (also referred to as In-Al-Zn oxide or IAZO), a Indium tin zinc oxide (In-Sn-Zn oxide), an indium titanium zinc oxide (In-Ti-Zn oxide), an indium gallium zinc oxide (also called In-Ga-Zn oxide or IGZO), an indium gallium tin zinc oxide (also called In-Ga-Sn-Zn oxide or IGZTO) or an indium gallium aluminum zinc oxide (also called In-Ga-Al-Zn oxide, IGAZO or IAGZO).Alternatively, an indium tin oxide containing silicon (also referred to as ITSO), a gallium tin oxide (Ga-Sn oxide), an aluminum tin oxide (Al-Sn oxide), or the like may be used. An indium oxide may be used as the metal oxide of one embodiment of the present invention. Alternatively, a gallium oxide, a zinc oxide, or the like may be used as the metal oxide of one embodiment of the present invention.

[0537] By increasing the proportion of the number of indium atoms in the total number of atoms of all metal elements contained in the metal oxide, a high forward current and high frequency characteristics of the transistor can be achieved.

[0538] Instead of indium, the metal oxide may contain one or more types of metal elements whose periodic number is large in the periodic table. Alternatively, in addition to indium, the metal oxide may contain one or more types of metal elements whose periodic number is large in the periodic table. The greater the overlap between orbitals of metal elements, the more likely the metal oxide is to have high carrier conductivity. Therefore, if a metal element with a large periodic number in the periodic table is included in the metal oxide, the field-effect mobility of the transistor can be increased in some cases. Examples of the metal element with a large periodic number in the periodic table include metal elements belonging to period 5 and metal elements belonging to period 6.Specific examples of the metallic element include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. It should be noted that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are referred to as light rare earth elements.

[0539] The metal oxide may contain one or more types selected from non-metal elements. A transistor containing the metal oxide containing a non-metal element can, in some cases, exhibit high field-effect mobility. Examples of the non-metal element include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0540] By increasing the proportion of zinc atoms in the total number of atoms of all metal elements contained in the metal oxide, the metal oxide exhibits high crystallinity, thus preventing the diffusion of impurities in the metal oxide. Consequently, changes in the electrical properties of the transistor are reduced, and the transistor can exhibit high reliability.

[0541] By increasing the proportion of atoms of element M in the total number of atoms of all metal elements contained in the metal oxide, oxygen vacancies can be prevented from forming in the metal oxide. Accordingly, the generation of charge carriers due to oxygen vacancies is prevented, which reduces the transistor's reverse current. Furthermore, changes in the transistor's electrical properties are reduced, and the transistor can exhibit high reliability.

[0542] In the description of this embodiment, an In-Ga-Zn oxide is given as an example of the metal oxide in some cases.

[0543] The oxide semiconductor layer of one embodiment of the present invention can be formed by forming metal oxides using two types of film formation methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be formed by forming metal oxides using a first film formation method and a second film formation method. Note that the oxide semiconductor layer formed using two types of film formation methods can be referred to as a hybrid OS.

[0544] The oxide semiconductor layer of one embodiment of the present invention has crystallinity. The oxide semiconductor layer of one embodiment of the present invention preferably has the CAAC structure.

[0545] In the formation of the oxide semiconductor layer of one embodiment of the present invention, a metal oxide having crystallinity is formed by the first film formation method. The resulting metal oxide particularly preferably has the CAAC structure. A metal oxide formed by, for example, a sputtering method is likely to exhibit crystallinity.

[0546] In the case where a metal oxide is formed by the first film formation method, in some cases, a mixture layer is formed at the interface between the metal oxide and a layer (formation surface) over which the metal oxide is formed. For example, in the case where a sputtering method is used as the first film formation method, the mixture layer is formed in some cases by, for example, particles emitted from a target or the like (also called sputtered particles) or energy applied to the substrate side by sputtered particles or the like. There is a risk that the mixture layer may hinder the crystallization of the metal oxide.

[0547] For example, in the case where a silicon-containing insulating layer, such as silicon oxide, is used as the formation surface and a metal oxide is formed over the silicon oxide by the first film formation process, silicon may penetrate into the metal oxide. There is a risk that the penetration of impurities, such as silicon, into the metal oxide may hinder the crystallization of the metal oxide.

[0548] In view of the above, in one embodiment of the present invention, a metal oxide is formed by the second film formation method before a metal oxide is formed by the first film formation method. In other words, a metal oxide is formed as a first layer by the second film formation method, and then a metal oxide is formed as a second layer over the first layer by the first film formation method. In this case, the second film formation method preferably causes less damage to a formation surface than the first film formation method. When a film formation method that causes less damage to a formation surface is used as the second film formation method, a mixture layer can be prevented from forming at an interface between the oxide semiconductor layer and a layer serving as a formation surface of the oxide semiconductor layer.In addition, impurities such as silicon can be prevented from penetrating the second layer, which can increase crystallinity. For example, atomic layer deposition (ALD) and chemical vapor deposition (CVD) are suitable as second film formation methods because they can reduce damage to a formation surface compared to a sputtering method.

[0549] In addition, for example, a metal oxide having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, is formed as the first layer in some cases. By forming the second layer with high crystallinity over the first layer with low crystallinity, or by forming the second layer followed by heat treatment, the crystallinity of the first layer can be increased in some cases with the second layer serving as the core. Consequently, the crystallinity in the entire oxide semiconductor layer, including the vicinity of the interface with the formation surface, can be increased in some cases.

[0550] In a preferred mode of the oxide semiconductor layer of one embodiment of the present invention, a metal oxide is formed over the formation surface by the second film formation method, and then a metal oxide is formed thereover by the first film formation method.

[0551] Examples of the first film forming method include a sputtering method and a PLD method.

[0552] Examples of the second film formation method include an ALD method, a plasma-enhanced CVD (PECVD) method, a thermal CVD method, a photo-CVD method, a metal-organic CVD (MOCVD) method, and a molecular beam epitaxy (MBE) method. The MBE method is a film formation method in which a thin film with a crystal structure reflecting a crystal system of a substrate is grown and is one of film formation methods that causes less damage to a formation surface. A wet method can be used as the second film formation method. The wet method is one of film formation methods that causes less damage to a formation surface. An example of the wet method is a spray coating method.

[0553] For example, the oxide semiconductor layer of one embodiment of the present invention can be formed in the following manner: A metal oxide is formed as the first layer by the second film formation method, and then a metal oxide is formed as the second layer by the first film formation method. Specifically, an ALD method can be used as the second film formation method, and a sputtering method can be used as the first film formation method. The metal oxide formed by the first film formation method preferably has the CAAC structure.

[0554] Furthermore, a third layer may be formed over the second layer. Since the second layer has high crystallinity, a crystal of the third layer can grow using a crystal of the second layer as a nucleus or seed. Therefore, the third layer can be crystallized even if a film formation method by which crystallinity can be easily obtained is not used as the film formation method of the third layer. Here, for example, if a film formation method by which a higher coverage can be obtained than that of the second layer is used for the formation of the third layer, the entire oxide semiconductor layer can have both high crystallinity and high coverage.

[0555] Furthermore, if the influence of the formation surface on the second layer is reduced by providing the first layer, the crystallinity of the second layer is increased to a very high level. Therefore, the third layer, whose crystal grows with the second layer as a nucleus or seed, is also expected to have very high crystallinity.

[0556] Note that the third layer is the topmost layer of the oxide semiconductor layer. For example, in the case where the oxide semiconductor layer is used as a semiconductor layer of a transistor, the third layer is a layer in contact with a gate insulating layer. By increasing the crystallinity of the layer in contact with the gate insulating layer, the charge carrier mobility in the on-state of the transistor can be increased.

[0557] The oxide semiconductor layer of one embodiment of the present invention can be formed, for example, in the following manner: a metal oxide is formed as the first layer by the second film formation method, a metal oxide is formed as the second layer by the first film formation method, and a metal oxide is formed as the third layer by the second film formation method. Specifically, an ALD method can be used as the second film formation method, and a sputtering method can be used as the first film formation method. The metal oxide formed by the first film formation method preferably has the CAAC structure.The ALD method is a film formation method that can achieve higher coverage than a sputtering method. When the ALD method is used as the film formation method of the first layer and the third layer, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be formed to advantageously cover a step, an opening portion, or the like with a high aspect ratio. [Formation method of the oxide semiconductor layer]

[0558] The oxide semiconductor layer 230 can be formed, for example, in the following manner: an oxide semiconductor 230a is formed by an ALD method over a layer 229 serving as a formation surface, an oxide semiconductor 230b is formed over the oxide semiconductor 230a by a sputtering method, and an oxide semiconductor 230c is formed over the oxide semiconductor 230b by an ALD method. Furthermore, a heat treatment is preferably performed after the formation of the oxide semiconductor layer 230. The heat treatment can increase the crystallinity of the oxide semiconductor layer 230. Here, the heat treatment is not limited to an annealing treatment. For example, heat applied in the formation process can be regarded as a heat treatment.The layer 229 is an insulating film and is, for example, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film.

[0559] The oxide semiconductor layer 230 can be used as the oxide semiconductor layer 230 or the like included in each of the transistors described in Embodiment 2. The layer 229 corresponds to one or more of the conductive layer 220, the insulating layer 235, the conductive layer 240, and the like described in Embodiment 2.

[0560] Layer 229 does not necessarily have crystallinity. If layer 229 does have crystallinity, the crystal structures of layer 229 and the metal oxide contained in oxide semiconductor 230 may have poor lattice matching.

[0561] An example of the formation process of the oxide semiconductor layer 230 is shown in Fig. 20A to Fig. 20D and Fig. 21A to Fig. 21D.

[0562] First, the oxide semiconductor 230a is formed over the layer 229 ( Fig. 20A). Next, the oxide semiconductor 230b is formed over the oxide semiconductor 230a ( Fig. 20B).

[0563] The oxide semiconductor 230b is preferably formed by a sputtering process. Furthermore, the oxide semiconductor 230b preferably has a composition suitable for forming the CAAC structure.

[0564] The oxide semiconductor 230a is preferably formed by a film formation method that causes less damage to a formation surface than the film formation method of the oxide semiconductor 230b. Here, the oxide semiconductor 230a is formed by an ALD method.

[0565] In the case where a metal oxide film is formed by a sputtering method, damage to a formation surface may cause alloying of a component contained in the metal oxide film with a component contained in a layer serving as a formation surface. In the case where alloying is caused, it is difficult to increase the crystallinity of the alloyed region even if a heat treatment described later is performed. When an oxide semiconductor layer including the alloyed region is used for a transistor, the initial characteristics or reliability of the transistor may be adversely affected. Therefore, alloying of the component contained in the metal oxide film with the component contained in the layer serving as a formation surface is preferably prevented.

[0566] In the formation method of the oxide semiconductor layer of one embodiment of the present invention, the oxide semiconductor 230a is formed over the layer 229, and then the oxide semiconductor 230b is formed thereover by a sputtering method. At this time, the oxide semiconductor 230a is preferably formed by a film formation method that causes less damage to a formation surface. The oxide semiconductor 230a is formed between the oxide semiconductor 230b and the layer 229 by a film formation method that causes less damage to a formation surface, thereby preventing alloying of the component contained in the oxide semiconductor layer 230 with the component contained in the layer 229 and further increasing the crystallinity of the oxide semiconductor layer 230.

[0567] The above structure allows the alloyed region to be thin or thin enough to be unobserved. For example, the thickness of the alloyed region may be greater than or equal to 0 nm and less than or equal to 3 nm, preferably greater than or equal to 0 nm and less than or equal to 2 nm, more preferably greater than or equal to 0 nm and less than or equal to 1 nm, even more preferably greater than or equal to 0 nm and less than or equal to 0.3 nm. It should be noted that Fig. 20A and Fig. 20B each illustrates an example in which the alloyed region is not formed between the layer 229 and the oxide semiconductor 230a.

[0568] It should be noted that in some cases, the thickness of the alloyed region can be calculated by performing SIMS analysis or composition line analysis by energy dispersive X-ray spectroscopy (EDX) on the region and its surroundings.

[0569] For example, EDX line analysis is performed on the region and its surroundings, wherein the direction perpendicular to the formation surface of the oxide semiconductor 230a is regarded as the depth direction. Next, in profiles of quantitative values ​​of elements in the depth direction obtained by the analysis, the depth at which the quantitative value of a metal that is the main component of the oxide semiconductor 230a and is not the main component of a layer (here, the layer 229) serving as the formation surface (the metal is In when the oxide semiconductor 230a contains In) becomes half is defined as the depth (position) of the interface between the region and the oxide semiconductor 230a. Further, the depth at which the quantitative value of an element (e.g.,Si), which is the main component of the layer serving as the formation surface and is not the main component of the oxide semiconductor 230a, is defined as the depth (position) of the interface between the region and the layer serving as the formation surface. In the above manner, the thickness of the alloyed region can be calculated.

[0570] In the case where the thickness of the alloyed region in the oxide semiconductor layer of one embodiment of the present invention is observed by EDX analysis, the thickness is, for example, greater than or equal to 0 nm and less than or equal to 3.0 nm, preferably greater than or equal to 0 nm and less than or equal to 2.0 nm, more preferably greater than or equal to 0 nm and less than or equal to 1.0 nm, even more preferably greater than or equal to 0 nm and less than 0.3 nm.

[0571] For example, in the case where SIMS analysis is performed on the oxide semiconductor layer 230 formed over the layer 229 formed using a silicon oxide layer, the depth at which the silicon concentration is 50% of the maximum silicon concentration in the layer 229 is defined as the interface, and the distance between the interface and the depth at which the silicon concentration is 1.0 × 10 21 atoms / cm 3 , preferably 5.0 × 10 20 atoms / cm 3 , preferably 1.0 × 10 20 atoms / cm 3 is reduced is defined as thickness t_s2. The thickness t_s2 is preferably less than or equal to 3 nm, more preferably less than or equal to 2 nm.

[0572] Reducing the thickness of the alloyed region allows the thickness t_s2 to be within the above range.

[0573] Note that reducing the thickness of the alloyed region enables the formation of the CAAC structure in the vicinity of the formation surface. Here, the vicinity of the formation surface refers, for example, to a region ranging from the formation surface of the oxide semiconductor layer 230 to greater than 0 nm and less than or equal to 3 nm, preferably greater than 0 nm and less than or equal to 2 nm, more preferably greater than or equal to 1 nm and less than or equal to 2 nm in a direction substantially perpendicular to the formation surface of the oxide semiconductor layer 230.

[0574] Note that in some cases, the CAAC structure in the vicinity of the formation surface can be confirmed by TEM obs...

Claims

[1] Semiconductor device comprising: an oxide semiconductor layer; a first conductive layer; a second conductive layer; a third conductive layer; a fourth conductive layer; a first insulating layer; a second insulating layer; a third insulating layer; and a fourth insulating layer, wherein the first insulating layer lies over the first conductive layer, wherein the second conductive layer lies over the first insulating layer, wherein the second insulating layer lies over the second conductive layer, wherein the third conductive layer lies above the second insulating layer, wherein the first conductive layer comprises a first recessed portion, wherein the first insulating layer, the second conductive layer, the second insulating layer and the third conductive layer include a first opening portion in a position overlapping with the first recessed portion, wherein the third insulating layer is in contact with at least one side surface of the second conductive layer in the first opening portion, wherein the oxide semiconductor layer is in contact with a top surface of the third conductive layer and a bottom surface and a side surface of the first recessed portion, and is in contact with the third insulating layer in the first opening portion, wherein the fourth insulating layer is located further inside the first opening portion than the oxide semiconductor layer, wherein the fourth conductive layer is located further inside the first opening portion than the fourth insulating layer, and wherein, in a cross-sectional view, the oxide semiconductor layer includes a region overlapping with the second conductive layer with the third insulating layer therebetween and overlapping with the fourth conductive layer with the fourth insulating layer therebetween. [2] A semiconductor device according to claim 1, further comprising a fifth insulating layer, wherein the first conductive layer and the second insulating layer lie above the fifth insulating layer, and wherein the shortest distance from a top surface of the fifth insulating layer to a top surface of the first conductive layer in contact with the first insulating layer is longer than the shortest distance from the top surface of the fifth insulating layer to a bottom surface of the fourth insulating layer. [3] A semiconductor device according to claim 1, further comprising a fifth insulating layer, wherein the first conductive layer and the fourth conductive layer lie above the fifth insulating layer, and wherein the shortest distance from a top surface of the fifth insulating layer to a top surface of the first conductive layer in contact with the first insulating layer is longer than or equal to the shortest distance from the top surface of the fifth insulating layer to a bottom surface of the fourth conductive layer. [4] A semiconductor device according to claim 1, wherein the first conductive layer comprises a fifth conductive layer and a sixth conductive layer over the fifth conductive layer, wherein the sixth conductive layer comprises a second recessed portion, wherein the first opening portion overlaps with the second recessed portion, and wherein the oxide semiconductor layer is in contact with a bottom surface and a side surface of the second recessed portion. [5] A semiconductor device according to claim 1, further comprising a sixth insulating layer, wherein the fourth insulating layer covers a top and a side surface of the oxide semiconductor layer over the second insulating layer, wherein the sixth insulating layer overlies the fourth insulating layer and includes a second opening portion in a position overlapping with the first opening portion, and wherein the fourth conductive layer includes a portion overlapping with the oxide semiconductor layer in the first opening portion with the fourth insulating layer therebetween, and a portion positioned in the second opening portion. [6] A semiconductor device according to claim 1, further comprising a sixth insulating layer, wherein the sixth insulating layer overlies the second insulating layer, covers a top and a side surface of the oxide semiconductor layer over the second insulating layer, and includes a second opening portion in a position overlapping with the first opening portion, wherein the fourth insulating layer comprises a portion positioned in the second opening portion, and wherein the fourth conductive layer is located further inside the second opening portion than the fourth insulating layer. [7] A semiconductor device according to claim 1, wherein the third insulating layer comprises a seventh insulating layer in contact with the oxide semiconductor layer and an eighth insulating layer positioned further outward than the seventh insulating layer in the first opening portion, and wherein one of the seventh insulating layer and the eighth insulating layer is an insulating oxide layer and the other is an insulating nitride layer. [8] A semiconductor device according to claim 1, further comprising: a fifth insulating layer; and a fifth conductive layer, wherein the fifth insulating layer overlies the fourth insulating layer and includes a second opening portion reaching the fourth conductive layer in a position overlapping with the first opening portion, and wherein the fifth conductive layer is in contact with the fourth conductive layer in the second opening portion. [9] Semiconductor device comprising: a first layer; and a second layer over the first layer, wherein the second layer comprises a first memory cell array and a second memory cell array, wherein the first memory cell array comprises a plurality of first memory cells, wherein the second memory cell array comprises a plurality of second memory cells, wherein the first layer comprises a transistor comprising silicon in a channel formation region, wherein the first memory cell and the second memory cell each comprise a vertical transistor, wherein the vertical transistor comprises an oxide semiconductor in a channel formation region, and wherein the first memory cell and the second memory cell have different structures. [10] Semiconductor device comprising: a first layer; a second layer over the first layer; and a third layer above the second layer, wherein the second layer comprises a first memory cell array, wherein the third layer comprises a second memory cell array, wherein the first memory cell array comprises a plurality of first memory cells, wherein the second memory cell array comprises a plurality of second memory cells, wherein the first layer comprises a transistor comprising silicon in a channel formation region, wherein the first memory cell and the second memory cell each comprise a vertical transistor, wherein the vertical transistor comprises an oxide semiconductor in a channel formation region, and wherein the first memory cell and the second memory cell have different structures. [11] The semiconductor device according to claim 9, wherein one of the first memory cell and the second memory cell holds data for a longer time than the other without a power supply. [12] The semiconductor device according to claim 10, wherein one of the first memory cell and the second memory cell holds data for a longer time than the other without a power supply. [13] Semiconductor device comprising: a first layer; and a second layer over the first layer, wherein the second layer comprises a first memory cell array and a second memory cell array, wherein the first memory cell array comprises a plurality of first memory cells, wherein the second memory cell array comprises a plurality of second memory cells, wherein the first layer comprises a transistor comprising silicon in a channel formation region, wherein the first memory cell consists of a vertical transistor and a capacitor, wherein the second memory cell consists of two vertical transistors, and wherein the vertical transistors included in the first memory cell and the second memory cell each comprise an oxide semiconductor in a channel formation region. [14] Semiconductor device comprising: a first layer; a second layer over the first layer; and a third layer above the second layer, wherein the second layer comprises a first memory cell array, wherein the third layer comprises a second memory cell array, wherein the first memory cell array comprises a plurality of first memory cells, wherein the second memory cell array comprises a plurality of second memory cells, wherein the first layer comprises a transistor comprising silicon in a channel formation region, wherein one of the first memory cell and the second memory cell consists of a vertical transistor and a capacitor and the other consists of two vertical transistors, and wherein the vertical transistors included in the first memory cell and the second memory cell each comprise an oxide semiconductor in a channel formation region.

Images