ACCELERATED MEMORY TRAINING THROUGH IN-BAND CONFIGURATION REGISTER UPDATE MODE

Abstract

A configuration register update mode can be implemented as an RWUPD (Register Word Update) mode for a registration clock driver (RCD) or as an MRUPD (Mode Register Update) mode for a DRAM (Dynamic Random Access Memory) device. In update mode, the memory device (either RCD or DRAM) can configure any number of configuration registers using in-band register writes. These in-band register writes can be used to configure DFE (Decision Feedback Equalization) settings, as well as other configuration settings for non-DFE configurations of a memory device interface.

Description

TECHNICAL FIELD

[0001] Descriptions generally refer to computer memory, and more specific descriptions refer to memory interface training. BACKGROUND OF THE INVENTION

[0002] The RCD was programmed using a sideband bus, such as the system management bus (SMBus), prior to training the command / address bus (CABus) and data bus (DQBus). Sideband buses operate at a very low speed (on the order of megahertz (MHz)) relative to the CABus and DQBus (on the order of gigahertz (GHz)). Using a sideband bus for training can result in significant training delays.

[0003] The registration clock driver (RCD) defines in-band training, which is available for the DFE (Decision Feedback Equalization) configuration training option. RCD in-band training defines entry into RWUPD (Register Word Update) mode. In RWUPD mode, the RCD can receive configuration updates until triggered to exit update mode. Because RWUPD mode is restricted to DFE configuration, its training scope is limited.

[0004] It is also understood that updates to the configuration of a DRAM (Dynamic Random Access Memory) device can be performed via mode register writes (MR writes). The writes were performed by the DRAM device in response to a Mode Register Write (MRW) command sent to the DRAM device. Traditionally, a memory controller must train the CA bus before a command such as MRW can be reliably sent to the DRAM device. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The following description includes a discussion of figures with illustrations given by way of example of an implementation. The drawings are to be considered as exemplary and not limiting. As used herein, references to one or more examples are to be understood as describing a particular feature, structure, or characteristic included in at least one implementation of the invention. Terms such as "in an example" or "in an alternative example" appearing herein provide examples of implementations of the invention and do not necessarily all refer to the same implementation. However, they are not necessarily mutually exclusive either. Fig. 1 is a block diagram of an example system with a memory module. Fig. 2 is a block diagram of an example memory module with an RCD having an in-band configuration mode. Fig. 3 is a block diagram of an example memory module with memory devices having an in-band configuration mode. Fig. Figure 4 is an example table for an RWUPD mode. Fig. Figure 5 is an example table for an MRUPD mode. Fig. Figure 6 is an example table for an MRUPD mode that also uses M3C. Fig. Figure 7 is a flowchart of an example process for RWUPD. Fig. Figure 8 is a flowchart of an example process for MRUPD. Fig. Figure 9 is a state diagram of an example of MRUPD. Fig. 10 is a block diagram of an example storage subsystem in which an in-band configuration mode may be implemented. Fig. 11 is a block diagram of an example computing system in which an in-band configuration mode may be implemented. Fig. Figure 12 is a block diagram of an example multi-node network in which an in-band configuration mode may be implemented.

[0006] Descriptions of specific details and implementations follow, including non-limiting descriptions of the figures that may illustrate some or all of the examples, as well as other possible implementations. DETAILED DESCRIPTION OF THE INVENTION

[0007] As described herein, a configuration register update mode can be implemented as a Register Word Update (RWUPD) mode for a registration clock driver (RCD) or as a Mode Register Update (MRUPD) mode for a Dynamic Random Access Memory (DRAM) device. In update mode, the memory device (either RCD or DRAM) can perform the configuration of any number of configuration registers using in-band register writes. The in-band register writes can be used to configure Decision Feedback Equalization (DFE) settings, as well as other configuration settings for non-DFE configurations of a memory device interface.

[0008] As described herein, in-band communication can be used to train any DRAM register or RCD register before training the chip select (CS). One concept involves an extension / enhancement of register word update (RWUPD). RWUPD has been limited to DCATM (Device Command / Address Training Mode) and DFE and can be extended to update any register or any register word. Thus, the system can update the register word configuration via RWUPD mode. By extending RWUPD to update other registers, the use of the SMBus is avoided, which increases the speed of training and setup. Another concept involves mode register update (MRUPD). MRUPD extends the idea of ​​register updates to include in-band communication. Using MRUPD can replace MPC.If the buses are not fully trained, the system can use in-band communication for training.

[0009] Fig. Figure 1 is a block diagram of an example system with a memory module. System 100 includes a socket 110 coupled to a DIMM 120. Socket 110 represents a CPU socket, which may include a CPU 112 and a memory controller 114. DIMM 120 contains multiple DRAM devices.

[0010] System 100 illustrates an example of a system with memory devices sharing a control bus or command bus (command / address bus (C / A bus) 126[0] for one channel and C / A bus 126[1] for the other channel) and data buses (data bus 116[0] for one channel and data bus 116[1] for the other channel). The memory devices are represented as dynamic random access memory (DRAM) devices. Each channel has N DRAM devices, DRAM 132[1:N] (collectively, DRAM devices 132) for one channel and DRAM 134[1:N] (collectively, DRAM devices 134) for the other channel, where N can be any integer. In one example, N includes one or more (error check and correction (ECC)) DRAM devices in addition to the data devices.Each DRAM device 132 and each DRAM device 134 may represent a memory chip with a command bus interface to the memory controller 114, which may be interfaced via the RCD 122.

[0011] In one example, the two separate channels share the C / A bus 124 connection between the memory controller 114 and the RCD 122. In one example, the separate channels have separate C / A buses. The DRAM devices can be accessed individually with device-specific commands and can be accessed in parallel with parallel commands.

[0012] The registration clock driver (RCD) 122 (which may also be referred to as a registered clock driver) provides control for the DIMM (Dual Inline Memory Module) 120. In one example, the RCD 122 receives information from the memory controller 114 and buffers the signals to the various DRAM devices. By buffering the input command signals from the memory controller 114, the controller sees only the RCD 122 load on the command / address bus (CA bus 124) and can then control the timing and signaling to the DRAM devices.

[0013] In one example, the RCD 122 controls the command signals to the DRAM devices 132 through the CA bus 126[0] and controls the signals to the DRAM devices 134 through the CA bus 126[1]. In one example, the RCD 122 has independent command ports for separate channels. In one example, the DIMM 120 includes data buffers to buffer the data bus signals between the DRAM devices of the DIMM 120 and the memory controller 114.

[0014] Data bus 116[0] provides a data bus for DRAM devices 132, which are buffered with data buffer (DB) 142[1:N] (collectively, DBs 142). Data bus 116[1] provides a data bus for DRAM devices 134, which are buffered with data buffer (DB) 144[1:N] (collectively, DBs 144). System 100 illustrates a one-to-one relationship between data buffers and DRAM devices. In one example, there are fewer data buffers than DRAM devices, with DRAM devices sharing a data buffer.

[0015] CA bus 126[0] and CA bus 126[1] (collectively, CA buses 126) are typically unilateral or unidirectional buses for transporting command and address information from memory controller 114 to the DRAM devices. Thus, CA buses 126 may be multi-drop buses. Data bus 116[0] and data bus 116[1], collectively, data buses 116, are traditionally bidirectional point-to-point buses.

[0016] In one example, memory controller 114 includes one or more sideband bus connections to other devices in system 100. Sideband buses refer to buses other than CA bus 124 and buses other than data buses 116. As illustrated, memory controller 114 includes a system management bus (SMBus, represented in system 100 as "SMB" for simplicity) for connection to RCD 122. In one example, memory controller 114 includes an SMBus connection or other sideband bus (SBB) for connection to the DRAM devices. In one example, the SBB connection represents a memory module management control (M3C) bus. Both the SMBus and SBB connections represent sideband bus communication in system 100.

[0017] The sideband bus allows memory controller 114 to provide a command to a device over a connection other than the CA bus. Communication on a sideband bus is not in-band because the command is not received on the CA bus. In one example, communication on the sideband bus allows memory controller 114 to send commands to place a device into a pre-training update mode, which uses in-band communication to perform configuration updates.

[0018] In one example, system 100 supports an RWUPD mode for configuring the RCD interface to the CA bus 124. In one example, system 100 supports an MRUPD mode for configuring the DRAM devices. Configuring the DRAM devices may include configuring the data bus interface, configuring the CA bus interface, or configuring both the CA bus interface and the data bus interface. In update modes, system 100 supports in-band writing of configuration parameters prior to chip select (CS) training.

[0019] With the update modes, system 100 can, in one example, accelerate backside and frontside training for all parametric sweeps. With the increase in in-band commands to perform configuration, system 100 can reduce sideband bus usage. Due to the significant speed difference between in-band communication and out-of-band communication (e.g., using the sideband bus), where in-band communication can be orders of magnitude faster, using in-band communication for configuration updates can improve system boot time.

[0020] The CA bus 124 provides a link for the memory controller 114 to provide command and address information to identify an instruction to be executed, as well as the address for executing the instruction. It is anticipated that the interface to the command bus (e.g., CA bus 124) can be trained to identify preferred settings to ensure proper reception of commands at the RCD 122. Training may iterate through various configuration settings to determine a setting with the best performance, which may vary from system to system.

[0021] With the introduction of a DDR (Double Data Rate) mode for command buses, the command bus interface can include a DFE (Decision Feedback Equalization) with multiple taps (e.g., 2 or 4 taps) to ensure proper data eye alignment on the CA signal lines. DFE refers to a nonlinear equalization circuit that uses information about previously received bits to determine a current bit being received and processed. Other configuration settings can include reference voltage settings, current settings, and other configuration settings. Training sets the parameters to ensure proper communication on the command bus.

[0022] In one example where system 100 supports MRUPD mode, update mode may reduce or eliminate the need for general-purpose instructions (MPC instructions) for configuration. In one implementation, system 100 may replace MPC instructions, replace the voltage reference for chip select (VrefCS) instruction, and replace the voltage reference for instruction / address (VrefCA) instruction. Full use of MRUPD mode for all training may enable the removal of the MPC-encoded opcode table. Alternatively, a system may limit the opcode to a few instructions. Both removing and reducing MPC opcodes may conserve hardware logic within the DRAM devices.

[0023] MRUPD mode and the described RWUPD mode can enable configuration for all possible training modes. In one example, enabling configuration for all training modes involves the following: when the device is triggered to enter update mode (e.g., an SMBus command to trigger RWUPD entry (RWUPDE) or an M3C command to trigger MRUPD entry (MRUPDE)), configuration writes are issued with two commands, one for the register address and another for the configuration data value. The register writes are in-band commands, which speeds up configuration setup.

[0024] As an alternative to triggering MRUPDE with an M3C instruction, in one example, the DRAM devices can enter MRUPD mode by default after power-up. The system can trigger the end of refresh mode with an RWUPD exit instruction (RWUPDX instruction) for the RCD or an MRUPD exit instruction (MRUPDX instruction) for a DRAM. The exit instruction can be used to terminate the refresh loop for issuing configuration register writes.

[0025] The above procedure works for the CA bus in DDR mode at double the data rate. If the DRAM defaults to MRUPD mode / state immediately after power-on, the system can perform MRUPD before chip select training mode (CSTM) and before command / address training mode (CATM). In such a procedure, timing and Vref values ​​can be set via an in-band command rather than using sideband communication. While MRUPD can replace MPC with a single-cycle command, a multi-cycle chip select feature may be required.

[0026] Fig. Figure 2 is a block diagram of an example memory module with an RCD having an in-band configuration mode. System 200 illustrates a system according to an example of system 100.

[0027] The system 200 contains a DIMM 210 (Dual Inline Memory Module), which represents a memory module with a module controller. The RCD 220 represents the module controller. The RCD 220 connects to a host via a CA bus 224 (not specifically shown). The RCD 220 has an interface to the CA bus 224 that can be configured by setting values ​​in registers 222.

[0028] Registers 222 may contain, but are not limited to, DFE settings and termination settings. Each register may contain one or more configuration settings. Registers 222 specifically illustrate DFE to represent configuration settings for the DFE for the CA bus 224, VREF to represent Vref configuration settings, and CA to represent other settings such as termination settings or other configurations for the CA bus 224.

[0029] The RCD 220 can be connected to DRAM devices 232 via the CA bus 244[0] and to DRAM devices 234 via the CA bus 244[1]. In one example, the configuration of registers 222 applies to the interface to the CA bus 224, and the DRAM devices have a separate configuration for the CA bus interconnection from the RCD 220.

[0030] By extending the RWUPD mode for the RCD 220, the system 200 can exit DCSTM in RWUPD and specify the configuration via in-band communication. In one example, the RCD 220 enters RWUPD using SMBus communication and exits RWUPD in response to a CS assertion. In one example, the system 200 has a setup / configuration qualifier when the RCD 220 is in RWUPD. For example, the qualifier can be a chip select (e.g., DCS0 / 1), where asserting the chip select can determine which channel is configured. In one example, each training mode can specify which qualifier is used for the specific training. The training mode qualifier can be the inverse of the RWUpdate qualifier.

[0031] In one example, the host may send the register address (e.g., RW address) and opcode for the RWUPD operation and perform the update operations internally with an RWUPD qualifier (e.g., with hardware acceleration). In one example, system 200 triggers RCD 220 to exit RWUPD with a write to an RCD register (RW32) or via an SMBus command. In one example, registers 222 may include the RW32 RCD register.

[0032] RWUPD can be extended to all training steps (instead of just DFE). In one example, the RWUPD extension can include modifications to significantly reduce training times (for both frontside and backside) and the logic in the RCD.

[0033] In one example, RWUPD entry occurs when the RCD is in training mode and DCS1_[B:A]_n is asserted. The RWUPD operation involves the memory controller sending pairs of DCS1_[B:A]_n asserts. On the first assert, the device samples the target RW address to {DCA[6:0]_[B:A], DPAR_[B:A]}. On the second assert, the device samples the value to be written to the target RW. RWUPD exit may involve writing to a register word, such as writing a one to RW32[7], which may trigger the RCD to exit the RWUPD branch and return to the startup training mode state.

[0034] Fig. 3 is a block diagram of an example memory module with memory devices having an in-band configuration mode. System 300 illustrates a system according to an example of system 100 or an example of system 200.

[0035] System 300 includes a DIMM 310 (Dual Inline Memory Module), which is a memory module with a module controller. The RCD 320 represents the module controller. The RCD 320 connects to a host (not specifically shown). The RCD 320 can connect to DRAM devices 332 via the CA bus 344[0] and to DRAM devices 334 via the CA bus 344[1].

[0036] In one example, DRAM devices 332 include registers 336, and DRAM devices 334 include registers 338. In one example, the configuration of registers 336 applies to the interface of DRAM devices 332 to CA bus 344[0]. In one example, the configuration of registers 338 applies to the interface of DRAM devices 334 to CA bus 344[1].

[0037] Registers 336 and registers 338 may include, but are not limited to, DFE settings and termination settings. Registers 336 and registers 338 specifically illustrate DFE representing a DFE configuration register for storing one or more configuration settings for the DFE for the CA buses, VREF representing Vref configuration settings, and CA representing other settings such as termination settings or other configurations for the CA buses. In one example, MRUPD may be applied to all configuration settings in the DRAM devices for the CA buses. MRUPD may provide a training mode for all configuration register training for the CA bus.

[0038] The system 300 enables a DRAM MRUPD (Mode Register Update) mode. In one example, the MRUPD mode has an MRUPD entry (MRUPDE) and an MRUPD exit (MRUPDX). In one example, MRUPD applies to DDR6 (double data rate version 6). In one example, MRUPD is used in conjunction with an M3C (Memory Module Management Control) bus. An MRUPD mode application can replace MPC, VrefCA, and VrefCS instructions. Without such instructions, the MPC opcode table would not be required. Removing the table saves logic in DRAM and allows access to the mode register at any time and without restriction to any set.

[0039] In one example, MRUPD provides an update mode in DRAM that the DRAM should use for all training steps. With the proposed MRUPD, the system does not need to access the SMBus to sweep any parameters, which is significantly slower than in-band commands. Performing training via in-band access accelerates backside training steps such as CSTM, CATM, and DFE training algorithms and improves system boot time.

[0040] In one example, the in-band register writes are mode register writes (MRWs) based on instructions on the instruction bus prior to the execution of an instruction / address training (CATM) mode. In one example, system 300 provides a first general-purpose instruction (MPC) to enter MRUPD mode. A second MPC may trigger an exit from MRUPD mode.

[0041] Fig. Figure 4 is an example table for an RWUPD mode. Table 400 shows various opcodes. Table 400 contains opcode bits (OP[0:7]), which are the settings column. The definition column describes the settings, and the encoding column contains details about the settings.

[0042] The opcode that configures whether DCSO is included in the exclusive-OR (XOR) operation can be set to OP0 = 0 to exclude DCSO (default), or to include DCSO with OP0 = 1. The opcode that configures whether DCS1 is included in the XOR can be set to OP1 = 0 to exclude DCS1 (default), or to include DCS1 with OP1 = 1. The opcode that configures control signal selection can be set to OP2 = 0 to select DCSO (default), or to select DCS1 with OP2 = 1.

[0043] In one example, there is a register word (RW) in-band update feature where activation is controlled by OP6, where OP6 = 0 disables the RWUPD feature, which is the default, and OP6 = 1 enables the RWUPD feature. In one example, exit from RWUPD can be controlled by OP7, where OP7 = 0 results in no action being taken, leaving the system in RWUPD, and OP7 = 1 results in exiting the RWUPD state (the default).

[0044] In Table 400, the following notes can be added to describe the opcode definitions:

[0045] Note A: DCS1 line - when RWUPD is enabled, DCS1 is the qualifier. DCS1 does not participate in XOR.

[0046] Note B: DCS1 line - if RWUPD is enabled, DCSO is the qualifier. DCSO does not participate in XOR.

[0047] Note C: Users can use RWUPD to change the RWUPD DCS qualifier in a single register setting with previous DCS qualifier.

[0048] Separating RWUPD from other training modes so it can be used for other purposes. RW7E can define a new mode and leave RW32 as it is for Legacy.

[0049] The descriptions for RWUPD refer specifically to configuring the RCD settings. The descriptions for MRUPD refer specifically to configuring the DRAM settings. The concepts of in-band communication for setting the configuration apply to both RWUPD and MRUPD.

[0050] There may be different options for applying MRUPD.

[0051] Option 1 applies to both M3C and MRUPD. With this architecture, using M3C can reduce training time. The system can use M3C communication to trigger MRUPDE and MRUPDX. The system can use MRUPD to configure all DRAM mode registers, where the CS can be a qualifier for MRUPD (e.g., use CS1 as the qualifier to train CS0, and use CS0 as the qualifier to train CS1). The system can use a multi-cycle CS for MRUPD to enter CSTM training and exit with a double CS. In Option 1, the system can switch to the other CS and change the values ​​using MRUPD. The system can then use the M3C instruction to exit. With this architecture, M3C can be used for initializations such as termination, device ID, etc.

[0052] The flow for Option 1 can be described using an example of a process 800. The advantages of Option 1 include: 1) configuration is significantly faster than SMBus training, even when MRUPD is a double instruction (one for address and one for data), 2) elimination of the VrefCA and VrefCS MPC encoding and instructions, 3) potential removal of MPC instructions and opcode tables; and 4) enabling MRUPD mode entry by default upon DRAM power-up, which can avoid M3C instructions.

[0053] Fig. Figure 5 is an example table for an MRUPD mode. Table 500 describes the application of Option 2 for implementing MRUPD. Table 500 contains a function of the initialization and training modes based on OP[7:0]. The Data column describes various modes. Selected modes are shown, while others are omitted.

[0054] The opcode “0000 0000” indicates an exit from CS training mode (CSTM).

[0055] The opcode “0000 0001” indicates entry into CSTM.

[0056] The opcode "0000 1010" indicates an exit from a per-device addressability (PDA) enumeration programming mode.

[0057] The opcode “0000 1011” indicates entry into the PDA enumeration programming mode.

[0058] The opcode "0000 1100" specifies a manual error checking and recovery (ECS) operation.

[0059] In one example, Option 2 applies MPC and M3C (without MRUPD). With such an architecture, additional opcodes can provide additional functionality. The timing of command / address (QCA) and chip select (QCS) signal lines can be controlled via a continuous time linear equalizer (CTLE) and DFE 1-tap, which could require hundreds of register accesses to set the configuration.

[0060] The M3C bus speed can be a controlling factor for training CA and CS signals. In one example, the system encodes the MPC opcodes to account for programming the DFE tap settings. There might be two settings for gain and two more for CTLE. Using the MPC would consume instruction bandwidth while reducing the load on the M3C. Such an architecture would leave VrefCA, VrefCS, and MPC as they are, compared to replacing them as in Option 1. The logic can be reduced with integrated DRAM logic to perform an automatic sweep and compare it internally against the pattern. With Option 2, the M3C can be used for initialization setup such as terminations, device ID, etc., as well as for debugging and validation. Using it for debugging and validation allows some of the MPC instructions to be avoided upfront.

[0061] In one example, Option 2 might contain new MPC opcodes. The 'x' indicates a variable, and therefore the opcodes with 'x' can specify a range.

[0062] The opcode "0000 1101" can be an MRUpdate mode entry (MRUPDE) (by default).

[0063] The opcode "0000 1110" can be an MRUpdate mode exit (MRUPDX).

[0064] The opcodes “101xxxxx” can specify MPC opcodes for DFE tap settings.

[0065] The opcodes “1100 0xxx” can be used for pattern registers.

[0066] The opcodes “1100 10xx” can be used for DFE-CTLE settings.

[0067] The opcodes “1100 11xx” can be used for DFE gain settings.

[0068] It is believed that using so many opcodes could significantly reduce the number of available opcodes for MPC instructions.

[0069] In one example, as described, there are in-band register writes based on instructions on the instruction bus without using a sideband bus. Therefore, the register writes can be RW writes without using the SMBus. The register writes can be mode register writes without using a sideband bus. In one example, as described, in-band register writes can be performed in combination with the use of the SMBus. The register writes can be mode register writes in combination with the use of a sideband bus.

[0070] Fig. Figure 6 is an example table for an MRUPD mode that also uses M3C. Table 600 describes the application of Option 3 for implementing MRUPD. Table 600 contains a function of the initialization and training modes based on OP[7:0]. The Data column describes various modes. Selected modes are shown, while others are omitted.

[0071] The opcode “0000 0000” indicates an exit from CS training mode (CSTM).

[0072] The opcode “0000 0001” indicates entry into CSTM.

[0073] The opcode "0000 1010" indicates an exit from a per-device addressability (PDA) enumeration programming mode.

[0074] The opcode “0000 1011” indicates entry into the PDA enumeration programming mode.

[0075] In one example, the opcodes “0000 1010” and “0000 1011” can be removed as unnecessary.

[0076] The opcode "0000 1100" specifies a manual error checking and recovery (ECS) operation.

[0077] The opcodes “0000 1101” to “0001 1110” represent opcodes reserved for future use (RFU).

[0078] Option 3 applies to MPC, M3C, and MRUPD. In such an architecture, MPC can be used to enter and exit MRUPD. The system can use MRUPD to sweep the DRAM mode registers (MRs). M3C can be used for initialization such as terminations, device ID, etc., as well as for debugging and validation.

[0079] In an example, Option 3 could use the opcodes “0001 1111” to “0110 xxxx” for the MRUPD / M3C command (CMD) operation.

[0080] The opcode “0001 1111” can trigger the application of VrefCA, VrefCS and internal resistance (RTT), including CA signal resistance (RTT_CA), chip select signal resistance (RTT_CS) and clock signal resistance (RTT_CK).

[0081] The opcodes “0010 0xxx” can be group A RTT_CK signals with termination set to ‘xxx’.

[0082] The opcodes “0010 1xxx” can be group B RTT_CK signals with termination set to ‘xxx’.

[0083] The opcodes “0011 0xxx” can be RTT_CS signals of group A, with the termination set to 'xxx'.

[0084] The opcodes “0011 1xxx” can be RTT_CS signals of group B, with the termination set to 'xxx'.

[0085] The opcodes “0100 0xxx” can be RTT_CA signals of group A, with the termination set to 'xxx'.

[0086] The opcodes “0100 1xxx” can be RTT_CA signals of group B, with the termination set to 'xxx'.

[0087] The opcodes '0101 0xxx' can be used to set the data strobe (DQS) park termination, DQS_RTT_PARK, to 'xxx'.

[0088] The opcodes "0101 1xxx" can be used to set the other parking terminations, RTT_PARK, to 'xxx'.

[0089] The opcodes "0110 xxxx" can be used to specify the PDA enumeration ID (the value is set to 'xxxx').

[0090] The opcodes "0111 xxxx" can be used to specify the PDA selection ID (the value is set to 'xxxx').

[0091] The opcodes '1000 xxxx' can be used to configure the delay lock loop timing (tDLLK) and the time required between column-to-column instructions (tCCD)L) (the value is set to 'xxxx').

[0092] The other opcode encodings can be reserved.

[0093] Fig. Figure 7 is a flowchart of an example process for RWUPD. Process 700 represents a process flow for in-band RCD configuration. In one example, the memory controller is to write the configuration to the RCD at 702. The controller may determine whether the command interface is trained at 704.

[0094] If the interface is already trained, the system can configure the RCD with regular RW write commands at 708 on the YES branch of 706. If the interface is not yet trained, the RCD can receive a command at 706 on the NO branch to trigger RWUPD (Register Word Update) mode at 710. For example, the system can trigger entry into RWUPD with one or more SMBus commands.

[0095] The RCD enters RWUPD at 712 and receives in-band commands to write the Vref configuration, the termination configuration, or the DFE configuration, or a combination of these, at 714. The controller can send any RWUPD settings that the RCD writes to the register.

[0096] The system can identify the configuration address identifier, e.g., with an RWUPD1 command, at 716. The system can identify configuration data, e.g., with an RWUPD2 command, at 718. The system can update the configuration settings until an RWUPD exit command is executed. Therefore, if there is no RWUPD exit, at 720 (NO branch), the configuration updates can continue at 716.

[0097] In response to an RWUPD exit, the RCD may exit RWUPD at 720, YES branch, and wait for the next configuration write event at 722. After configuration with regular RW write commands, the system may also exit configuration mode at 708 and wait for the next configuration write event at 722.

[0098] Fig. Figure 8 is a flowchart of an example process for MRUPD. Process 800 represents a process flow for in-band DRAM configuration. In one example, the memory controller is to write the configuration to the DRAM at 802. The controller may determine whether the DRAM's command interface is trained at 804.

[0099] If the interface is already trained, the system can configure the DRAM at 808 using regular mode register write (MRW) commands on the YES branch of 806. If the interface is not yet trained, the RCD can receive a command on the NO branch of 806 to initiate MRUPD (Mode Register Update) mode at 810.

[0100] The device enters MRUPD at 812 and receives in-band commands to write the Vref configuration, the termination configuration, or the DFE configuration, or a combination of these, at 814. The controller can send any MRUPD settings that the DRAM writes to the register.

[0101] The system can identify the configuration address identifier, e.g., with an MRUPD1 command, at 816. The system can identify configuration data, e.g., with an MRUPD2 command, at 818. The system can update the configuration settings until an MRUPD exit command is executed. Therefore, if there is no MRUPD exit, at 820, the NO branch, the configuration updates can continue at 816.

[0102] In response to an MRUPD exit, the DRAM may exit MRUPD at 820 (YES branch) and wait for the next configuration write event at 822. After configuration with regular RW write commands, the system may also exit configuration mode at 808 and wait for the next configuration write event at 822.

[0103] Fig. 9 is a state diagram of an example MRUPD. System 900 illustrates various states in an example MRUPD flow. In one example, in response to a power-on reset, the memory enters the MRUPD Inactive state 902, which is a state in which the memory can perform in-band training with MRUPD but is inactive because it does not currently need to perform any operations.

[0104] As an alternative to entering MRUPD-Inactive on power-on reset during debugging time, commands on the M3C bus (which may be a subset of I3C-Basic).

[0105] In one example, the memory may be shifted to the MRUPD-ADR state 904 with a multi-cycle chip select (CS) assertion. In response to a CS assertion, the selected memory device may look for an MRUPD address for a configuration update. Upon another CS assertion, which may also be a multi-cycle assertion, the memory is shifted to the MRUPD-Data state 906, where the memory device acquires the data to be written to the address of the previous state.

[0106] In one example, the written mode register update may be an update that disables MRUPD mode. In response to such an update, memory may enter the MRUPD Exit state 908 and exit MRUPD mode.

[0107] In one example, 902 and 906 may represent states for general mode register updates. Such general updates are not necessarily associated with the activation of a training mode. The update may be used, for example, for Vref configuration. If Vref is swept out of range in one example, the system may use the M3C bus for recovery.

[0108] In one example, MRUPD data 906 may trigger CSTM entry 910 with a mode register configuration write to enable CSTM. In one example, upon a CS enable, where all CA pins are high (e.g., to a high logic state), the memory enters the CSTM state 912 to perform chip select training. In one example, during CS training, the CA pins may be held high. In one example, no instructions are supported during CSTM. Alternatively, the DRAM device may disable decoding of any instructions.

[0109] In one example, in response to a CS assertion in which all CA pins are driven low, the memory may be shifted to the CSTM exit state 914. In response to exiting CSTM mode, the memory may return to the MRUPD inactive state 902.

[0110] In one example, MRUPD data 906 may trigger CATM entry 920 with a mode register configuration write to enable CATM. In one example, upon a CS assertion with a proper CA pattern on the CA pins (e.g., CA encoding or a CATM command), the memory enters the CATM state 922 to perform CA bus training. In one example, during CA bus training, the CA pins may be held at the CA encoding, which triggers entry into CATM.

[0111] In one example, in response to a multi-cycle CS assertion in which all CA pins are driven high, the memory may be shifted to the CATM exit state 924. In response to exiting CATM mode, the memory may return to the MRUPD inactive state 902.

[0112] Fig. 10 is a block diagram of an example memory subsystem in which an in-band configuration mode may be implemented. System 1000 includes a processor and elements of a memory subsystem in a computing device. System 1000 represents a system having a memory subsystem according to an example of system 100, an example of system 200, or an example of system 300.

[0113] In one example, system 1000 includes an RCD 1072 in memory module 1070. The configuration of RCD 1072 may be programmed using in-band register writes as described herein. Memory device 1040 may represent a DRAM device, the configuration of which may be programmed using in-band register writes as described herein.

[0114] The processor 1010 represents a processing unit of a computing platform that may execute an operating system (OS) and applications, which may collectively be referred to as hosts or users of the memory. The OS and the applications perform operations that result in memory accesses. The processor 1010 may include one or more separate processors. Each separate processor may include a single processing unit, a multi-core processing unit, or a combination. The processing unit may be a primary processor such as a CPU (central processing unit), a peripheral processor such as a GPU (graphics processing unit), or a combination. The memory accesses may also be initiated by devices such as a network controller or a disk controller. Such devices may be integrated with the processor in some systems or may be connected via a bus (e.g.,PCI Express) to the processor, or a combination of both. The System 1000 can be implemented as a SOC (System-on-a-Chip) or can be implemented with standalone components.

[0115] Reference to memory devices can apply to different memory types. Memory devices often refer to volatile memory technologies. Volatile memory is memory whose state (and thus the data stored on it) is indeterminate if the power supply to the device is interrupted. Non-volatile memory refers to memory whose state is determined even if the power supply to the device is interrupted. Dynamic volatile memory requires refreshing the data stored in the device to maintain a state. An example of dynamic volatile memory includes DRAM (Dynamic Random Access Memory) or some variant, such as synchronous DRAM (SDRAM). A memory subsystem as described herein may be compatible with a number of memory technologies, such as DDR4 (Double Data Rate Version 4, JESD79-4,originally published in September 2012 by JEDEC (Joint Electron Device Engineering Council, now JEDEC Solid State Technology Association)), LPDDR4 (Low Power DDR Version 4, JESD209-4, originally published by JEDEC in August 2014), WIO2 (Wide I / O 2 (WidelO2), JESD229-2, originally published by JEDEC in August 2014), HBM (High Bandwidth Memory DRAM, JESD235A, originally published by JEDEC in November 2015), DDR5 (DDR Version 5, originally published by JEDEC in July 2020), LPDDR5 (LPDDR Version 5, JESD209-5, originally published by JEDEC in February 2019), HBM2 (HBM Version 2, JESD235C, originally published by JEDEC in January 2020), HBM3 (HBM Version 3, JESD238, originally published by JEDEC in January 2022), DDR6 (DDR version 6, currently under discussion), GDDR7 (Graphics DDR version 7,currently being discussed) or other or combinations of storage technologies and technologies based on derivatives or extensions of such specifications.

[0116] Memory controller 1020 represents one or more memory control circuits or devices for system 1000. In one example, memory controller 1020 is located on the same semiconductor substrate as processor 1010. Memory controller 1020 represents control logic that generates memory access commands in response to the execution of operations by processor 1010. Memory controller 1020 accesses one or more memory devices 1040. Memory devices 1040 may be DRAM devices according to any of the above. In one example, memory devices 1040 are organized and managed as different channels, with each channel coupled to buses and signal lines coupled in parallel to multiple memory devices. Each channel is independently operable.Thus, each channel is accessed and controlled independently, and timing, data transfer, command and address exchange, and other operations are separate for each channel. Coupling can refer to electrical coupling, communicative coupling, physical coupling, or a combination of these. Physical coupling can involve direct contact. Electrical coupling involves an interface or interconnection that allows electrical flow between components or enables signaling between components, or both. Communicative coupling involves connections, including wired or wireless, that allow components to exchange data.

[0117] In one example, settings for each channel are controlled by separate mode registers or other register settings. In one example, each memory controller 1020 manages a separate memory channel, although system 1000 may be configured to have multiple channels managed by a single controller or to have multiple controllers on a single channel. In one example, memory controller 1020 is part of host processor 1010, such as logic implemented on the same die or implemented in the same package space as the processor.

[0118] The memory controller 1020 includes I / O interface logic 1022 for coupling to a memory bus, such as a memory channel, as mentioned above. The I / O interface logic 1022 (as well as the I / O interface logic 1042 of the memory device 1040) may include pins, pads, connectors, signal lines, traces, or wires, or other hardware for connecting the devices, or a combination thereof. The I / O interface logic 1022 may include a hardware interface. As illustrated, the I / O interface logic 1022 includes at least drivers / transceivers for signal lines. Typically, wires in an IC interface are coupled to interface signal lines or traces or other wires between devices via a contact pad, pin, or connector.The I / O interface logic 1022 may include drivers, receivers, transceivers, or terminators, or other circuitry or combinations of circuitry for exchanging signals on the signal lines between the devices. Exchanging signals includes transmitting and / or receiving. Although the I / O 1022 from the memory controller 1020 is shown coupled to the I / O 1042 of the memory device 1040, it should be understood that in an implementation of the system 1000 where groups of memory devices 1040 are accessed in parallel, multiple memory devices may include I / O interfaces to the same interface of the memory controller 1020. In an implementation of the system 1000 that includes one or more memory modules 1070, the I / O 1042 may include interface hardware of the memory module in addition to interface hardware on the memory device itself.Other memory controllers 1020 will have separate interfaces to other memory devices 1040.

[0119] The bus between the memory controller 1020 and the memory devices 1040 may be implemented as multiple signal lines coupling the memory controller 1020 to the memory devices 1040. The bus may typically include at least clock (CLK) 1032, command / address (CMD) 1034, data (DQ) 1036, and zero or more other signal lines 1038. In one example, a bus or connection between the memory controller 1020 and the memory may be referred to as a memory bus. In one example, the memory bus is a multi-drop bus. The signal lines for CMD may be referred to as a "C / A bus" (or ADD / CMD bus, or another designation indicating transfer of command (C or CMD) and address (A or ADD) information), and the signal lines for write and read DQ may be referred to as a "data bus."In one example, independent channels include different clock signals, C / A buses, data buses, and other signal lines. Thus, system 1000 can be considered to include multiple "buses" in the sense that an independent interface path can be considered a separate bus. It should be understood that a bus may include, in addition to the lines explicitly shown, strobe signaling lines, warning lines, auxiliary lines, and / or other signal lines, or a combination thereof. It should also be understood that serial bus technologies may be used to connect between memory controller 1020 and memory devices 1040. One example of a serial bus technology is 8B10B encoding and transmission of high-speed data with embedded clock over a single differential pair of signals in each direction.In one example, CMD 1034 represents signal lines shared in parallel with multiple memory devices. In one example, multiple memory devices share encode command signal lines of CMD 1034 and each have a separate chip select (CS_n) signal line to select individual memory devices.

[0120] It should be understood that in the example of system 1000, the bus between the memory controller 1020 and the memory devices 1040 includes a slave command bus CMD 1034 and a slave bus for carrying write and read data, DQ 1036. In one example, the data bus may include bidirectional lines for read data and for write / command data. In another example, the slave bus DQ 1036 may include unidirectional write signal lines for writing data from the host to the memory and may include unidirectional lines for reading data from the memory to the host. Depending on the selected memory technology and the selected system design, the other signal lines 1038 may accompany a bus or subbus, such as the strobe lines DQS.Based on an embodiment of the system 1000, or an implementation if an embodiment supports multiple implementations, the data bus may have more or less bandwidth per memory device 1040. For example, the data bus may support memory devices having either a x4 interface, an x8 interface, a x16 interface, or another interface. The convention "xW," where W is an integer related to an interface size or width of the interface of the memory device 1040, represents a number of signal lines for exchanging data with the memory controller 1020. The interface size of the memory devices is a controlling factor in how many memory devices can be used simultaneously per channel in the system 1000 or can be coupled in parallel with the same signal lines.In one example, high-bandwidth memory devices, wide interface devices, or stacked memory configurations or combinations may enable wider interfaces, such as an x128 interface, an x256 interface, an x512 interface, an x1024 interface, or other data bus interface width.

[0121] In one example, the memory devices 1040 and the memory controller 1020 exchange data over the data bus in a burst or a sequence of consecutive data transfers. The burst corresponds to a number of transfer cycles related to a bus frequency. In one example, the transfer cycle may be an entire clock cycle for transfers that occur on the same clock or strobe signal edge (e.g., on the rising edge). In one example, each clock cycle, which relates to a cycle of the system clock, is separated into multiple unit intervals (UI), where each UI is a transfer cycle. For example, double-data-rate transfers trigger on both edges of the clock signal (e.g., rising and falling). A burst may last for a configured number of UIs, which may be a configuration stored in a register, or may be triggered spontaneously.For example, a sequence of eight consecutive transfer periods can be considered a burst length of eight (BL8), and each memory device 1040 can transfer data in each UI. Accordingly, an x8 memory device operating at BL8 can transfer 64 data bits (8 data signal lines times 8 data bits transferred per line over the burst). It should be understood that this simple example is merely illustrative and not limiting.

[0122] The memory devices 1040 represent memory resources for the system 1000. In one example, each memory device 1040 is a separate memory die. In one example, each memory device 1040 may interface with multiple (e.g., 2) channels per device or die. Each memory device 1040 includes I / O interface logic 1042, which has a bandwidth determined by the device implementation (e.g., x16 or x8 or other interface bandwidth). The I / O interface logic 1042 enables the memory devices to interface with the memory controller 1020. The I / O interface logic 1042 may include a hardware interface and may correspond to the memory controller's I / O 1022, but at the memory device end. In one example, multiple memory devices 1040 are connected in parallel to the same command and data buses.In another example, multiple memory devices 1040 are connected in parallel to the same command bus and connected to different data buses. For example, system 1000 may be configured with multiple memory devices 1040 coupled in parallel, with each memory device responding to a command and accessing memory resources 1060 within each. For a write operation, a single memory device 1040 may write a portion of the overall data word, and for a read operation, a single memory device 1040 may retrieve a portion of the overall data word. The remaining bits of the word are provided or received from other memory devices in parallel.

[0123] In one example, the memory devices 1040 are disposed directly on a motherboard or host system platform (e.g., a PCB (printed circuit board) or substrate on which the processor 1010 is disposed) of a computing device. In one example, the memory devices 1040 may be organized into memory modules 1070. In one example, the memory modules 1070 may represent dual in-line memory modules (DIMMs). In one example, the memory modules 1070 represent another organization of multiple memory devices to share at least a portion of access or control circuitry, which may be a separate circuit, a separate device, or a separate board from the host system platform.The memory modules 1070 may include multiple memory devices 1040, and the memory modules may include support for multiple separate channels to the included memory devices disposed thereon. In another example, the memory devices 1040 may be integrated into the same package as the memory controller 1020, such as through techniques such as multi-chip module (MCM), package-on-package, through-silicon via (TSV), or other techniques or combinations. Likewise, in one example, multiple memory devices 1040 may be integrated into memory modules 1070, which themselves may be integrated into the same package as the memory controller 1020. It should be understood that for these and other implementations, the memory controller 1020 may be part of the host processor 1010.

[0124] The memory devices 1040 each include one or more memory arrays 1060. The memory array 1060 represents addressable memory locations or storage locations for data. Typically, the memory array 1060 is managed as rows of data accessed via wordline (rows) and bitline (individual bits within a row) control. The memory array 1060 may be organized as separate channels, ranks, and memory banks. Channels may refer to independent control paths to memory locations within the memory devices 1040. Ranks may refer to common locations across multiple parallel memory devices (e.g., same row addresses within different devices). Banks may refer to subarrays of memory locations within a memory device 1040. In one example, banks are divided into subbanks with at least some of the shared circuitry (e.g.,Drivers, signal lines, control logic) for the subbanks, allowing separate addressing and access. It is understood that channels, ranks, banks, subbanks, bank groups, or other organizations of memory locations and combinations of organizations may overlap in their application to physical resources. For example, the same physical memory locations may be accessed via a specific channel as a specific bank, which may also belong to a rank. Thus, the organization of memory resources is understood to be inclusive and not exclusive.

[0125] In one example, the memory devices 1040 include one or more registers 1044. The register 1044 represents one or more storage devices or locations that provide configuration or settings for the operation of the memory device. In one example, the register 1044 may provide a storage location for the memory device 1040 to store data for access by the memory controller 1020 as part of a control or management operation. In one example, the register 1044 includes one or more mode registers. In one example, the register 1044 includes one or more general-purpose registers. The configuration of locations within the register 1044 may configure the memory device 1040 to operate in different "modes," where command information may trigger different operations within the memory device 1040 based on the mode.Additionally or alternatively, different modes may also trigger different operations of address information or other signal lines depending on the mode. Settings of register 1044 may specify a configuration for I / O settings (e.g., timing, termination or ODT (on-die termination) 1046, driver configuration, or other I / O settings).

[0126] In one example, memory device 1040 includes ODT 1046 as part of the interface hardware associated with I / O 1042. ODT 1046 may be configured as mentioned above and may provide specified signal lines with settings for an impedance to be applied to the interface. In one example, ODT 1046 is applied to DQ signal lines. In one example, ODT 1046 is applied to command signal lines. In one example, ODT 1046 is applied to address signal lines. In one example, ODT 1046 may be applied to any combination of the foregoing. The ODT settings may be changed based on whether a memory device is a selected target of an access operation or a non-target device. The ODT 1046 settings may affect the timing and reflections of signaling on the terminated lines.Careful control via the ODT 1046 can enable higher-speed operation with improved applied impedance and load matching. The ODT 1046 can be applied to specific signal lines of the I / O interface 1042, 1022 (for example, ODT for DQ lines or ODT for CA lines) and is not necessarily applied to all signal lines.

[0127] The storage device 1040 includes a controller 1050 that represents control logic within the storage device for controlling internal operations within the storage device. For example, the controller 1050 decodes commands sent by the storage controller 1020 and generates internal operations to execute or satisfy the commands. The controller 1050 may be referred to as an internal controller and is separate from the host's storage controller 1020. The controller 1050 may determine which mode is selected based on the register 1044 and configure the internal execution of operations for accessing the storage resources 1060 or other operations based on the selected mode.Controller 1050 generates control signals to control the routing of bits within memory device(s) 1040, to provide an appropriate interface for the selected mode, and to route a command to the appropriate memory locations or addresses. Controller 1050 includes command logic 1052 that can decode an instruction encoding received on command and address signal lines. Thus, command logic 1052 can be or include an instruction decoder. With command logic 1052, the memory device can identify instructions and generate internal operations to execute requested instructions.

[0128] Referring again to memory controller 1020, memory controller 1020 includes command logic (CMD logic) 1024, which represents logic or circuitry for generating commands to be sent to memory device 1040. Generation of the commands may refer to pre-scheduling the command or preparing queued commands ready to be sent. Generally, signaling in memory subsystems includes address information within or accompanying the command to specify or select one or more memory locations where the memory devices should execute the command. In response to scheduling transactions for memory device 1040, memory controller 1020 may issue commands via I / O 1022 to cause memory device 1040 to execute the commands.In one example, the controller 1050 of the memory device 1040 receives and decodes command and address information received from the memory controller 1020 via I / O 1042. Based on the received command and address information, the controller 1050 can control the timing of operations of the logic and circuitry within the memory device 1040 to execute the commands. The controller 1050 is responsible for compliance with standards or specifications within the memory device 1040, such as timing and signaling requirements. The memory controller 1020 can implement compliance with standards or specifications through access scheduling and control.

[0129] The memory controller 1020 includes a scheduler 1030, which represents logic or circuitry for generating and ordering transactions to be sent to the memory device 1040. From one perspective, the primary function of the memory controller 1020 could be said to be scheduling memory access and other transactions to the memory device 1040. Such scheduling may include generating the transactions themselves to implement the processor 1010's requests for data and to maintain the integrity of the data (such as with instructions related to updating). The transactions may include one or more instructions and result in the transfer of instructions or data, or both, over one or more timing cycles, such as clock cycles or unit intervals.Transactions can be for access such as read or write or related commands or a combination, and other transactions can include memory management commands for configuration, settings, data integrity or other commands or a combination.

[0130] The memory controller 1020 typically includes logic, such as the scheduler 1030, to enable selection and ordering of transactions to improve the performance of the system 1000. Thus, the memory controller 1020 can choose which of the pending transactions should be sent to the memory device 1040 and in what order, which is typically achieved using far more complex logic than a simple first-in, first-out algorithm. The memory controller 1020 manages the transmission of the transactions to the memory device 1040 and manages the timing associated with the transaction. In one example, transactions include deterministic timing, which is managed by the memory controller 1020 and can be used in determining how to schedule the transactions with the scheduler 1030.

[0131] In one example, memory controller 1020 includes refresh (REF) logic 1026. Refresh logic 1026 may be used for memory resources that are volatile and need to be refreshed to maintain a deterministic state. In one example, refresh logic 1026 specifies a location for refresh and a type of refresh to be performed. Refresh logic 1026 may trigger a self-refresh within memory device 1040 or perform external refreshes, which may be referred to as auto-refresh commands, by sending refresh commands, or a combination. In one example, controller 1050 includes refresh logic 1054 within memory device 1040 to apply refresh within memory device 1040.In one example, refresh logic 1054 generates internal operations to perform a refresh according to an external refresh received from memory controller 1020. Refresh logic 1054 may determine whether a refresh is directed to memory device 1040 and which memory resources 1060 are to be refreshed in response to the command.

[0132] Fig. 11 is a block diagram of an example computing system in which an in-band configuration mode may be implemented. System 1100 represents a computing device according to any present example and may be a laptop computer, a desktop computer, a tablet computer, a server, a gaming or entertainment control system, an embedded computing device, or another electronic device. System 1100 represents a system with storage according to an example of system 100, an example of system 200, or an example of system 300.

[0133] In one example, system 1100 includes a memory subsystem 1120 with RCD 1124 in a memory module. The configuration of RCD 1124 may be programmed using in-band register writes as described herein. Memory 1130 may represent a DRAM device whose configuration may be programmed using in-band register writes as described herein. In-Band Configuration (CONFIG) 1190 represents the components that enable the system to perform in-band register configuration updates using an update mode.

[0134] System 1100 includes a processor 1110, which may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware, or a combination thereof, to provide processing or execution of instructions for system 1100. Processor 1110 may be a host processor device. Processor 1110 controls the overall operation of system 1100 and may be or include one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or a combination of such devices.

[0135] System 1100 includes Boot / Config 1116, which represents storage for storing boot code (e.g., Basic Input / Output System (BIOS)), configuration settings, security hardware (e.g., Trusted Platform Module (TPM)), or other system-level hardware operating outside of a host OS. Boot / Config 1116 may include a non-volatile storage device, such as read-only memory (ROM), flash memory, or other storage devices.

[0136] In one example, system 1100 includes an interface 1112 coupled to processor 1110, which may represent a higher-speed or high-throughput interface for system components requiring higher-bandwidth connections, such as memory subsystem 1120 or graphics interface components 1140. Interface 1112 represents interface circuitry, which may be a standalone component or integrated on a processor die. Interface 1112 may be integrated as circuitry into the processor chip or as a component into a system-on-a-chip. Where present, graphics interface 1140 is linked to graphics components to provide a visual display to a user of system 1100. Graphics interface 1140 may be a standalone component or integrated into the processor chip or system-on-a-chip.In one example, graphics interface 1140 may drive a high-definition (HD) display or an ultra-high-definition (UHD) display that provides output to a user. In one example, the display may include a touchscreen display. In one example, graphics interface 1140 generates a display based on data stored in memory 1130, or based on operations performed by processor 1110, or both.

[0137] The memory subsystem 1120 represents the main memory of the system 1100 and provides storage for code to be executed by the processor 1110 or data values ​​to be used in executing a routine. The memory subsystem 1120 may include one or more variants of random access memory (RAM), such as DRAM, 3DXP (three-dimensional crosspoint), or other storage devices, or a combination of such devices. The memory 1130 stores and hosts, among other things, the operating system (OS) 1132 to provide a software platform for executing instructions in the system 1100. In addition, the applications 1134 may be executed on the software platform of the OS 1132 from the memory 1130. The applications 1134 represent programs that have their own operating logic for performing the execution of one or more functions.The processes 1136 represent agents or routines that provide support functions to the OS 1132 or one or more applications 1134, or a combination. The OS 1132, the applications 1134, and the processes 1136 provide software logic to provide functions for the system 1100. In one example, the memory subsystem 1120 includes a memory controller 1122, which is a memory controller for generating and issuing commands to the memory 1130. It is understood that the memory controller 1122 could be a physical part of the processor 1110 or a physical part of the interface 1112. For example, the memory controller 1122 may be an integrated memory controller integrated into circuitry with the processor 1110, such as integrated into the processor chip or a system-on-a-chip.

[0138] Although not specifically illustrated, it should be understood that system 1100 may include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, interface buses, or others. Buses or other signal lines may communicatively or electrically couple components together, or may couple components both communicatively and electrically. Buses may include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuitry, or a combination thereof. The buses may include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB) bus, another bus, or a combination thereof.

[0139] In one example, system 1100 includes an interface 1114 that can be coupled to interface 1112. Interface 1114 can be a lower-speed interface than interface 1112. In one example, interface 1114 represents interface circuitry that can include standalone components and integrated circuitry. In one example, multiple user interface components or peripheral components, or both, are coupled to interface 1114. Network interface 1150 provides system 1100 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks.Network interface 1150 may include an Ethernet adapter, wireless connection components, cellular network connection components, USB (Universal Serial Bus), or other wired or wireless standards-based or proprietary interfaces. Network interface 1150 may exchange data with a remote device, which may include sending data stored in memory or receiving data to be stored in memory.

[0140] In one example, system 1100 includes one or more input / output (I / O) interfaces 1160. I / O interface 1160 may include one or more interface components through which a user interacts with system 1100 (e.g., audio interfaces, alphanumeric, tactile / touch-sensitive, or other interfaces). Peripheral interface 1170 may include any hardware interface not specifically mentioned above. Peripherals generally refer to devices that establish a dependent connection to system 1100. A dependent connection is a connection where system 1100 provides the software platform or hardware platform, or both, on which the operation is performed and with which a user interacts.

[0141] In one example, system 1100 includes a storage subsystem 1180 for storing data in a non-volatile manner. In one example, in certain system implementations, at least certain components of storage 1180 may overlap with components of memory subsystem 1120. Storage subsystem 1180 includes one or more storage devices 1184, which may be or include any conventional medium for storing large amounts of data in a non-volatile manner, such as one or more magnetic, solid-state, NAND, 3DXP, or optical disks, or a combination. Storage 1184 maintains code or instructions and data 1186 in a persistent state (i.e., the value is retained despite power interruption to system 1100).Storage 1184 may generally be considered "memory," although memory 1130 is typically the execution or working memory for providing instructions to processor 1110. While storage 1184 is non-volatile, memory 1130 may include volatile storage (i.e., the value or state of the data is indeterminate if power to system 1100 is interrupted). In one example, storage subsystem 1180 includes a controller 1182 for interfacing with storage 1184. In one example, controller 1182 is a physical part of interface 1114 or processor 1110, or may include circuitry or logic in both processor 1110 and interface 1114.

[0142] The power source 1102 provides power to the components of the system 1100. More specifically, the power source 1102 typically interfaces with one or more power supplies 1104 in the system 1100 to provide power to the components of the system 1100. In one example, the power supply 1104 includes an AC-to-DC (alternating current to direct current) adapter for plugging into a wall outlet. Such AC power may be a renewable energy power source 1102 (e.g., solar power). In one example, the power source 1102 includes a DC power source, such as an external AC-to-DC converter. In one example, the power source 1102 or the power supply 1104 includes wireless charging hardware for charging via proximity to a charging pad. In one example, the power source 1102 may include an internal battery or fuel cell source.

[0143] Fig.12 is a block diagram of an example multi-node network in which an in-band configuration mode can be implemented. System 1200 represents a network of nodes capable of applying adaptive ECC. In one example, system 1200 represents a data center. In one example, system 1200 represents a server farm. In one example, system 1200 represents a data cloud or a processing cloud.

[0144] System 1200 illustrates a system with storage according to an example of system 100, or an example of system 200, or an example of system 300. In one example, storage node 1222 includes memory modules with an RCDr (not explicitly shown). The configuration of the RCD may be programmed using in-band register writes according to any descriptions herein, as represented by in-band configuration (CONFIG) 1292. System 1200 may include memory devices according to any descriptions herein, and in-band configuration (CONFIG) 1290 illustrates the ability to use in-band register writes according to any descriptions herein to program an RCD and / or a memory device.

[0145] One or more clients 1202 make requests to system 1200 over network 1204. Network 1204 represents one or more local area networks or wide area networks, or a combination thereof. Clients 1202 may be human or machine clients that generate requests for system 1200 to perform operations. System 1200 executes applications or data computing tasks requested by clients 1202.

[0146] In one example, system 1200 includes one or more racks representing structural and interconnect resources for housing and connecting multiple compute nodes. In one example, rack 1210 includes multiple nodes 1230. In one example, rack 1210 hosts multiple blade components, blade 1220[0], ..., blade 1220[N-1], collectively blades 1220. Hosting refers to providing power, structural or mechanical support, and interconnection. Blades 1220 may refer to printed circuit board (PCB) computing resources, where a PCB houses the hardware components for one or more nodes 1230. In one example, blades 1220 do not include a chassis or enclosure or other "box" other than that provided by rack 1210. In one example, blades 1220 include an exposed connector enclosure for connecting to rack 1210.In one example, the system 1200 does not include a rack 1210, and each blade 1220 includes a chassis or enclosure that may be stacked with or otherwise located in close proximity to other blades and enables interconnection of the nodes 1230.

[0147] The system 1200 includes a fabric 1270 that represents one or more interconnectors for nodes 1230. In one example, the fabric 1270 includes multiple switches 1272 or routers or other hardware to route signals between the nodes 1230. Additionally, the fabric 1270 may couple the system 1200 to the network 1204 for access by the clients 1202. In addition to routing devices, the fabric 1270 may be considered to include the cables or ports or other hardware devices for coupling the nodes 1230 together. In one example, the fabric 1270 has one or more associated protocols to manage the routing of signals through the system 1200. In one example, the protocol or protocols depend at least in part on the hardware devices used in the system 1200.

[0148] As illustrated, rack 1210 includes N blades 1220. In one example, system 1200 includes a rack 1250 in addition to rack 1210. As illustrated, rack 1250 includes M blade components, blade 1260[0], ..., blade 1260[M-1], collectively blades 1260. M does not necessarily equal N; accordingly, it is understood that various different hardware device components could be used and coupled together via fabric 1270 to form system 1200. Blades 1260 may be the same as or similar to blades 1220. Nodes 1230 may be any type of node and are not necessarily all the same type of node. System 1200 is neither limited to being homogeneous nor is it limited to being non-homogeneous.

[0149] The nodes in system 1200 may include compute nodes, memory nodes, storage nodes, accelerator nodes, or other nodes. Rack 1210 is represented by storage node 1222 and storage node 1224, which represent shared system memory resources and shared persistent storage, respectively. One or more nodes of rack 1250 may be a memory node or a storage node.

[0150] Nodes 1230 represent examples of compute nodes. For simplicity, only the compute node in blade 1220[0] is illustrated in detail. However, other nodes in system 1200 may be the same or similar. At least some nodes 1230 are compute nodes with processor (Proc) 1232 and memory 1240. A compute node refers to a node with processing resources (e.g., one or more processors) that executes an operating system and can receive and process one or more tasks. In one example, at least some nodes 1230 are server nodes with a server as processing resources, represented by processor 1232 and memory 1240.

[0151] Storage node 1222 represents an example of a storage node with system memory external to the compute nodes. The storage nodes may include a controller 1282 representing a processor on the node for managing access to the memory. The storage nodes include memory 1284 as storage resources to be shared among multiple compute nodes.

[0152] Storage node 1224 represents an example of a storage server, which refers to a node with more storage resources than a compute node. Instead of having processors for executing tasks, a storage server includes processing resources for managing access to the storage nodes within the storage server. The storage nodes may include the controller 1286 for managing access to the storage 1288 of the storage node.

[0153] In one example, node 1230 includes an interface controller 1234 that represents logic for controlling access by node 1230 to fabric 1270. The logic may include hardware resources for interconnecting with the physical interconnect hardware. The logic may include software or firmware logic for managing the interconnect. In one example, interface controller 1234 is or includes a host fabric interface, which may be a fabric interface according to any example described herein. The interface controllers for storage node 1222 and storage node 1224 are not explicitly shown.

[0154] Processor 1232 may include one or more separate processors. Each separate processor may include a single processing unit, a multi-core processing unit, or a combination. The processing unit may be a primary processor such as a CPU (central processing unit), a peripheral processor such as a GPU (graphics processing unit), or a combination. Memory 1240 may be or include storage devices represented by memory 1240 and a memory controller represented by controller 1242.

[0155] In one aspect, a device includes: a hardware interface for coupling to a command bus, wherein the hardware interface is to receive a configuration register update mode command to trigger entry into a configuration register update mode; a decision feedback equalization (DFE) configuration register for storing a first configuration setting for the hardware interface to the command bus; and a second configuration register for a configuration setting other than DFE, wherein the second configuration register is to store a second configuration setting for the hardware interface to the command bus; wherein the device is to update the second configuration register with in-band register writes in the configuration register update mode.

[0156] In one example of the device, the in-band register writes avoid using sideband bus communication to update the second configuration register. According to one of the preceding examples of the device, in one example, the configuration register update mode includes a training mode for the entire configuration register training. According to one of the preceding examples of the device, in one example, the configuration register update mode includes a register word update (RWUPD) mode for a registration clock driver (RCD). According to a preceding example of the device, in one example, the in-band register writes include register word (RW) writes based on commands on the command bus, without using a system management bus (SMBus).According to a previous example of the device, in one example, the in-band register writes include register word (RW) writes based on commands on the command bus in combination with the use of a system management bus (SMBus). According to one of the previous examples of the device, in one example, the configuration register update mode includes a mode register update (MRUPD) mode for a dynamic random access memory (DRAM) device. According to a previous example of the device, in one example, the in-band register writes include mode register writes (MRWs) based on commands on the command bus prior to execution of a chip select training (CSTM) mode.According to a previous example of the device, in one example, the in-band register writes include mode register writes (MRWs) based on instructions on the instruction bus prior to execution of an instruction / address training mode (CATM). According to a previous example of the device, in one example, the in-band register writes avoid using a general-purpose instruction (MPC) to train the DFE configuration register and the second configuration register. According to a previous example of the device, in one example, the configuration register update mode instruction includes a first general-purpose instruction (MPC) for entering the configuration register update mode and further includes a second MPC for exiting the configuration register update mode.

[0157] In one aspect, a first computer system includes: a memory controller coupled to a command bus; and a memory chip coupled to the command bus via a command bus interface, wherein the memory chip is to receive a configuration register update mode command from the memory controller to cause the memory chip to enter a configuration register update mode, the memory chip including: a DFE (Decision Feedback Equalization) configuration register for storing a first configuration setting for the command bus interface and a second configuration register for a configuration setting other than DFE, the second configuration register is to store a second configuration setting for the command bus interface;and wherein the memory chip is to update the second configuration register with in-band register writes in configuration register update mode;

[0158] In an example of the first computer system of claim 12, wherein the in-band register writes avoid using sideband bus communication to update the second configuration register. According to a previous example of the first computer system, in one example, the memory chip comprises a registration clock driver (RCD), and wherein the configuration register update mode comprises a register word update (RWUPD) mode for the RCD. According to a previous example of the first computer system, in one example, the in-band register writes comprise register word (RW) writes based on commands on the command bus, without using a system management bus (SMBus).According to a previous example of the first computer system, in one example, the in-band register writes include register word (RW) writes based on instructions on the instruction bus in combination with the use of a system management bus (SMBus). According to a previous example of the first computer system, in one example, the memory chip includes a dynamic random access memory (DRAM) device, and wherein the configuration register update mode includes a mode register update (MRUPD) mode for the DRAM device. According to a previous example of the first computer system, in one example, the in-band register writes include mode register writes (MRWs) based on instructions on the instruction bus prior to execution of a chip select training mode (CSTM) and prior to execution of an instruction / address training mode (CATM).According to a preceding example of the first computer system, in one example, the in-band register writes avoid using a general-purpose instruction (MPC) to train the DFE configuration register and the second configuration register. According to any preceding example of the first computer system, in one example, the first computer system includes one or more of: a host processor device coupled to the memory controller; a display communicatively coupled to a host processor coupled to the memory controller; a network interface communicatively coupled to a host processor coupled to the memory controller; or a battery to power the computer system.

[0159] In one aspect, a first method includes: in a device having a decision feedback equalization (DFE) configuration register for storing a first configuration setting for a hardware interface to a command bus and a second configuration register for a configuration setting other than DFE, the second configuration register to store a second configuration setting for the hardware interface to the command bus, receiving a configuration register update mode command to trigger entry into a configuration register update mode; and updating the second configuration register with in-band register writes in the configuration register update mode.

[0160] In one example of the first method, the in-band register writes avoid using sideband bus communication to update the second configuration register. According to one of the preceding examples of the first method, in one example, the configuration register update mode includes a training mode for the entire configuration register training. According to one of the preceding examples of the first method, in one example, the configuration register update mode includes a register word update (RWUPD) mode for a registration clock driver (RCD). According to a preceding example of the first method, in one example, the in-band register writes include register word (RW) writes based on commands on the command bus, without using a system management bus (SMBus).According to a previous example of the first method, in one example, the in-band register writes include register word (RW) writes based on commands on the command bus in combination with the use of a system management bus (SMBus). According to one of the previous examples of the first method, in one example, the configuration register update mode includes a mode register update (MRUPD) mode for a dynamic random access memory (DRAM) device. According to a previous example of the first method, in one example, the in-band register writes include mode register writes (MRWs) based on commands on the command bus prior to execution of a chip select training (CSTM) mode.According to a previous example of the first method, in one example, the in-band register writes include mode register writes (MRWs) based on instructions on the instruction bus prior to execution of an instruction / address training mode (CATM). According to a previous example of the first method, in one example, the in-band register writes avoid using a general-purpose instruction (MPC) to train the DFE configuration register and the second configuration register. According to a previous example of the first method, in one example, the configuration register update mode instruction includes a first general-purpose instruction (MPC) for entering the configuration register update mode and further includes a second MPC for exiting the configuration register update mode.

[0161] In one aspect, a registration clock driver (RCD) includes: a hardware interface for coupling to a command bus, wherein the hardware interface is to receive a command to trigger entry into a register word update (RWUPD) mode; and a register word for a configuration setting other than a decision feedback equalization (DFE) configuration, wherein the register word is to store a configuration setting for the hardware interface to the command bus; wherein the RCD is to update the register word with in-band register writes in the RWUPD mode.

[0162] In one example of the RCD, in-band register writes avoid using sideband bus communication to update the register word. According to one of the preceding examples of the RCD, in one example, the RWUPD mode includes a training mode for the entire configuration of register words. According to one previous example of the RCD, in one example, the in-band register writes include register word (RW) writes based on instructions on the instruction bus without using a system management bus (SMBus). According to one previous example of the RCD, in one example, the in-band register writes include register word (RW) writes based on instructions on the instruction bus in combination with the use of a system management bus (SMBus).

[0163] In one aspect, a second computer system includes: a memory controller coupled to a command bus; and a dual in-line memory module (DIMM) having a registration clock driver (RCD) coupled to the command bus with a command bus interface, wherein the RCD is to receive a command to trigger entry into a register word update (RWUPD) mode; wherein the RCD includes: a register word for a configuration setting other than a decision feedback equalization (DFE) configuration, the register word to store a configuration setting for a hardware interface to the command bus; wherein the RCD is to update the register word with in-band register writes in the RWUPD mode.

[0164] In one example of the second computer system, the in-band register writes avoid using sideband bus communication to update the register word. According to a previous example of the second computer system, in one example, the in-band register writes include register word (RW) writes based on instructions on the instruction bus without using a system management bus (SMBus). According to a previous example of the second computer system, in one example, the in-band register writes include register word (RW) writes based on instructions on the instruction bus in combination with the use of a system management bus (SMBus).According to a previous example of the second computer system, in one example, the in-band register writes include mode register writes (MRWs) based on instructions on the instruction bus before executing a chip select training mode (CSTM) and before executing an instruction / address training mode (CATM). According to a previous example of the second computer system, in one example, the in-band register writes avoid using a general-purpose instruction (MPC) to configure the register word.According to any preceding example of the second computer system, in one example, the second computer system includes one or more of: a host processor device coupled to the memory controller; a display communicatively coupled to a host processor coupled to the memory controller; a network interface communicatively coupled to a host processor coupled to the memory controller; or a battery to power the computer system.

[0165] In one aspect, a second method includes: in a registration clock driver (RCD) having a configuration register for storing a second configuration setting other than DFE (Decision Feedback Equalization) for a hardware interface to a command bus, receiving a command to trigger entry into a RWUPD (Register Word Update) mode; and updating the register word with in-band register writes in the RWUPD mode.

[0166] In one example of the second method, the in-band register writes avoid using sideband bus communication to update the register word. According to one of the preceding examples of the second method, in one example, the RWUPD mode includes a training mode for the entire register word configuration. According to a preceding example of the second method, in one example, the in-band register writes include register word (RW) writes based on instructions on the instruction bus without using a system management bus (SMBus). According to a preceding example of the second method, in one example, the in-band register writes include register word (RW) writes based on instructions on the instruction bus in combination with the use of a system management bus (SMBus).

[0167] In one aspect, a dynamic random access memory (DRAM) device includes: a hardware interface for coupling to a command bus, the hardware interface to receive a command to trigger entry into a mode register update (MRUPD) mode; and a mode register for a configuration setting other than a decision feedback equalization (DFE) configuration, the mode register to store a configuration setting for the hardware interface to the command bus; the DRAM device to update the mode register with in-band register writes in the MRUPD mode.

[0168] In one example of DRAM, in-band register writes avoid using sideband bus communication to update the mode register. According to one of the preceding examples of DRAM, in one example, the MRUPD mode includes a training mode for the entire mode register configuration. According to one of the preceding examples of DRAM, in one example, the in-band register writes include mode register writes (MRWs) based on commands on the command bus without using a sideband bus. According to one of the preceding examples of DRAM, in one example, the sideband bus includes a memory module management control (M3C) bus. According to one of the preceding examples of DRAM, in one example, the in-band register writes include mode register writes (MRWs) based on commands on the command bus in combination with the use of a sideband bus.According to one of the preceding examples of DRAM, in one example, the sideband bus comprises a memory module management control (M3C) bus. According to one preceding example of DRAM, in one example, the in-band register writes comprise mode register writes (MRWs) based on commands on the command bus prior to execution of a chip select training mode (CSTM). According to one preceding example of DRAM, in one example, the in-band register writes comprise mode register writes (MRWs) based on commands on the command bus prior to execution of a command / address training mode (CATM). According to one preceding example of DRAM, in one example, the in-band register writes avoid using a general purpose instruction (MPC) to configure the mode register.According to a previous example of the DRAM, in one example, the instruction includes a first general purpose instruction (MPC) for entering the MRUPD mode and further includes a second MPC for exiting the MRUPD mode.

[0169] In one aspect, a third computer system includes: a memory controller coupled to a command bus; and a dynamic random access memory (DRAM) device coupled to the command bus with a command bus interface, wherein the DRAM device is to receive a command from a memory controller to trigger entry into a mode register update (MRUPD) mode; wherein the DRAM device includes: a mode register for a configuration setting other than a decision feedback equalization (DFE) configuration, wherein the mode register is to store a configuration setting for a hardware interface to the command bus; wherein the DRAM device is to update the mode register with in-band register writes in the MRUPD mode.

[0170] In one example of the third computer system, the in-band register writes avoid using sideband bus communication to update the mode register. According to one of the preceding examples of the third computer system, in one example, the MRUPD mode includes a training mode for the entire mode register configuration. According to one of the preceding examples of the third computer system, in one example, the in-band register writes include register word writes (RW writes) based on instructions on the instruction bus, without using a sideband bus. According to one of the preceding examples of the third computer system, in one example, the sideband bus includes an M3C (Memory Module Management Control) bus.According to one of the preceding examples of the third computer system, in one example, the in-band register writes include mode register writes (MRWs) based on instructions on the instruction bus in combination with the use of a sideband bus. According to one of the preceding examples of the third computer system, in one example, the sideband bus includes an M3C (Memory Module Management Control) bus. According to one of the preceding examples of the third computer system, in one example, the in-band register writes include mode register writes (MRWs) based on instructions on the instruction bus prior to the execution of a chip select training mode (CSTM).According to a previous example of the third computer system, in one example, the in-band register writes include mode register writes (MRWs) based on instructions on the instruction bus prior to execution of an instruction / address training (CATM) mode. According to a previous example of the third computer system, in one example, the in-band register writes avoid using a general-purpose instruction (MPC) to configure the mode register. According to a previous example of the third computer system, in one example, the instruction includes a first general-purpose instruction (MPC) for entering MRUPD mode and further includes a second MPC for exiting MRUPD mode.According to any preceding example of the third computer system, in one example, the third computer system includes one or more of: a host processor device coupled to the memory controller; a display communicatively coupled to a host processor coupled to the memory controller; a network interface communicatively coupled to a host processor coupled to the memory controller; or a battery to power the computer system.

[0171] In one aspect, a third method includes: in a dynamic random access memory (DRAM) device having a mode register for storing a second configuration setting other than decision feedback equalization (DFE) for a hardware interface to a command bus, receiving a command to trigger entry into a mode register update (MRUPD) mode; and updating the mode register with in-band register writes in the MRUPD mode.

[0172] In one example of the third method, the in-band register writes avoid using sideband bus communication to update the mode register. According to one of the preceding examples of the third method, in one example, the MRUPD mode includes a training mode for the entire mode register configuration. According to one of the preceding examples of the third method, in one example, the in-band register writes include register word writes (RW writes) based on instructions on the instruction bus, without using a sideband bus. According to one of the preceding examples of the third method, in one example, the sideband bus includes an M3C (Memory Module Management Control) bus.According to one of the preceding examples of the third method, in one example, the in-band register writes include register word writes (RW writes) based on commands on the command bus in combination with the use of a sideband bus. According to one of the preceding examples of the third method, in one example, the sideband bus includes a memory module management control (M3C) bus. According to one of the preceding examples of the third method, in one example, the in-band register writes include mode register writes (MRWs) based on commands on the command bus prior to the execution of a chip select training mode (CSTM).According to a previous example of the third method, in one example, the in-band register writes include mode register writes (MRWs) based on instructions on the instruction bus prior to execution of an instruction / address training (CATM) mode. According to a previous example of the third method, in one example, the in-band register writes avoid using a general-purpose instruction (MPC) to train the mode register. According to a previous example of the third method, in one example, the instruction includes a first general-purpose instruction (MPC) for entering MRUPD mode and further includes a second MPC for exiting MRUPD mode.

[0173] Flowcharts, as illustrated here, provide examples of sequences of various process actions. The flowcharts may specify operations to be performed by a software or firmware routine, as well as physical operations. A flowchart may illustrate an example implementation of states of a finite state machine (FSM), which may be implemented in hardware and / or software. Although they are shown in a particular sequence or order, the order of the actions may be modified unless otherwise noted. Accordingly, the illustrated diagrams are only examples, and the process may be performed in a different order, and some actions may be performed in parallel. Additionally, one or more actions may be omitted; thus, not all actions are performed in all implementations.

[0174] To the extent that various operations or functions are described herein, they may be described or defined as software code, instructions, a configuration, and / or data. The content may be directly executable (“object” or “executable” form), source code, or difference code (“delta” or “patch” code). The software content described herein may be provided via an article of manufacture having the content stored thereon or via a method for operating a communications interface for sending data over the communications interface. A machine-readable storage medium may cause a machine to perform the described functions or operations and includes any mechanism that stores information in a form accessible by a machine (e.g., a computing device, an electronic system, etc.), such as writable / non-writable media (e.g.,Read-only memory (ROM), random-access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communications interface includes any mechanism that interfaces with any of a wired, wireless, optical, etc., medium to communicate with another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communications interface may be configured to provide configuration parameters and / or send signals to prepare the communications interface to provide a data signal describing the software content. The communications interface may be accessed via one or more commands or signals sent to the communications interface.

[0175] Various components described herein may be a means for performing the described operations or functions. Each component described herein includes software, hardware, or a combination thereof. The components may be implemented as software modules, hardware modules, special-purpose hardware (e.g., application-specific hardware, application-specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, hard-wired circuitry, etc.

[0176] Apart from what is described herein, various modifications may be made to what is disclosed herein and to implementations of the invention without departing from its scope. Therefore, the present illustrations and examples should be considered in an illustrative rather than a limiting sense. The scope of the invention should be measured solely by reference to the following claims.

Claims

[1] Device for updating a configuration register, comprising: a hardware interface for coupling to a command bus, the hardware interface to receive a configuration register update mode command to trigger entry into a configuration register update mode; a DFE (Decision Feedback Equalization) configuration register for storing a first configuration setting for the hardware interface to the command bus; and a second configuration register for a configuration setting other than DFE, the second configuration register to store a second configuration setting for the hardware interface to the command bus; wherein the device is to update the second configuration register with in-band register writes in configuration register update mode. [2] The device of claim 1, wherein the in-band register writes avoid the use of sideband bus communication to update the second configuration register. [3] The device according to any one of claims 1 to 2, wherein the configuration register update mode comprises a training mode for the entire configuration register training. [4] The device of any one of claims 1 to 3, wherein the configuration register update mode comprises a register word update (RWUPD) mode for a registration clock driver (RCD). [5] The device of claim 4, wherein the in-band register writes comprise register word (RW) writes based on instructions on the instruction bus without using a system management bus (SMBus). [6] The device of claim 4, wherein the in-band register writes comprise register word (RW) writes based on instructions on the instruction bus in combination with the use of a system management bus (SMBus). [7] The device of any one of claims 1 to 6, wherein the configuration register update mode comprises a mode register update (MRUPD) mode for a DRAM (Dynamic Random Access Memory) device. [8] The device of claim 7, wherein the in-band register writes comprise mode register writes (MRWs) based on commands on the command bus prior to execution of a chip select training mode (CSTM). [9] The device of claim 7, wherein the in-band register writes comprise mode register writes (MRWs) based on instructions on the instruction bus prior to execution of an instruction / address training mode (CATM). [10] The device of claim 7, wherein the in-band register writes avoid the use of a general purpose instruction (MPC) to train the DFE configuration register and the second configuration register. [11] The device of claim 7, wherein the configuration register update mode instruction comprises a first general purpose instruction (MPC) for entering the configuration register update mode and further comprises a second MPC for exiting the configuration register update mode. [12] Computer system comprising: a memory controller coupled to a command bus; and a memory chip coupled to the command bus with a command bus interface, the memory chip to receive a configuration register update mode command from the memory controller to cause the memory chip to enter a configuration register update mode, the memory chip including: a DFE (Decision Feedback Equalization) configuration register for storing a first configuration setting for the command bus interface; and a second configuration register for a configuration setting other than DFE, wherein the second configuration register is to store a second configuration setting for the command bus interface; and wherein the memory chip is to update the second configuration register with in-band register writes in configuration register update mode. [13] The computer system of claim 12, wherein the in-band register writes avoid the use of sideband bus communication to update the second configuration register. [14] The computer system of any of claims 12 to 13, wherein the memory chip comprises a registration clock driver (RCD), and wherein the configuration register update mode comprises a register word update (RWUPD) mode for the RCD. [15] The computer system of claim 14, wherein the in-band register writes comprise register word (RW) writes based on instructions on the instruction bus without using a system management bus (SMBus). [16] The computer system of claim 14, wherein the in-band register writes comprise register word (RW) writes based on instructions on the instruction bus in combination with the use of a system management bus (SMBus). [17] The computer system of any of claims 12 to 16, wherein the memory chip comprises a DRAM (Dynamic Random Access Memory) device, and wherein the configuration register update mode comprises a mode register update (MRUPD) mode for the DRAM device. [18] The computer system of claim 17, wherein the in-band register writes comprise mode register writes (MRWs) based on instructions on the instruction bus prior to execution of a chip select training mode (CSTM) and prior to execution of an instruction / address training mode (CATM). [19] The computer system of claim 17, wherein the in-band register writes avoid the use of a general purpose instruction (MPC) to train the DFE configuration register and the second configuration register. [20] A computer system according to any one of claims 12 to 19, further comprising one or more of the following: a host processor device coupled to the memory controller; a display communicatively coupled to a host processor coupled to the memory controller; a network interface communicatively coupled to a host processor coupled to the memory controller; or a battery to power the computer system.

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