GATE-ALL-AROUND-INTEGRATED-SCREEN-STRUCTURES WITH DEPOPULATED CHANNEL STRUCTURES USING SEPARATE SOURCE OR DRAIN APPROACHES

Abstract

Gate-all-around integrated circuit structures with depopulated channel structures and methods for fabricating depopulated channel structures using separate source or drain approaches are described. For example, an integrated circuit structure has a first vertical array of nanowires, wherein the first vertical array of nanowires has one or more dielectric nanowires coupled to a dielectric source or drain structure. A first gate stack is placed above the first vertical array of nanowires.A second vertical array of nanowires is arranged laterally spaced from the first vertical array of nanowires. This second vertical array of nanowires comprises one or more semiconductor nanowires coupled to an epitaxial source or drain structure. The one or more semiconductor nanowires correspond horizontally to the one or more dielectric nanowires, and the epitaxial source or drain structure is laterally spaced from the dielectric source or drain structure. A second gate stack is positioned above the second vertical array of nanowires.

Description

BACKGROUND

[0001] In recent decades, the scaling of functions in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to ever smaller features enables higher densities of functional units within the limited footprint of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, leading to the production of products with increased capacity. However, the evolution to ever larger capacities also presents problems. The need to optimize the performance of each device is becoming increasingly important.

[0002] In the fabrication of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more common with the continued downscaling of device dimensions. In conventional processes, tri-gate transistors are generally fabricated either on bulk silicon substrates or on silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred due to their lower cost and because they enable less complicated tri-gate fabrication processes. In another aspect, maintaining mobility enhancement and short-channel control as microelectronic device dimensions scale below the 10-nanometer (nm) node presents a device fabrication challenge. Nanowires used to fabricate devices provide improved short-channel control.

[0003] However, the scaling of multi-gate and nanowire transistors has not been without consequences. As the dimensions of these fundamental building blocks of a microelectronic circuit assembly are reduced, and as the sheer number of fundamental building blocks fabricated in a given area increases, the constraints on the lithography processes used to pattern these building blocks have become overwhelming. In particular, there can be a trade-off between the smallest dimension of a feature patterned in a semiconductor stack (the critical dimension) and the spacing of such features. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A-1H illustrate cross-sectional views representing various operations in a method of fabricating a gate-all-around integrated circuit structure with a depopulated channel structure using a separate source or drain approach according to an embodiment of the present disclosure. Fig. 2A-2D illustrate cross-sectional views representing various gate-all-around integrated circuit structures with a depopulated channel structure using a separate source or drain approach according to an embodiment of the present disclosure. Fig. 3A-3C and 4 illustrate cross-sectional views representing various operations in a method of fabricating another gate-all-around integrated circuit structure having a depopulated channel structure according to an embodiment of the present disclosure. Fig. 5 illustrates a cross-sectional view of a non-planar integrated circuit structure along a gate line according to an embodiment of the present disclosure. Fig. 6 illustrates cross-sectional views through nanowires and fins for a non-endcap architecture (left side (a)) versus a self-aligned gate endcap (SAGE) architecture (right side (b)) according to an embodiment of the present disclosure. Fig. 7 illustrates cross-sectional views representing various operations in a method of fabricating a self-aligned gate end cap (SAGE) structure with gate all-around devices according to an embodiment of the present disclosure. Fig. 8A illustrates a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure. Fig. Figure 8B illustrates a cross-sectional source or drain view of the nanowire-based integrated circuit structure of Fig. 8A along the a-a' axis according to an embodiment of the present disclosure. Fig. Figure 8C illustrates a cross-sectional channel view of the nanowire-based integrated circuit structure from Fig. 8A along the b-b' axis according to an embodiment of the present disclosure. Fig. 9A-9E illustrate three-dimensional cross-sectional views representing various operations in a method for fabricating a nanowire portion of a fin / nanowire structure, according to an embodiment of the present disclosure. Fig. 10 illustrates a computing device according to an implementation of an embodiment of the disclosure. Fig. 11 illustrates an interposer incorporating one or more embodiments of the disclosure. DESCRIPTION OF THE EMBODIMENTS

[0004] Gate-all-around integrated circuit structures with depopulated channel structures and methods of fabricating gate-all-around integrated circuit structures with depopulated channel structures are described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be understood by one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order not to unnecessarily obscure embodiments of the present disclosure.Furthermore, it is to be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0005] Certain terminology may be used in the following description for reference purposes only and is not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the drawings to which reference is made. Terms such as "front," "rear," "back," and "side" describe the orientation and / or location of parts of the component within a consistent but arbitrary frame of reference, which is made clear by reference to the text and associated drawings describing the component being discussed. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

[0006] Embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of an integrated circuit (IC) fabrication, where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the final FEOL process, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0007] Embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of an IC fabrication, where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, such as the metallization layer or layers. BEOL includes contacts, insulation layers (dielectrics), metal levels, and bond pads for chip-to-package connections. In the BEOL part of the fabrication phase, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added in BEOL.

[0008] Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. Although an example processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be particularly applicable to BEOL processing. Likewise, although an example processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be particularly applicable to FEOL processing.

[0009] One or more embodiments described herein are directed to separate source or drain fabrication between adjacent gates for depopulation of nanowire transistor channels. It should be understood that, unless otherwise noted, reference to nanowires herein may indicate nanowires, nanoribbons, or nanosheets.

[0010] To provide some context, it would be advantageous to enable a bottom NMOS nanowire or nanoribbon depopulation etch while maintaining N-type epitaxial source or drain structures in adjacent gates. However, anisotropic silicon etch may not be selective for the N-type epitaxial source or drain structures. Due to the lack of etch selectivity between Si and phosphorus-doped Si, NMOS nanowires cannot be depopulated using isotropic etching without removing the source or drain structures (S / D structures). Once the S / D structures are etched out, the adjacent gates no longer function.

[0011] According to one or more embodiments of the present disclosure, depopulation is achieved by separating a bottom source or drain structure. Advantages to implementing embodiments described herein may include enabling bottom NMOS nanowire depopulation by maintaining the S / D of the adjacent gates and reducing capacitance. Detectable implementation of the embodiments described herein may include SEM or TEM cross-sectional imaging to show a bottom source or drain structure separated between adjacent gates. A source or drain structure connected to depopulated structures is etched out and effectively replaced with an oxide or dielectric source or drain structure, while the source or drain structure connected to an adjacent non-depopulated structure is intact.

[0012] To provide more general context, the integration of nanowire and / or nanoribbon complementary metal oxide semiconductor (CMOS) transistors faces the challenge of creating devices with varying thicknesses. In current FinFET technology, device thickness granularity is achieved by varying the number of fins in the device channel. Unfortunately, this option is not readily available for nanowire and nanoribbon architectures because the channels are stacked vertically. This requirement is even more challenging for nanowire and / or nanoribbon (NW / NR) structures in a self-aligned, stacked CMOS structure, where NMOS and PMOS channels are patterned with the same width.Previous attempts to address the above problems included (1) integrating NW / NR devices with different channel widths (an option available only for nanoribbon, which requires complex patterning) or (2) subtractively removing wires / ribbons from source / drain or channel regions (an option challenging for stacked CMOS architectures).

[0013] To provide further context, transistors with different drive currents may be required for different circuit types. Embodiments disclosed herein aim to achieve different drive currents by depopulating (depopping) the number of nanowire transistor channels in device structures. One or more embodiments provide an approach for deleting discrete numbers of wires from a transistor structure. Approaches may be suitable for both ribbons and wires (RAW). Furthermore, transistor leakage current flowing through a subfin must be controlled for proper circuit function. Embodiments disclosed herein provide a method for subfin isolation of nanowire transistors. For depopping, technologies using FinFETs can depopulate the number of fins in each device to achieve different drive current levels.For subfin isolation, subfin implants are used to dope a subfin to reduce leakage. However, because nanowires are stacked and self-aligned, they cannot be depopped in the same way as fins. Additionally, subfin dopants must be targeted and can diffuse back into the channel, degrading carrier transport.

[0014] The process flows described herein can be implemented to achieve depopulation of the nanowire transistor channel. Embodiments may include channel depopulation of nanowire transistors to provide modulation of drive currents in various devices, which may be required for different circuits. As an example process flow, Fig. 1A-1H are cross-sectional views representing various operations in a method of fabricating a gate-all-around integrated circuit structure with a depopulated channel structure using a separate source or drain approach according to an embodiment of the present disclosure.

[0015] In order to provide an output structure 100, with respect to Fig. 1A, processing of a stack of alternating Si 102 and 104 / SiGe 106 (with a possible channel cap 105 thereon) is first performed and includes patterning the stack into fins. Generic dummy gates 107 (which may or may not be poly dummy gates) are patterned and etched. Gate spacers 108 are formed (including outer and inner portions), and a bottom source or drain structure 110 is formed between adjacent structures, such as a bottom epitaxial N-type source or drain structure including silicon and phosphorus.

[0016] In relation to Fig. 1B, the lower source or drain structure 110 of the initial structure 100 is masked and etched to form separate source or drain structures 110A. The separate source or drain structures 110A of adjacent structures are completely separated by a gap 112.

[0017] In relation to Fig. 1C is placed over the structure of Fig. 1B, a dielectric material is formed and recessed to form a dielectric plug 114, such as a silicon oxide plug, that fills the gap 112.

[0018] In relation to Fig. 1D, a top epitaxial source or drain structure 116 is formed between the top nanowires of adjacent structures. In one embodiment, the top epitaxial source or drain structure 116 is a P-type epitaxial source or drain structure including silicon, germanium, and boron.

[0019] In relation to Fig. 1E, an insulating material 118, e.g., a silicon oxide insulating material, is formed on the upper epitaxial source or drain structure 116.

[0020] In relation to Fig. 1F, the sacrificial gate structures 107 are removed to form gate trenches 120 and expose channel portions of the nanowires. The nanowires 102 and 104, such as the upper silicon nanowires 104 and the lower silicon nanowires 102, are then exposed in opened gate trenches (and optionally, a dielectric cap 105, such as a silicon nitride cap, is also exposed), e.g., by removing the sacrificial SiGe layer 106.

[0021] In relation to Fig. 1G will be the structure of Fig. 1F, with the top nanowires 104 and the bottom left nanowires 102 masked, subjected to an isotropic etch that removes the bottom right nanowires 102 and the bottom right split source or drain structure 110A. The bottom left split source or drain structure 110A remains intact. In one embodiment, the formation of split source or drain structures 110A and the formation of a dielectric plug 114 therebetween allows for the localization of a depopulation process to the bottom right nanowires 102 without inadvertently removing the bottom left nanowires 102. A cavity structure 122 is formed at the locations of the bottom right nanowires 102 and the bottom right split source or drain structure 110A.

[0022] In relation to Fig. 1H is in the cavity structure 122 of the Fig. 1G, a dielectric structure 124, such as a silicon oxide structure, a silicon nitride structure, or a silicon oxynitride structure, is formed, e.g., by a deposit and reset approach. The dielectric structure 124 effectively comprises dielectric nanowires 124A coupled to a source or drain dielectric structure 124B. After the formation of the dielectric structure 124, a permanent gate structure, such as a gate structure including a high-k dielectric layer and a metal gate electrode, may be formed in the remaining portions of the gate trenches 120.

[0023] It should be noted that the information associated with the Fig. 1A-1H can be modified to depopulate regions of neighboring structures other than the bottom nanowires coupled to a lower N-type source or drain structure, as described above. As example implementations, Fig. 2A-2D are cross-sectional views representing various gate-all-around integrated circuit structures with a depopulated channel structure using a separate source or drain approach according to an embodiment of the present disclosure.

[0024] In relation to Fig. 2A, structure 200A is an example of an intermediate structure in a top nanowire depopulation process that uses separate epitaxial source or drain structure formation. Structure 200A includes a bottom intact N-type epitaxial source or drain structure 202A, a top cavity 206A formed by depopulation, a dielectric channel cap 205A overlying cavity 206A, and a top left separate P-type source or drain structure 204A. Note that the structure of Fig. 2A can vary depending on whether an isotropic or anisotropic etch is used. For example, only the wires can be removed, or the wires and at least a portion of the material under the spacers can be removed, or the wires and the portions under the spacers and the separated epitaxial structure can all be removed. The upper portion of Fig. Figure 2A shows the wires and the sections under the spacers and the separated epitaxial structure, all removed.

[0025] In relation to Fig. 2B, structure 200B is an example of an intermediate structure in a top nanowire depopulation process that uses separate epitaxial source or drain structure formation. Structure 200B has a bottom intact epitaxial P-type source or drain structure 204B, an upper cavity 206B formed by depopulation, and an upper left separated N-type source or drain structure 202B. Note that the structure of Fig. 2B can vary depending on whether an isotropic or anisotropic etch is used. For example, only the wires can be removed, or the wires and at least a portion of the material under the spacers can be removed, or the wires and the portions under the spacers and the separated epitaxial structure can all be removed. The upper portion of Fig. 2B is presented in general terms to cover all possibilities.

[0026] In relation to Fig. 2C, structure 200C is an example of an intermediate structure in a bottom nanowire depopulation process that uses separate epitaxial source or drain structure formation. Structure 200C has an upper intact epitaxial P-type source or drain structure 204C, a lower dielectric depopulation structure 208C, and a lower left separated N-type source or drain structure 202C. Note that the structure of Fig. 2C can vary depending on whether an isotropic or anisotropic etch is used. For example, only the wires can be removed, or the wires and at least a portion of the material under the spacers can be removed, or the wires and the portions under the spacers and the separated epitaxial structure can all be removed. The lower portion of Fig. Figure 2C shows the wires and the sections under the spacers and the separated epitaxial structure, all removed.

[0027] In relation to Fig. Figure 2D shows structure 200D as an example of an intermediate structure in a bottom nanowire depopulation process using separate epitaxial source or drain structure formation. Structure 200D includes an upper intact epitaxial N-type source or drain structure 202D, a lower dielectric depopulation structure 208D, and a lower left separated P-type source or drain structure 204C. Note that the structure of Fig. 2D can vary depending on whether an isotropic or anisotropic etch is used. For example, only the wires can be removed, or the wires and at least a portion of the material under the spacers can be removed, or the wires and the portions under the spacers and the separated epitaxial structure can all be removed. The lower portion of Fig. 2D is presented in a general way to capture all possibilities.

[0028] It should be noted that embodiments described herein may be implemented to fabricate nanowire and / or nanoribbon structures having a different number of active (semiconductor) wire / ribbon channels. It should be noted that embodiments described herein may include separate epitaxial source or drain approaches to achieve such structures. Embodiments described herein may be implemented to enable the fabrication of nanowire / nanoribbon-based CMOS architectures.

[0029] In one embodiment, to develop various devices with different drive currents, a self-aligned depopulation flow (depop flow) can be patterned using lithography to depopulate ribbons and wires (RAW) only from specific devices. In another embodiment, the entire wafer can be depopulated uniformly so that all devices have the same number of RAW.

[0030] In another aspect, front-to-back vias may be formed through depopulated gate regions. Embodiments described herein may provide a space-efficient way to transfer signals from front-to-back interconnects (or vice versa) that does not necessarily require extreme etching or additional patterning operations.

[0031] To provide some context, fabricating state-of-the-art vias that transfer either signals or power from one side of a wafer to the other requires additional lithographic patterning and aggressive etching, which can damage surrounding materials. Such earlier approaches have designs that allow the via to be shorted into adjacent source or drain regions. However, such a short may not be permissible with the current design of self-aligned transistors.

[0032] According to one or more embodiments of the present disclosure, a fin, nanowire, or nanoribbon structure, or the like, is constructed to include a conductive via structure in a self-aligned transistor technology. In one particular embodiment, a front-to-back via occupies the space of a gate region in which all corresponding channels have been depopulated. In one embodiment, the via is composed of the same gate metal(s) as the surrounding active gate regions. The via connects the front and back interconnects in the same manner as the surrounding active gate regions.

[0033] Advantages of implementing embodiments described herein include enabling the ability to fabricate a front-to-back via that does not necessarily require additional lithographic patterning operations, e.g., because depopulation processing is already required elsewhere in a self-aligned transistor processing flow. Embodiments may also be implemented to enable a front-to-back via that does not necessarily require extremely aggressive etches that would otherwise damage surrounding materials (e.g., gate spacers, isolation caps / walls, plugs, etc.).

[0034] As an overview, in one embodiment, a self-aligned transistor is fabricated by removing a polysilicon gate (or other dummy gate). The transistor channels are exposed in the gate regions. Upon exposure of the transistor channels, portions of the channels may be depopulated, as defined by lithographic patterning. In one example, depopulation may be achieved through a separate source or drain structure, as described above.

[0035] As an example double depopulation processing scheme, Fig. 3A-3C and 4 are cross-sectional views illustrating various operations in a method for fabricating another gate-all-around integrated circuit structure with a depopulated channel structure, according to an embodiment of the present disclosure. It should be noted that although two groups of three nanowires are demonstrated in each transistor region, any number of groupings, number of channels in each grouping, or channel geometry (e.g., nanoribbon, nanowire, fin) may be used. It should also be appreciated that the source or drain structures are in and out of the side of the perspective shown.

[0036] With reference to Fig. 3A illustrates a method for fabricating an integrated circuit structure by forming a vertical array 300 of semiconductor nanowires or nanoribbons over a substrate 302. Multiple adjacent device sites, such as device sites 330A, 330B, and 330C, may be fabricated adjacent to one another. In one embodiment, gate endcap structures separate device sites 330A, 330B, and 330C. In such an embodiment, each of the gate endcap structures sits within a trench isolation layer 320A and includes a dielectric liner layer 320B and a dielectric fill layer 320C. A dielectric cap 320D may be formed on each of the endcap structures, examples of which are described in more detail below.

[0037] In one embodiment, each of the device sites 330A, 330B, and 330C includes a lower set of nanowires 304A, 304B, and 304C and an upper set of nanowires 314A, 314B, and 314C provided as a vertical stack. A dielectric nanowire cap layer 314D is included over each of the sets of nanowires, the formation of which is described below by way of example. As explained in more detail in other embodiments described below, channel regions of the lower set of nanowires 304A, 304B, and 304C and the upper set of nanowires 314A, 314B, and 314C may be exposed during a replacement gate process in which an open trench 308A is formed to expose the channel regions. The trench 308A may be separated from other replacement gate trenches (e.g., 308B and 308C) by sidewall spacers 310A, dielectric trench fill layers 310B, and hard mask caps or helmets 310C

[0038] In relation to Fig. 3B, the lower set of nanowires 304A, 304B, and 304C of device sites 330A and 330B is depopulated in a first separate source or drain depopulation process. The lower set of nanowires 304A, 304B, and 304C of device site 330C is not depopulated. In one embodiment, the lower set of nanowires 304A, 304B, and 304C of device sites 330A and 330B is depopulated using a separate source or drain process to limit the depopulation process to lower sets of nanowires 304A, 304B, and 304C of device sites 330A and 330B. A dielectric deposition is then performed to form dielectric nanowires 350A, 350B and 350C as described in connection with Fig. 1H. A lower set of semiconductor nanowires 304A, 304B, and 304C is retained at device location 330C.

[0039] In relation to Fig. 3C, nanowires 314A, 314B, and 314C of the upper set of nanowires of device sites 330A and 330C are depopulated in a second, separate source or drain depopulation process. Nanowires 314A, 314B, and 314C of the upper set of nanowires of device sites 330B are not depopulated. In one embodiment, nanowires 314A, 314B, and 314C of the upper set of nanowires of device sites 330A and 330C are depopulated using a separate source or drain process to restrict depopulation to nanowires 314A, 314B, and 314C of the upper set of nanowires of device sites 330A and 330C.

[0040] In one embodiment, the lower sets of nanowires previously subjected to the first separate source or drain depopulation process are blocked by a lower masking layer to restrict a second separate source or drain depopulation process to the upper sets of nanowires. A second separate source or drain depopulation process is then performed to form dielectric nanowires 360A, 360B, and 360C. It should be noted that, compared to semiconductor nanowires, the specific example of depopulated nanowires may retain any suitable number of nanowires or be oxidized to form dielectric nanowires using a first separate source or drain depopulation approach for lower sets of nanowires and then using a second separate source or drain depopulation approach for upper sets of nanowires.

[0041] In relation to Fig. 4, a permanent gate structure may be formed in trench 308A. In one exemplary embodiment, the permanent gate structure includes a bottom gate dielectric 370 and a bottom P-type gate electrode 372 thereon, and an top gate dielectric 370 and an top N-type gate electrode 374 thereon. In another exemplary embodiment, the permanent gate structure includes a bottom gate dielectric and a bottom N-type gate electrode thereon, and an top gate dielectric and a top P-type gate electrode thereon. In one embodiment, the permanent gate structure is formed around all nanowire / nanoribbon (NW / NR) channels, including the oxide NW / NR channels.

[0042] With further reference to Fig. 4, an integrated circuit structure according to an embodiment of the present disclosure includes a first vertical array of nanowires (e.g., nanowires 350A, 350B, and 350C of device site 308B). The first vertical array of nanowires has one or more dielectric nanowires (e.g., nanowires 350A, 350B, and 350C). A first gate stack (e.g., 370 / 372) is located above the first vertical array of nanowires and around one or more dielectric nanowires of the first vertical array of nanowires. A second vertical array of nanowires is located above the first vertical array of nanowires (e.g., nanowires 314A, 314B, and 314C of device site 308B). The second vertical arrangement of nanowires comprises one or more semiconductor nanowires.A second gate stack is located above the vertical array of nanowires and around one or more semiconductor nanowires of the second vertical array of nanowires.

[0043] In one embodiment, the one or more dielectric nanowires are coupled to a dielectric source or drain region, e.g., as a residual or artifact layer remaining from a separate source or drain channel depopulation process, as described in connection with the Fig. 1A-1H and 2A-2D.

[0044] In one embodiment, the integrated circuit structure includes epitaxial source or drain structures at the ends of the first and second vertical arrays of nanowires. In such an embodiment, the epitaxial source or drain structures are either non-discrete epitaxial source or drain structures, structural examples of which are described below, or a separate structure in the case of depopulation. In one embodiment, the first and second gate stacks include dielectric sidewall spacers, and the epitaxial source or drain structures are embedded epitaxial source or drain structures that extend beneath the dielectric sidewall spacers of the gate stack, structural examples of which are described below.

[0045] In one embodiment, the integrated circuit structure further comprises a pair of conductive contact structures coupled to the epitaxial source or drain structures. In such an embodiment, the pair of conductive contact structures is an asymmetric pair of conductive contact structures, structural examples of which are described below.

[0046] In one embodiment, the first vertical array of nanowires is located above a fin, structural examples of which are described below. In one embodiment, the first gate stack includes a first high-k gate dielectric layer and a first metal gate electrode, and the second gate stack includes a second high-k gate dielectric layer and a second metal gate electrode.

[0047] It should be noted that embodiments described herein may be implemented to fabricate nanowire and / or nanoribbon structures having a different number of semiconductor wire / ribbon channels. It should be noted that embodiments described herein may incorporate separate source or drain depopulation approaches to achieve such structures. Embodiments described herein may be implemented to enable the fabrication of nanowire / nanoribbon-based CMOS architectures.

[0048] With further reference to Fig. 4, an integrated circuit structure according to an embodiment of the present disclosure includes a first vertical array of nanowires (e.g., nanowires at device site 308B) and a second vertical array of nanowires (e.g., nanowires at device site 308C). The first vertical array of nanowires has a topmost semiconductor nanowire (e.g., semiconductor nanowire 314C of device site 308B) and a bottommost dielectric nanowire (e.g., dielectric nanowire 304A of device site 308B). The second vertical array of nanowires has a topmost oxide nanowire (e.g., dielectric nanowire 360C of device site 308C) and a bottommost semiconductor nanowire (e.g., semiconductor nanowire 304C of device site 308C), and the first and second vertical arrays of nanowires have coplanar topmost nanowires and coplanar bottommost nanowires.A first gate structure 370 / 372 lies above the first vertical array of nanowires. A second gate structure 370 / 372 lies above the second vertical array of nanowires.

[0049] In one embodiment, the nanowires of the first vertical array of nanowires have a horizontal width that corresponds to the horizontal width of the nanowires of the second vertical array of nanowires. In one embodiment, the nanowires of the first vertical array of nanowires have a horizontal width that is greater than a horizontal width of the nanowires of the second vertical array of nanowires. In one embodiment, the nanowires of the first vertical array of nanowires have a horizontal width that is less than a horizontal width of the nanowires of the second vertical array of nanowires.

[0050] With further reference to Fig. 4, according to one or more embodiments of the present disclosure, all of the nanowire channels of the integrated circuit structure formed in device site 330A have been depopulated, e.g., to provide a "fully" depopulated structure in device site 330A. In one embodiment, the full depopulation is achieved using two successively separate source or drain depopulation approaches. In one embodiment, the gate structure (e.g., 372 / 374) highlighted in illustrated box 382 acts as a conductive via. In one embodiment, the conductive via is a front-to-back via.

[0051] Furthermore, in one embodiment, the substrate 302 of the Fig. 3A-3C is replaced by a backside interconnect layer. The backside interconnect layer may include conductive lines 394 and conductive vias 396 in a dielectric layer 392 formed on an etch stop layer 398. In one embodiment, the substrate portion of Fig. 3C in a back-grinding process, examples of which are described in more detail below, and then the interconnect layer is formed thereon. In addition, the structure in Fig. 4 front-side gate contacts or vias 380A, 380B and 380C, which may have an insulating cap layer 390 formed thereon.

[0052] In relation to Fig. 4, an integrated circuit structure 330A, in one embodiment, includes a vertical array of nanowires 350A, 350B, 350C, 360A, 360B, and 360C. All nanowires 350A, 350B, 350C, 360A, 360B, and 360C of the vertical array of nanowires are dielectric nanowires. A gate stack 370 / 372 / 374 overlies the vertical array of nanowires to connect each of the dielectric nanowires 350A, 350B, 350C, 360A, 360B, and 360C. The gate stack 370 / 372 / 374 includes a conductive gate electrode 372 / 374.

[0053] In one embodiment, the integrated circuit structure 330A further includes a gate contact 380A above the vertical array of nanowires 350A, 350B, 350C, 360A, 360B, and 360C. The gate contact 380A is in contact with a top surface of the conductive gate electrode 372 / 374. An interconnect structure 394 / 396 is located below the vertical array of nanowires 350A, 350B, 350C, 360A, 360B, and 360C. A conductive via 396 of the interconnect structure 394 / 396 is in contact with a bottom surface of the conductive gate electrode 372 / 374. The conductive gate electrode 372 / 374 acts as a conductive via between the gate contact 380A and the interconnect structure 394 / 396.

[0054] According to one embodiment of the present disclosure, the formation of gate regions that become front-to-back vias does not necessarily require special lithographic patterning to define the via. For example, in one embodiment, complete depopulation at selected locations is achieved by combining other depopulation processes. As described herein, such front-to-back via fabrication may also not require aggressive etching to remove the depopulated channels, thus avoiding the eroding of surrounding materials (e.g., gate spacers, isolation walls, etc.).However, in some embodiments, the depopulated channels are selectively removed in the front-to-back via regions prior to gate metallization using a less aggressive etch than might otherwise be associated with the opening of similar vias.

[0055] As mentioned above, nanowire release processing may be performed through a replacement gate trench. Furthermore, in another aspect, backend (BE) interconnect scaling may result in lower performance and higher manufacturing costs due to patterning complexity. Embodiments described herein may be implemented to enable integration of the front- and back-side interconnects for nanowire transistors, e.g., through an exposure process. Embodiments described herein may provide an approach to achieving a relatively wider interconnect pitch. The result may be improved product performance and lower patterning costs. Embodiments may be implemented to enable robust functionality of scaled low-power, high-performance nanowire or nanoribbon transistors.

[0056] The exposure techniques described here can enable a paradigm shift from bottom-up device fabrication to center-out fabrication, where the center is any layer inserted during front-side fabrication, exposed from the backside, and reinserted during backside fabrication. Processing both a front side and an exposed backside of a device structure can address many of the challenges associated with manufacturing 3D ICs when primarily relying on front-side processing.

[0057] For example, one approach for exposing the backside of a transistor may be used to remove at least a portion of a support layer and an intermediate layer of a donor-host substrate assembly. The process flow begins with an input of a donor-host substrate assembly. A thickness of a support layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing, and / or wet / dry etching process known to be suitable for the composition of the support layer may be used. For example, if the support layer is a Group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning the semiconductor may be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning the Group IV semiconductor may also be used.

[0058] In some embodiments, the above is preceded by cleaving the support layer along a fracture plane substantially parallel to the intermediate layer. The cleaving or fracture process can be used to remove a substantial portion of the support layer as a bulk mass, thereby reducing the polishing or etching time required to remove the support layer. For example, if a support layer has a thickness of 400-900 µm, 100-700 µm can be cleaved away by applying any blanket implantation known to promote wafer-level fracture. In some embodiments, a light element (e.g., H, He, or Li) is implanted to a uniform target depth within the support layer where the fracture plane is desired.Following such a cleavage process, the thickness of the support layer remaining in the donor-host substrate assembly can then be polished or etched to complete the removal. Alternatively, if the support layer is not fractured, grinding, polishing, and / or etching can be used to remove a greater thickness of the support layer.

[0059] Next, exposure of an intermediate layer is detected. Detection is used to identify a point at which the backside surface of the donor substrate has nearly approached the device layer. It is known that any endpoint detection technique suitable for detecting a transition between the materials used for the support layer and the intermediate layer can be implemented. In some embodiments, one or more endpoint criteria are based on detecting a change in the optical absorbance or emission of the backside surface of the donor substrate while polishing or etching is performed. In some other embodiments, the endpoint criteria are associated with a change in the optical absorbance or emission of byproducts during polishing or etching of the donor substrate backside surface.For example, the absorbance or emission wavelengths associated with the byproducts of support layer etching may change as a function of the varying compositions of the support layer and the intervening layer. In other embodiments, the endpoint criteria are associated with a change in the mass of species in byproducts of polishing or etching the backside surface of the donor substrate. For example, the processing byproducts may be sampled by a quadrupole mass analyzer, and a change in species mass may be correlated with the varying compositions of the support layer and the intervening layer. In another exemplary embodiment, the endpoint criteria are associated with a change in friction between a backside surface of the donor substrate and a polishing surface in contact with the backside surface of the donor substrate.

[0060] Detection of the interlayer can be improved if the removal process is selective to the carrier layer relative to the interlayer, since non-uniformity of the carrier removal process can be mitigated by an etch rate delta between the carrier layer and the interlayer. Detection can even be skipped if the grinding, polishing, and / or etching process removes the interlayer at a rate sufficiently slower than the rate at which the carrier layer is removed. If no endpoint criterion is employed, a grinding, polishing, and / or etching process of a predetermined fixed duration can stop on the interlayer material if the interlayer thickness is sufficient for etch selectivity. In some examples, the carrier etch rate:intermediate layer etch rate ratio is 3:1-10:1 or more.

[0061] In exposing the intervening layer, at least a portion of the intervening layer may be removed. For example, one or more component layers of the intervening layer may be removed. A thickness of the intervening layer may be uniformly removed, for example, by polishing. Alternatively, a thickness of the intervening layer may be removed using a masked or blanket etching process. The process may employ the same polishing or etching process as that used to thin the carrier, or may be a distinct process with distinct process parameters. For example, if the intervening layer provides an etch stop for the carrier removal process, the latter process may employ a different polishing or etching process that promotes removal of the intervening layer over removal of the device layer.When less than a few hundred nanometers of interlayer thickness are to be removed, the removal process can be relatively slow, optimized for uniformity across the wafer, and more precisely controlled than that used to remove the support layer. For example, a CMP process employed may employ a slurry that provides very high selectivity (e.g., 100:1–300:1 or more) between semiconductor (e.g., silicon) and a dielectric material (e.g., SiO) surrounding the device layer and embedded within the interlayer, for example, as electrical insulation between adjacent device regions.

[0062] For embodiments where the device layer is exposed by completely removing the intervening layer, backside processing may begin on an exposed backside of the device layer or specific device regions therein. In some embodiments, the backside device layer processing includes further polishing or wet / dry etching through a thickness of the device layer located between the intervening layer and a device region previously fabricated in the device layer, such as a source or drain region.

[0063] In some embodiments where the support layer, the intermediate layer, or the device layer backside is recessed with a wet and / or plasma etch, such etch may be a patterned etch or a materially selective etch that introduces significant non-planarity or topography into the device layer backside surface. As described further below, the patterning may be within a device cell (i.e., "intracell patterning") or may be across device cells (i.e., "intercell patterning"). In some embodiments with patterned etching, at least a partial thickness of the intermediate layer is employed as a hard mask for backside device layer patterning. Therefore, a masked etch process may precede a correspondingly masked device layer etch.

[0064] The processing scheme described above may result in a donor-host substrate assembly including IC devices having a backside of an intermediate layer, a backside of the device layer, and / or a backside of one or more semiconductor regions within the device layer and / or frontside metallization exposed. Additional backside processing of any of these exposed regions may then be performed during downstream processing.

[0065] It is understood that the structures resulting from the preceding processing schemes may be used in a same or similar form for subsequent processing operations to complete device fabrication, such as CMOS, PMOS, and / or NMOS device fabrication. As an example of a completed device, Fig. 5 is a cross-sectional view of a non-planar integrated circuit structure along a gate line according to an embodiment of the present disclosure.

[0066] With reference to Fig. 5, a semiconductor structure or device 500 includes a non-planar active region (e.g., a fin structure including a protruding fin portion 504 and a subfin region 505) within a trench isolation region 506. In one embodiment, the non-planar active region is separated into nanowires (such as nanowires 504A and 504B) above the subfin region 505, as represented by the dashed lines, instead of a solid fin. In both cases, for ease of description of the non-planar integrated circuit structure 500, a non-planar active region 504 is hereinafter referred to as a protruding fin portion. In one embodiment, a manufacturing process includes using a process scheme that provides active regions 504 as a depopulated channel structure, examples of which are described above in connection with the Fig. 1A-1H, 2A-2D, 3A-3C, and 4. For example, in one embodiment, the bottom nanowires 504B are dielectric nanowires and the top nanowires 504A are active semiconductor nanowires.

[0067] A gate line 508 is disposed over the protruding portions 504 of the non-planar active region (including, if applicable, surrounding nanowires 504A and 504B) as well as over a portion of the trench isolation region 506. As shown, the gate line 508 includes a gate electrode 550 and a gate dielectric layer 552. In one embodiment, the gate line 508 may also include a dielectric cap layer 554. A gate contact 514 and the overlying gate contact via 516 are also seen from this perspective, along with an overlying metal interconnect 560, all disposed in interlayer dielectric stacks or layers 570. Also from the perspective of Fig. 5, in one embodiment, the gate contact 514 is disposed over the trench isolation region 506, but not over the non-planar active regions.

[0068] In one embodiment, the semiconductor structure or device 500 is a non-planar device, such as, among others, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, a corresponding semiconducting channel region consists of or is formed within a three-dimensional body. In such an embodiment, the gate electrode stacks of the gate lines 508 surround at least a top surface and a pair of sidewalls of the three-dimensional body.

[0069] As in Fig. As shown in Figure 5, in one embodiment, there is an interface 580 between a protruding fin portion 504 and a subfin region 505. The interface 580 may be a transition region between a doped subfin region 505 and a lightly or undoped upper fin portion 504. In such an embodiment, each fin is approximately 10 nanometers or less wide, and subfin dopants are supplied from an adjacent solid-state doping layer at the subfin location. In one particular such embodiment, each fin is less than 10 nanometers wide.

[0070] Although this is Fig. 5, it is understood that source or drain regions of or adjacent to the protruding fin portions 504 are located on both sides of the gate line 508, i.e., into and out of the side. In one embodiment, the source and drain regions are doped portions of the original material of the protruding fin portions 504. In another embodiment, the material of the protruding fin portions 504 is removed and replaced with another semiconductor material, e.g., by epitaxial deposition, to form discrete epitaxial bumps or non-discrete epitaxial structures. In either embodiment, the source or drain regions may extend below the level of the dielectric layer of the trench isolation region 506, i.e., into the subfin region 505. According to one embodiment of the present disclosure, the more heavily doped subfin regions, i.e.,The doped portions of the fins below interface 580 exhibit source-to-drain leakage through this portion of the bulk semiconductor fins. In one implementation, the source and drain structures are epitaxial N-type source and drain structures, both including impurity atoms of phosphorus dopants. According to one or more embodiments of the present disclosure, the source and drain regions have associated asymmetric source and drain contact structures, as previously described in connection with

[0044] FIG. Fig. 4 described.

[0071] With further reference to Fig. 5, in one embodiment, the fins 504 / 505 (and possibly the nanowires 504A and 504B) are made of a crystalline silicon, silicon / germanium, or germanium layer doped with a charge carrier, such as, but not limited to, phosphorus, arsenic, boron, or a combination thereof. In one embodiment, the concentration of silicon atoms is greater than 97%. In another embodiment, the fins 504 / 505 are made of a Group III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. The trench isolation region 506 may be made of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0072] The gate line 508 may be comprised of a gate electrode stack including a gate dielectric layer 552 and a gate electrode layer 550. In one embodiment, the gate electrode of the gate electrode stack is comprised of a metal gate, and the gate dielectric layer is comprised of a high-k material. For example, in one embodiment, the gate dielectric layer is comprised of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of the gate dielectric layer may include a layer of native oxide formed by the top few layers of the protruding fin portions 504.In one embodiment, the gate dielectric layer consists of an upper high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer consists of an upper portion of hafnium oxide and a lower portion of silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric is a "U"-shaped structure including a lower portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the upper surface of the substrate.

[0073] In one embodiment, the gate electrode is composed of a metal layer, such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In a specific embodiment, the gate electrode is composed of a non-work-function-tuning fill material formed above a work-function-tuning metal layer. The gate electrode layer may be composed of a p-type work-function metal or an n-type work-function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may be composed of a stack of two or more metal layers, wherein one or more metal layers are work-function metal layers and at least one metal layer is a conductive fill layer.For a PMOS transistor, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. A p-type metal layer will enable the formation of a PMOS gate electrode with a work function ranging between approximately 4.9 eV and approximately 5.2 eV. For an NMOS transistor, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An n-type metal layer will enable the formation of an NMOS gate electrode with a work function ranging between approximately 3.9 eV and approximately 4.2 eV.In some implementations, the gate electrode may consist of a "U"-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and not including sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0074] Spacers associated with the gate electrode stacks may be made of a material suitable for ultimately electrically isolating or contributing to the isolation of a permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are made of a dielectric material such as, among others, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0075] The gate contact 514 and the overlying gate contact via 516 may be made of a conductive material. In one embodiment, one or more of the contacts or vias may be made of a metal species. The metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy, such as a metal-metal alloy or a metal-semiconductor alloy (such as, for example, a silicide material).

[0076] In one embodiment (although not shown), a contact structure is formed that is substantially perfectly aligned with an existing gate structure 508 while eliminating the use of a lithographic step with an extremely tight coverage accuracy budget. In one embodiment, the contact pattern is a vertically asymmetric contact pattern, such as in connection with Fig. 4. In other embodiments, all contacts are front-connected and are not asymmetric. In one such embodiment, the self-aligned approach enables the use of an intrinsically highly selective wet etch (e.g., versus conventionally implemented dry or plasma etching) to create contact openings. In one embodiment, a contact structure is formed by utilizing an existing gate structure in combination with a contact plug lithography process. In one such embodiment, the approach enables the elimination of the need for an otherwise critical lithography process to create contact patterning, as used in conventional approaches. In one embodiment, a trench contact grid is not separately patterned, but is instead formed between poly (gate) lines.For example, in such an embodiment, a trench contact grid is formed subsequent to gate grid patterning but prior to gate grid cutting.

[0077] In one embodiment, providing structure 500 involves fabricating gate stack structure 508 through a replacement gate process. In such a scheme, dummy gate material, such as polysilicon or silicon nitride pillar material, may be removed and replaced with a permanent gate electrode material. In such an embodiment, a permanent gate dielectric layer is also formed in this process rather than being carried over from prior processing. In one embodiment, dummy gates are removed through a dry etch or wet etch process. In one embodiment, dummy gates are made of polycrystalline silicon or amorphous silicon and are removed using a dry etch process including the use of SF6.In another embodiment, dummy gates are made of polycrystalline silicon or amorphous silicon and are removed using a wet etching process including aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, dummy gates are made of silicon nitride and are removed using a wet etch including aqueous phosphoric acid.

[0078] With further reference to Fig. 5, the arrangement of a semiconductor structure or device 500 places the gate contact over isolation regions. Such an arrangement may be considered an inefficient use of layout space. However, in another embodiment, a semiconductor device includes contact structures that contact portions of a gate electrode formed over an active region, e.g., over a subfin 505, and in a same layer as a trench contact via.

[0079] It should be understood that not all aspects of the processes described above need to be implemented to fall within the spirit and scope of embodiments of the present disclosure. Furthermore, the processes described herein may be used to form one or a plurality of semiconductor devices. The semiconductor devices may be transistors or similar devices. For example, in one embodiment, the semiconductor devices are metal-oxide-semiconductor (MOS) transistors for logic or memory, or are bipolar transistors. Furthermore, in one embodiment, the semiconductor devices have a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a gate-all-around (GAA) device, a tri-gate device, a dual-gate independent access device, or a FIN-FET.One or more embodiments may be particularly useful for fabricating semiconductor devices with a sub-10 nanometer (10 nm) technology node.

[0080] In one embodiment, the interlayer dielectric (ILD) material, as used throughout this specification, consists of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or other deposition methods.

[0081] In one embodiment, as used throughout this specification, metal lines or an interconnect line material (and via material) consist of one or more metal structures or other conductive structures. A common example is the use of copper lines and structures, which may or may not include barrier layers between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers (e.g., layers including Ta and / or TaN and / or Ti and / or TiN), stacks of different metals or alloys, etc. Accordingly, the interconnect lines may be a single layer of material or may be formed from several layers, including conductive liner layers and fill layers.Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, can be used to form interconnect lines. In one embodiment, the interconnect lines are made of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. The interconnect lines are sometimes referred to in the art as traces, wires, lines, metal, or simply interconnect.

[0082] In one embodiment, hard mask materials, cap layers, or plugs, as also used throughout this specification, are made of dielectric materials different from the interlayer dielectric material. In one embodiment, different hard mask, cap, or plug materials may be used in different regions to provide different growth or etch selectivity to each other and to underlying dielectric and metal layers. In some embodiments, a hard mask layer, cap, or plug layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials.Alternatively, depending on the particular implementation, other hard mask, cap, or plug layers known in the art may be used. The hard mask, cap, or plug layers may be formed by CVD, PVD, or other deposition techniques.

[0083] In one embodiment, as used throughout this specification, lithographic processes are performed using 193 nm immersion lithography (i193), EUV and / or EBDW lithography, or the like. A positive or negative photoresist may be used. In one embodiment, a lithographic mask is a three-layer mask consisting of a topographic mask portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In one specific such embodiment, the topographic mask portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0084] In another aspect, one or more embodiments relate to adjacent semiconductor structures or devices separated by self-aligned gate endcap (SAGE) structures. Certain embodiments may relate to the integration of multi-width (multi-WSI) nanowires and nanoribbons in a SAGE architecture and separated by a SAGE wall. In one embodiment, nanowires / nanoribbons with multiple WSI are integrated in a SAGE architecture portion of a front-end process flow. Such a process flow may involve the integration of nanowires and nanoribbons of different WSI to provide robust functionality of next-generation low-power and high-performance transistors. Associated epitaxial source or drain regions may be embedded (e.g.,parts of nanowires are removed and then source-or-drain (S / D) growth is performed) or can be formed by vertical fusion (e.g. epitaxial regions are formed around existing wires), as described below in connection with the . Fig. 9A-9E are described in more detail.

[0085] To provide further context, advantages of a self-aligned gate endcap (SAGE) architecture can include enabling higher layout density and, in particular, scaling diffusion-to-diffusion spacing. To provide an illustrative comparison, Fig. 6 Cross-sectional views through nanowires and fins for a non-endcap architecture (left side (a)) versus a self-aligned gate endcap (SAGE) architecture (right side (b)) according to an embodiment of the present disclosure.

[0086] Referring to the left side (a) of Fig. 6, an integrated circuit structure 600 includes a substrate 602 with subfins 604 protruding therefrom within an isolation structure 608 that laterally surrounds the subfins 604. Corresponding nanowires 649 and 605 are located above the subfins 604. In one embodiment, the lower nanowires 649 are dielectric nanowires and the upper nanowires 605 are semiconductor nanowires. A gate structure may be formed over the integrated circuit structure 600 to fabricate a device. However, discontinuities in such a gate structure may be accommodated by increasing the spacing between the subfins 604 / nanowire 649 / 605 pairs.

[0087] In contrast, referring to the right-hand side (b) of Fig. 6, an integrated circuit structure 650 includes a substrate 652 with subfins 654 protruding therefrom within an isolation structure 658 that laterally surrounds the subfins 654. Corresponding nanowires 699 and 655 are located above the subfins 654. In one embodiment, the lower nanowires 699 are dielectric nanowires and the upper nanowires 655 are semiconductor nanowires. Insulating SAGE walls 660 are included within the isolation structure 658 and between adjacent pairs of subfin 654 / nanowire 699 / 655. The distance between an isolation SAGE wall 660 and a nearest pair of subfins 654 / nanowires 699 / 655 defines the gate endcap spacing 662. A gate structure can be formed over the integrated circuit structure 600 between isolation SAGE walls to fabricate a device. Discontinuities in such a gate structure are imposed by the isolation SAGE walls.Because the isolation SAGE walls 660 are self-aligned, limitations of conventional approaches can be minimized to enable more aggressive diffusion-to-diffusion spacing. Furthermore, because gate structures include discontinuities at all locations, individual gate structure portions may be one layer connected by local interconnects formed over the isolation SAGE walls 660. In one embodiment, as shown, the SAGE walls 660 each include a bottom dielectric portion and a dielectric cap on the bottom dielectric portion, as shown.

[0088] According to one embodiment of the present disclosure, a manufacturing process for structures comprising Fig. 6, the use of a process scheme providing a gate-all-around integrated circuit structure with a depopulated channel structure, examples of which are described above in connection with the Fig. 1A-1H, 2A-2D, 3A-3C and 4.

[0089] A self-aligned gate endcap (SAGE) processing scheme involves the formation of gate / trench contact endcaps that are self-aligned with fins without requiring additional length to account for mask misregistration. Accordingly, embodiments may be implemented to enable a reduction in transistor layout area. Embodiments described herein may include the fabrication of gate endcap isolation structures, which may also be referred to as gate walls, isolation gate walls, or self-aligned gate endcap (SAGE) walls.

[0090] An example processing scheme for structures with SAGE walls separating adjacent devices is shown in Fig. 7 Cross-sectional views representing various operations in a method of fabricating a self-aligned gate end cap (SAGE) structure with gate all-around devices according to an embodiment of the present disclosure.

[0091] With reference to part (a) of Fig. 7, a starting structure includes a nanowire patterning stack 704 above a substrate 702. A lithographic patterning stack 706 is formed above the nanowire patterning stack 704. The nanowire patterning stack 704 includes alternating silicon-germanium layers 710 and silicon layers 712. A protective mask 714 is located between the nanowire patterning stack 704 and the lithographic patterning stack 706. In one embodiment, the lithographic patterning stack 706 is a three-layer mask consisting of a topographic mask portion 720, an anti-reflective coating (ARC) layer 722, and a photoresist layer 724. In one particular such embodiment, the topographic mask portion 720 is a carbon hard mask (CHM) layer, and the anti-reflective coating layer 722 is a silicon ARC layer.

[0092] With reference to part (b) of Fig. 7, the stack of part (a) is lithographically patterned and then etched to provide an etched structure including a patterned substrate 702 and trenches 730.

[0093] With reference to part (c) of Fig. 7, the structure of part (b) includes an isolation layer 740 and a SAGE material 742 formed in trenches 730. The structure is then planarized to leave the patterned topographic masking layer 720' as an exposed top layer.

[0094] With reference to part (d) of Fig. 7, the isolation layer 740 is recessed below a top surface of the patterned substrate 702, for example, to define a protruding fin portion and to provide a trench isolation structure 741 below the SAGE walls 742.

[0095] With reference to part (e) of Fig. 7, the silicon germanium layers 710 are removed at least in the channel region to expose the silicon nanowires 712A and 712B.

[0096] According to one embodiment of the present disclosure, a manufacturing process for structures comprising Fig. 7, the use of a process scheme providing a gate-all-around integrated circuit structure with a depopulated channel structure, examples of which are described above in connection with the Fig. 1A-1H, 2A-2D, 3A-3C and 4. For example, with reference to part (e) of Fig. 7, in one embodiment, nanowire 712B and nanoribbon 712A are a semiconductor nanowire and nanoribbon, respectively. In one such embodiment, nanowire 799B is a dielectric nanowire and nanoribbon 799A is a dielectric nanoribbon, as shown. In another such embodiment, nanowire 799B is a dielectric nanowire and nanoribbon 799A is a semiconductor nanoribbon. In another such embodiment, nanowire 799B is a semiconductor nanowire and nanoribbon 799A is a dielectric nanoribbon.

[0097] After forming the structure from part (e) of Fig. 7, one or more gate stacks may be formed around the semiconductor and dielectric nanowires and / or nanoribbons, over protruding fins of substrate 702, and between SAGE walls 742. In one embodiment, prior to forming the gate stacks, the remaining portion of the protective mask 714 is removed. In another embodiment, the remaining portion of the protective mask 714 is retained as an insulating fin cap as an artifact of the processing scheme.

[0098] Referring again to part (e) of Fig. 7, it is understood that a channel view is depicted with source or drain regions extending into and out of the side. In one embodiment, the channel region including nanowires 712B has a width that is smaller than the channel region including nanowires 712A. Accordingly, in one embodiment, an integrated circuit structure includes multi-width (multi-Wsi) nanowires. Although the structures of 712B and 712A may be differentiated as nanowires and nanoribbons, respectively, both such structures are typically referred to herein as nanowires. It is also understood that reference to or depiction of a fin / nanowire pair throughout may refer to a structure including a fin and one or more overlying nanowires (e.g., in Fig. 7 two overlying nanowires are shown), with one or more lower wires being oxidized for depopulation.

[0099] Referring again to part (e) of Fig. 7 and the subsequent description, an integrated circuit structure according to an embodiment of the present disclosure includes a first vertical array of nanowires and a second vertical array of nanowires above a substrate. The first vertical array of nanowires includes a greater number of semiconductor nanowires than the second vertical array of nanowires. The first and second vertical arrays of nanowires include coplanar topmost nanowires and coplanar bottommost nanowires. The second vertical array of nanowires includes a dielectric bottommost nanowire. A first gate stack overlies the first vertical array of nanowires. A second gate stack overlies the second vertical array of nanowires and surrounds the dielectric bottommost nanowire.

[0100] In one embodiment, the nanowires of the first vertical array of nanowires have a horizontal width that corresponds to the horizontal width of the nanowires of the second vertical array of nanowires. In another embodiment, the nanowires of the first vertical array of nanowires have a horizontal width that is greater than a horizontal width of the nanowires of the second vertical array of nanowires. In another embodiment, the nanowires of the first vertical array of nanowires have a horizontal width that is less than a horizontal width of the nanowires of the second vertical array of nanowires.

[0101] To provide an example integrated circuit structure with three vertically arranged nanowires, Fig. 8A is a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure. Fig. Figure 8B illustrates a cross-sectional source or drain view of the nanowire-based integrated circuit structure of Fig. 8A along the a-a' axis. Fig. Figure 8C illustrates a cross-sectional channel view of the nanowire-based integrated circuit structure from Fig. 8A along the b-b' axis.

[0102] With reference to Fig. 8A, an integrated circuit structure 800 includes one or more vertically stacked nanowires (set 804) above a substrate 802. An optional fin between the bottommost nanowire and the substrate 802 is omitted to highlight the nanowire portion for illustrative purposes. Embodiments herein address both single-wire and multi-wire devices. As an example, three nanowire-based devices with nanowires 804A, 804B, and 804C are shown for illustrative purposes. For simplicity of description, nanowire 804A is used as an example, with the description focusing on one of the nanowires. It should be understood that where attributes of one nanowire are described, embodiments based on a plurality of nanowires may have the same or substantially the same attributes for each of the nanowires.

[0103] Each of the nanowires 804 includes a channel region 806 within the nanowire. The channel region 806 has a length (L). Referring to Fig. 8C, the channel area also has a perimeter (Pc) orthogonal to the length (L). With reference to both Fig. 8A and 8C, a gate electrode stack 808 surrounds the entire perimeter (Pc) of each of the channel regions 806. The gate electrode stack 808 includes a gate electrode along with a gate dielectric layer between the channel region 806 and the gate electrode (not shown). In one embodiment, the channel region is discrete in that it is completely surrounded by the gate electrode stack 808 without any intervening material, such as underlying substrate material or overlying channel fabrication materials. Accordingly, in embodiments with multiple nanowires, the channel regions 806 of the nanowires 804 are also discrete relative to each other.

[0104] According to one embodiment of the present disclosure, a manufacturing process for structures comprising Fig. 8A-8C, the use of a process scheme providing a gate-all-around integrated circuit structure with a depopulated channel structure 806, examples of which are described above in connection with the Fig. 1A-1H, 2A-2D, 3A-3C, and 4. For example, in one embodiment, nanowire 804A is a dielectric nanowire. In another embodiment, both nanowire 804A and nanowire 804B are dielectric nanowires.

[0105] With reference to both Fig. 8A and 8B, the integrated circuit structure 800 includes a pair of non-discrete source or drain regions 810 / 812. The pair of non-discrete source or drain regions 810 / 812 are located on either side of the channel regions 806 of the plurality of vertically stacked nanowires 804. Furthermore, the pair of non-discrete source or drain regions 810 / 812 are adjacent to the channel regions 806 of the plurality of vertically stacked nanowires 804. In one such embodiment, not shown, the pair of non-discrete source or drain regions 810 / 812 are directly vertically adjacent to the channel regions 806 in that epitaxial growth occurs on and between nanowire portions extending beyond the channel regions 806, with nanowire ends shown within the source or drain structures. In another embodiment, as in Fig. As shown in Figure 8A, the pair of non-discrete source or drain regions 810 / 812 indirectly vertically adjoin the channel regions 806 in that they are formed at the ends of the nanowires and not between the nanowires.

[0106] In one embodiment, as illustrated, the source or drain regions 810 / 812 are non-discrete in that there are no individual and discrete source or drain regions for each channel region 806 of a nanowire 804. Accordingly, in embodiments with multiple nanowires 804, the source or drain regions 810 / 812 of the nanowires are global or unified source or drain regions, as opposed to discrete ones for each nanowire. In one embodiment, from a cross-sectional perspective orthogonal to the length of the discrete channel regions 806, each of the pair of non-discrete source or drain regions 810 / 812 is approximately rectangular with a lower tapered portion and an upper vertex portion, as shown in Fig. 8B. However, in other embodiments, the source or drain regions 810 / 812 of the nanowires are relatively larger, but discrete, non-vertically joined epitaxial structures, such as nubs, which may be formed in conjunction with Fig. 4 are described.

[0107] According to one embodiment of the present disclosure, and as in Fig. 8A and Fig. 8B, the integrated circuit structure 800 further includes a pair of contacts 814, wherein each contact 814 is on one of the pair of non-discrete source or drain regions 810 / 812. In such an embodiment, in a vertical sense, each contact 814 completely surrounds the respective non-discrete source or drain region 810 / 812. In another aspect, the entire perimeter of the non-discrete source or drain regions 810 / 812 may not be accessible for contact with contacts 814, and the contact 814 accordingly only partially surrounds the non-discrete source or drain regions 810 / 812, as in Fig. 8B. In a contrasting embodiment (not shown), the entire perimeter of the non-discrete source or drain regions 810 / 812 along the a-a' axis is surrounded by the contacts 814. According to an embodiment of the present disclosure, the pair of contacts 814, although not shown, is an asymmetric pair of contacts, as described in connection with Fig. 4 described.

[0108] With reference to Fig. 8B and Fig. 8C, the non-discrete source or drain regions 810 / 812 are global in the sense that a single unified feature is used as a source or drain region for multiple (in this case, 3) nanowires 804, and in particular, for more than one discrete channel region 806. In one embodiment, the pair of non-discrete source or drain regions 810 / 812 is made of a semiconductor material that is different from the semiconductor material of the discrete channel regions 806, e.g., the pair of non-discrete source or drain regions 810 / 812 is made of silicon germanium, while the discrete channel regions 806 is made of silicon. In another embodiment, the pair of non-discrete source or drain regions 810 / 812 is made of a semiconductor material that is the same or substantially the same as the semiconductor material of the discrete channel regions 806, e.g.,the pair of both the non-discrete source or drain regions 810 / 812 and the discrete channel regions 806 are made of silicon.

[0109] With further reference to Fig. 8A, in one embodiment, the integrated circuit structure 800 further includes a pair of spacers 816. As illustrated, outer portions of the pair of spacers 816 may overlap portions of the non-discrete source or drain regions 810 / 812, thereby providing "embedded" portions of the non-discrete source or drain regions 810 / 812 beneath the pair of spacers 816. As also illustrated, the embedded portions of the non-discrete source or drain regions 810 / 812 may not extend beneath the entirety of the pair of spacers 816.

[0110] Substrate 802 may be made of a material suitable for fabricating an integrated circuit structure. In one embodiment, substrate 802 includes a lower bulk substrate made of a single crystal of a material that may include, but is not limited to, silicon, germanium, silicon germanium, or a Group III-V compound semiconductor material. An upper insulator layer made of a material that may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride is disposed on the lower bulk substrate. Accordingly, structure 800 may be fabricated from an initial semiconductor-on-insulator substrate. Alternatively, structure 800 is formed directly from a bulk substrate, and local oxidation is used to form electrically insulating portions instead of the previously described upper insulator layer.In another alternative embodiment, structure 800 is formed directly from a bulk substrate, and doping is used to form electrically isolated active regions, such as nanowires, thereon. In such an embodiment, the first nanowire (i.e., near the substrate) is in the form of an omega-FET-type structure.

[0111] In one embodiment, the nanowires 804 may be sized as wires or ribbons, as described below, and may have square or rounded corners. In one embodiment, the nanowires 804 are made of a material such as, but not limited to, silicon, germanium, or a combination thereof. In such an embodiment, the nanowires are single-crystalline. For example, for a silicon nanowire 804, a single-crystalline nanowire may be oriented in a global (100) orientation, e.g., with a <100> -plane in the z-direction. As described below, other orientations may also be considered. In one embodiment, the dimensions of the nanowires 804 are in the nanoscale from a cross-sectional perspective. For example, in one particular embodiment, the smallest dimension of the nanowires 804 is less than about 20 nanometers.In one embodiment, the nanowires 804 are made of a material under mechanical stress, particularly in the channel regions 806.

[0112] With reference to Fig. 8C, in one embodiment, each of the channel regions 806 has a width (Wc) and a height (Hc), where the width (Wc) is approximately equal to the height (Hc). That is, in both cases, the channel regions 806 are rectangular or, if with rounded corners, circular in cross-sectional profile. In another aspect, the width and height of the channel region need not be equal, as in the case of nanoribbons, as described throughout.

[0113] In another aspect, methods are provided for fabricating a nanowire portion of a fin / nanowire integrated circuit structure. For example, Fig. 9A-9E are three-dimensional cross-sectional views representing various operations in a method for fabricating a nanowire portion of a fin / nanowire structure, according to an embodiment of the present disclosure.

[0114] A method of fabricating a nanowire integrated circuit structure may include forming a nanowire over a substrate. In a specific example showing the formation of two silicon nanowires, Fig. 9A illustrates a substrate 902 (e.g., consisting of a bulk silicon substrate 902A with an insulating silicon dioxide layer 902B thereon) with a silicon layer 904 / silicon germanium layer 906 / silicon layer 908 stack thereon. It should be understood that in another embodiment, a silicon germanium layer / silicon layer / silicon germanium layer stack may be used to ultimately form two silicon germanium nanowires.

[0115] In relation to Fig. 9B, a portion of the stack of silicon layer 904 / silicon germanium layer 906 / silicon layer 908 and an upper portion of the silicon dioxide layer 902B is patterned into a fin-type structure 910, e.g., using a mask and plasma etching process. For illustrative purposes, it should be noted that the etching for Fig. 9B as forming two silicon nanowire precursor sections. Although the etch is shown as terminating within a lower insulation layer for ease of illustration, more complex stacks are contemplated in the context of embodiments of the present disclosure. For example, the process may be applied to a nanowire / fin stack, as described in connection with Fig. 4 described.

[0116] The method may also include forming a channel region in the nanowire, wherein the channel region has a length and a perimeter orthogonal to the length. In a specific example showing the formation of three gate structures over the two silicon nanowires, Fig. 9C shows the fin-type structure 910 with three sacrificial gates 912A, 912B, and 912C thereon. In such an embodiment, the three sacrificial gates 912A, 912B, and 912C consist of a sacrificial gate oxide layer 914 and a sacrificial polysilicon gate layer 916, which are deposited and patterned over the entire area using a plasma etching process.

[0117] After patterning to form the three sacrificial gates 912A, 912B, and 912C, spacers may be formed on the sidewalls of the three sacrificial gates 912A, 912B, and 912C, doping may be performed (e.g., tip and / or source and drain doping), and an interlayer dielectric layer may be formed to cover the three sacrificial gates 912A, 912B, and 912C. The interlayer dielectric layer may be polished to expose the three sacrificial gates 912A, 912B, and 912C for a replacement gate or gate-last process.

[0118] In relation to Fig. 9D, the three sacrificial gates 912A, 912B, and 912C are removed, leaving the spacers 918 and a portion of the interlayer dielectric layer 920. In addition, the portions of the silicon germanium layer 906 and the portion of the insulating silicon dioxide layer 902B of the fin structure 910 are removed in the areas originally covered by the three sacrificial gates 912A, 912B, and 912C. Discrete portions of the silicon layers 904 and 908 are thus retained, as shown in Fig. 9D.

[0119] The discrete sections of silicon layers 904 and 908 formed in Fig. 9D, ultimately become channel regions in a nanowire-based device in one embodiment. Therefore, in the Fig. 9D, channel engineering or tuning may be performed. For example, in one embodiment, the Fig. 9D are thinned using oxidation and etching processes. Such an etching process may be performed concurrently when the wires are separated by etching the silicon-germanium layer 906. Accordingly, the starting wires formed from the silicon layers 904 and 908 start thicker and thin to a size suitable for a channel region in a nanowire device, regardless of the size of the device's source and drain regions. Thus, in one embodiment, forming the channel region includes removing a portion of the nanowire, and the resulting perimeters of the source and drain regions (described below) are larger than the perimeter of the resulting channel region.

[0120] According to an embodiment of the present disclosure, after removing the three sacrificial gates 912A, 912B and 912C and removing the portions of the silicon germanium layer 906 and the portion of the insulating silicon dioxide layer 902B of the fin structure 910 from the regions originally covered by the three sacrificial gates 912A, 912B and 912C, a manufacturing process is performed that provides a gate-all-around integrated circuit structure with a depopulated channel structure, examples of which are described above in connection with the Fig. 1A-1H, 2A-2D, 3A-3C, and 4. For example, in one embodiment, nanowire 904 is a dielectric nanowire in the channel region.

[0121] The method may also include the formation of a gate electrode stack surrounding the entire perimeter of the channel region. In the specific example showing the formation of three gate structures over the two silicon nanowires, Fig. 9E the structure after the deposition of a gate dielectric layer 922 (such as a high-k gate dielectric layer) and a gate electrode layer 924 (such as a metal gate electrode layer) and subsequent polishing between the spacers 918. That is, gate structures are formed in the trenches 921 of Fig. 9D. In addition, Fig. 9E shows the result of the subsequent removal of the interlayer dielectric layer 920 after formation of the permanent gate stack. The portions of the silicon germanium layer 906 and the portion of the insulating silicon dioxide layer 902B of the fin structure 910 are also removed in the areas originally formed by the Fig. 9D. Discrete sections of the silicon layers 904 and 908 are thus preserved, as shown in Fig. 9E.

[0122] The method may also include forming a pair of source and drain regions in the nanowire on either side of the channel region, each source and drain region having a perimeter orthogonal to the length of the channel region. In particular, the discrete portions of silicon layers 904 and 908 formed in Fig. 9E, in one embodiment, ultimately at least a portion of the source and drain regions in a nanowire-based device. In such an embodiment, epitaxial source or drain structures are formed by fusing epitaxial material around the existing nanowires 904 and 908. In another embodiment, epitaxial source or drain structures are embedded, e.g., portions of the nanowires 904 and 908 are removed and then source-or-drain (S / D) growth is performed. In the latter case, according to an embodiment of the present disclosure, such epitaxial source or drain structures may be non-discrete, as described in connection with the Fig. 8A and Fig. 8B, or may be discrete, as in connection with Fig. 4 by way of example. In both cases, source or drain structures are, in one embodiment, epitaxial N-type source or drain structures, both including impurity atoms of phosphorus dopants.

[0123] The method may then include forming a pair of contacts, wherein a first of the pair of contacts completely or almost completely surrounds the perimeter of the source region and a second of the pair of contacts completely or almost completely surrounds the perimeter of the drain region. In one embodiment, the pair of contacts is an asymmetric pair of source and drain structures, as described in connection with Fig. 4. In other embodiments, the pair of contacts is a symmetric pair of source and drain contact structures. In particular, contacts are formed in the trenches 925 of Fig. 9E after epitaxial growth. One of the trenches 925 may initially be deepened further than the other of the trenches 925. In one embodiment, the contacts are formed from a metallic species. In such an embodiment, the metallic species is formed by conformally depositing a contact metal and then filling the remaining trench volume. The conformal aspect of the deposition may be performed using chemical vapor deposition (CVD), atomic layer deposition (ALD), or metal reflow.

[0124] In one embodiment, as described herein, an integrated circuit structure includes non-planar devices, such as, but not limited to, a FinFET or a tri-gate device with one or more corresponding overlying nanowire structures. In such an embodiment, a corresponding semiconducting channel region consists of or is formed within a three-dimensional body with one or more discrete nanowire channel portions overlying the three-dimensional body. In such an embodiment, the gate structures surround at least a top surface and a pair of sidewalls of the three-dimensional body and further surround each of the one or more discrete nanowire channel portions.

[0125] In one embodiment, as described herein, a substrate may be composed of a semiconductor material that can withstand a manufacturing process and in which charge can migrate. In one embodiment, the substrate is a bulk substrate composed of a crystalline silicon, silicon / germanium, or germanium layer doped with a charge carrier, such as, but not limited to, phosphorus, arsenic, boron, or a combination thereof, to form an active region. In one embodiment, the concentration of silicon atoms in a bulk substrate is greater than 97%. In another embodiment, a bulk substrate consists of an epitaxial layer grown on a distinct crystalline substrate, e.g., an epitaxial silicon layer grown on a boron-doped monocrystalline bulk silicon substrate. A bulk substrate may alternatively be composed of a Group III-V material.In one embodiment, a bulk substrate is made of a Group III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, a bulk substrate is made of a Group III-V material, and the charge carrier dopant impurity atoms are those such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0126] In one embodiment, as described herein, a trench isolation layer may be comprised of a material suitable for ultimately electrically isolating or contributing to the isolation of portions of a permanent gate structure from an underlying bulk substrate, or for isolating active regions formed in an underlying bulk substrate, such as isolating active fin regions. For example, in one embodiment, a trench isolation layer may be comprised of a dielectric material such as, among others, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0127] In one embodiment, as described herein, self-aligned gate endcap isolation structures may be comprised of a material or materials suitable for ultimately electrically isolating or contributing to the isolation of portions of permanent gate structures. Example materials or material combinations include a single-material structure, such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other example materials or material combinations include a multilayer stack having a lower portion of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper portion of a higher dielectric constant material, such as hafnium oxide.

[0128] Embodiments disclosed herein may be used to fabricate a wide variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, a semiconductor memory may be fabricated. Furthermore, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the art. For example, in computer systems (e.g., desktop computers, laptop computers, servers), mobile phones, personal electronic devices, etc. The integrated circuits may be coupled to a bus and other components in the systems.For example, a processor may be coupled to a memory, a chipset, etc., by one or more buses. Each of the processor, the memory, and the chipset may potentially be fabricated using the approaches disclosed herein.

[0129] Fig. 10 illustrates a computing device 1000 according to an implementation of an embodiment of the present disclosure. Computing device 1000 houses a circuit board 1002. Circuit board 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006. Processor 1004 is physically and electrically coupled to circuit board 1002. In some implementations, at least one communication chip 1006 is also physically and electrically coupled to circuit board 1002. In further implementations, communication chip 1006 is part of processor 1004.

[0130] Depending on its applications, computing device 1000 may include other components that may not be physically and electrically coupled to circuit board 1002. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard disk drive, a compact disk (CD), a digital versatile disk (DVD), and so on).

[0131] The communication chip 1006 enables wireless communications for transferring data to and from the computing device 1000. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through a non-solid-state medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not include any wires, although in some embodiments they may not. The communication chip 1006 can implement any of a number of wireless standards or protocols, including, but not limited to, WiFi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, LTE (Long Term Evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols referred to as 3G, 4G, 5G, and beyond. Computing device 1000 may include a plurality of communication chips 1006. For example, a first communication chip 1006 may be dedicated to shorter-range wireless communication, such as WiFi and Bluetooth, and a second communication chip 1006 may be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0132] The processor 1004 of the computing device 1000 includes an integrated circuit die encapsulated within the processor 1004. The integrated circuit die of the processor 1004 may include one or more structures, such as gate-all-around integrated circuit structures with depopulated channel structures, constructed according to implementations of embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that may be stored in registers and / or memory.

[0133] The communication chip 1006 also includes an integrated circuit die encapsulated within the communication chip 1006. The integrated circuit die of the communication chip 1006 may include one or more structures, such as gate-all-around integrated circuit structures with depopulated channel structures, constructed according to implementations of embodiments of the present disclosure.

[0134] In further implementations, another component housed within the computing device 1000 may include an integrated circuit die including one or more structures, such as gate-all-around integrated circuit structures with depopulated channel structures constructed according to implementations of embodiments of the disclosure.

[0135] In various implementations, computing device 1000 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultramobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 1000 may be any other electronic device that processes data.

[0136] Fig.11 illustrates an interposer 1100 incorporating one or more embodiments of the present disclosure. The interposer 1100 is an intermediate substrate used as a bridge from a first substrate 1102 to a second substrate 1104. The first substrate 1102 may be, for example, an integrated circuit die. The second substrate 1104 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 1100 is to spread an interconnect to a wider pitch or to reroute an interconnect to another interconnect. For example, an interposer 1100 may couple an integrated circuit die to a ball grid array (BGA) 1106, which may then be coupled to the second substrate 1104.In some embodiments, the first and second substrates 1102 / 1104 are mounted on opposite sides of the interposer 1100. In other embodiments, the first and second substrates 1102 / 1104 are mounted on the same side of the interposer 1100. And in further embodiments, three or more substrates are connected together via the interposer 1100.

[0137] The interposer 1100 may be formed from an epoxy resin, a glass-fiber-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer 1100 may be formed from alternating rigid or flexible materials, which may include the same materials previously described for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials.

[0138] The interposer 1100 may include metal interconnects 1108 and through-silicon vias 1110, including, but not limited to, through-silicon vias (TSVs) 1112. The interposer 1100 may further include embedded devices 1114, which may include both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on the interposer 1100.According to embodiments of the disclosure, devices or processes disclosed herein may be used in the manufacture of the interposer 1100 or in the manufacture of components included in the interposer 1100.

[0139] Thus, embodiments of the present disclosure include gate-all-around integrated circuit structures with depopulated channel structures and methods of fabricating gate-all-around integrated circuit structures with depopulated channel structures.

[0140] The above description of illustrated implementations of embodiments of the disclosure, including what is described in the abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Although specific implementations of the disclosure and examples thereof have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as one skilled in the art will recognize.

[0141] These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and claims. Rather, the scope of the disclosure is determined entirely by the following claims, which are to be interpreted in accordance with established doctrines for claim interpretation.

[0142] Exemplary Embodiment 1: An integrated circuit structure comprises a first vertical array of nanowires, the first vertical array of nanowires comprising one or more dielectric nanowires coupled to a dielectric source or drain structure. A first gate stack overlies the first vertical array of nanowires. A second vertical array of nanowires is arranged laterally spaced from the first vertical array of nanowires, the second vertical array of nanowires comprising one or more semiconductor nanowires coupled to an epitaxial source or drain structure, the one or more semiconductor nanowires horizontally corresponding to the one or more dielectric nanowires, and the epitaxial source or drain structure is laterally spaced from the dielectric source or drain structure.A second gate stack lies above the second vertical array of nanowires.

[0143] Exemplary Embodiment 2: The integrated circuit structure of Exemplary Embodiment 1, further including a dielectric plug laterally between and in contact with the epitaxial source or drain structure and the dielectric source or drain structure.

[0144] Exemplary Embodiment 3: The integrated circuit structure of exemplary embodiment 1 or 2, wherein the epitaxial source or drain structure includes silicon and phosphorus.

[0145] Exemplary Embodiment 4: The integrated circuit structure of exemplary embodiment 1, 2, or 3, wherein the source or drain dielectric structure includes silicon oxide, silicon nitride, or silicon oxynitride.

[0146] Exemplary Embodiment 5: The integrated circuit structure of exemplary embodiment 1, 2, 3, or 4, wherein the epitaxial source or drain structure and the dielectric source or drain structure are formed using a separate source or drain depopulation approach.

[0147] Exemplary Embodiment 6: An integrated circuit structure comprises a first vertical array of nanowires, the first vertical array of nanowires comprising one or more dielectric nanowires coupled to a dielectric source or drain structure. A second vertical array of nanowires lies vertically above the first vertical array of nanowires, the second vertical array of nanowires comprising one or more semiconductor nanowires coupled to an epitaxial source or drain structure. A gate stack lies above the second vertical array of nanowires.

[0148] Exemplary Embodiment 7: The integrated circuit structure of exemplary embodiment 6, further including a dielectric plug laterally adjacent to and in contact with the source or drain dielectric structure.

[0149] Exemplary Embodiment 8: The integrated circuit structure of exemplary embodiment 6 or 7, wherein the epitaxial source or drain structure includes silicon, germanium, and boron.

[0150] Exemplary Embodiment 9: The integrated circuit structure of exemplary embodiment 6, 7, or 8, wherein the source or drain dielectric structure includes silicon oxide, silicon nitride, or silicon oxynitride.

[0151] Exemplary Embodiment 10: The integrated circuit structure of exemplary embodiment 6, 7, 8, or 9, wherein the source or drain dielectric structure is formed using a separate source or drain depopulation approach.

[0152] Example Embodiment 11: A computing device includes a circuit board and a component coupled to the circuit board. The component comprises an integrated circuit structure including a first vertical array of nanowires, the first vertical array of nanowires comprising one or more dielectric nanowires coupled to a dielectric source or drain structure. A first gate stack overlies the first vertical array of nanowires.A second vertical array of nanowires is arranged laterally spaced from the first vertical array of nanowires, the second vertical array of nanowires comprising one or more semiconductor nanowires coupled to an epitaxial source or drain structure, the one or more semiconductor nanowires horizontally corresponding to the one or more dielectric nanowires, and the epitaxial source or drain structure laterally spaced from the dielectric source or drain structure. A second gate stack overlies the second vertical array of nanowires.

[0153] Example Embodiment 12: The computing device of Example Embodiment 11, further including a dielectric plug laterally between and in contact with the epitaxial source or drain structure and the dielectric source or drain structure.

[0154] Example Embodiment 13: The computing device of example embodiment 11 or 12, wherein the epitaxial source or drain structure and the dielectric source or drain structure are formed using a separate source or drain depopulation approach.

[0155] Example Embodiment 14: The computing device of example embodiment 11, 12, or 13, further including a memory coupled to the board.

[0156] Example Embodiment 15: The computing device of example embodiment 11, 12, 13, or 14, further including a communication chip coupled to the circuit board.

[0157] Example Embodiment 16: The computing device of example embodiment 11, 12, 13, 14, or 15, further including a camera coupled to the circuit board.

[0158] Example Embodiment 17: The computing device of example embodiment 11, 12, 13, 14, 15, or 16, further including a display coupled to the circuit board.

[0159] Example Embodiment 18: The computing device of example embodiment 11, 12, 13, 14, 15, 16, or 17, further including a battery coupled to the circuit board.

[0160] Example Embodiment 19: The computing device of example embodiment 11, 12, 13, 14, 15, 16, 17, or 18, wherein the component is an encapsulated integrated circuit die.

[0161] Example Embodiment 20: The computing device of example embodiment 11, 12, 13, 14, 15, 16, 17, 18, or 19, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Claims

[1] Integrated circuit structure comprising: a first vertical array of nanowires, the first vertical array of nanowires comprising one or more dielectric nanowires coupled to a dielectric source or drain structure; a first gate stack over the first vertical array of nanowires; a second vertical array of nanowires arranged laterally spaced from the first vertical array of nanowires, the second vertical array of nanowires comprising one or more semiconductor nanowires coupled to an epitaxial source or drain structure, the one or more semiconductor nanowires horizontally corresponding to the one or more dielectric nanowires, and the epitaxial source or drain structure being laterally spaced from the dielectric source or drain structure; and a second gate stack above the second vertical array of nanowires. [2] The integrated circuit structure of claim 1, further comprising a dielectric plug laterally between and in contact with the epitaxial source or drain structure and the dielectric source or drain structure. [3] The integrated circuit structure of claim 1 or 2, wherein the epitaxial source or drain structure comprises silicon and phosphorus. [4] The integrated circuit structure of claim 1, 2 or 3, wherein the source or drain dielectric structure comprises silicon oxide, silicon nitride or silicon oxynitride. [5] The integrated circuit structure of claim 1, 2, 3 or 4, wherein the epitaxial source or drain structure and the dielectric source or drain structure are formed using a separate source or drain depopulation approach. [6] Integrated circuit structure comprising: a first vertical array of nanowires, the first vertical array of nanowires comprising one or more dielectric nanowires coupled to a dielectric source or drain structure; a second vertical array of nanowires vertically overlying the first vertical array of nanowires, the second vertical array of nanowires comprising one or more semiconductor nanowires coupled to an epitaxial source or drain structure; and a gate stack above the second vertical array of nanowires. [7] The integrated circuit structure of claim 6, further comprising a dielectric plug laterally adjacent to and in contact with the source or drain dielectric structure. [8] The integrated circuit structure of claim 6 or 7, wherein the epitaxial source or drain structure comprises silicon, germanium and boron. [9] The integrated circuit structure of claim 6, 7 or 8, wherein the source or drain dielectric structure comprises silicon oxide, silicon nitride or silicon oxynitride. [10] The integrated circuit structure of claim 6, 7, 8 or 9, wherein the source or drain dielectric structure is formed using a separate source or drain depopulation approach. [11] Computing device comprising: a circuit board; and a component coupled to the board, the component including an integrated circuit structure comprising: a first vertical array of nanowires, the first vertical array of nanowires comprising one or more dielectric nanowires coupled to a dielectric source or drain structure; a first gate stack over the first vertical array of nanowires; a second vertical array of nanowires arranged laterally spaced from the first vertical array of nanowires, the second vertical array of nanowires comprising one or more semiconductor nanowires coupled to an epitaxial source or drain structure, the one or more semiconductor nanowires horizontally corresponding to the one or more dielectric nanowires, and the epitaxial source or drain structure being laterally spaced from the dielectric source or drain structure; and a second gate stack above the second vertical array of nanowires. [12] The computing device of claim 11, further comprising a dielectric plug laterally between and in contact with the epitaxial source or drain structure and the dielectric source or drain structure. [13] The computing device of claim 11 or 12, wherein the epitaxial source or drain structure and the dielectric source or drain structure are formed using a separate source or drain depopulation approach. [14] A computing device according to claim 11, 12 or 13, further comprising: a memory that is coupled to the circuit board. [15] A computing device according to claim 11, 12, 13 or 14, further comprising: a communication chip that is coupled to the circuit board. [16] A computing device according to claim 11, 12, 13, 14 or 15, further comprising: a camera that is coupled to the board. [17] A computing device according to claim 11, 12, 13, 14, 15 or 16, further comprising: a display coupled to the circuit board. [18] A computing device according to claim 11, 12, 13, 14, 15, 16 or 17, further comprising: a battery that is coupled to the circuit board. [19] The computing device of claim 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is an encapsulated integrated circuit die. [20] The computing device of claim 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communications chip and a digital signal processor.

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