DISPLAY DEVICE

Abstract

A display device (1000) can comprise a display panel (DP) having a plurality of pixels (PX); and a data driver circuit (400) configured to supply a data signal to the plurality of pixels (PX) via data lines. A gate driver circuit (GD) configured to supply a gate signal to the plurality of pixels (PX) via gate lines is arranged in the display panel (DP). The display panel (DP) has a drive layer (DRL) comprising a gate region (GIA) with the gate driver circuit (GD); and a pixel circuit layer comprising an active region (AA) with a pixel area (PXA) in which each of the plurality of pixels (PX) is arranged, and a non-active region (NA) surrounding the active region (AA).The pixel circuit layer includes a light-emitting diode (LD), a timing line (CLK) configured to supply a timing signal to the gate driver circuit (GD), and a shielding structure (SM) between the light-emitting diode (LD) and the timing line (CLK).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to Korean Patent Application No. 10-2023-0115320, filed on August 31, 2023, in the Korean Intellectual Property Office. BACKGROUND TECHNICAL AREA

[0002] The present disclosure relates to a display device. DISCUSSION OF THE RELATED TECHNOLOGY

[0003] With the advent of the information age, a display panel that visually expresses electrical information signals has been rapidly developed, and in response, various display devices with excellent performance, such as thinness, light weight, and low power consumption, have been developed. Examples of such display devices include a liquid crystal display (LCD), an organic light-emitting display (OLED), and the like.

[0004] Such a display device may include a display panel in which pixels are arranged to display images, and a drive circuit. The drive circuit includes a data driver configured to supply a data signal to the pixels through data lines, a gate driver configured to supply a gate signal to the pixels through gate lines, and a timing controller that controls the data driver and the gate driver. OVERVIEW

[0005] Accordingly, embodiments of the present disclosure are directed to a display device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

[0006] One aspect of the present disclosure is to provide a display device that minimizes or at least reduces a bezel area.

[0007] Another aspect of the present disclosure is to provide a display device implemented to have high resolution and large area.

[0008] Another aspect of the present disclosure is to provide a display device in which a distance between each signal line and / or a power supply line connected to a pixel is minimized or at least reduced and a simple design is ensured.

[0009] Additional features and aspects will be set forth in the following description, and in part will be apparent from the description or may be learned by practice of the inventive concepts provided herein. Other features and aspects of the inventive concepts may be realized and achieved by, or derived from, the structure particularly pointed out in the written description and the claims hereof, as well as the accompanying drawings.

[0010] To achieve these and other aspects of the inventive concepts as embodied and generally described herein, a display device is provided according to claim 1. Further embodiments are described in the dependent claims. In accordance with one aspect of the present disclosure, a display device may comprise a display panel having a plurality of pixels; and a data driver circuit configured to supply a data signal to the plurality of pixels through data lines, wherein a gate driver circuit configured to supply a gate signal to the plurality of pixels through gate lines is disposed in the display panel, the display panel comprising a drive layer having a gate region with the gate driver circuit;and a pixel circuit layer having an active region with a pixel region in which each of the plurality of pixels is arranged and a non-active region around the active region, and wherein the pixel circuit layer has a light-emitting diode, a timing line configured to supply a timing signal to the gate driver circuit, and a shield structure between the light-emitting diode and the timing line.;

[0011] Further details of the exemplary embodiments are included in the detailed description and drawings.

[0012] In the display device according to the exemplary embodiments of the present disclosure, a display panel may include a pixel circuit layer in which a pixel is arranged, and a driving layer in which a gate driver is arranged. Here, a gate region in which various elements constituting the gate driver are arranged may be configured to overlap at least a part of an active region in which various elements constituting the pixel are arranged. For example, transistors included in the driving layer may be arranged on the same layer as at least some of the transistors included in the pixel circuit layer.For example, the gate driver is arranged and formed on a gate region overlapping the active region, on the same layer as the pixel circuit layer in which a pixel is arranged, in a gate-in-matrix (GIA) manner, so that a bezel area of ​​the display device can be minimized or at least reduced.

[0013] Compared to the gate-in-panel (GIP) manner, in which the gate driver is configured to supply a gate signal to the pixels on the outside of the active area, the gate driver in the display device according to the exemplary embodiments of the present disclosure is arranged in at least a partial area of ​​the active area, for example, on the gate area, in the gate-in-matrix (GIA) manner. Therefore, the delay of the gate signal according to the relative position of the pixel is minimized or at least reduced, improving the luminance uniformity of the entire active area, so that the display device can be implemented with a high resolution and a large area with low power consumption.

[0014] Furthermore, in the display device according to the exemplary embodiments of the present disclosure, a seventh conductive layer disposed over the second planarization layer is arranged in a part of a fifth conductive layer that forms a timing line that supplies a timing signal to the gate driver and an anode electrode of the light-emitting diode, so as to function as a shielding structure that shields a signal. Therefore, display quality can be improved.

[0015] Furthermore, a pixel included in the display device according to the exemplary embodiments of the present disclosure has a vertical flip structure. Therefore, space can be secured for disposing a transistor, a capacitor, and the like constituting the gate driver on the gate region of the drive layer overlapping a central region of the pixel circuit layer.

[0016] Furthermore, in the display device according to the exemplary embodiments of the present disclosure, a third power supply line, a second scanning line, and an emission line included in a first conductive layer, and a fourth scanning line, a first scanning line, and a third scanning line included in a fourth conductive layer formed of a different metal material than the first conductive layer are alternately arranged along one direction (a second direction). Therefore, a distance between each signal line and / or a power supply line can be minimized or at least reduced. Accordingly, a simple design can be ensured.

[0017] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and, together with the description, serve to explain various principles. In the drawings: Fig. 1 is a block diagram illustrating a display device according to exemplary embodiments of the present disclosure; Fig. 2A is a view illustrating an example of a gate driver used in a display device of the Fig. 1 is included; Fig. Fig. 2B is a view illustrating another example of a gate driver used in a display device of the Fig. 1 is included; Fig. 3 is a circuit diagram showing an example of a circuit used in a display device of the Fig. 1 contained gate driver; Fig. 4 is a circuit diagram showing an example of a circuit used in a display device of the Fig. 1 contained pixel; Fig. 5 is a plan view illustrating a display device according to exemplary embodiments of the present disclosure; Fig. 6A is a view for explaining an example of an active region and a gate region used in a display device of the Fig. 5 are included; Fig. 6B is a view for explaining another example of an active region and a gate region used in a display device of the Fig. 5 are included; Fig. Fig. 7 is a cross-sectional view schematically illustrating an example of a display panel used in a display device of the Fig. 5 is included; Fig. 8 is a cross-sectional view showing an example of a display panel of the Fig. 7 represents; Fig. Fig. 9 is a layout illustrating an example of a pixel used in a display device of the Fig. 5 is included; and Fig. 10 is a cross-sectional view showing an example along line II' of Fig. 9 represents. DETAILED DESCRIPTION

[0019] Advantages and features of the present disclosure and a method for achieving the advantages and features will become apparent by reference to the exemplary embodiments described in detail below, together with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but may be implemented in various forms. The exemplary embodiments are provided by way of example only so that those skilled in the art can fully understand the disclosures of the present disclosure and the scope of the present disclosure.

[0020] The shapes, sizes, ratios, angles, numbers, and the like illustrated in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Like reference numerals generally designate like elements throughout the application. Furthermore, in the following description of the present disclosure, detailed explanation of known related technologies may be omitted in order not to unnecessarily obscure the subject matter of the present disclosure. The terms used herein, such as "comprising," "having," and "consisting of," are generally intended to permit the addition of other components unless the terms are used with the term "only." Any reference to the singular may include the plural unless expressly stated otherwise.

[0021] Components are interpreted to have a normal error range, even if this is not explicitly stated.

[0022] When the spatial relationship between two parts is described using terms such as "on", "over", "under" and "beside", one or more parts may be positioned between the two parts, unless the terms are used together with the term "immediate" or "direct".

[0023] When one element or layer is placed "on top of" another element or layer, another layer or element may be placed directly on top of the other element or in between.

[0024] Although the terms "first," "second," and the like are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from the other components. Therefore, a first component mentioned below may be a second component in a technical concept of the present disclosure.

[0025] The same reference numerals generally refer to the same elements throughout the application.

[0026] A size and a thickness of each component illustrated in the drawing are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the illustrated component.

[0027] The features of various embodiments of the present disclosure may be partially or fully coupled or combined with each other and may interact and operate in technically different ways, and the embodiments may be practiced independently of each other or in conjunction with each other.

[0028] Hereinafter, a display device according to exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0029] Fig. 1 is a block diagram illustrating a display device according to example embodiments of the present disclosure.

[0030] With reference to Fig. 1, a display device 1000 according to exemplary embodiments of the present disclosure may include a pixel unit 100, a gate driver GD (e.g., a gate driver circuit), a data driver 400 (e.g., a data driver circuit), and a timing controller 500. In an exemplary embodiment, a gate driver GD may include a scan driver 200 and an emission driver 300.

[0031] The display device 1000 can display images at different frame rates (a refresh rate, a drive frequency, or a screen refresh rate) depending on a drive condition. The frame rate is the frequency at which a data voltage is actually written to a drive transistor of a pixel PX for one second. The frame rate is also referred to, for example, as a screen scanning rate or screen refresh rate and indicates the frequency at which the screen is updated for one second.

[0032] In an exemplary embodiment, an output frequency of a scanning signal (e.g., a second scanning signal) supplied to a scanning line (e.g., the second scanning line) for supplying a data signal output frequency and / or a data signal of the data driver 400 may be changed in response to the frame rate. For example, if the frame rate is 120 Hz, the second signal may be supplied to each horizontal line (a pixel row) 120 times per second.

[0033] In an exemplary embodiment, the display device 1000 may adjust the output frequencies of the scanning driver 200 and the emission driver 300, and the output frequency of the data driver 400 in accordance with the driving condition. For example, the display device 1000 may display images at various frame frequencies from 1 Hz to 120 Hz. Here, the frame frequency may be adjusted based on a maximum frequency at which the scanning signal is supplied by a divider of the maximum frequency other than the maximum frequency itself. For example, the scanning signal may be supplied at a maximum of 240 Hz, and accordingly, the display device 1000 may display images at frame frequencies corresponding to dividers of 240 Hz, excluding 240 Hz.However, this is illustrative, and the display device 1000 may also display images at a frame rate (e.g., 240 Hz or 480 Hz) that is 120 Hz or higher.

[0034] Here, the display device 1000 can be operated at different frame rates. In the case of low-frequency driving, image defects such as flickering may be visible due to current leakage in the pixel. Furthermore, afterimages such as image distortion may be visible due to a change in the bias state of the drive transistor due to driving at different frame rates, or a change in response speed due to a threshold voltage shift, etc., caused by changes in the hysteresis characteristic.

[0035] To improve image quality, a frame period may include a plurality of non-emission periods and emission periods in accordance with the frame frequency. For example, a first non-emission period and an emission period of a frame may be defined as a first drive period and a subsequent non-emission period, and an emission period may be defined as a second drive period. For example, in the first drive period, to substantially display images in the first drive period, a data signal may be written to the pixel PX, and an on-bias voltage may be applied to the drive transistor of the pixel PX in the second drive period.

[0036] The pixel unit 100 may include scanning lines S11 to S1n, S21 to S2n, S31 to S3n, and S41 to S4n, emission control lines E1 to En, and data lines D1 to Dm, and pixels PX connected to the scanning lines S11 to S1n, S21 to S2n, S31 to S3n, and S41 to S4n, the emission control lines E1 to En, and the data lines D1 to Dm (where m and n are integers greater than 0). Each pixel PX may include a drive transistor and a plurality of switching transistors.

[0037] A pixel PX of pixels PX arranged in an i-th row and a j-th column may be connected to a corresponding first scan line (e.g., an i-th first scan line S1i) of first scan lines S11 to S1n, a corresponding second scan line (e.g., an i-th second scan line S2i) of second scan lines S21 to S2n, a corresponding third scan line (e.g., an i-th third scan line S3i) of third scan lines S31 to S3n, a corresponding fourth scan line (e.g., an i-th fourth scan line S4i) of fourth scan lines S41 to S4n, a corresponding emission control line (e.g., an i-th emission control line Ei) of emission control lines E1 to En, and a corresponding data line (e.g., a j-th data line Dj) of data lines D1 to Dm (where i and j are integers greater than 0).

[0038] The pixels PX can be supplied with a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage VINIT (for example, a first initialization voltage), a fourth power supply voltage VAR (for example, a second initialization voltage), and a fifth power supply voltage VOBS (for example, a bias voltage).

[0039] A voltage level of the second power supply voltage VSS may be lower than a voltage level of the first power supply voltage VDD. For example, the first power supply voltage VDD may be a positive voltage, and the second power supply voltage VSS may be a negative voltage.

[0040] The third power supply voltage VINIT (e.g., first initialization voltage) and the fourth power supply voltage VAR (e.g., second initialization voltage) are initialization voltages that initialize the pixel PX, and, for example, the driving transistor and / or the light-emitting diode included in the pixel PX can be initialized by the initialization voltage.

[0041] The fifth power supply voltage VOBS (e.g., bias voltage) may be a voltage for supplying a predetermined bias voltage to the source electrode and / or the drain electrode of the driving transistor included in the pixel PX. For example, the fifth power supply voltage VOBS may be a positive voltage. However, a voltage level of the fifth power supply voltage VOBS is not limited to this, and the fifth power supply voltage VOBS may be set as a negative voltage. In the exemplary embodiments of the present disclosure, signal lines connected to the pixel PX may be set in various ways in accordance with a circuit structure of the pixel PX.

[0042] Timing controller 500 can receive first data DATA1 (e.g., input image data) and an input control signal CS from a host system through a predetermined interface. Timing controller 500 can control the drive timings of scan driver 200, emission driver 300, and data driver 400.

[0043] Timing controller 500 may generate a first control signal SCS, a second control signal ECS, and a third control signal DCS based on the first data DATA1 and the input control signal CS. For example, the input control signal CS may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a timing signal. The first control signal SCS may be supplied to scan driver 200, the second control signal ECS may be supplied to emit driver 300, and the third control signal DCS may be supplied to data driver 400. Timing controller 500 realigns the first data DATA1 to generate the second data DATA2 and supply the second data to data driver 400.

[0044] The scan driver 200 receives a first control signal SCS (e.g., a scan control signal) from the timing controller 500. The scan driver 200 may supply a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to the first scan lines S11 to S1n, the second scan lines S21 to S2n, the third scan lines S31 to S3n, and the fourth scan lines S41 to S4n in an associated manner based on the first control signal SCS.

[0045] The first sensing signal to the fourth sensing signal may be set as a gate on-voltage (e.g., a low voltage or a high voltage) according to a type of transistor to which the respective sensing signals are supplied. The transistor receiving the sensing signal may be set to an on-state when the sensing signal is supplied. For example, a gate on-voltage of a sensing signal supplied to a P-channel metal oxide semiconductor (PMOS) transistor may be a logic low level, and a gate on-voltage of a sensing signal supplied to an N-channel metal oxide semiconductor (NMOS) transistor may be a logic high level. Hereinafter, "sensing signal is supplied" means that the sensing signal is supplied at a logic level that turns on the transistor controlled by the sensing signal.

[0046] The emission driver 300 may supply an emission control signal to emission control lines E1 to En based on a second control signal ECS (e.g., an emission drive control signal). For example, the emission control signal may be supplied sequentially to the emission control lines E1 to En.

[0047] The emission control signal may be set as a gate-off voltage (e.g., a high voltage). A transistor receiving the emission control signal may be turned off when the emission control signal is applied, and may be turned on in other cases. Hereinafter, the meaning of "emission control signal is applied" means that the emission control signal is applied at a logic level that turns off the transistor controlled by the emission control signal.

[0048] For convenience of description, Fig. 1 illustrates that the scan driver 200 and the emission driver 300 are each individual structures, however, the present disclosure is limited thereto. Depending on the configuration, the scan driver 200 may include a plurality of scan drivers configured to supply at least one of the first scan signal to the fourth scan signal. Furthermore, at least some of the scan drivers 200 and the emission driver 300 may be integrated as a drive circuit or module.

[0049] The data driver 400 may receive a third control signal DCS (e.g., a data control signal) and second data DATA2 (e.g., image data) from the timing controller 500. The data driver 400 may convert a digital type of second data DATA2 into an analog data signal (e.g., a data voltage). The data driver 400 may supply the data signal to the data lines D1 to Dm in response to the third control signal DCS. At this time, the data signal supplied to the data lines D1 to Dm may be supplied in such a way that it is synchronized with the second scanning signal supplied to the second scanning lines S21 to S2n.

[0050] Here, the normal gate driver is formed independently of the display panel such that it is electrically connected to the display panel in various ways. However, in the display device according to the exemplary embodiments of the present disclosure, the gate driver GD, for example, the scanning driver 200 and the emission driver 300, are formed during the manufacture of a substrate of a display panel such that it is formed on at least a partial region (for example, a gate region GIA (see Fig. 5)) of the active area AA (see Fig. 5) of the display panel is formed in the form of a gate-in-matrix arrangement.

[0051] This will be explained below with reference to Fig. 1 to Fig. 5 are described in more detail.

[0052] Fig. 2A is a view illustrating an example of a gate driver used in a display device of the Fig. 1 is included. Fig. Fig. 2B is a view illustrating another example of a gate driver used in a display device of the Fig. 1 is included.

[0053] With reference to Fig. 1 and Fig. 2A, the gate driver GD may include a scan driver 200 and an emission driver 300, and the scan driver 200 may include a first scan driver 210, a second scan driver 220, a third scan driver 230, and a fourth scan driver 240. The first control signal SCS (e.g., a scan control signal) may include a first scan start signal SST1 through a fourth scan start signal SST4. The first scan start signal SST1 through a fourth scan start signal SST4 may be supplied to the first through fourth scan drivers 210, 220, 230, and 240.

[0054] The widths and supply timings of the first scanning start signal SST1 to the fourth scanning start signal SST4 may be set according to a driving condition and a frame rate of the pixel PX. The first scanning signal to the fourth scanning signal may be output based on the first scanning start signal SST1 to the fourth scanning start signal SST4. For example, a signal width of at least one of the first scanning signal to the fourth scanning signal may be different from a signal width of the others.

[0055] The first scanning driver 210 can sequentially supply the first scanning signal to the first scanning lines S11 to S1n in response to the first scanning start signal SST1. The second scanning driver 220 can sequentially supply the second scanning signal to the second scanning lines S21 to S2n in response to the second scanning start signal SST2. The third scanning driver 230 can sequentially supply the third scanning signal to the third scanning lines S31 to S3n in response to the third scanning start signal SST3. The fourth scanning driver 240 can sequentially supply the fourth scanning signal to the fourth scanning lines S41 to S4n in response to the fourth scanning start signal SST4.

[0056] Furthermore, the second control signal ECS (e.g., an emission control signal) may include an emission start signal EST. The emission start signal EST may be supplied to the emission driver 300.

[0057] A width and supply timing of the emission start signal EST may be determined according to a driving condition and a frame rate of the pixel PX. The emission signal may be output based on the emission start signal EST. The emission driver 300 may sequentially supply the emission signal to the emission control lines E1 to En in response to the emission start signal EST.

[0058] Although in Fig. 2A, a second scan driver 220 supplies second scan signals through second scan lines S21 to S2n connected to the respective pixels PX arranged in all rows (or all horizontal lines), the exemplary embodiments of the present disclosure are not limited thereto.

[0059] For example, with reference to Fig. 2B, pixels PX_1 included in the pixel unit 100_1 are divided into pixels PX_Odd arranged in odd-numbered rows, for example, in i-th rows, and pixels PX_Even arranged in even-numbered rows, for example, in i+1-th rows (where i is an odd natural number).

[0060] Here, a pixel PX_Odd arranged in a j-th column of pixels PX_Odd arranged in the odd-numbered row, for example, the i-th row, may be connected to a corresponding first scanning line (for example, an i-th first scanning line S1i) of first scanning lines S11 to S1n, a corresponding first sub-scanning line (for example, a k-th first sub-scanning line S2ka) of first sub-scanning lines S21a to S2pa as a second scanning line, a corresponding third scanning line (for example, an i-th third scanning line S3i) of third scanning lines S31 to S3n, a corresponding fourth scanning line (for example, an i-th fourth scanning line S4i) of fourth scanning lines S41 to S4n, a corresponding emission control line (for example, an i-th emission control line Ei) of emission control lines E1 to En,and a corresponding data line (for example, a j-th data line Dj) of data lines D1 to Dm (in this case, 2p is equal to n, and 2k is equal to i+1).

[0061] Furthermore, a pixel PX_Even arranged in a j-th column of pixels PX_Even arranged in the even-numbered row, for example, the i+1-th row, may be connected to a corresponding first scanning line (for example, an i+1-th first scanning line S1i+1) of first scanning lines S11 to S1n, a corresponding second sub-scanning line (for example, a k-th second sub-scanning line S2kb) of second sub-scanning lines S21b to S2pb as a second scanning line, a corresponding third scanning line (for example, an i+1-th third scanning line S3i+1) of third scanning lines S31 to S3n, a corresponding fourth scanning line (for example, an i+1-th fourth scanning line S4i+1) of fourth scanning lines S41 to S4n,a corresponding emission control line (for example, an i+1-th emission control line Ei+1) of emission control lines E1 to En and a corresponding data line (for example, a j-th data line Dj) of data lines D1 to Dm.

[0062] The first control signal SCS (e.g., a sampling control signal) may include a first sampling start signal through a fourth sampling start signal SST1, SST2_1, SST3, and SST4. The first sampling start signal through a fourth sampling start signal SST1, SST2_1, SST3, and SST4 may be supplied in a dedicated manner to the first sampling driver through the fourth sampling driver 210, 220_1, 230, and 240. Here, the second sampling start signal SST2_1 may include a first sub-sampling start signal SST2a and a second sub-sampling start signal SST2b.

[0063] The gate driver GD_1 may include a scan driver 200_1 and an emission driver 300, and the scan driver 200_1 may include a first scan driver 210, a second scan driver 220_1, a third scan driver 230, and a fourth scan driver 240. In an exemplary embodiment, the second scan driver 220_1 may include a first sub-scan driver 221 and a second sub-scan driver 222.

[0064] The first sub-scan driver 221 of the second scan driver 220 may sequentially supply a first sub-scan signal to the first sub-scan lines S21a to S2pa in response to a first sub-scan start signal SST2a. Further, the second sub-scan driver 222 of the second scan driver 220 may sequentially supply a second scan signal to the second sub-scan lines S21b to S2pb in response to a second sub-scan start signal SST2b.

[0065] As described above, in the display device 1000 according to the exemplary embodiments of the present disclosure, the second scanning driver 220_1 included in the scanning driver 200_1 may also be configured to be divided into a first sub-scanning driver 221 and a second sub-scanning driver 222. The first sub-scanning driver 221 supplies second scanning signals (e.g., first sub-scanning signals) to pixels PX_Odd arranged in odd-numbered rows, and the second sub-scanning driver 222 supplies second scanning signals (e.g., second sub-scanning signals) to pixels PX_Even arranged in even-numbered rows.

[0066] Hereinafter, for the convenience of description, unless otherwise stated, the description will be based on a second scanning driver 220 provided via second scanning lines S21 to S2n connected to each of the pixels PX arranged in each row (or each horizontal line), as shown in Fig. 2A, supplies second scanning signals.

[0067] Fig. 3 is a circuit diagram illustrating an example of a gate driver used in a display device of the Fig. 1 is included.

[0068] Here, Fig. 3 is a circuit diagram illustrating, among emission stages included in the emission driver 300 between the scan driver 200 and the emission driver 300 included in the gate driver GD, an example of an emission stage configured to supply an emission control signal (e.g., an i-th emission control signal EMi) to pixels PX arranged in an i-th row.

[0069] With reference to Fig. 1 and Fig. 3, the emission stage included in the emission driver 300 may receive an input signal INP (e.g., an emission start signal EST or a previous emission control signal (e.g., an i-1th emission control signal EMi-1)) and an emission timing signal ECLK. The emission stage may receive a first drive power supply voltage VEH and a second drive power supply voltage VEL.

[0070] A voltage level of a second drive power supply voltage VEL may be lower than a voltage level of the first drive power supply voltage VEH. For example, the first drive power supply voltage VEH may be a positive voltage, and the second drive power supply voltage VEL may be a negative voltage. However, these are only illustrative, and the exemplary embodiments of the present disclosure are not limited thereto.

[0071] In an exemplary embodiment, the emission stage may generate and output an i-th emission control signal EMi based on an input signal INP, an emission timing signal ECLK, a first drive power supply voltage VEH, and a second drive power supply voltage VEL.

[0072] For this purpose, the emission stage may comprise first-stage transistor M1 to seventh-stage transistor M7, a first capacitor CB, a second capacitor CQB and a third capacitor C_ON.

[0073] Here, a transistor is a three-electrode element that has a gate electrode, a source electrode, and a drain electrode. The source electrode is an electrode designed to supply charge carriers to the transistor. In the transistor, charge carriers start flowing from the source electrode. The drain electrode is an electrode through which the charge carriers are discharged from the transistor to the outside. Accordingly, in the MOSFET, the charge carrier flows from the source electrode to the drain electrode. In the case of the n-type MOSFET (NMOS), since the charge carriers are electrons, in order for the electrons to flow from the source electrode to the drain electrode, a voltage of the source electrode is lower than a voltage of the drain electrode. In the n-type MOSFET, since the charge carriers are electrons, in order for the electrons to flow from the source electrode to the drain electrode, the current flows from the drain electrode to the source electrode.In the case of the p-type MOSFET (PMOS), since the carriers are holes, a voltage of the source electrode is higher than a voltage of the drain electrode so that the holes can flow from the source electrode to the drain electrode. In the p-type MOSFET, since the holes flow from the source electrode to the drain electrode, the current flows from the source electrode to the drain electrode. However, it should be noted that the source electrode and the drain electrode of the MOSFET are not fixed. For example, the source electrode and the drain electrode of the MOSFET may be swapped depending on the applied voltage. In the following exemplary embodiment, the present disclosure should not be limited by the source electrode and the drain electrode of the transistor.

[0074] In an exemplary embodiment, the stage transistors forming the gate driver GD may be p-type MOSFET (PMOS) transistors or low-temperature polycrystalline silicon (LTPS) thin-film transistors. For example, the first-stage transistor M1 through the seventh-stage transistor M7 forming the emission stage included in the emission driver 300 may be PMOS LTPS thin-film transistors.

[0075] The first-stage transistor M1 is connected between a power supply terminal (hereinafter referred to as "second power supply terminal") to which the second drive power supply voltage VEL is supplied and an output terminal from which the i-th emission control signal EMi is output, and may have a gate electrode connected to a Q node Q. The first-stage transistor M1 may be turned on or off based on a voltage of the Q node Q.

[0076] For example, the first-stage transistor M1 is turned on when a voltage of the Q node Q has a gate-on level (e.g., a low level), such that the second power supply terminal to which the second drive power supply voltage VEL is supplied and an output terminal to which the i-th emission control signal EMi is output are electrically connected. For example, in a portion where the first-stage transistor M1 is turned on, the i-th emission control signal EMi may have a gate-on level (e.g., a low level).

[0077] The second-stage transistor M2 is connected between a power supply terminal (hereinafter "first power supply terminal") to which the first drive power supply voltage VEH is supplied and an output terminal from which the i-th emission control signal EMi is output, and may have a gate electrode connected to a QB node QB. The second-stage transistor M2 can be turned on or off based on a voltage of the QB node QB.

[0078] For example, the second-stage transistor M2 is turned on when a voltage of the QB node QB has a gate-on level (e.g., a low level), such that the first power supply terminal to which the first drive power supply voltage VEH is supplied and an output terminal to which the i-th emission control signal EMi is output are electrically connected. For example, in a portion where the second-stage transistor M2 is turned on, the i-th emission control signal EMi may have an off level (e.g., a high level).

[0079] As described above, the first-stage transistor M1 of the emission stage can perform a pull-up function, and the second-stage transistor M2 can perform a pull-down function.

[0080] The third-stage transistor M3 is connected between an input terminal (hereinafter referred to as the "first input terminal") to which the input signal INP is input, and the second control node Q2. The third-stage transistor M3 may include a gate electrode connected to an input terminal (hereinafter referred to as the "second input terminal") to which the emission timing signal ECLK is applied. The third-stage transistor M3 is turned on when the timing signal ECLK supplied via the second input terminal has a gate-on level (for example, a low level), such that the first input terminal and the second control node Q2 are electrically connected. When the third-stage transistor M3 is turned on, the input signal INP supplied via the first input terminal may be supplied to the second control node Q2.

[0081] The fourth-stage transistor M4 is connected between the first power supply terminal, to which the first drive power supply voltage VEH is supplied, and the first control node Q1, and may have a gate electrode connected to the first power supply terminal to which the input signal INP is input. The fourth-stage transistor M4 is turned on when the input signal INP supplied through the first input terminal has a gate-on level (for example, a low level), such that the first power supply terminal and the first control node Q1 are electrically connected. When the fourth-stage transistor M4 is turned on, the first drive power supply voltage VEH having a high level supplied through the first power supply terminal may be supplied to the first control node Q1.

[0082] The third capacitor C_ON may be connected between the second input terminal, to which the emission timing signal ECLK is supplied, and the first control node Q1. For example, the third capacitor C_ON may have a first electrode connected to the second input terminal and a second electrode connected to the first control node Q1.

[0083] The third capacitor C_ON can maintain a voltage between the second input terminal and the first control node Q1. Therefore, the third capacitor C_ON can boost the voltage level of the first control node Q1 in response to the voltage level change of the emission timing signal ECLK supplied through the second input terminal.

[0084] The fifth-stage transistor M5 is connected between the second input terminal, to which the emission timing signal ECLK is supplied, and the QB node QB, and may include a gate electrode connected to the first control node Q1. The fifth-stage transistor M5 may be turned on or off in response to a voltage level of the first control node Q1. When the fifth-stage transistor M5 is turned on, the emission timing signal ECLK supplied via the second terminal may be supplied to the QB node QB.

[0085] The sixth-stage transistor M6 is connected between the first input terminal, to which the first drive power supply voltage VEH is supplied, and the QB node QB, and may have a gate electrode connected to the second control node Q2. The sixth-stage transistor M6 may be turned on or off in response to the voltage level of the second control node Q2. When the sixth-stage transistor M6 is turned on, the first drive power supply voltage VEH at a high level, supplied through the first power supply terminal, may be supplied to the QB node QB.

[0086] The seventh-stage transistor M7 is connected between the second control node Q2 and the Q node Q and may have a gate electrode connected to the second power supply terminal to which the second drive power supply voltage VEL is supplied. Here, the second drive power supply voltage VEL has a low voltage level, so that the seventh-stage transistor M7 can always maintain an on-state, and the second control node Q2 and the Q node Q can maintain an electrically connected state.

[0087] The first capacitor CB (or a boost capacitor) may be connected between the Q node Q and the output terminal. For example, the first capacitor CB may have a first electrode connected to the Q node Q and a second electrode connected to the output terminal.

[0088] The second capacitor CQB may be connected between the first power supply terminal and the QB node QB. For example, the second capacitor CQB may have a first electrode connected to the first power supply terminal and a second electrode connected to the QB node QB. Here, one electrode (for example, a first electrode) of the second capacitor CQB is connected to the first power supply terminal, to which the first drive power supply voltage VEH, which is a constant current source, is supplied, so that the second capacitor CQB can charge a voltage applied to the QB node QB and stably maintain a voltage of the QB node QB.

[0089] Fig. 4 is a circuit diagram illustrating an example of a pixel used in a display device of the Fig. 1 is included.

[0090] In Fig. 4, for the convenience of description, a pixel PX will be shown that is located in an i-th horizontal line (or an i-th pixel row) and is connected to a j-th data line Dj (where i and j are integers greater than 0). Here, the Fig. 4 may be substantially the same as the pixel PX described with reference to Fig. 1 was described.

[0091] With reference to Fig. 1 and Fig. 4, the pixel PX may comprise a light-emitting diode LD, a drive transistor DT, a first transistor T1 to a seventh transistor T7, and a storage capacitor Cst.

[0092] A first electrode (e.g., an anode electrode) of the light-emitting diode LD may be connected to a fourth node N4 (or a second electrode of a fourth transistor T4), and a second electrode (e.g., a cathode electrode) may be connected to a second power supply line PL2 that transmits a second power supply voltage VSS. The light-emitting diode LD may generate light with a predetermined luminance in response to a current amount (a drive current) supplied by the drive transistor DT.

[0093] The second power supply line PL2 may be a conductive type, but is not limited to this. For example, the second power supply line PL2 may be a conductive plate type or a conductive layer.

[0094] In one exemplary embodiment, the light-emitting diode LD may be an organic light-emitting diode having an organic emission layer. In another exemplary embodiment, the light-emitting diode LD may be an inorganic light-emitting diode formed with an inorganic material, such as a micro light-emitting diode (LED) or a quantum dot light-emitting diode. In another exemplary embodiment, the light-emitting diode LD may be a light-emitting diode in which an organic material and an inorganic material are mixed.

[0095] Although in Fig. While the pixel PX includes a single light-emitting diode LD in FIG. 4, according to another exemplary embodiment, the pixel PX includes a plurality of light-emitting diodes, and the plurality of light-emitting diodes may be connected in series, parallel, or serial-parallel to each other. For example, in the light-emitting diode LD, the plurality of light-emitting diodes (e.g., organic light-emitting diodes and / or inorganic light-emitting diodes) may be connected in series, parallel, or serial-parallel between the second power supply line PL2 and the fourth node N4.

[0096] The first electrode (e.g., a source electrode) of the drive transistor DT may be connected to the first node N1, and the second electrode (e.g., a drain electrode) may be connected to the second node N2. The gate electrode of the drive transistor DT may be connected to the third node N3. The drive transistor DT may, in response to the voltage of the third node N3, e.g., the gate electrode voltage, control a drive current (e.g., an amount of drive current) flowing from the first power supply line PL1 configured to supply the first drive voltage VDD, via the light-emitting diode LD to the second power supply line PL2 configured to supply the second drive voltage VSS. For this purpose, the first power supply voltage VDD may be set to be higher than the second power supply voltage VSS.For example, the first power supply voltage VDD may be a positive voltage, and the second power supply voltage VSS may be a negative voltage.

[0097] The first transistor T1 may be connected between the second electrode (e.g., the second node N2) and the gate electrode (e.g., the third node N3) of the driving transistor DT. For example, the first electrode (e.g., a drain electrode) of the first transistor T1 may be connected to the second node N2, and the second electrode (e.g., a source electrode) may be connected to the third node N3. The gate electrode of the first transistor T1 may be connected to the i-th first scanning line S1i. When the first scanning signal is supplied to the i-th first scanning line S1i, the first transistor T1 is turned on such that the second electrode and the gate electrode of the driving transistor DT (e.g., the second node N2 and the third node N3) are electrically connected.For example, the timing of connecting the second electrode (e.g., the drain electrode) and the gate electrode of the drive transistor DT can be controlled by the first sensing signal. When the first transistor T1 is turned on, the drive transistor DT can be switched into a diode-like configuration.

[0098] The second transistor T2 may be connected between a j-th data line Dj and the first node N1. For example, the first electrode (e.g., a source electrode) of the second transistor T2 may be connected to the j-th data line Dj, and the second electrode (e.g., a drain electrode) may be connected to the first node N1. The gate electrode of the second transistor T2 may be connected to the i-th second scan line S2i. When the second scan signal is supplied to the i-th second scan line S2i, the second transistor T2 is turned on, such that the j-th data line Dj and the first node N1 are electrically connected.

[0099] The third transistor T3 may be connected between the first power supply line PL1 and the first node N1. For example, the first electrode (e.g., a source electrode) of the third transistor T3 may be connected to the first power supply line PL1, and the second electrode (e.g., a drain electrode) may be connected to the first node N1. The gate electrode of the third transistor T3 may be connected to the i-th emission control line Ei. When the emission control signal is supplied to the i-th emission control line Ei, the third transistor T3 may be turned off, and may otherwise be turned on. When the third transistor T3 is turned on, the first node N1 may be electrically connected to the first power supply line PL1.

[0100] The fourth transistor T4 may be connected between the second electrode (e.g., a second node N2) of the driving transistor DT and the first electrode (e.g., the fourth node N4) of the light-emitting diode LD. For example, the first electrode (e.g., a source electrode) of the fourth transistor T4 may be connected to the second node N2, and the second electrode (e.g., a drain electrode) may be connected to the fourth node N4. The gate electrode of the fourth transistor T4 may be connected to the i-th emission control line Ei. The fourth transistor T4 may be controlled in substantially the same manner as the third transistor T3. When the fourth transistor T4 is turned on, the second node N2 and the fourth node N4 may be electrically connected.

[0101] In Fig. Figure 4 shows that the third transistor T3 and the fourth transistor T4 are connected to the same emission control line (e.g., the i-th emission control line Ei), but this is illustrative, and the present disclosure is not limited thereto. For example, the third transistor T3 and the fourth transistor T4 may each be connected to separate emission control lines to which different emission control signals are supplied.

[0102] The fifth transistor T5 may be connected between the third node N3 (e.g., the gate electrode of the drive transistor DT) and the third power supply line PL3, which is configured to supply the third supply voltage VINIT (hereinafter referred to as "first initialization voltage"). For example, the first electrode (e.g., a drain electrode) of the fifth transistor T5 may be connected to the third power supply line PL3, and the second electrode (e.g., a source electrode) may be connected to the third node N3. The gate electrode of the fifth transistor T5 may be connected to the i-th fourth scan line S4i. When the fourth scan signal is supplied to the i-th fourth scan line S4i, the fifth transistor T5 is turned on, such that the first initialization voltage VINIT is supplied to the third node N3.Here, the first initialization voltage VINIT may be set to be lower than a lowest level of the data signal DATA supplied to the j-th data line Dj. The fifth transistor T5 is turned on by supplying the fourth strobe signal, such that a voltage of the gate electrode (or the third node N3) of the drive transistor DT is initialized to the first initialization voltage VINIT.

[0103] The sixth transistor T6 may be connected between the first electrode (or the fourth node N4) of the light-emitting diode LD and the fourth power supply line PL4, which is configured to supply the fourth supply voltage VAR (hereinafter referred to as a "second initialization voltage"). For example, the first electrode (e.g., a source electrode) of the sixth transistor T6 may be connected to the fourth power supply line PL4, and the second electrode (e.g., a drain electrode) may be connected to the fourth node N4. The gate electrode of the sixth transistor T6 may be connected to the i-th third scanning line S3i. When the third scanning signal is supplied to the i-th third scanning line S3i, the sixth transistor T6 is turned on, such that the second initialization voltage VAR is supplied to the fourth node N4 (e.g., a first electrode of the light-emitting diode LD).

[0104] In an exemplary embodiment, when the third scanning signal is supplied, the second initialization voltage VAR can be supplied to the first electrode of the light-emitting diode LD by means of the turned-on sixth transistor T6. In this case, the parasitic capacitor of the light-emitting diode LD can be discharged. As described above, since a residual voltage charged in the parasitic capacitor of the light-emitting diode LD is discharged (removed), unintentional micro-light emission can be suppressed. Accordingly, the ability of the pixel PX to display black image content can be improved.

[0105] Here, a voltage level of the first initialization voltage VINIT and a voltage level of the second initialization voltage VAR may be different from each other. For example, a voltage that initializes the third node N3 and a voltage that initializes the fourth node N4 may be set to be different from each other.

[0106] When the first initialization voltage VINIT supplied to the third node N3 is significantly low during low-frequency driving where a frame period length is increased, a strong on-bias is applied to the driving transistor DT, so that a threshold voltage of the driving transistor DT may be shifted in the corresponding frame period. Such a hysteresis characteristic may cause flickering during low-frequency driving. Accordingly, in the display device driven at the low frequency, the first initialization voltage VINIT higher than the second power supply voltage VSS may be required.

[0107] However, when a voltage level of the second initialization voltage VAR supplied to the fourth node N4 for initializing the light-emitting diode LD is higher than a predetermined reference value, the voltage of the parasitic capacitor of the light-emitting diode LD cannot be discharged but can be charged. Accordingly, the voltage level of the second initialization voltage VAR should be sufficiently low such that the voltage of the parasitic capacitor of the light-emitting diode LD is discharged. For example, taking into account the threshold voltage of the light-emitting diode LD, a voltage level of the second initialization voltage VAR can be set to be lower than the sum of the threshold voltage of the light-emitting diode LD and the second power supply voltage VSS.

[0108] However, this is illustrated so that the voltage level of the first initialization voltage VINIT and the voltage level of the second initialization voltage VAR can be set to different levels. For example, the voltage level of the first initialization voltage VINIT and the voltage level of the second initialization voltage VAR can be substantially the same.

[0109] The seventh transistor T7 may be connected between the first node N1 (or the first electrode of the drive transistor DT) and a fifth power supply line PL5 configured to supply a fifth power supply voltage VOBS (hereinafter referred to as "bias"). For example, the first electrode (e.g., a source electrode) of the seventh transistor T7 may be connected to the fifth power supply line PL5, and the second electrode (e.g., a drain electrode) may be connected to the first node N1. The gate electrode of the seventh transistor T7 may be connected to the i-th third scan line S3i.

[0110] When the third scanning signal is supplied to the i-th third scanning line S3i, the seventh transistor T7 is turned on, so that the bias voltage VOBS is supplied to the first node N1. In an exemplary embodiment, the bias voltage VOBS may have a level similar to a voltage level of a black grayscale data signal DATA. For example, the bias voltage VOBS may have a voltage level of approximately 5 to 7 V, however, this is illustrative, and the voltage level of the bias voltage VOBS is not limited thereto.

[0111] Accordingly, the seventh transistor T7 is turned on, such that a predetermined high voltage is applied to the first electrode (e.g., a source electrode) of the drive transistor DT. Here, when the first transistor T1 is in an on-state, the drive transistor DT may be in an on-bias state (a state in which it is to be turned on) (e.g., such that it has an on-bias).

[0112] Here, the bias voltage VOBS is periodically supplied to the first node N1, the bias state of the drive transistor DT is periodically changed, and a threshold voltage of the drive transistor DT can be changed. Accordingly, the characteristics of the drive transistor DT can be prevented from being fixed to a specific state during low-frequency driving, resulting in deterioration.

[0113] The storage capacitor Cst may be connected between the first power supply line PL1 and the third node N3. One electrode of the storage capacitor Cst is connected to the first power supply line PL1, so that a first power supply voltage VDD, which is a constant voltage, can be continuously supplied to one electrode of the storage capacitor Cst. Accordingly, a voltage of the third node N3 cannot be affected by other parasitic capacitors and can be maintained at a voltage level of a voltage directly supplied to the third node N3. For example, the storage capacitor Cst can store a voltage applied to the third node N3.

[0114] In an exemplary embodiment, a pixel PX may include four p-type PMOS transistors comprising polysilicon semiconductor layers and four n-type NMOS transistors comprising oxide semiconductor layers.

[0115] For example, the drive transistor DT, the second transistor T2, the third transistor T3, and the fourth transistor T4 may be formed by polysilicon semiconductor transistors. For example, the drive transistor DT, the second transistor T2, the third transistor T3, and the fourth transistor T4 may include polysilicon semiconductor layers formed by a low-temperature polysilicon (LTPS) process as active layers (channels). Furthermore, the drive transistor DT, the second transistor T2, the third transistor T3, and the fourth transistor T4 may be polysilicon semiconductor transistors. Therefore, a gate-on voltage that turns on the drive transistor DT, the second transistor T2, the third transistor T3, and the fourth transistor T4 may be a logic low level.

[0116] The polysilicon semiconductor transistor has an advantage in terms of fast response speed, so that it can be used in a switching element that requires fast switching.

[0117] The first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be formed by oxide semiconductor transistors. For example, the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be N-type oxide semiconductor transistors (e.g., NMOS transistors) and may have oxide semiconductor layers as active layers. Therefore, a gate on voltage that turns on the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a logic high level.

[0118] The oxide semiconductor transistor can be processed at low temperatures and has lower charge mobility than the polysilicon semiconductor transistor. For example, the oxide semiconductor transistor has excellent off-current characteristics.

[0119] However, the drive transistor DT and the first transistor T1 to the seventh transistor T7 are not limited thereto. Therefore, at least one of the drive transistor DT, the second transistor T2, the third transistor T3, and the fourth transistor T4 may be formed as an oxide semiconductor transistor. Furthermore, at least one of the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be formed as a polysilicon semiconductor transistor.

[0120] Fig. 5 is a plan view illustrating a display device according to exemplary embodiments of the present disclosure. Fig. 6A is a view for explaining an example of an active region and a gate region used in a display device of the Fig. 5 are included. Fig. 6B is a view for explaining another example of an active region and a gate region used in a display device of the Fig. 5 are included. Fig. Fig. 7 is a cross-sectional view schematically illustrating an example of a display panel used in a display device of the Fig. 5 is included.

[0121] To avoid redundant description, mainly contents are described that do not correspond to the description in relation to Fig. 1 to Fig. 4 overlap. A part that is not specifically described follows the exemplary embodiment described above, and the same reference numeral denotes the same component.

[0122] In relation to Fig. 5, a display device 1000 according to exemplary embodiments of the present disclosure may include a display panel DP, a plurality of pixels PX, a gate driver GD, and a data driver (DD) 400. In an exemplary embodiment, the display device 1000 may further include a printed circuit board PCB and a connection film COF.

[0123] The display panel DP may have an active area AA and a non-active area NA surrounding the active area AA. For example, the display panel DP may have a substrate divided into an active area AA and a non-active area NA.

[0124] The active area AA may be an area where images are displayed. A plurality of pixels PX may be arranged on the active area AA. Each pixel PX may include a display element and various drive elements for driving the display element. For example, various drive elements may include at least one thin-film transistor (TFT) and one capacitor. Furthermore, the pixels PX may each be connected to various wiring lines. For example, each of the pixels PX may be connected to various wiring lines, such as a gate line (e.g., a scanning signal line or an emission signal line), a data line, and a power supply line.

[0125] The active area AA may be provided in various shapes. For example, the active area AA of the display device 1000 may be provided to have a rectangular shape with two pairs of parallel sides, but the exemplary embodiments of the present disclosure are not limited to this. According to the exemplary embodiment, the active area AA provided in a rectangular shape may have a rounded corner in which a longer side and a shorter side contact each other. However, the exemplary embodiments are not limited to this, so the active area AA may have a square shape, a polygonal shape, or a circular shape.

[0126] For the convenience of description, although in Fig. As shown in Figure 5, the active area AA has a rectangular shape with rounded corners, and a direction parallel to one pair of sides of the active area AA is a first direction DR1, and a direction parallel to the other pair of sides is a second direction DR2. A normal direction of the active area AA, for example, the thickness direction of the display device 1000, may be defined as a third direction DR3.

[0127] The front (or top) and rear (or bottom) sides of components or units of the display device 1000 to be described below can be distinguished by the third direction DR3. However, the first direction through third direction DR1, DR2, and DR3 shown in the application are illustrative, and the first direction through third direction DR1, DR2, and DR3 are relative concepts, so they are converted to other directions. Hereinafter, for convenience of description, the same reference numerals refer to the first direction through third direction DR1, DR2, and DR3.

[0128] Here, when it is referred to as “overlapping” in the present disclosure, it means that two components overlap in the thickness direction (for example, the third direction DR3) of the display device 1000, unless otherwise defined.

[0129] The non-active area NA may be an area where no image is displayed. The non-active area NA may be arranged so that it is adjacent to the active area AA. For example, the non-active area NA may be an area that surrounds the active area AA. However, this is not limited to this, so the non-active area NA corresponds to an area that excludes the active area AA from the display panel DP, and may be modified and / or separated in various forms. Components for driving the pixels PX arranged in the active area AA may be arranged in the non-active area NA. For example, a plurality of pads connected to the data driver (DD) 400 may be arranged in the non-active area NA, and each pad may be connected to the plurality of pixels PX of the active area AA by data lines extending from the non-active area NA to the active area AA.

[0130] Furthermore, the display panel DP may have a gate region GIA. The gate region GIA may overlap at least a portion of the active region AA.

[0131] The gate driver GD may be arranged on the gate region GIA. For example, the gate driver GD may be formed on the gate region GIA, which overlaps at least a portion of the active region AA in a gate-in-matrix (GIA) manner.

[0132] For a more detailed description, with further reference to Fig. 6A, the gate region GIA may overlap at least a portion of the active region AA. For example, it may be defined that a portion of the active region AA overlaps the gate region GIA.

[0133] The gate area GIA may be divided into a plurality of blocks Block1 to Block5. For example, the gate area GIA may be divided into a plurality of blocks Block1 to Block5 arranged sequentially along the first direction DR1.

[0134] Here, even if in Fig. 6A illustrates that the gate area GIA is divided into five blocks, Block1 to Block5, and the exemplary embodiments of the present disclosure are not limited thereto. For example, the gate area GIA may be divided into four or fewer blocks or six or more blocks.

[0135] In each of the blocks Block1 to Block5 of the gate area GIA, the scanning driver 200 and the emission driver 300 included in the gate driver GD may be arranged.

[0136] For example, in each of the blocks Block1 to Block5 of the gate region GIA, a first scan driver 210, a third scan driver 230, a second scan driver 220, a fourth scan driver 240, an emission driver 300, and a second scan driver 220 may be arranged sequentially along the first direction DR1. Components (e.g., transistors, capacitors, and various connection signal lines) included in the first scan driver 210, components (e.g., transistors, capacitors, and various connection signal lines) included in the third scan driver 230, components (e.g., transistors, capacitors, and various connection signal lines) included in the second scan driver 220, components (e.g., transistors, capacitors, and various signal lines) included in the fourth scan driver 240, components (e.g., transistors,Capacitors and various connection signal lines) included in the emission driver 300 and components (e.g., transistors, capacitors, and various connection signal lines) included in the second scan driver 220 may be arranged sequentially along the first direction DR1 in each of the blocks Block1 to Block5 of the gate region GIA.

[0137] However, this is illustrative and the order of placement of the drivers is not limited to this.

[0138] In this case, as explained with reference to Fig. 2B, when the second scan driver 220_1 included in the scan driver 200_1 of the gate driver GD_1 has two sub-scan drivers 221 and 222 in each of the blocks Block1 to Block5 of the gate area GIA_1, the first scan driver 210, the third scan driver 230, a first sub-scan driver 221, a second sub-scan driver 222, the fourth scan driver 240, the emission driver 300, a first sub-scan driver 221, and a second sub-scan driver 222 may be arranged sequentially along the first direction DR1.

[0139] Again with reference to Fig. 5, in an exemplary embodiment, the display panel DP may include a drive layer DRL on which a gate driver GD and signal lines connected thereto are arranged, and a pixel circuit layer DSL on which a pixel PX and signal lines connected thereto are arranged. For example, again with reference to Fig. 7, the display panel DP may comprise a driving layer DRL and a pixel circuit layer DSL.

[0140] On the drive layer DRL, various elements (e.g., transistors and capacitors) constituting the gate driver GD and signal lines may be arranged. For example, various elements (e.g., transistors and capacitors) constituting the gate driver GD and the signal lines may be arranged on a region defined as the above-described gate region GIA among the regions of the drive layer DRL. For example, it may be understood that the above-described gate region GIA is defined by the regions of the display panel DP on the drive layer DRL on which the gate driver GD is arranged, but is not limited to this.

[0141] Various elements (e.g., transistors, capacitors, and light-emitting diodes) constituting the pixel PX, and signal lines may be disposed on the pixel circuit layer DSL. For example, the pixel circuit layer DSL may include a display element layer DPL on which a display element such as a transistor and a capacitor is disposed, and a light-emitting diode layer EPL disposed on the display element layer DPL and including a light-emitting diode. For example, the display element included in the display element layer DPL and the light-emitting diode included in the light-emitting diode layer EPL may be disposed on the active area AA.For example, it is assumed that the active area AA (or the active area AA and the non-active area NA) of the above-described area of ​​the display panel DP is defined on the pixel circuit layer DSL on which a display element and a light-emitting diode included in the pixel PX are arranged, but is not limited to this.

[0142] In an exemplary embodiment, the drive layer DRL may be arranged on the same layer as the pixel circuit layer DSL. For example, the drive layer DRL may be arranged on the same layer as the display element layer DPL of the pixel circuit layer DSL. In addition to the above description, various elements (e.g., transistors and capacitors) forming the gate driver GD may be arranged on the drive layer DRL, and various elements (e.g., transistors and capacitors) forming the pixel PX may be arranged on the display element layer DPL. As described with reference to Fig. 3, the transistors forming the gate driver GD may be implemented by PMOS LTPS thin-film transistors. Furthermore, as described with reference to Fig. 4, the transistors forming the pixel PX may be implemented by PMOS LTPS thin film transistors or NMOS oxide thin film transistors. Here, as described below with reference to Fig. 8, in the transistors constituting the pixel PX, the PMOS LTPS thin-film transistors are arranged in a lower portion, and the NMOS oxide thin-film transistors are arranged in an upper portion. For example, the PMOS LTPS thin-film transistors included in the gate driver GD of the driving layer DRL may be arranged on the same layer as a layer on which the PMOS LTPS thin-film transistors included in the pixel PX of the pixel circuit layer DSL, for example, the display element layer DPL, are arranged. For example, the PMOS LTPS thin-film transistors included in the pixel circuit layer DSL, for example, the display element layer DPL, and the PMOS LTPS thin-film transistors included in the driving layer DRL may be arranged on the same layer.

[0143] As described above, in the case of the display device 1000 according to the exemplary embodiments of the present disclosure, the display panel DP includes the drive layer DRL on which various elements constituting the gate driver GD are arranged, and the pixel circuit layer DSL on which various elements constituting the pixel PX are arranged. The gate region GIA on which various elements constituting the gate driver GD are arranged may be arranged to overlap at least a part of the active area AA on which various elements constituting the pixel PX are arranged. For example, the transistors (e.g., the PMOS LTPS transistors) included in the drive layer DRL may be arranged on the same layer as at least a part (e.g., the PMOS LTPS transistors) of transistors included in the pixel circuit layer DSL.For example, the gate driver GD is arranged on the same layer as the pixel circuit layer DSL on which the pixel PX is arranged, and is arranged and formed on the gate region GIA that overlaps the active region AA in the gate-in-matrix manner, so that the bezel area of ​​the display device 1000 can be minimized or at least reduced.

[0144] Furthermore, compared to the gate-in-panel (GIP) manner in which the gate driver GD is formed on the outside of the active area such that a gate signal is supplied to the pixels, in the display device 1000 according to the exemplary embodiments of the present disclosure, the gate driver GD is arranged in the gate-in-matrix (GIA) manner in at least a partial area of ​​the active area AA, for example, on the gate area GIA. Therefore, the gate signal delay is minimized or at least reduced to improve the luminance uniformity of the entire active area AA according to the relative position of the pixel PX, so that the display device 1000 can be implemented with a high resolution and a large area.

[0145] Again with reference to Fig. 5, the printed circuit board (PCB) can transmit signals and voltages for driving the display element from a control device to the display element. Therefore, the printed circuit board (PCB) can also be referred to as a control substrate. A control device, such as an IC chip or a circuit unit, can be mounted on the printed circuit board (PCB). Furthermore, a memory, a processor, or the like can also be mounted on the printed circuit board (PCB).

[0146] The data driver (DD) 400 can supply a data signal to the pixels PX arranged in the active area AA. For example, the data driver (DD) 400 can supply the data signal to the pixels PX via data lines.

[0147] In an exemplary embodiment, the data driver (DD) 400 is implemented as an integrated circuit (IC) chip, referred to as an integrated data circuit. The data driver (DD) 400 may be mounted on the interconnect layer COF in the form of an IC chip. Fig. 5 illustrates that the data driver (DD) 400 is mounted in a chip-on-film (COF) fashion, however, the exemplary embodiments of the present disclosure are not limited thereto. For example, the data driver (DD) 400 may also be mounted in a chip-on-board (COB) fashion, a chip-on-glass (COG) fashion, or a tape-on-carrier (TCP) fashion.

[0148] Hereinafter, a specific cross-sectional structure of a pixel circuit layer DSL included in the display panel DP will be described with reference to Fig. 8 are described. Fig. 8 is a cross-sectional view showing an example of a display panel of the Fig. 7 represents.

[0149] Referring to the Fig. 5, Fig. 7 and Fig. 8, at least one transistor TR_P and TR_O and one light-emitting diode LD may be arranged on the substrate SUB. Here, among the transistors arranged on the substrate SUB, a first-type transistor TR_P may be a polysilicon semiconductor transistor. For example, the first-type transistor TR_P may be a p-type MOSFET (PMOS) transistor having a polysilicon semiconductor layer formed by a low-temperature polysilicon (LTPS) process as an active layer (channel).

[0150] In an exemplary embodiment, as in Fig. 8, a second type transistor TR_O may be arranged on the first type transistor TR_P. In an exemplary embodiment, the first type transistor TR_P may be at least one of the drive transistor DT, the second transistor T2, the third transistor T3, and the fourth transistor T4 included in the pixel PX described with reference to Fig. 4 have been described.

[0151] Furthermore, in an exemplary embodiment, the transistors (e.g., the PMOS LTPS transistors) of the gate driver GD are arranged on the same layer as the PMOS LTPS transistors of transistors forming the pixel PX. Therefore, the first-type transistor TR_P may be at least one of the first-stage transistor M1 to the seventh-stage transistor M7 included in the gate driver GD and described with reference to Fig. 3 have been described.

[0152] Furthermore, the second type transistor TR_O of transistors arranged on the substrate SUB may be an oxide semiconductor transistor. For example, the second type transistor TR_O may be an n-type MOSFET (NMOS) transistor having an oxide semiconductor layer as an active layer (channel). For example, the second type transistor TR_O may be at least one of the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 included in the pixel PX and described with reference to Fig. 4 have been described.

[0153] The substrate SUB is a basic element of the pixel circuit layer DSL and can essentially be a transparent and translucent substrate. The substrate SUB can be a flexible substrate made of a plastic material. In this case, the flexible property can be interpreted as synonymous with bendable, unbreakable, rollable, and foldable properties.

[0154] For example, the substrate SUB may contain plastic, and in this case, the substrate SUB may be referred to as a plastic layer or a plastic substrate. For example, the substrate SUB may be at least one selected from a group consisting of a polyester-based polymer, a silicone-based polymer, an acrylic polymer, a polyolefin-based polymer, and a polymer thereof. For example, the substrate SUB may comprise polyimide (PI).

[0155] Here, when the substrate SUB comprises polyimide (PI), moisture penetrates through the substrate SUB formed of polyimide (PI) and penetrates into the thin film transistor, etc. included in the pixel PX, so that the reliability of the pixel PX is lowered and thus a performance of the display device 1000 may be deteriorated.

[0156] Accordingly, in an exemplary embodiment, the substrate SUB may comprise double polyimide (PI). Furthermore, the substrate SUB further comprises an inorganic layer formed between two polyimides (PI) to prevent moisture components from penetrating the lower polyimide (PI), thus further improving product performance reliability. Furthermore, to block charges from being loaded into the lower polyimide (PI), an inorganic layer is formed between two polyimides (PI), thereby further improving product reliability.

[0157] For example, as in Fig. 8, the substrate SUB may comprise a first sub-substrate SUBa comprising polyimide (PI), a second substrate SUBb disposed on the first sub-substrate SUBa and comprising an inorganic insulating material, and a third sub-substrate SUBc disposed on the second sub-substrate SUBb and comprising polyimide PI.

[0158] The inorganic insulating material included in the second sub-substrate SUBb may be formed by a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or a multilayer thereof. However, this is illustrative, and exemplary embodiments of the present disclosure are not limited thereto. For example, the inorganic insulating material included in the second sub-substrate SUBb may include a silicon oxide (SiOx) material. For example, the inorganic insulating material included in the second sub-substrate SUBb may include silicon dioxide (silicon oxide, SiO2). As another example, the inorganic insulating material included in the second sub-substrate SUBb may be formed by a double layer of silicon dioxide (SiO2) and silicon nitride (SiNx).

[0159] In this case, even if this is Fig. 8 is not shown separately, a back plate and a metal plate may be further arranged under the substrate SUB.

[0160] A shielding metal layer including at least one shielding metal structure BSM may be disposed on the substrate SUB. The shielding metal structure BSM included in the shielding metal layer may be formed by a single-layer or multi-layer layer made of one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0161] According to an exemplary embodiment, the shield metal structure BSM may be defined as a component included in the first type transistor TR_P. For example, the shield metal structure BSM may form a bottom gate electrode of the first type transistor TR_P.

[0162] The first buffer layer BUF1 can be arranged on the substrate SUB. For example, the first buffer layer BUF1 can be arranged on the substrate SUB to cover the shielding metal structure BSM.

[0163] In an exemplary embodiment, the first buffer layer BUF1 may include a multiple buffer layer BUF1a arranged on the substrate SUB and an active buffer layer BUF1b arranged on the multiple buffer layer BUF1a.

[0164] The first type transistor TR_P may be arranged on the first buffer layer BUF1. The first type transistor TR_P may include a first semiconductor structure ACT_P, a first gate electrode G1, a source electrode SE1, and a drain electrode DE1. In accordance with the exemplary embodiment, the first type transistor TR_P, as described above, may further include the shield metal structure BSM arranged between the first buffer layer BUF1 and the substrate SUB. A first semiconductor layer including at least a first semiconductor structure ACT_P may be arranged on the first buffer layer BUF1.

[0165] For example, the first semiconductor structure ACT_P of the first semiconductor layer included in the first-type transistor TR_P may be arranged on the first buffer layer BUF1. The first semiconductor structure ACT_P may include a first region S1 (or a source electrode or a source region), a second region D1 (or a drain electrode or a drain region), and a channel region A1 therebetween. Furthermore, as described above, the first semiconductor structure ACT_P may include a polysilicon semiconductor layer formed by a low-temperature polysilicon (LTPS) process.

[0166] For example, a first gate insulating layer GI1 may be arranged on the first semiconductor layer, for example, the first semiconductor structure ACT_P. For example, the first gate insulating layer GI1 is arranged to cover the first semiconductor layer, for example, the first semiconductor structure ACT_P, such that the first semiconductor structure ACT_P of the first-type transistor TR_P is insulated from the first gate electrode G1.

[0167] For example, the first gate insulating layer GI1 may be configured by a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof, but is not limited thereto.

[0168] A first conductive layer GAT1 may be disposed on the first gate insulating layer GI1. The first conductive layer GAT1 may form at least a part of the emission control line Ei, the third power supply line PL3 configured to supply the first initialization voltage VINIT, or the second scanning line S2i. Here, the first conductive layer GAT1 forms at least a part of the third power supply line PL3 configured to supply the first initialization voltage VINIT, so the first conductive layer GAT1 may comprise a material with high conductivity, such as a metal or conductive oxide. For example, the first conductive layer GAT1 may be formed by a single-layer film or a multi-layer film comprising aluminum (Al), copper (Cu), or titanium (Ti).In some exemplary embodiments, the first conductive layer GAT1 may be provided as a three-layer layer of titanium, aluminum, and titanium (Ti / Al / Ti) arranged sequentially.

[0169] A first gate electrode G1 of the first type transistor TR_P, which forms at least a part of the emission control line (e.g., Ei) or the scanning line (e.g., S2i) of the first conductive layer GAT1, may be arranged on the first gate insulating layer GI1.

[0170] The first gate electrode G1 of the first type transistor TR_P may be arranged such that it at least partially overlaps the first semiconductor structure ACT_P.

[0171] A first insulating layer ILD1 may be arranged on the first conductive layer GAT1, for example, the first gate electrode G1 of the first-type transistor TR_P. For example, the first insulating layer ILD1 may be arranged to cover the first conductive layer GAT1, for example, the first gate electrode G1 of the first-type transistor TR_P. The first insulating layer ILD1 may be formed by, but is not limited to, a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof.

[0172] A second conductive layer TM1 may be disposed on the first insulating layer ILD1. The second conductive layer TM1 comprises molybdenum (Mo), copper (Cu), and titanium (Ti) and may be formed by a single layer or a multilayer layer.

[0173] A second insulating layer ILD2 may be disposed on the second conductive layer TM1. For example, the second insulating layer ILD2 may be disposed such that it covers the second conductive layer TM1.

[0174] The first insulating layer ILD1 may be configured by a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof, but is not limited thereto.

[0175] A third conductive layer TM2 may be disposed on the second insulating layer ILD2. The third conductive layer TM2 comprises molybdenum (Mo), copper (Cu), and titanium (Ti) and may be formed by a single layer or a multilayer layer.

[0176] For example, a first source electrode SE1 and a first drain electrode DE1 of the first-type transistor TR_P of the third conductive layer TM2 may be arranged on the second insulating layer ILD2. The first source electrode SE1 of the first-type transistor TR_P of the third conductive layer TM2 may be in contact with a first region S1 of the first semiconductor structure ACT_P through a contact hole extending through the second insulating layer ILD2, the first insulating layer ILD1, and the first gate-insulating layer GI1. The first drain electrode DE1 of the first-type transistor TR_P of the third conductive layer TM2 may be in contact with a second region D1 of the first semiconductor structure ACT_P through the contact hole extending through the second insulating layer ILD2, the first insulating layer ILD1, and the first gate-insulating layer GI1.

[0177] A third insulating layer ILD3 may be arranged on the third conductive layer TM2, for example, on the first source electrode SE1 and the first drain electrode DE1 of the first-type transistor TR_P. For example, the third insulating layer ILD3 may be arranged to cover the third conductive layer TM2.

[0178] The third insulating layer ILD3 may be formed by a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof, but is not limited thereto.

[0179] A second buffer layer BUF2 may be arranged on the third insulating layer ILD3.

[0180] The second buffer layer BUF2 may be formed by a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof, but is not limited thereto.

[0181] A second semiconductor layer having at least one second semiconductor structure ACT_O may be arranged on the second buffer layer BUF2.

[0182] For example, the second semiconductor structure ACT_O of the second semiconductor layer included in the second-type transistor TR_O may be arranged on the second buffer layer BUF2. The second semiconductor structure ACT_O may include a first region S2 (or a source electrode or a source region), a second region D2 (or a drain electrode or a drain region), and a channel region A2 therebetween. Furthermore, as described above, the second semiconductor structure ACT_O may include an oxide semiconductor layer.

[0183] A second gate insulating layer GI2 may be arranged on the second semiconductor layer, for example, the second semiconductor structure ACT_O. The second gate insulating layer GI2 may be formed by a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof, but is not limited thereto.

[0184] A fourth conductive layer GAT2 may be disposed on the second gate insulating layer GI2. The fourth conductive layer GAT2 comprises molybdenum (Mo), copper (Cu), and titanium (Ti) and may be formed by a single layer or a multilayer.

[0185] For example, the second gate electrode G2 of the second type transistor TR_O, which forms at least some of the scanning lines (e.g., S1i, S3i, and S4i) of the fourth conductive layer GAT2, may be arranged on the second gate insulating layer GI2.

[0186] The second gate electrode G2 of the transistor of the second type TR_O can be arranged such that it at least partially overlaps the second semiconductor structure ACT_O.

[0187] A fourth insulating layer ILD4 may be arranged on the fourth conductive layer GAT2, for example, the second gate electrode G2 of the second-type transistor TR_O. For example, the fourth insulating layer ILD4 may be arranged such that it covers the fourth conductive layer GAT2, for example, the second gate electrode G2 of the second-type transistor TR_O.

[0188] A fifth conductive layer SD1 may be arranged on the fourth insulating layer ILD4. The fifth conductive layer SD1 may form at least a part of the fourth power supply line PL4, which is configured to supply the second initialization voltage VAR, or the fifth power supply line PL5, which is configured to supply the bias voltage VOBS, as described with reference to Fig. 4. Here, the fifth conductive layer SD1 establishes at least a part of the fourth power supply line PL4 configured to supply the second initialization voltage VAR or the fifth power supply line PL5 configured to supply the bias voltage VOBS, so that the fifth conductive layer SD1 may comprise a material with high conductivity, such as a metal or conductive oxide. For example, the fifth conductive layer SD1 may be formed by a single-layer film or a multi-layer film comprising aluminum (Al), copper (Cu), or titanium (Ti). In some exemplary embodiments, the fifth conductive layer SD1 may be provided as a three-layer film of titanium, aluminum, and titanium (Ti / Al / Ti) arranged sequentially.

[0189] Furthermore, at least a portion of the fifth conductive layer SD1 may serve as a connection electrode. For example, at least a portion of the fifth conductive layer SD1 is connected to the source electrode SE1 and / or the drain electrode DE1 of the first-type transistor TR_P of the third conductive layer TM2 through a contact hole extending through the fourth insulating layer ILD2, the second gate insulating layer GI2, the second buffer layer BUF2, and the third insulating layer ILD3. Alternatively, at least a portion of the fifth conductive layer SD1 may be in contact with a portion of the fourth conductive layer GAT2 through a contact hole extending through the fourth insulating layer ILD4.

[0190] Furthermore, at least a part of the fifth conductive layer SD1 can form the second source electrode SE2 and the second drain electrode DE2 of the second-type transistor TR_O. For example, the second source electrode SE2 of the second-type transistor TR_O of the fifth conductive layer SD1 can be in contact with a first region S2 of the second semiconductor structure ACT_O through a contact hole extending through the fourth insulating layer ILD4 and the second gate-insulating layer GI2. The second drain electrode DE2 of the second-type transistor TR_O of the fifth conductive layer SD1 can be in contact with a second region D2 of the second semiconductor structure ACT_O through the contact hole extending through the fourth insulating layer ILD4 and the second gate-insulating layer GI2.

[0191] In an exemplary embodiment, at least a part of the fifth conductive layer SD1 may form a timing line CLK connected to the drive layer DRL of the display panel DP described with reference to Fig. 5 to Fig. 7. For example, at least a portion of the fifth conductive layer SD1 may form a timing line CLK that transmits a timing signal that is an input signal to each stage included in the gate driver GD (e.g., the sense driver 200 and / or the emission driver 300). For example, the timing line CLK of the fifth conductive layer SD1 that transmits a timing signal may be electrically connected to each stage (e.g., at least a portion of a transistor constituting each stage) of the gate driver GD disposed on the drive layer DRL by means of a line hopping structure.For example, as described above, at least some of the first type transistors TR_P configure at least some of the stage transistors M1 to M7 of the gate driver GD, so that at least a part of the fifth conductive layer SD1, which configures the timing line CLK, can be electrically connected to one of the first type transistors TR_P.

[0192] A first planarization layer PNL1 may be disposed on the fifth conductive layer SD1. The first planarization layer PNL1 may be an organic layer that flattens an upper portion and protects underlying components. For example, the first planarization layer PNL1 may comprise an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0193] A sixth conductive layer SD2 may be arranged on the first planarization layer PNL1.

[0194] The sixth conductive layer SD2 may form at least a part of the data line Dj or the first power supply line PL1 configured to supply the first power supply voltage VDD, as described with reference to Fig. 4. Here, the sixth conductive layer SD2 establishes at least a part of the first power supply line PL1, which is configured to supply the first supply voltage VDD, so that the sixth conductive layer SD2 may comprise a material with high conductivity, such as a metal or conductive oxide. For example, the sixth conductive layer SD2 may be formed by a single layer or a multi-layer layer comprising aluminum (Al), copper (Cu), or titanium (Ti). In some exemplary embodiments, the sixth conductive layer SD2 may be provided as a three-layer layer of titanium, aluminum, and titanium (Ti / Al / Ti) arranged sequentially.

[0195] Furthermore, at least a portion of the sixth conductive layer SD2 may serve as a connection electrode. For example, at least a portion of the sixth conductive layer SD2 may be connected to at least a portion of the fifth conductive layer SD1 through a contact hole extending through the first planarization layer PNL1.

[0196] A second planarization layer PNL2 may be disposed on the sixth conductive layer SD2. The second planarization layer PNL2 may be an organic layer that flattens an upper portion and protects components disposed underneath. For example, the second planarization layer PNL2 may comprise an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0197] A seventh conductive layer SD3 may be disposed on the second planarization layer PNL2. The seventh conductive layer SD3 may be formed from a single layer or a multilayer layer composed of one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0198] In an exemplary embodiment, at least a part of the seventh conductive layer SD3 may serve as a shielding structure SM. For example, as described above, at least a part of the fifth conductive layer SD1 establishes at least a part of a timing line CLK that transmits a timing signal to the gate driver GD of the drive layer DRL. Therefore, signal interference may occur between the timing line CLK of the fifth conductive layer SD1 and the anode electrode AND of the light-emitting diode LD of the light-emitting diode layer EPL arranged above the display element layer DPL. In this case, the voltage of the anode electrode AND of the light-emitting diode LD (for example, a voltage of the fourth node N4, as described with reference to Fig. 4) is unstable, so that a display quality of the desired pixel PX may be degraded. Therefore, in the case of the display device 1000 according to the exemplary embodiments of the present disclosure, the seventh conductive layer SD3 disposed over the second planarization layer PNL2 serves as a shielding structure SM that shields a signal between at least a part (e.g., a timing line CLK) of the fifth conductive layer SD1 and the anode electrode AND the light-emitting diode LD of the light-emitting diode layer EPL. Therefore, the display quality can be improved.

[0199] According to the exemplary embodiment, the shielding structure SM of the seventh conductive layer SD3 for the shielding function may have a width greater than a width of the anode electrode AND of the light-emitting diode LD. Furthermore, at least a portion of the seventh conductive layer SD3 may be connected to at least a portion of the sixth conductive layer SD2 through a contact hole extending through the second planarization layer PNL2.

[0200] A third planarization layer PNL3 may be disposed on the seventh conductive layer SD3. The third planarization layer PNL3 may be an organic layer that flattens an upper portion and protects underlying components. For example, the third planarization layer PNL3 may comprise an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0201] The light-emitting diode LD may be arranged on the third planarization layer PNL3. The light-emitting diode LD may have an anode electrode AND (or a first electrode), a cathode electrode CAD (or a second electrode), and an emission layer EML formed therebetween. The anode electrode AND may be arranged on the third planarization layer PNL3.

[0202] Here, if the display device 1000 is a top-emission type in which the light emitted from the light-emitting diode LD is emitted above the substrate SUB in which the light-emitting diode LD is disposed, the anode electrode AND may further include a light-transmitting conductive layer and a reflective layer on the light-transmitting conductive layer. The light-transmitting conductive layer may be formed of a light-transmitting conductive oxide such as ITO or IZO, and the reflective layer may include, for example, silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof.

[0203] A dam layer BNK is arranged to cover at least a portion of the anode electrode AND and may expose the remaining portion of the anode electrode AND. For example, the dam layer BNK may be arranged to expose a portion corresponding to an emission region of the pixel PX. Therefore, a portion of the anode electrode AND may be exposed through the exposed portion of the dam layer BNK. The dam layer BNK may comprise an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material such as, but is not limited to, benzocyclobutene resin, acrylic resin, or imide resin.

[0204] The emission layer EML may be disposed on the entire surface of the pixel PX on upper surfaces of the dam layer BNK and the anode electrode AND. Here, a portion of the emission layer EML may be in contact with the exposed portion of the anode electrode AND through the exposed portion of the dam layer BNK. In accordance with the exemplary embodiment, the emission layer EML may include a plurality of organic layers.

[0205] The cathode electrode CAD can be arranged on the emission layer EML. For example, the cathode electrode CAD can be arranged on the front side of the pixel PX. The light-emitting diode LD can be formed by the anode electrode AND, the emission layer EML, and the cathode electrode CAD.

[0206] Here, a spacer SPC may be provided to prevent a screen mask and the substrate from coming into contact during a deposition process of the emission layer EML. The spacer SPC is arranged on the dam layer BNK, and the emission layer EML and the cathode electrode CAD may be deposited such that they extend over the spacer SPC arranged in the active region AA.

[0207] According to the exemplary embodiment, the emission layer EML and / or the cathode electrode CAD may not extend over the spacer SPC. The spacer SPC is arranged in the active region AA only in a portion of the dam layer BNK, so that even though the cathode electrode CAD does not extend over the spacer SPC, the cathode electrode CAD can be connected while covering the entire active region AA.

[0208] An encapsulation layer may be disposed over the light-emitting diode LD. For example, the encapsulation layer may include a first inorganic encapsulation layer PAS1, an organic encapsulation layer PCL on the first inorganic encapsulation layer PAS1, and a second inorganic encapsulation layer PAS2 on the organic encapsulation layer PCL. The first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 may serve to block the penetration of moisture or oxygen. For example, the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 may be formed from an inorganic material such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium nitride.The first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 can be formed by a chemical vapor deposition process or an atomic layer deposition process.

[0209] The organic encapsulation layer PCL can be arranged between the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2. The organic encapsulation layer PCL can be formed with a thickness greater than that of the first inorganic encapsulation layer PAS1 and / or the second inorganic encapsulation layer PAS2, such that particles that may be generated during the manufacturing process are sucked in and / or blocked. The organic encapsulation layer PCL can be formed from an organic material, such as silicon oxycarbon SiOCz, acrylic, or epoxy resin. The organic encapsulation layer PCL can be formed by a coating process, such as an inkjet coating process or a slot coating process.

[0210] Fig. Fig. 9 is a layout illustrating an example of a pixel used in a display device of the Fig. 5 is included. Fig. 10 is a cross-sectional view showing an example along line II' of Fig. 9 represents.

[0211] To avoid redundant descriptions, mainly content will be described that does not correspond to the description with reference to Fig. 1 to Fig. 8 overlap. A part not specifically described follows the exemplary embodiment described above, and the same reference numeral denotes the same component.

[0212] Here, Fig. 9 a first pixel PX1, a second pixel PX2, a third pixel PX3 and a fourth pixel PX4, which are substantially the same as the pixel PX described with reference to Fig. 4 and which are arranged in an associated manner in a first pixel area PXA1, a second pixel area PXA2, a third pixel area PXA3 and a fourth pixel area PXA4.

[0213] Here, the Fig. 9 are substantially equal to the pixel PX arranged on the display panel DP (for example, a pixel circuit layer DSL) of the display device 1000, which is shown with reference to Fig. 1 to Fig. 8 has been described. With reference to Fig. 1 to Fig. 9, the display panel DP, for example the pixel circuit layer DSL, may have a pixel area PXA in which the pixel PX is arranged. For example, as in Fig. As shown in Figure 9, the pixel region PXA may include a first pixel region PXA1, a second pixel region PXA2, a third pixel region PXA3, and a fourth pixel region PXA4. The first pixel PX1 is provided in the first pixel region PXA1, the second pixel PX2 is provided in the second pixel region PXA2, the third pixel PX3 is provided in the third pixel region PXA3, and the fourth pixel PX4 is provided in the fourth pixel region PXA4.

[0214] In an exemplary embodiment, the pixel PX (or pixel region PXA) may have a vertical flip structure. For example, the first pixel region PXA1 and the second pixel region PXA2 are arranged to be adjacent to each other along the first direction DR1 and may be symmetrical to each other with respect to the first power supply line PL1 extending along the second direction DR2.

[0215] Furthermore, the third pixel region PXA3 and the fourth pixel region PXA4 are arranged to be adjacent to each other along the first direction DR1, and may be symmetrical to each other with respect to the first power supply line PL1 extending along the second direction DR2. Furthermore, the first pixel region PXA1 and the third pixel region PXA3 are arranged to be adjacent to each other along the second direction DR2, and may be symmetrical to each other with respect to the fourth power supply line PL4 and / or the fifth power supply line PL5 extending along the first direction DR1.Furthermore, the second pixel region PXA2 and the fourth pixel region PXA4 are arranged to be adjacent to each other along the second direction DR2, and may be symmetrical to each other with respect to the fourth power supply line PL4 and / or the fifth power supply line PL5 extending along the first direction DR1.

[0216] Accordingly, the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 may have a substantially similar or the same configuration. Accordingly, hereinafter, a pixel PX located in a pixel region PXA will be described with reference to the first pixel PX1 located in the first pixel region PXA1. For the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 located in the second pixel region PXA2, the third pixel region PXA3, and the fourth pixel region PXA4, respectively, redundant descriptions will not be repeated.

[0217] In an exemplary embodiment, the pixel region PXA may include a central region CA located between the first pixel region PXA1 and the second pixel region PXA2, and between the third pixel region PXA3 and the fourth pixel region PXA4. Here, the central region CA may be a region overlapping the gate region GIA, which is described with reference to Fig. 5 to Fig. 7. For example, the gate driver GD disposed on the gate region GIA of the drive layer DRL may be disposed in the central region CA of the pixel region PXA of the pixel circuit layer DSL. In other words, a transistor, a capacitor, and a signal line constituting the gate driver GD may be disposed on the central region CA of the pixel region PXA of the pixel circuit layer DSL.

[0218] According to the exemplary embodiment, the central region CA extends along the first direction DR1 such that it is arranged on the entire active region AA. For example, the central region CA may be defined in response to the gate region GIA, which may be described with reference to Fig. 5. Furthermore, according to the exemplary embodiment, a width of the central region CA along the second direction DR2 may be smaller than a width of each pixel region PXA1, PXA2, PXA3, or PXA4 along the second direction DR2. However, this is illustrative, and the exemplary embodiments of the present disclosure are not limited thereto.

[0219] Again with reference to Fig. 10, the substrate SUB and the first buffer layer BUF1 may be sequentially disposed on the pixel region PXA. In accordance with the exemplary embodiment, a shield metal layer having a shield metal pattern BSM may be disposed between the substrate SUB and the first buffer layer BUF1.

[0220] A first semiconductor layer comprising at least one first semiconductor structure ACT_P may be arranged on the first buffer layer BUF1. For example, as shown in Fig. 10, a first semiconductor structure ACT_P of the second transistor T2 and a first semiconductor structure ACT_P of the third transistor T3 may be arranged.

[0221] The first gate insulating layer GI1 may be disposed on the first semiconductor layer, and the first conductive layer GAT1 may be disposed on the first gate insulating layer GI1. For example, as shown in Fig. 10, the gate electrode G1_T2 of the second transistor T2, which forms at least a part of the second scanning line S2i of the first conductive layer GAT1, may be arranged on the first gate insulating layer GI1.

[0222] Furthermore, as in Fig. 9, the first conductive layer GAT1 is arranged along the first direction DR1 with respect to the first pixel region PXA1 and the second pixel region PXA2, and may include the third power supply line PL3, the second scanning line S2i, and the emission control line Ei arranged sequentially along the second direction DR2.

[0223] Here, the pixel PX (or pixel region PXA) has a vertical flip structure as described above (for example, the first pixel region PXA1 and the third pixel region PXA3 are symmetrical to each other, and the second pixel region PXA2 and the fourth pixel region PXS4 are symmetrical to each other). With respect to the third pixel region PXA3 and the fourth pixel region PXA4, an emission control line Ei+1, a second scanning line S2i+1, and a third power supply line PL3 included in the first conductive layer GAT1 extend along the first direction DR1. The emission control line Ei+1, the second scanning line S2i+1, and the third power supply line PL3 may be sequentially arranged along the second direction DR2 in this order.

[0224] For example, a placement order of the third power supply line PL3, the second scanning line S2i, and the emission control line Ei included in the first conductive layer GAT1 in the first pixel region PXA1 and in the second pixel region PXA2 along the second direction DR2 and a placement order of the emission control line Ei+1, the second scanning line S2i+1, and the third power supply line PL3 included in the first conductive layer GAT1 in the third pixel region PXA3 and in the fourth pixel region PXA4 along the second direction DR2 may be opposite to each other.

[0225] The first insulating layer ILD1, the second conductive layer TM1 and the second insulating layer ILD2 may be arranged sequentially on the first conductive layer GAT1.

[0226] The third conductive layer TM2 may be arranged on the second insulating layer ILD2. For example, as shown in Fig. 10, a part of the third conductive layer TM2 may form a drain electrode DE1_T2 of the second transistor T2, and the other part may form a source electrode SE1_T3 of the third transistor T3.

[0227] The third insulating layer ILD3, the second buffer layer BUF2, the second semiconductor layer and the second gate insulating layer GI2 may be arranged sequentially on the third conductive layer TM2.

[0228] The fourth conductive layer GAT2 may be arranged on the second gate insulating layer GI2. For example, as shown in Fig. 10, at least a part of the fourth conductive layer GAT2 may form the first scanning line S1i, and at least the other part of the fourth conductive layer GAT2 may form the third scanning line S3i.

[0229] Furthermore, as in Fig. 9, the fourth conductive layer GAT2 is arranged with respect to the first pixel region PXA1 and the second pixel region PXA2 along the first direction DR1, and may include the fourth scanning line S4i, the first scanning line S1i, and the third scanning line S3i arranged sequentially along the second direction DR2.

[0230] Here, the pixel PX (or pixel region PXA) has a vertical flip structure as described above (for example, the first pixel region PXA1 and the third pixel region PXA3 are symmetrical to each other, and the second pixel region PXA2 and the fourth pixel region PXS4 are symmetrical to each other). With respect to the third pixel region PXA3 and the fourth pixel region PXA4, the third scan line S3i+1, the first scan line S1i+1, and the fourth scan line S4i+1 included in the fourth conductive layer GAT2 extend along the first direction DR1. The third scan line S3i+1, the first scan line S1i+1, and the fourth scan line S4i+1 may be sequentially arranged along the second direction DR2 in this order.

[0231] For example, a placement order of the fourth scan line S4i+1, the first scan line S1i, and the third scan line S3i included in the fourth conductive layer GAT2 in the first pixel region PXA1 and the second pixel region PXA2 along the second direction DR2 and a placement order of the third scan line S3i+1, the first scan line S1i+1, and the fourth scan line S4i+1 included in the fourth conductive layer GAT2 in the third pixel region PXA3 and the fourth pixel region PXA4 along the second direction DR2 may be opposite to each other.

[0232] In accordance with the exemplary embodiments, as in Fig. 9, the first conductive layer GAT1 and the second conductive layer GAT2 comprise different types of metal materials. For example, the first conductive layer GAT1 and the second conductive layer GAT2 may comprise different metal materials.

[0233] Here, the third power supply line PL3, the second scanning line S2i, and the emission control line Ei included in the first conductive layer GAT1, and the fourth scanning line S4i, the first scanning line S1i, and the third scanning line S3i included in the fourth conductive layer GAT2 may be arranged alternately along the second direction DR2. For example, the third power supply line PL3 of the first conductive layer GAT1, the fourth scanning line S4i of the fourth conductive layer GAT2, the second scanning line S2i of the first conductive layer GAT1, the first scanning line S1i of the fourth conductive layer GAT2, the emission control line Ei of the first conductive layer GAT1, and the third scanning line S3i of the fourth conductive layer GAT2 may be arranged sequentially with respect to the first pixel region PXA1 and the second pixel region PXA2.As another example, the third scan line S3i of the fourth conductive layer GAT2, the emission control line Ei of the first conductive layer GAT1, the first scan line S1i of the fourth conductive layer GAT2, the second scan line S2i of the first conductive layer GAT1, the fourth scan line S4i of the fourth conductive layer GAT2, and the third power supply line PL3 of the first conductive layer GAT1 may be arranged sequentially with respect to the third pixel region PXA3 and the fourth pixel region PXA4.

[0234] As described above, the third power supply line PL3, the second scanning line S2i, and the emission control line Ei included in the first conductive layer GAT1, and the fourth scanning line S4i, the first scanning line S1i, and the third scanning line S3i included in the fourth conductive layer GAT2, which may be formed with a different metal material from the first conductive layer GAT1, may be alternately arranged along the second direction DR2. Therefore, the distance between the signal line and / or the power supply line can be minimized or at least reduced. Thus, a simple design can be ensured.

[0235] A fourth insulating layer ILD4 may be disposed on the fourth conductive layer GAT2, and a fifth conductive layer SD1 may be disposed on the fourth insulating layer ILD4.

[0236] Furthermore, the fifth conductive layer SD1, as shown in Fig. 9, a fourth power supply line PL4 and a fifth power supply line PL5 extending on the central region CA along the first direction DR1. In accordance with exemplary embodiments, the fourth power supply line PL4 may include a first sub-power supply line PL4a, a second sub-power supply line PL4b, and a third sub-power supply line PL4c, and the fifth power supply line PL5 may include a fourth sub-power supply line PL5a and a fifth sub-power supply line PL5b.According to exemplary embodiments, the first sub-power supply line PL4a and the third sub-power supply line PL4c may be fourth power supply lines PL4 that supply the second initialization voltage VAR to a red pixel and a blue pixel, and the second sub-power supply line PL4b may be a fourth power supply line PL4 that supplies the second initialization voltage VAR to a green pixel. This is illustrative, and exemplary embodiments of the present disclosure are not limited thereto.Furthermore, the fourth sub-power supply line PL5a may be a fifth power supply line PL5 configured to supply the bias voltage VOBS to the first pixel PX1 and the second pixel PX2, and the fifth sub-power supply line PL5b may be a fifth power supply line PL5 configured to supply the bias voltage VOBS to the third pixel PX3 and the fourth pixel PX4. However, this is illustrative, and the exemplary embodiments of the present disclosure are not limited thereto.

[0237] In an exemplary embodiment, the fourth sub-power supply line PL5a, the first sub-power supply line PL4a, the second sub-power supply line PL4b, the third sub-power supply line PL4c, and the fifth sub-power supply line PL5b each extend in the first direction DR1 and may be sequentially arranged in the central region CA along the second direction DR2.

[0238] Here, except for a vertical line (for example, as a wiring line extending along the second direction DR2, a data line Dj included in the sixth conductive layer SD2, and a first power supply line PL1 configured to supply the first power supply voltage VDD), only the fourth power supply line PL4 and the fifth power supply line PL5 substantially included in the fifth conductive layer SD1 and extending along the first direction DR1 are arranged in the central region CA apart from the first pixel region PXA1 to the fourth pixel region PXA4 of the pixel region PXA.Therefore, a space for placing another element (e.g., stage transistors included in the gate driver GD) can be ensured on the gate region GIA, which corresponds to the central region CA of the drive layer DRL, which is arranged on the same layer as the pixel circuit layer DSL. Therefore, transistors and capacitors constituting the gate driver GD can be arranged on the gate region GIA of the drive layer DRL.

[0239] Again referring to Fig. 10, the first planarization layer PNL1 may be arranged on the fifth conductive layer SD1, and the sixth conductive layer SD2 may be arranged on the first planarization layer PNL1.

[0240] In this case, as explained with reference to Fig. 8, at least a part of the sixth conductive layer SD2 may form a data line Dj extending along the second direction DR2.

[0241] The second planarization layer PNL2, the seventh conductive layer SD3, the third planarization layer PNL3, the light-emitting diode LD and the encapsulation layer may be arranged sequentially on the sixth conductive layer SD2.

[0242] As described above, in the display device according to the exemplary embodiments of the present disclosure, a display panel may include a pixel circuit layer in which a pixel is arranged, and a driving layer in which a gate driver is arranged. Here, a gate region in which various elements constituting the gate driver are arranged may be arranged to overlap at least a part of an active region in which various elements constituting the pixel are arranged. For example, transistors included in the driving layer may be arranged on the same layer as at least a part of the transistor included in the pixel circuit layer.For example, the gate driver may be arranged and formed on a gate region overlapping the active region on the same layer as the pixel circuit layer in which a pixel is arranged, in a gate-in-matrix (GIA) manner, so that a bezel area of ​​the display device may be minimized or at least reduced.

[0243] Compared to the gate-in-panel (GIP) method, in which the gate driver is formed on the outside of the active area to supply a gate signal to the pixels, the gate driver in the display device according to the exemplary embodiments of the present disclosure is arranged in the gate-in-matrix (GIA) method in at least a partial area of ​​the active area, for example, on the gate area. Therefore, the delay of the gate signal corresponding to the relative position of the pixel is minimized or at least reduced, such that the luminance uniformity of the entire active area is improved, so that the display device can be implemented with a high resolution and a large area.

[0244] Furthermore, in the display device according to the exemplary embodiments of the present disclosure, a seventh conductive layer disposed over the second planarization layer is disposed in a part of a fifth conductive layer that forms a timing line that supplies a timing signal to the gate driver and an anode electrode of the light-emitting diode, so as to function as a shielding structure that shields a signal. Therefore, display quality can be improved.

[0245] Furthermore, a pixel included in the display device according to the exemplary embodiments of the present disclosure has a vertical flip structure. Therefore, space can be secured for disposing a transistor and a capacitor constituting the gate driver on the gate region of the drive layer, which overlaps a central region of the pixel circuit layer.

[0246] Furthermore, in the display device according to the exemplary embodiments of the present disclosure, a third power supply line, a second scanning line, and an emission line included in a first conductive layer, and a fourth scanning line, a first scanning line, and a third scanning line included in a fourth conductive layer formed of a different metal material than the first conductive layer are alternately arranged along one direction (a second direction). Therefore, a distance between each signal line and / or a power supply line can be minimized or at least reduced, and a simple design can be ensured.

[0247] The exemplary embodiments of the present disclosure may also be described as follows:

[0248] In accordance with one aspect of the present disclosure, a display device may include a display panel having a plurality of pixels; and a data driver circuit configured to supply a data signal to the plurality of pixels through data lines. A gate driver circuit configured to supply a gate signal to the plurality of pixels through gate lines may be disposed in the display panel. The display panel may include: a drive layer having a gate region including the gate driver circuit; and a pixel circuit layer having an active region including a pixel region in which each of the plurality of pixels is disposed, and a non-active region around the active region.The pixel circuit layer may include a light-emitting diode, a timing line configured to supply a timing signal to the gate driver circuit, and a shield structure between the light-emitting diode and the timing line.

[0249] The pixel region may include a first pixel region in which a first pixel of the plurality of pixels is arranged, a second pixel region in which a second pixel is arranged, a third pixel region in which a third pixel is arranged, a fourth pixel region in which a fourth pixel is included, and a central region overlapping the gate region.

[0250] The second pixel region may be arranged along a first direction adjacent to the first pixel region, the third pixel region is arranged along a second direction different from the first direction at a predetermined distance away from the first pixel region, and the fourth pixel region is arranged along the first direction adjacent to the third pixel region and is arranged along the second direction at a predetermined distance away from the second pixel region.

[0251] The central region may be located in a region between the first pixel region and the third pixel region and a region between the second pixel region and the fourth pixel region.

[0252] At least one of the plurality of pixels may be connected to each of a first scanning line to a fourth scanning line, an emission control line, a data line, and a first power supply line to a fifth power supply line. The first scanning line to a fourth scanning line, the emission control line, and the third power supply line to a fifth power supply line may extend along the first direction such that they are spaced apart from each other. The data line and the first power supply line may extend along the second direction.

[0253] On the first pixel region and the second pixel region, the third power supply line, the fourth scanning line, the second scanning line, the first scanning line, the emission control line, and the third scanning line may be sequentially arranged so as to be spaced apart from each other along the second direction, and on the third pixel region and the fourth pixel region, the third scanning line, the emission control line, the first scanning line, the second scanning line, the fourth scanning line, and the third power supply line are sequentially arranged so as to be spaced apart from each other along the second direction.

[0254] The fourth power supply line may include a first sub-power supply line to a third sub-power supply line, and the fifth power supply line may include a fourth sub-power supply line and a fifth sub-power supply line, and in the central region, the fourth sub-power supply line, the first sub-power supply line, the second sub-power supply line, the third sub-power supply line, and the fifth sub-power supply line are sequentially arranged to be spaced apart from each other along the second direction.

[0255] The first pixel and the second pixel may be symmetrical to each other with respect to the second direction, the third pixel and the fourth pixel are symmetrical to each other with respect to the second direction, the first pixel and the third pixel are symmetrical to each other with respect to the first direction, and the second pixel and the fourth pixel are symmetrical to each other with respect to the first direction.

[0256] The pixel circuit layer may include a display element layer including at least one first type transistor, at least one second type transistor, and at least one capacitor, and a light emitting diode layer including the light emitting diode.

[0257] The first type transistor may comprise a polysilicon semiconductor layer, and the second type transistor may comprise an oxide semiconductor layer.

[0258] The display element layer may include a first buffer layer, a first semiconductor layer on the first buffer layer, and having a first semiconductor structure of the first type transistor, a first gate insulating layer on the first semiconductor layer, a first conductive layer on the first gate insulating layer, and having a first gate electrode of the first type transistor, a first insulating layer on the first conductive layer, a second conductive layer on the first insulating layer, a second insulating layer on the second conductive layer, a third conductive layer on the second insulating layer, and having a first source electrode and a first drain electrode of the first type transistor, and a third insulating layer on the third conductive layer.

[0259] The display element layer may further comprise a second buffer layer on the third insulating layer, a second semiconductor layer on the second buffer layer, and comprising a second insulating semiconductor structure of the second type transistor, a second gate insulating layer on the second semiconductor layer, a fourth conductive layer on the second gate insulating layer, and comprising a second gate electrode of the second type transistor, a fourth insulating layer on the fourth conductive layer, and a fifth conductive layer on the fourth insulating layer, and comprising a second source electrode and a second drain electrode of the second type transistor.

[0260] The fifth conductive layer may further comprise the timing line.

[0261] The display element layer may further include a first planarization layer on the fifth conductive layer, a sixth conductive layer on the first planarization layer, a second planarization layer on the sixth conductive layer, and a seventh conductive layer on the second planarization layer. The seventh conductive layer may include the shielding structure.

[0262] A width of the shielding structure may be larger than a width of an anode electrode of the light-emitting diode.

[0263] Each of the plurality of pixels may include a drive transistor, a second transistor, a third transistor, and a fourth transistor each having a polysilicon semiconductor layer, and a first transistor, a fifth transistor, a sixth transistor, and a seventh transistor each having an oxide semiconductor layer, and each of a plurality of transistors included in the gate drive circuit may include the polysilicon semiconductor layer.

[0264] Each of the plurality of pixels may include a light-emitting diode; a drive transistor connected between a first node and a second node and configured to generate a drive current flowing from a first power supply line such that a first power supply voltage is supplied to a second power supply line such that a second power supply voltage is supplied through the light-emitting diode; a first transistor connected between the second node and a third node corresponding to a gate electrode of the drive transistor and configured to turn on in response to a first scanning signal supplied to a first scanning line; a second transistor connected between a data line and the first node and configured to turn on in response to a second scanning signal supplied to a second scanning line;a third transistor connected between the first power supply line and the first node, and configured to turn off in response to an emission control signal supplied to an emission control line; a fourth transistor connected between the second node and a fourth node corresponding to a first electrode of the light-emitting diode, and configured to turn off in response to the emission control signal; and a fifth transistor connected between the third node and a third power supply line, configured to supply a third power supply voltage, and configured to turn on in response to a fourth scanning signal supplied to a fourth scanning line;a sixth transistor connected between the fourth node and a fourth power supply line configured to supply a fourth power supply voltage, and configured to turn on in response to a third scanning signal supplied to a third scanning line; a seventh transistor connected between the first node and a fifth power supply line configured to supply a fifth power supply voltage, and configured to turn on in response to the third scanning signal; and a storage capacitor connected between the first power supply line and the third node.

[0265] The drive transistor, the second transistor, the third transistor, and the fourth transistor include a polysilicon semiconductor layer, and the first transistor, the fifth transistor, the sixth transistor, and the seventh transistor may include an oxide semiconductor layer.

[0266] The drive layer and the pixel circuit layer may be arranged on the same layer.

[0267] The display panel may include a plurality of first type transistors and a plurality of second type transistors, and at least some of the plurality of first type transistors may be included in the pixel circuit layer, and the remainder of the plurality of first type transistors may be included in the driving layer.

[0268] The majority of pixels may be located directly above the gate drive circuit in a plan view of the display panel.

[0269] Those skilled in the art will appreciate that various modifications and variations can be made to the display device of the present disclosure without departing from the technical spirit or scope of the disclosure. Therefore, the present disclosure is intended to cover the modifications and variations of this disclosure provided they fall within the scope of the appended claims. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] KR 10 - 2023 - 0 115 320

[0001]

Claims

[1] A display device (1000) comprising: a display panel (DP) having a plurality of pixels (PX); and a data driver circuit (400) configured to supply a data signal to the plurality of pixels (PX) through data lines (D1, ... Dm); wherein a gate driver circuit (GD) configured to supply a gate signal to the plurality of pixels (PX) through gate lines is arranged in the display panel (DP), where the display panel (DP) comprises: a drive layer (DRL) having a gate region (GIA) with the gate driver circuit (GD); and a pixel circuit layer (DSL) having an active area (AA) with a pixel area (PXA) in which each of the plurality of pixels (PX) is arranged, and a non-active area (NA) around the active area (AA), and wherein the pixel circuit layer (DSL) comprises a light-emitting diode (LD), a timing line (CLK) configured to supply a timing signal to the gate driver circuit (GD), and a shielding structure (SM) between the light-emitting diode (LD) and the timing line (CLK). [2] The display device (1000) according to claim 1, wherein the pixel region (PXA) comprises a first pixel region (PXA1) in which a first pixel (PX1) of the plurality of pixels (PX) is arranged, a second pixel region (PXA2) in which a second pixel (PX2) is arranged, a third pixel region (PXA3) in which a third pixel (PX3) is arranged, a fourth pixel region (PXA4) in which a fourth pixel (PX4) is included, and a central region (CA) overlapping the gate region (GIA). [3] The display device (1000) according to claim 2, wherein the second pixel region (PXA2) is arranged along a first direction (DR1) adjacent to the first pixel region (PXA1), the third pixel region (PXA3) is arranged along a second direction (DR2) different from the first direction (DR1) at a predetermined distance from the first pixel region (PXA1), and the fourth pixel region (PXA4) is adjacent to the third pixel region (PXA3) along the first direction (DR1) and is arranged along the second direction (DR2) at a predetermined distance. [4] The display device (1000) according to claim 3, wherein the central region (CA) is located in a region between the first pixel region (PXA1) and the third pixel region (PXA3) and a region between the second pixel region (PXA2) and the fourth pixel region (PXA4). [5] The display device (1000) according to claim 3 or 4, wherein at least one pixel (PX) of the plurality of pixels (PX) is connected to each of a first scanning line to a fourth scanning line (S1i, S2i, S3i, S4i), an emission control line (Ei), a data line (Dj), and a first power supply line to a fifth power supply line (PL1, ..., PL5), wherein the first scanning line to fourth scanning line (S1i, S2i, S3i, S4i), the emission control line (Ei) and the third power supply line to fifth power supply line (PL3, PL4, PL5) extend along the first direction (DR1) such that they are arranged at a distance from each other, and wherein the data line (Dj) and the first power supply line (PL1) extend along the second direction (DR2). [6] The display device (1000) according to claim 5, wherein on the first pixel region (PXA1) and the second pixel region (PXA2), the third power supply line (PL3), the fourth scanning line (S4i), the second scanning line (S2i), the first scanning line (S1i), the emission control line (Ei), and the third scanning line (S3i) are sequentially arranged such that they are spaced apart from each other along the second direction (DR2), and wherein on the third pixel region (PXA3) and the fourth pixel region (PXA4), the third scanning line (S3i+1), the emission control line (Ei+1), the first scanning line (S1i+1), the second scanning line (S2i+1), the fourth scanning line (S4i+1), and the third power supply line (PL3) are sequentially arranged such that they are spaced apart from each other along the second direction (DR2). [7] The display device (1000) according to claim 5 or 6, wherein the fourth power supply line (PL4) has a first sub-power supply line to a third sub-power supply line (PL4a, PL4b, PL4c), and the fifth power supply line (PL5) has a fourth sub-power supply line (PL5a) and a fifth sub-power supply line (PL5b), and wherein on the central region (CA), the fourth sub-power supply line (PL5a), the first sub-power supply line (PL4a), the second sub-power supply line (PL4b), the third sub-power supply line (PL4c), and the fifth sub-power supply line (PL5b) are arranged sequentially so as to be spaced apart from each other along the second direction (DR2). [8] The display device (1000) according to any one of claims 3 to 7, wherein the first pixel (PX1) and the second pixel (PX2) are symmetrical to each other with respect to the second direction (DR2), the third pixel (PX3) and the fourth pixel (PX4) are symmetrical to each other with respect to the second direction (DR2), the first pixel (PX1) and the third pixel (PX3) are symmetrical to each other with respect to the first direction (DR1), and the second pixel (PX2) and the fourth pixel (PX4) are symmetrical to each other with respect to the first direction (DR1). [9] The display device (1000) according to any one of claims 1 to 8, wherein the pixel circuit layer (DSL) comprises: a display element layer (DPL) having at least one transistor of the first type (TR_P), at least one transistor of the second type (TR_O) and at least one capacitor; and a light-emitting diode layer (EPL) with the light-emitting diode (LD). [10] The display device (1000) according to claim 9, wherein the first type transistor (TR_P) comprises a polysilicon semiconductor layer and the second type transistor (TR_O) comprises an oxide semiconductor layer. [11] The display device (1000) according to claim 9 or 10, wherein the display element layer (DPL) comprises: a first buffer layer (BUF1); a first semiconductor layer on the first buffer layer (BUF1), and having a first semiconductor structure (ACT_P) of the first type transistor (TR_P); a first gate insulating layer (GI1) on the first semiconductor layer; a first conductive layer (GAT1) on the first gate insulating layer (GI1), and having a first gate electrode (G1) of the first type transistor (TR_P); a first insulating layer (ILD1) on the first conductive layer (GAT1); a second conductive layer (TM1) on the first insulating layer (ILD1); a second insulating layer (ILD2) on the second conductive layer (TM1); a third conductive layer (TM2) on the second insulating layer (ILD2), and having a first source electrode (SE1) and a first drain electrode (DE1) of the first type transistor (TR_P); and a third insulating layer (ILD3) on the third conductive layer (TM2). [12] The display device (1000) according to claim 11, wherein the display element layer (DPL) further comprises: a second buffer layer (BUF2) on the third insulating layer (ILD3); a second semiconductor layer on the second buffer layer (BUF2), and having a second semiconductor structure (ACT_O) of the second type transistor (TR_O); a second gate insulating layer (GI2) on the second semiconductor layer; a fourth conductive layer (GAT2) on the second gate insulating layer (GI2) and having a second gate electrode (G2) of the second type transistor (TR_O); a fourth insulating layer (ILD4) on the fourth conductive layer (GAT2); and a fifth conductive layer (SD1) on the fourth insulating layer (ILD4), and having a second source electrode (SE2) and a second drain electrode (DE2) of the second type transistor (TR_O). [13] The display device (1000) according to claim 12, wherein the fifth conductive layer (SD1) further comprises the timing line (CLK). [14] The display device (1000) according to claim 12 or 13, wherein the display element layer (DPL) further comprises: a first planarization layer (PNL1) on the fifth conductive layer (SD1); a sixth conductive layer (SD2) on the first planarization layer (PNL1); a second planarization layer (PNL2) on the sixth conductive layer (SD2); and a seventh conductive layer (SD3) on the second planarization layer (PNL2), wherein the seventh conductive layer (SD3) has the shielding structure (SM). [15] The display device (1000) according to claim 14, wherein a width of the shielding structure (SM) is larger than a width of an anode electrode (AND) of the light-emitting diode (LD). [16] The display device (1000) according to any one of claims 1 to 15, wherein each of the plurality of pixels (PX) comprises a drive transistor (DT), a second transistor (T2), a third transistor (T3), and a fourth transistor (T4), each having a polysilicon semiconductor layer, and a first transistor (T1), a fifth transistor (T5), a sixth transistor (T6), and a seventh transistor (T7), each having an oxide semiconductor layer, and each of a plurality of transistors included in the gate drive circuit (GD) comprises the polysilicon semiconductor layer. [17] The display device (1000) according to any one of claims 1 to 15, wherein each of the plurality of pixels (PX) comprises: a light-emitting diode (LD); a drive transistor (DT) connected between a first node (N1) and a second node (N2), which is configured to generate a drive current flowing from a first power supply line (PL1) such that a first supply voltage (VDD) is supplied to a second power supply line (PL2) such that a second supply voltage (VSS) is supplied through the light-emitting diode (LD); a first transistor (T1) connected between the second node (N2) and a third node (N3) corresponding to a gate electrode of the drive transistor (DT), the first transistor (T1) being configured to turn on in response to a first scanning signal (SC1i) supplied to a first scanning line (S1i); a second transistor (T2) connected between a data line (Di) and the first node (N1), the second transistor (T2) being configured to turn on in response to a second scanning signal (SC2i) supplied to a second scanning line (S2i); a third transistor (T3) connected between the first power supply line (PL1) and the first node (N1), the third transistor (T3) being configured to turn off in response to an emission control signal (EMi) supplied to an emission control line (Ei); a fourth transistor (T4) connected between the second node (N2) and a fourth node (N4) corresponding to a first electrode of the light-emitting diode (LD), the fourth transistor (T4) being configured to turn off in response to the emission control signal (EMi); a fifth transistor (T5) connected between the third node (N3) and a third power supply line (PL3) configured to supply a third power supply voltage (VINIT), the fifth transistor (T5) being configured to turn on in response to a fourth scanning signal (SC4i) supplied to a fourth scanning line (S4i); a sixth transistor (T6) connected between the fourth node (N4) and a fourth power supply line (PL4) configured to supply a fourth power supply voltage (VAR), the sixth transistor (T6) being configured to turn on in response to a third scanning signal (SC3i) supplied to a third scanning line (S3i); a seventh transistor (T7) connected between the first node (N1) and a fifth power supply line (PL5) configured to supply a fifth power supply voltage (VOBS), the seventh transistor (T7) being configured to turn on in response to the third scanning signal (SC3i); and a storage capacitor (Cst) connected between the first power supply line (PL1) and the third node (N3). [18] The display device (1000) according to claim 17, wherein the drive transistor (DT), the second transistor (T2), the third transistor (T3) and the fourth transistor (T4) comprise a polysilicon semiconductor layer and the first transistor (T1), the fifth transistor (T5), the sixth transistor (T6) and the seventh transistor (T7) comprise an oxide semiconductor layer. [19] The display device (1000) according to any one of claims 1 to 18, wherein the drive layer (DRL) and the pixel circuit layer (DSL) are arranged on the same layer. [20] The display device (1000) according to any one of claims 1 to 19, wherein the display panel (DP) comprises a plurality of first type transistors and a plurality of second type transistors, and wherein at least some of the plurality of first type transistors are included in the pixel circuit layer (DSL) and the rest of the plurality of first type transistors are included in the drive layer (DRL).

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