SEMICONDUCTOR DEVICE HAVING AN ELECTRODE AND AN INSULATION PATTERN AND METHOD FOR FORMING THE SAME

Abstract

A semiconductor device may include a stacked structure bonded to circuitry and comprising a plurality of mold layers alternately stacked with a plurality of electrodes. A source line may be disposed on the stacked structure. A channel structure may be provided extending through the stacked structure into the source line. An insulating isolation pattern may be provided disposed in a slot extending through the source line and the stacked structure. The insulating isolation pattern may include a first portion adjacent to the source line and a second portion adjacent to the stacked structure. The insulating isolation pattern may include a convergence interface between the first portion and the second portion. The convergence interface may be disposed between one end of the channel structure and one end of the plurality of electrodes.

Description

BACKGROUND 1. Technical field

[0001] Various embodiments of the disclosed technology generally relate to a semiconductor device including, but not limited to, an electrode and an insulation pattern, and a method of forming the same. 2. State of the art

[0002] In response to the demand for high integration of a semiconductor device, there is a technology for bonding two wafers. Bonding between a lower wafer and an upper wafer can be achieved using coupling between insulating layers. Electrical connection between the lower wafer and the upper wafer can be achieved using coupling between pads disposed in the insulating layers. Physical deformations such as warpage or deformation of the upper wafer lead to a reduction in the yield of a bonding process and the bonded wafers. SUMMARY

[0003] In one embodiment, a semiconductor device may include a stacked structure bonded to a circuit assembly and comprising a plurality of mold layers alternately stacked with a plurality of electrodes. A source line may be disposed on the stacked structure. A channel structure extending through the stacked structure into the source line may be provided. An insulating isolation pattern disposed in a slot extending through the source line and the stacked structure may be provided. The insulating isolation pattern may include a first portion adjacent to the source line and a second portion adjacent to the stacked structure. The insulating isolation pattern may include a convergence interface between the first portion and the second portion.The convergence interface may be arranged between an end of the channel structure disposed in the source line and a surface of the plurality of electrodes closest to the source line.

[0004] In one embodiment, a semiconductor device may include a stacked structure on a substrate. The stacked structure may include a plurality of mold layers alternately stacked with a plurality of electrodes. A source line may be disposed on the stacked structure. A channel structure extending through the stacked structure into the source line may be provided. An insulating isolation pattern disposed in a slot extending through the source line and the stacked structure may be provided. The insulating isolation pattern may include a first portion adjacent to the source line and a second portion adjacent to the stacked structure. A side surface of the insulating isolation pattern may include a convergence interface between the first portion and the second portion.The convergence interface may be arranged between an end of the channel structure disposed in the source line and a surface of the plurality of electrodes closest to the source line. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a cross-sectional view illustrating a semiconductor device based on an embodiment of the disclosed technology. Fig. 2 to Fig. 8 show partial views illustrating embodiments of Fig. 1 according to various embodiments. Fig. 9 shows a flowchart illustrating a method of forming a semiconductor device based on an embodiment of the disclosed technology. Fig. 10 to Fig. 25 show cross-sectional and top views of a semiconductor device formed using the method of forming a semiconductor device based on various embodiments of the disclosed technology.

[0005] The cross-hatching in the figures represents corresponding or similar areas between the figures and does not indicate the materials for the areas. DETAILED DESCRIPTION

[0006] Various embodiments of the disclosed technology are directed to providing a semiconductor device having excellent electrical characteristics and advantageous for increasing mass production efficiency, and a method for forming the same.

[0007] Terms such as “vertical,” “horizontal,” “top,” “bottom,” “uppermost,” “lowermost,” “above,” “below,” and other terms implying a particular spatial relationship and / or orientation are used for convenience of description or reference only and are not otherwise limiting.

[0008] Fig. 1 shows a sectional view illustrating a semiconductor device based on an embodiment of the disclosed technology, Fig. 2 to Fig. 6 show partial views illustrating section 10 of Fig. 1, and Fig. 7 and Fig. 8 show partial views illustrating section 15 of Fig. 1 represent.

[0009] With reference to Fig. 1, the semiconductor device based on embodiments of the disclosed technology comprises a circuit arrangement CS on a first substrate 21. The circuit arrangement CS comprises an insulation layer 23, a transistor TR, a circuit insulation layer 25, a vertical connection 26, and a horizontal connection 27. A first insulating bonding layer 35 and a first pad 36 are arranged on the circuit arrangement CS.

[0010] A first direction FD, a second direction SD, and a third direction VD are shown for ease of reference with respect to the orientation of the drawing. The first direction FD and the second direction SD are parallel to the top and / or bottom of the first substrate 21. The second direction SD is perpendicular to the first direction FD. The third direction VD is perpendicular to the first direction FD and the second direction SD. The third direction VD is perpendicular to the top and / or bottom of the first substrate 21.

[0011] In this example, a second insulating bonding layer 135 is bonded to the first insulating bonding layer 35 in the third direction VD. A second pad 136 is bonded to the first pad 36. The second pad 136 is disposed in the second insulating bonding layer 135. An insulating interlayer 125 and an interconnect 126 are disposed on the second insulating bonding layer 135 and the second pad 136. A stack structure ST is disposed on the insulating interlayer 125 and the interconnect 126.

[0012] A source line 142 is arranged on the stack structure ST. A channel structure CH extends through the stack structure ST 142 in the third direction VD into the source line. An insulating isolation pattern 250 is arranged in a slot 157SLT that extends through the source line 142 and the stack structure ST in the third direction VD. The top surface of the source line 142 and the top surface of the insulating isolation pattern 250 are formed substantially in the same plane. The bottom surface of the insulating isolation pattern 250 contacts the insulating interlayer 125.

[0013] The stack structure ST includes a first stack structure ST1, a second stack structure ST2, and a third stack structure ST3. The first stack structure ST1 includes a plurality of first mold layers 53 alternately stacked with a plurality of first horizontal electrodes 155. The second stack structure ST2 includes a plurality of second mold layers 63 alternately stacked with a plurality of second horizontal electrodes 165. The third stack structure ST3 includes a plurality of third mold layers 73 alternately stacked with a plurality of third horizontal electrodes 175. Mold layers are also known as insulating layers, and horizontal electrodes are also known as electrodes or conductive layers.

[0014] As in Fig. 2 to Fig. 8, the channel structure CH comprises a core layer CO extending through the stack structure ST into the source line 142, a channel pattern CP surrounding the side surface and the top surface of the core layer CO, an information storage pattern DSL between the channel pattern CP and the stack structure ST, and a bit plug DP contacting the core layer CO and the channel pattern CP at one end of the channel structure CH, as shown in Fig. 8. The information storage pattern DSL includes a tunnel layer TL disposed on the channel pattern CP, a charge trap layer CTL disposed on the tunnel layer TL, and a blocking layer BL disposed on the charge trap layer CTL. The charge trap layer CTL is disposed between the tunnel layer TL and the blocking layer BL.

[0015] The slot 157SLT extends completely through the source line 142 and the entire stack structure ST in the third direction VD, as shown in Fig. 1. The slot 157SLT includes an upper slot 157 and a lower slot 157L. The lower slot 157L is open, connected to, or adjacent to the upper slot 157. The upper slot 157 extends at least partially through the source line 142 in the third direction VD. The upper slot 157 may have the shape of an inverted trapezoid.

[0016] The lower slot 157L extends through the stack structure ST in the third direction VD. The lower slot 157L includes a first lower slot 57, a second lower slot 67, and a third lower slot 77. The first lower slot 57, the second lower slot 67, and the third lower slot 77 are open, connected to each other, or adjacent to each other. The first lower slot 57 extends through the first stack structure ST1. The first lower slot 57 may have the shape of a trapezoid. The second lower slot 67 extends through the second stack structure ST2. The second lower slot 67 may have the shape of a trapezoid. The third lower slot 77 extends through the third stack structure ST3. The third lower slot 77 may have the shape of a trapezoid.

[0017] The insulating isolation pattern 250 includes an upper portion 250U, also referred to as a first portion, and a lower portion 250L, also referred to as a second portion. The lower portion 250L may be adjacent to the upper portion 250U in the third direction VD. The upper portion 250U is disposed in the upper slot 157. The upper portion 250U may have the shape of an inverted trapezoid. The lower portion 250L is disposed in the lower slot 157L.

[0018] The lower portion 250L includes a first lower portion 250L1, a second lower portion 250L2, and a third lower portion 250L3. The first lower portion 250L1, the second lower portion 250L2, and the third lower portion 250L3 may be adjacent to one another. The first lower portion 250L1 is disposed in the first lower slot 57. The first lower portion 250L1 may have the shape of a trapezoid. The second lower portion 250L2 is disposed in the second lower slot 67. The second lower portion 250L2 may have the shape of a trapezoid. The third lower portion 250L3 is disposed in the third lower slot 77. The third lower portion 250L3 may have the shape of a trapezoid.

[0019] The side surface of the insulating isolation pattern 250 includes a convergence interface 250CIF between the upper portion 250U and the lower portion 250L. The convergence interface 250CIF is arranged between a plane at the top of the channel structure CH and a plane at the top of the top horizontal electrode 155, the top being closest to the source line 142.

[0020] In the examples of Fig. 1 to Fig. 8, source line 142 corresponds to a common source line. The plurality of horizontal electrodes 155, 165, and 175 include a plurality of word lines, a plurality of select lines, and at least one GIDL (Gate Induced Drain Leakage) control line. A plurality of memory cells are formed at the intersection points of the channel structure CH and the plurality of word lines.

[0021] In one embodiment, at least one of the plurality of horizontal electrodes 155, 165, and 175 closest to the source line 142 corresponds to a source select line. At least one of the plurality of horizontal electrodes 155, 165, and 175 closest to the bit plug DP corresponds to a drain select line. One of the plurality of horizontal electrodes 155, 165, and 175 closest to the source line 142 and / or one of the plurality of horizontal electrodes 155, 165, and 175 closest to the bit plug DP corresponds to the GIDL control line. A plurality of word lines are arranged between at least one drain select line and at least one source select line among the plurality of horizontal electrodes 155, 165, and 175.

[0022] With reference to Fig. 2, the convergence interface 250CIF is arranged in a horizontal plane at an uppermost end of the channel structure CH. The upper portion 250U of the insulating isolation pattern 250 is adjacent to the lower portion 250L. The lateral slope of the upper portion 250U and the lateral slope of the lower portion 250L of the insulating isolation pattern 250 may be different from each other. In one embodiment, the convergence interface 250CIF may be arranged on a horizontal plane that is lower than the uppermost end of the channel structure CH.

[0023] The channel structure CH includes the core layer CO, the channel pattern CP, and the information storage pattern DSL. The information storage pattern DSL includes the tunnel layer TL, the charge trap layer CTL, and the depletion layer BL. The channel pattern CP surrounds the side surface and top surface of the core layer CO. The information storage pattern DSL surrounds the side surface of the channel pattern CP. The channel pattern CP and the core layer CO may extend into the source line 142. The channel pattern CP may directly contact the source line 142. The top end of the information storage pattern DSL does not extend further than or terminates at the bottom surface of the source line 142.

[0024] The information storage pattern DSL is arranged between the channel pattern and the plurality of first mold layers 53, which are alternately stacked with the plurality of first horizontal electrodes 155. The charge trap layer CTL is arranged between the tunnel layer TL and the barrier layer BL. The tunnel layer TL is arranged between the charge trap layer CTL and the channel pattern CP. The barrier layer BL is arranged between the charge trap layer CTL and the plurality of first mold layers 53, which are alternately stacked with the plurality of first horizontal electrodes 155.

[0025] Between successive first mold layers 53, an undercut region 157LUC is formed, which is open, connected to, or adjacent to the lower slot 157L. The lower portion 250L of the insulating pattern 250 includes a side extension 250LUC extending into the undercut region 157LUC. The side extension 250LUC contacts a side surface of the first horizontal electrode 155.

[0026] With reference to Fig. 3, the convergence interface 250CIF is arranged on a horizontal plane in which the uppermost surface of the plurality of first mold layers 53 contacts the lowermost surface of the source line 142.

[0027] With reference to Fig. 4, the convergence interface 250CIF is disposed at a level above the uppermost surface of the plurality of first horizontal electrodes 155. In one embodiment, the convergence interface 250CIF is disposed between the uppermost surface of the plurality of first horizontal electrodes 155 and the lowermost surface of the source line 142.

[0028] With reference to Fig. 5, the upper portion 250U and the lower portion 250L of the insulating isolation pattern 250 may have different horizontal widths when the upper portion 250U is adjacent to the lower portion 250L. A horizontal width is a width in the first direction FD. The upper portion 250U of the insulating isolation pattern 250 has a greater horizontal width than the width of the lower portion 250L at the intersection of the upper portion 250U and the lower portion 250L. The upper portion 250U of the insulating isolation pattern 250 may have an inverted trapezoidal shape, and the lower portion 250L of the insulating isolation pattern 250 may have a trapezoidal shape. The convergence interface 250CIF may include a step.

[0029] With reference to Fig. 6, the center of the upper portion 250U of the insulating insulation pattern 250 is offset from the center of the lower portion 250L. Referring to Fig. 1 and Fig. 6 is a straight line passing vertically through the center of the upper portion 250U of the insulating isolation pattern 250 and extending in the third direction VD, offset from a straight line passing vertically through the center of the lower portion 250L of the insulating isolation pattern 250 in the third direction VD. The convergence interface 250CIF may include a step.

[0030] With reference to Fig. 7, the lowermost end of the lower portion 250L of the insulating insulation pattern 250 is located on a horizontal plane where the lowermost end of the plurality of third mold layers 73 and the lowermost end of the bit plug DP are located. The lowermost end of the lower portion 250L of the insulating insulation pattern 250 is located on a horizontal plane at the boundary between the lowermost surface of the plurality of third mold layers 73 and the insulating interlayer 125.

[0031] The channel structure CH includes the core layer CO, the channel pattern CP, the information storage pattern DSL, and the bit connector DP. The information storage pattern DSL includes the tunnel layer TL, the charge trap layer CTL, and the depletion layer BL. The bit connector DP directly contacts the core layer CO and the channel pattern CP. The bit connector DP contacts the connection 126.

[0032] With reference to Fig. 8, the lowermost end of the lower slot 157L extends into the insulating interlayer 125. The lowermost end of the lower portion 250L of the insulating insulation pattern 250 extends into the insulating interlayer 125. The lowermost end of the lower slot 157L is located at a level lower than the uppermost surfaces of the insulating interlayer 125 and the connection 126. The lowermost end of the lower portion 250L of the insulating insulation pattern 250 is located at a level lower than the uppermost surfaces of the insulating interlayer 125 and the connection 126. The lowermost end of the lower portion 250L of the insulating insulation pattern 250 is located at a level lower than the boundary between the bit plug DP and the connection 126.

[0033] Fig. 9 shows a flowchart illustrating a method of forming a semiconductor device based on an embodiment of the disclosed technology. Fig. 10, Fig. 11, Fig. 13 to Fig. 19, and Fig. 21 to Fig. 24 show sectional views of the semiconductor device. Fig. 12, Fig. 20 and Fig. 25 show plan views of the semiconductor device according to Fig. 11, Fig. 19 or Fig. 24.

[0034] With reference to Fig. 9, the method of forming a semiconductor device based on an embodiment of the disclosed technology includes forming B910 a circuit arrangement, forming B920 a stack arrangement, bonding B930 the stack arrangement to the circuit arrangement, forming B940 a source line on the stack arrangement, forming B950 a slot extending through the source line and the stack arrangement, removing B960 sacrificial layers in the stack arrangement, and forming B970 horizontal electrodes and forming an insulating isolation pattern in the slot.

[0035] With reference to Fig. 9 and Fig. 10, a circuit arrangement CS is formed B910 on a first substrate 21. The circuit arrangement CS comprises an insulating layer 23, a transistor TR, a circuit insulating layer 25, a vertical connection 26, and a horizontal connection 27. A first insulating bonding layer 35 is formed on the circuit arrangement CS. A first terminal pad 36 is formed in the first insulating bonding layer 35. The top surfaces of the first insulating bonding layer 35 and the first terminal pad 36 are exposed and are formed substantially in the same plane.

[0036] The first substrate 21 comprises a semiconductor substrate such as a silicon wafer or an SOI (silicon on insulator) wafer. The first substrate 21 may comprise a III-V group semiconductor substrate, for example, a compound semiconductor substrate such as gallium arsenide GaAs. The first substrate 21 may comprise monocrystalline silicon, polysilicon, amorphous silicon, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, or a combination thereof. The circuit arrangement CS is formed in and / or on the first substrate 21.

[0037] The circuit arrangement CS comprises various types of active / passive elements, for example, one or more transistors TR. The transistors TR can be a planar transistor, a recess-channel transistor, a vertical transistor, a fin-field-effect transistor (finFET), a gate-all-around transistor (GAA), a multi-bridge channel transistor, or a combination thereof. In one embodiment, the transistor can be part of a peripheral circuit such as a page buffer or a decoder.

[0038] The insulation layer 23 may be formed in the first substrate 21 using a shallow trench isolation (STI) method. The transistor TR may be delimited on the first substrate 21 by the insulation layer 23. The circuit insulation layer 25 covers the insulation layer 23 and the transistor TR. The vertical connection 26 and the horizontal connection 27 are formed in the circuit insulation layer 25. The vertical connection 26 and the horizontal connection 27 are connected to the transistor TR. The first pad 36 is connected to the transistor TR via the vertical connection 26 and the horizontal connection 27.

[0039] Each of the insulating layer 23, the circuit insulating layer 25, and the first insulating bonding layer 35 may be a single layer or a multi-layer. Each of the insulating layer 23, the circuit insulating layer 25, and the first insulating bonding layer 35 may comprise at least two selected from the group consisting of silicon Si, oxygen O, nitrogen N, carbon C, and boron B. Each of the insulating layer 23, the circuit insulating layer 25, and the first insulating bonding layer 35 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), low-k dielectric, high-k dielectric, or a combination thereof. In one embodiment, the first insulating bonding layer 35 may comprise silicon carbonitride (SiCN).

[0040] Each of the vertical interconnect 26, the horizontal interconnect 27, and the first land 36 may be a single layer or a multi-layer. Each of the vertical interconnect 26, the horizontal interconnect 27, and the first land 36 may comprise a conductive material such as metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or a combination thereof. Each of the vertical interconnect 26, the horizontal interconnect 27, and the first land 36 may comprise a conductive material such as copper Cu, aluminum Al, nickel Ni, cobalt Co, ruthenium Ru, tungsten W, tungsten nitride WN, titanium Ti, titanium nitride TiN, tantalum Ta, tantalum nitride TaN, tin Sn, platinum Pt, gold Au, silver Ag, or a combination thereof. In one embodiment, the first land 36 may comprise a Cu layer formed using an electroplating process.

[0041] With reference to Fig. 9 and Fig. 11, a first stacked structure ST1, in which a plurality of first mold layers 53 are alternately stacked with a plurality of first sacrificial layers 54, is formed on or above a second substrate 51. A first channel hole 56 and a first lower slot 57 are formed and extend through the first stacked structure ST1 into the second substrate 51. A first channel sacrificial layer 58 is formed in each first channel hole 56, and a first lower slot 57 is formed in each first slot sacrificial layer 59.

[0042] The plurality of first sacrificial layers 54 comprise a material whose etch selectivity differs from the etch selectivity of the plurality of first mold layers 53. In one embodiment, the plurality of first mold layers 53 may comprise insulating oxide, such as silicon oxide, and the plurality of first sacrificial layers 54 may comprise nitride, such as silicon nitride. The bottommost layer of the first stack structure ST1 may be one of the plurality of first mold layers 53, and the topmost layer of the first stack structure ST1 may be one of the plurality of first sacrificial layers 54 and the plurality of first mold layers 53.

[0043] Each of the first channel hole 56s and the first lower slot 57 extends through the first stack structure ST1 into the second substrate 51 in the third direction VD. The first channel sacrificial layer 58 and the first slot sacrificial layer 59 comprise materials that are different from the materials of the plurality of first sacrificial layers 54 and the plurality of first mold layers 53. In one embodiment, the first channel sacrificial layer 58 and the first slot sacrificial layer 59 may comprise polysilicon, carbon, or metal.

[0044] With reference to Fig. 9 and Fig. 12, a plurality of first channel holes 56 are arranged at regular intervals in the first direction FD and in the second direction SD. A plurality of first lower slots 57 are arranged at regular intervals in the second direction SD. In one embodiment, the first lower slots 57 may have a similar size and shape to the first channel holes 56.

[0045] With reference to Fig. 9 and Fig. 13 is a second stack structure ST2 in which a plurality of second mold layers 63, alternately stacked with a plurality of second sacrificial layers 64, are formed on or above the first stack structure ST1. A second channel hole 66 and a second lower slot 67 are formed through the second stack structure ST2. A second channel sacrificial layer 68 is formed in each second channel hole 66, and a second lower slot 67 is formed in each second lower slot 67.

[0046] A third stack structure ST3, in which a plurality of third mold layers 73 alternately stacked with a plurality of third sacrificial layers 74 are formed on or above the second stack structure ST2. A third channel hole 76 and a third lower slot 77 are formed through the third stack structure ST3. A third channel sacrificial layer 78 is formed in each third channel hole 76, and a third slot sacrificial layer 79 is formed in each third lower slot 77.

[0047] As described above, B920, the first stack structure ST1, the second stack structure ST2, and the third stack structure ST3 in combination form a stack structure ST. The first channel hole 56, the second channel hole 66, and the third channel hole 76 are open, interconnected, or adjacent to each other in the third direction VD. Components included in the second stack structure ST2 and the third stack structure ST3 may be formed using a similar method used to form the first stack structure ST1. Components included in the second stack structure ST2 and the third stack structure ST3 may comprise materials substantially the same as the materials included in the first stack structure ST1. The topmost layer of the third stack structure ST3 is one of the plurality of third mold layers 73. The topmost layer of the third stack structure ST3 corresponds to the topmost layer of the stack structure ST.The lowest layer of the first stack structure ST1 corresponds to the lowest layer of the stack structure ST.

[0048] With reference to Fig. 9 and Fig. 14, the third channel sacrificial layer 78, the second channel sacrificial layer 68, and the first channel sacrificial layer 58 are removed, and a channel structure CH is formed in the first channel hole 56, the second channel hole 66, and the third channel hole 76. The channel structure CH extends into the second substrate 51 through the stack structure ST in the third direction VD. The sacrificial layers 58, 68, and 78 can be removed, for example, using an etching process.

[0049] The channel structure CH comprises a core layer CO, a channel pattern CP, an information storage pattern DSL and a bit connector DP. As shown in Fig. As shown in Figure 7, the information storage pattern DSL includes a tunnel layer TL, a charge trap layer CTL, and a barrier layer BL. The channel pattern CP is formed to surround the side surface and end of the core layer CO disposed in the second substrate 51. The information storage pattern DSL is formed to surround the side surface and end of the channel pattern CP disposed in the second substrate 51. The channel pattern CP is disposed between the core layer CO and the information storage pattern DSL. The bit plug DP is formed on the channel pattern CP and the core layer CO. The bit plug DP directly contacts the core layer CO and the channel pattern CP.The channel structure CH can be formed within the stack ST, for example, by forming the outermost layer first and forming each subsequent layer toward the innermost layer, such as forming the depletion layer BL, the charge-trapping layer CTL, the tunneling layer TL, the channel pattern CP, and the core layer CO in order, after which the bit plug DP is formed. The depletion layer BL, the charge-trapping layer CTL, the tunneling layer TL, the channel pattern CP, and the core layer CO are adjacent to each other throughout the stack ST, as shown in the figures.

[0050] In one embodiment, the core layer CO may comprise silicon oxide, silicon nitride, silicon oxynitride, polysilicon, or a combination thereof. The channel pattern CP may comprise a semiconductor material such as polysilicon. The bit plug DP may comprise a semiconductor material such as polysilicon. The tunnel layer TL may comprise silicon oxide, the charge trap layer CTL may comprise silicon nitride, and the barrier layer BL may comprise silicon oxide.

[0051] With reference to Fig. 9 and Fig. 15, an insulating interlayer 125 is formed on or above the stack structure ST. One or more interconnects 126 are formed in the insulating interlayer 125. A second insulating bonding layer 135 is formed on or above the insulating interlayer 125 and the interconnects 126. Second terminal pads 136 are formed in the second insulating bonding layer 135. The top surfaces of the second insulating bonding layer 135 and the second terminal pads 136 are exposed and are formed substantially in the same plane.

[0052] The connection 126 directly contacts the bit connector DP. The connection 126 may comprise a vertical connection in the third direction VD and / or a horizontal connection in the first direction FD. In one embodiment, the connection 126 comprises a bit line. The second connection pad 136 is electrically connected to the bit connector DP via the connection 126.

[0053] Each of the interlayer insulating layer 125 and the second bonding insulating layer 135 may be a single layer or a multilayer. Each of the interlayer insulating layer 125 and the second bonding insulating layer 135 may comprise at least two selected from the group consisting of Si, O, N, C, and B. Each of the interlayer insulating layer 125 and the second bonding insulating layer 135 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), low-k dielectric, high-k dielectric, or a combination thereof. In one embodiment, the second bonding insulating layer 135 comprises silicon carbonitride (SiCN).

[0054] Each of the interconnects 126 and the second pads 136 may be a single layer or a multi-layer. Each of the interconnects 126 and the second pads 136 may comprise a conductive material such as metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or a combination thereof. Each of the interconnects 126 and the second pad 136 may comprise a conductive material such as Cu, Al, Ni, Co, Ru, W, WN, Ti, TiN, Ta, TaN, Sn, Pt, Au, Ag, or a combination thereof. In one embodiment, the second pads 136 include a Cu layer formed using an electroplating process.

[0055] With reference to Fig. 9 and Fig. 16, the second substrate 51 comprising the stack structure ST is bonded B930 to the first substrate 21 comprising the circuit arrangement CS. The second insulating bonding layer 135 faces the first insulating bonding layer 35, and each of the second pads 136 faces each of the first pads 36. The first substrate 21 and the second substrate 51 may be formed on separate semiconductor wafers.

[0056] With reference to Fig. 9 and Fig. 17, the second insulating bonding layer 135 is bonded to the first insulating bonding layer 35. The second terminal pads 136 are bonded to the first terminal pads 36. The first slot sacrificial layer 59 and the channel structure CH are exposed by removing the second substrate 51. The channel pattern CP is exposed by removing an uppermost part of the information storage pattern DSL.

[0057] With reference to Fig. 9 and Fig. 18, a source line 142 is formed B940 on the stack structure ST. The source line 142 directly contacts the channel pattern CP. The first slot sacrificial layer 59 extends into the source line 142 in the third direction VD.

[0058] Source line 142 may be a single layer or a multi-layer. Source line 142 may comprise a conductive material such as polysilicon, metal, metal silicide, metal nitride, or a combination thereof. In one embodiment, source line 142 may comprise a semiconductor material such as polysilicon.

[0059] With reference to Fig. 9 and Fig. 19, by patterning the source line 142, an upper slot 157 is formed B950, which is open, connected to, or adjacent to the first lower slot 57 (B950). The first slot sacrificial layer 59 is exposed in the upper slot 157. As shown in Fig. 2 to Fig. 6, the upper slot 157 can be formed with different depths and shapes.

[0060] In one embodiment, the bottom of the upper slot 157 is formed on a plane that is lower in the third direction VD than the plane of the top end of the first slot sacrificial layer 59, as shown in Fig. 19. The bottom of the upper slot 157 may be formed at a level that is lower in the third direction VD than the level of the uppermost surface of the channel structure CH. The bottom of the upper slot 157 may be formed at a horizontal level that corresponds to the level of the uppermost surface of the channel structure CH. The bottom of the upper slot 157 may be formed at a level that is higher in the third direction VD than a level of the uppermost end of the plurality of first sacrificial layers 54. The bottom of the upper slot 157 may be formed at a level that is higher in the third direction VD than the level of the upper surface of the stacked structure ST. The bottom of the upper slot 157 may be formed at a level that is higher in the third direction VD than the level of the lowest end of the source line 142.

[0061] With reference to Fig. 9 and Fig. 20, the upper slot 157 extends in the second direction SD within the source line 142. In a plan view including the first direction FD and the second direction SD, the aspect ratio of the upper slot 157 may be 100 times to 1e+100 times when comparing the measurement of the upper slot 157 in the second direction SD with the measurement of the upper slot 157 in the first direction FD.

[0062] With reference to Fig. 9 and Fig. 21, the lower slot 157L B950 is formed with a first lower slot 57, a second lower slot 67, and a third lower slot 77 open, connected to, or adjacent to the upper slot 157 when the first slot sacrificial layer 59, the second slot sacrificial layer 69, and the third slot sacrificial layer 79 are removed. The sacrificial layers 59, 69, and 79 may be removed, for example, using an etching process.

[0063] With reference to Fig. 9, Fig. 22 and Fig. 25, the first lower slot 57, the second lower slot 67, and the third lower slot 77 are radially expanded in one embodiment. The first lower slot 57, the second lower slot 67, and the third lower slot 77 form the lower slot 157L. The upper slot 157 and the lower slot 157L form the slot 157SLT. The lower slot 157L is open, connected to, or adjacent to the upper slot 157. A plurality of first lower slots 57, which, as in Fig. 12, are aligned in the second direction SD, are open, connected to each other, or adjacent to each other after performing a lateral expansion, which includes an expansion in the first direction FD and the second direction SD or an expansion in the radial direction. The plurality of first lower slots 57 can be expanded, for example, using an etching process. The dashed lines in Fig. 22 and Fig. 25 show the shape of the lower slots 57, 67, and 77 before expansion, and the solid lines show the shape of the lower slots 57, 67, and 77 after expansion. A plurality of second lower slots 67 and a plurality of third lower slots 77 can be expanded using a method similar to the method for expanding the first lower slots 57, and are open, connected, or adjacent to each other in the second direction SD.

[0064] The slot 157SLT extends completely through the source line 142 and the stacked structure ST in the third direction VD. The edges of each of the plurality of first sacrificial layers 54, the plurality of second sacrificial layers 64, and the plurality of third sacrificial layers 74 are exposed in the lower slot 157L.

[0065] With reference to Fig. 9 and Fig. 23, a plurality of gap regions 54G, 64G, and 74G are formed by removing B960 the plurality of first sacrificial layers 54, the plurality of second sacrificial layers 64, and the plurality of third sacrificial layers 74. The plurality of gap regions 54G, 64G, and 74G include a plurality of first gap regions 54G, a plurality of second gap regions 64G, and a plurality of third gap regions 74G. The sacrificial layers 54, 64, and 74 may be removed, for example, using an etching process.

[0066] With reference to Fig. 9 and Fig. 24, a plurality of horizontal electrodes 155, 165, and 175 are formed in the plurality of gap regions 54G, 64G, and 74G. The plurality of horizontal electrodes 155, 165, and 175 include a plurality of first horizontal electrodes 155, a plurality of second horizontal electrodes 165, and a plurality of third horizontal electrodes 175.

[0067] Each of the plurality of horizontal electrodes 155, 165, and 175 may be a single layer or a multilayer. The plurality of horizontal electrodes 155, 165, and 175 may comprise a conductive material such as metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or a combination thereof. The plurality of horizontal electrodes 155, 165, and 175 may comprise a conductive material such as W, WN, Ti, TiN, Ta, TaN, Ru, or a combination thereof. In one embodiment, the plurality of horizontal electrodes 155, 165, and 175 comprise W.

[0068] With reference to Fig. 9 and Fig. 25, the lower slot 157L extends in the second direction SD. In a plan view encompassing the first direction FD and the second direction SD, the aspect ratio of the lower slot 157L may be 100 times to 1e+100 times when comparing the measurement of the upper slot 157 in the second direction SD with the measurement of the upper slot 157 in the first direction FD. The sidewalls of the lower slot 157L may have a wave shape in the second direction SD.

[0069] With reference to Fig. 9 and Fig.1, an insulating isolation pattern 250 is formed in the slot 157SLT B970. The top surface of the source line 142 and the top surface of the insulating isolation pattern 250 are formed substantially in the same plane. The insulating isolation pattern 250 includes an upper portion 250U and a lower portion 250L. The lower portion 250L is adjacent to the upper portion 250U in the third direction VD. The lower portion 250L may include a first lower portion 250L1, a second lower portion 250L2, and a third lower portion 250L3.

[0070] The insulating isolation pattern 250 may be a single layer or a multi-layer. The insulating isolation pattern 250 may comprise a material comprising at least two selected from the group consisting of Si, O, N, C, and B. The insulating isolation pattern 250 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), a low-k dielectric, a high-k dielectric, or a combination thereof.

[0071] According to the embodiment of the disclosed technology, the stacked structure ST is bonded to the circuit assembly CS (B930), and after removing the sacrificial layers 54, 64, and 74 in the stacked structure ST, the horizontal electrodes 155, 165, and 175 are formed (B960). Physical deformations such as warpage can be relatively reduced in the stacked structure ST by using the sacrificial layers 54, 64, and 74 and the second substrate 51 in forming the horizontal electrodes 155, 165, and 175 after bonding the stacked structure ST to the circuit assembly CS. Bonding defects can also be reduced when the deformation is reduced.Since the bonding B930 of the stack structure ST formed on the second substrate 51 to the circuit pattern CS formed on the first substrate 21 is performed before the formation B960 of the horizontal electrodes 155, 165, and 175, the coupling strength of the first insulating bonding layer 35 and the second insulating bonding layer 135 can be increased, and the coupling strength of the first pad 36 and the second pad 136 can also be increased.

[0072] In one embodiment, a method of forming a semiconductor device may include bonding a stacked structure to a circuit assembly. The stacked structure may include a plurality of mold layers alternately stacked with a plurality of sacrificial layers. After bonding the stacked structure to the circuit assembly, the plurality of sacrificial layers in the stacked structure may be removed, and a plurality of electrodes may be formed. An insulating isolation pattern may be formed in a slot extending through the stacked structure.

[0073] In one embodiment, a method of forming a semiconductor device may include bonding a stacked structure to a circuit assembly. The stacked structure may include a plurality of mold layers alternately stacked with a plurality of sacrificial layers. A source line may be formed on the stacked structure. A channel structure may be formed extending through the stacked structure into the source line. An insulating isolation pattern may be formed in a slot extending through the source line and the stacked structure. The insulating isolation pattern may include a first portion adjacent to the source line and a second portion adjacent to the stacked structure. The insulating isolation pattern may include a convergence interface between the first portion and the second portion.The convergence interface may be formed between one end of the channel structure disposed in the source line and a surface of the plurality of electrodes closest to the source line.

[0074] In one embodiment, a semiconductor device may include a stacked structure formed on a first semiconductor wafer and including a plurality of insulating layers alternately stacked with a plurality of electrode layers that have replaced a plurality of sacrificial layers. It may include circuitry formed on a second wafer and connected to the stacked structure prior to forming the plurality of electrodes. A source line may be disposed on the stacked structure. A first insulating layer of the plurality of insulating layers may be closest to the source line. It may include a channel structure extending through the stacked structure into the source line. One end of the channel structure may extend into the source line. An insulating isolation pattern may be disposed in a slot extending through the source line and the stacked structure.The insulating isolation pattern may include a convergence interface between a first portion adjacent to the source line and a second portion adjacent to the stacked structure. The convergence interface may be arranged at a level within the source line or the first insulation layer.

[0075] Although embodiments of the disclosure are described for illustrative purposes, one skilled in the art will understand that various changes, additions, and substitutions are possible without departing from the scope and spirit of the disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered only in a descriptive sense and not as a limitation on the technological scope. The technological scope of the disclosure is not limited by the embodiments and the accompanying drawings. All changes within the meaning and range of equivalence of the claims are included within their scope.

Claims

[1] A semiconductor device comprising: a circuit arrangement; a stack structure bonded to the circuit assembly and comprising a plurality of mold layers alternately stacked with a plurality of electrodes; a source line arranged on the stack structure; a channel structure extending through the stack structure into the source line; and an insulating isolation pattern arranged in a slot extending through the source line and the stack structure; wherein the insulating isolation pattern comprises a first portion adjacent to the source line and a second portion adjacent to the stack structure; wherein the insulating isolation pattern comprises a convergence interface between the first portion and the second portion; and wherein the convergence interface is arranged between an end of the channel structure disposed in the source line and a surface of the plurality of horizontal electrodes closest to the source line. [2] The semiconductor device according to claim 1, wherein a surface of the insulating isolation pattern and a surface of the source line are formed substantially in the same plane. [3] The semiconductor device of claim 1, wherein the convergence interface is disposed between the end of the channel structure and a first mold layer of the plurality of mold layers, the first mold layer being closer to the source line than any other of the plurality of mold layers. [4] The semiconductor device according to claim 1, wherein the first portion of the insulating isolation pattern has a width different from a width of the second portion when the first portion is adjacent to the second portion, and the convergence interface comprises a step. [5] The semiconductor device according to claim 1, wherein a side surface of the first portion of the insulating isolation pattern has a different inclination than a side surface of the second portion of the insulating isolation pattern. [6] A semiconductor device according to claim 1, wherein the first portion of the insulating insulation pattern has an inverted trapezoidal shape, and wherein the second portion of the insulating insulation pattern has a trapezoidal shape. [7] The semiconductor device according to claim 1, further comprising: a first insulating bonding layer disposed on the circuit assembly; a first terminal surface in the first insulating bonding layer; a second insulating bonding layer disposed between the first insulating bonding layer and the stack structure and connected to the first insulating bonding structure; and a second terminal surface disposed in the second insulating bonding layer and connected to the first terminal surface. [8] A semiconductor device according to claim 7, further comprising: an insulating intermediate layer between the first insulating bonding layer and the stack structure; and a compound arranged in the insulating interlayer and connected to the channel structure. [9] The semiconductor device according to claim 8, wherein the second portion of the insulating isolation pattern extends into the insulating interlayer. [10] A semiconductor device according to claim 8, wherein the channel structure comprises: a channel pattern connected to the source line; and a bit connector that contacts the channel pattern, wherein the connection contacts the bit connector on a first level. [11] The semiconductor device according to claim 10, wherein the interconnection has a first surface on the first level and a second surface on a second level and opposite to the first surface, and wherein one end of the insulating isolation pattern is disposed between the first level and the second level. [12] A semiconductor device according to claim 10, wherein the channel structure further comprises a core layer extending through the stack structure into the source line, wherein the channel pattern surrounds a side surface and an end of the core layer, and where the channel pattern directly contacts the source line. [13] Semiconductor device according to claim 10, wherein the channel structure further comprises an information storage pattern between the channel pattern and the stack structure, and wherein one end of the information storage pattern contacts the source line. [14] A semiconductor device according to claim 13, wherein the information storage pattern comprises: a tunnel layer on the channel pattern; a charge trap layer on the tunnel layer; and a barrier layer on the charge trap layer; wherein the charge trapping layer is arranged between the tunneling layer and the barrier layer. [15] Semiconductor device comprising: a stacked structure having a plurality of mold layers alternately stacked with a plurality of electrodes; a source line arranged on the stack structure; a channel structure extending through the stack structure into the source line; and an insulating isolation pattern arranged in a slot extending through the source line and the stack structure, wherein the insulating isolation pattern comprises a first portion adjacent to the source line and a second portion adjacent to the stack structure; wherein a side surface of the insulating insulation pattern comprises a convergence interface between the first portion and the second portion; and wherein the convergence interface is arranged between an end of the channel structure disposed in the source line and a surface of the plurality of electrodes closest to the source line. [16] The semiconductor device according to claim 15, wherein the plurality of electrodes comprises: at least one source select line closest to the source line; at least one drain select line closest to a bit connector; and a plurality of word lines between the at least one source select line and the at least one drain select line. [17] The semiconductor device according to claim 15, further comprising: an insulating interlayer between a substrate and the stack structure; and a compound arranged in the insulating interlayer and connected to the channel structure. [18] A semiconductor device according to claim 17, wherein the channel structure comprises: a channel pattern connected to the source line; an information storage pattern between the channel pattern and the stack structure; and a bit connector that contacts the channel pattern; where the connection contacts the bit connector. [19] The semiconductor device according to claim 18, wherein one end of the insulating isolation pattern is disposed within the insulating interlayer. [20] A semiconductor device according to claim 18, wherein the information storage pattern comprises: a tunnel layer on the channel pattern; a charge trap layer on the tunnel layer; and a barrier layer on the charge trap layer; wherein the charge trapping layer is arranged between the tunneling layer and the barrier layer.

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