Unit cell arrangement and printed circuit board

Abstract

The invention relates to a unit cell arrangement and a printed circuit board. The unit cell arrangement comprises a first unit cell assembly, a dielectric layer arranged vertically in contact with the first unit cell assembly, and a second unit cell assembly arranged vertically in contact with the dielectric layer, wherein a first unit cell of the first unit cell assembly is electrically connected to a third unit cell of the second unit cell assembly by means of at least one electrically conductive connecting element on a first contacting element arranged on the first unit cell and the third unit cell, and wherein a second unit cell of the first unit cell assembly is connected to a fourth unit cell of the second unit cell assembly by means of at least one second electrically conductive connecting element on a second contacting element.The second contacting element is electrically connected to the second unit cell and the fourth unit cell.

Description

[0001] The invention relates to a unit cell arrangement and a printed circuit board.

[0002] Printed circuit boards (PCBs) are used in most high-speed / frequency or sensitive electronic systems. In recent decades, the data rate and operating frequency of such electronic systems have steadily increased. This increase brings with it qualitative challenges, particularly the prevention of noise to ensure optimal operation of the electrical system and to prevent interference with the surrounding environment.

[0003] To realize high-quality electronic systems, electromagnetic compatibility (EMC / EMI), power supply integrity (PI), and signal integrity (SI) are evaluated in particular. A large proportion of electronic circuits are implemented on printed circuit boards (PCBs), and electronic systems often incorporate a multitude and / or different types of PCBs. It is important to note that electronic circuits and enclosures should not only refrain from emitting electromagnetic radiation into the environment but should also be robust against incoming signals. The presence of simultaneous switching noise (SSN), also known as noise, ground bounce noise (GBN), or delta-I noise, is unavoidable in power distribution and supply networks (PDNs) that utilize power and ground planes; however, the overall noise level should be kept as low as possible.

[0004] Since the power supply and ground planes used in prior art printed circuit boards form a cavity structure, any current change or the presence of external or internal noise can lead to resonant modes in this cavity and / or excite it to vibrations, which in turn increases the noise, which can also propagate between the power supply and ground planes. Furthermore, noise propagation between the power and ground planes can cause unwanted radiation emissions from the edges of the printed circuit board, which can disrupt the operation of external systems.

[0005] The aforementioned problem is further exacerbated in the case of multilayer printed circuit boards used in the prior art, on which a large number of housings and electronic components are mounted. Consequently, these known printed circuit boards cannot achieve the required robustness against external disturbances and interference and / or the desired performance in many applications.

[0006] One of the most common solutions for reducing noise, especially SSN, and eliminating the resulting radiation emissions is the use of decoupling capacitors. It should be noted that the inductance resulting from the metal connections and the resistance present in series with these capacitors lead to an increase in impedance at high frequencies, rendering these capacitors ineffective. Therefore, this method is limited to the frequency range of a few hundred MHz and does not offer a satisfactory solution.

[0007] The use of embedded capacitors is another effective method for reducing noise, but this is not practical due to the high manufacturing costs of the correspondingly designed printed circuit boards.

[0008] Another well-known solution for noise reduction is the use of electromagnetic bandgap structures (EBGs). EBGs are typically implemented in planar and mushroom configurations. The three-layer mushroom configuration is difficult to manufacture and expensive. With planar configurations, the design and the cutting of power or ground planes can lead to interruptions in the signal return path, resulting in signal integrity issues or increased radiation from the layers. Furthermore, planar EBGs cannot be used in layers mounted on metallic enclosures. Consequently, the signal quality decreases compared to the reference structure. Another disadvantage of the EBG structure is that optimal response requires metal feedthroughs between the metal layers, which can add further complexity.

[0009] The use of absorbent material at the edges of a printed circuit board or a printed circuit board segment is another known solution for reducing noise, which is not practical due to the high production costs.

[0010] Another approach to reducing noise is the use of seams and short circuits across connections. This solution reduces noise at the edges of a printed circuit board or board segment, but not between the power and ground planes, which is why it does not significantly improve performance.

[0011] Another known solution for reducing edge noise is the placement of resistors between the power and ground planes at the edges of the printed circuit board. Such systems are disclosed in DE 10 2006 031 037 B3, DE 10 2007 036 698 B4, and US 7 674 988 B2, which propose a solution using special structures for shielding printed circuit boards and reducing radiation emissions, and also in US 7 786 621 B2, DE 10 2005 050 147 B4, and DE 10 2005 050 147 B8, which propose the use of nonlinear or time-varying elements between the power supply and ground planes, shifting the noise power to higher frequencies and reducing it within the frequency range of the EMI standard.

[0012] No efficient solution for the design of printed circuit boards or circuit board segments is known using existing methods and devices, which adequately addresses all aspects of electromagnetic compatibility (EMC / EMI), power supply integrity (PI), and signal integrity (SI). In particular, it is important that the noise and EMC / EMI of the circuit boards are as low as possible without significantly impairing power supply and signal integrity.

[0013] The purpose of the invention is to improve the state of the art.

[0014] The problem is solved by a unit cell arrangement according to claim 1.

[0015] The unit cell arrangement, also called a printed circuit board segment, is characterized in particular by a new structure for the power distribution and power supply network. Advantageously, the unit cell arrangement according to the invention reduces radiation emission emanating from the unit cell arrangement, in particular far- and near-field interference emission, also called noise, and increases the robustness of the unit cell arrangement against external emissions.

[0016] The device according to the invention advantageously reduces electromagnetic interference by reducing far-field and near-field radiation from edges of the unit cell arrangement through its specific design.

[0017] Furthermore, the inventive design of the unit cell arrangement advantageously increases the resistance of the unit cell arrangement and of a printed circuit board constructed from the inventive unit cell arrangement against external disturbances, such as radiation emissions.

[0018] The inventive design of the unit cell arrangement advantageously achieves the required functionality without significantly increasing the complexity of the construction process, thereby avoiding unnecessary increases in manufacturing costs.

[0019] The inventive design of the unit cell arrangement advantageously has only very minor negative effects on signal integrity (SI), switching noise (SSN) and power supply integrity (PI), and in some cases even improves them.

[0020] A key aspect of the invention is that the power supply in a multilayer circuit board constructed from circuit board segments is routed in such a way as to reduce noise.

[0021] The following terms will be explained:

[0022] A "unit cell array" is understood to be, in particular, an element that can be used as a printed circuit board, either alone or in combination with a multitude of unit cell arrays. Electrically conductive traces and / or electrical components can be applied to the unit cell array.

[0023] The unit cell assembly comprises, in particular, three layers: a first unit cell assembly, a dielectric layer arranged in a vertical direction and contacting the first unit cell assembly, and a second unit cell assembly arranged in a vertical direction and contacting the dielectric layer. Further layers, in particular adhesive layers or the like, may be arranged between or additionally between the layers of the unit cell assembly. The orientation of the layers is essentially irrelevant.

[0024] The term "first unit cell array" refers in particular to an arrangement of a first unit cell and a second unit cell arranged laterally adjacent to the first unit cell at a distance from it. The first unit cell is specifically configured as a power supply cell. The second unit cell is specifically configured as a ground cell.

[0025] The term "second unit cell array" refers in particular to an arrangement of a third unit cell and a fourth unit cell arranged laterally adjacent to the third unit cell at a distance from it. The third unit cell is specifically configured as a power supply cell. The fourth unit cell is specifically configured as a ground cell.

[0026] In the unit cell arrangement, the first unit cell of the first unit cell assembly is electrically connected to the third unit cell of the second unit cell assembly, in particular by means of at least one electrically conductive connecting element. The first electrically conductive connecting element is arranged, in particular, on at least one contacting element of the first unit cell and on at least one contacting element of the third unit cell. Additionally or alternatively, the first electrically conductive connecting element penetrates the dielectric layer that exists between the at least one contacting element of the first unit cell and the at least one contacting element of the third unit cell.

[0027] A first form, also called contour, of the first unit cell, which is characterized in particular by an arrangement of the at least one contacting element at an edge of the first unit cell and / or which includes the at least one contacting element of the first unit cell, corresponds in particular to a third form of the third unit cell, which is characterized in particular by an arrangement of the at least one contacting element at an edge of the third unit cell and / or which includes the at least one contacting element of the third unit cell, such that the at least one contacting element of the first unit cell and the third unit cell are at least partially overlapping in the unit cell arrangement.

[0028] In the unit cell arrangement, the second unit cell of the first unit cell assembly is additionally or alternatively electrically connected to the fourth unit cell of the second unit cell assembly, in particular by means of at least one second electrically conductive connecting element. The second electrically conductive connecting element is specifically arranged on at least one contacting element of the second unit cell and on at least one contacting element of the fourth unit cell. Additionally or alternatively, the second electrically conductive connecting element penetrates the dielectric layer that exists between the at least one contacting element of the second unit cell and the at least one contacting element of the fourth unit cell.

[0029] A second form of the second unit cell, which is characterized in particular by an arrangement of the at least one contacting element on the second unit cell and / or which includes the at least one contacting element of the second unit cell, corresponds in particular to a fourth form of the fourth unit cell, which is characterized in particular by an arrangement of the at least one contacting element on the fourth unit cell and / or which includes the at least one contacting element of the fourth unit cell, such that the at least one contacting element of the second unit cell and the fourth unit cell are at least partially overlapping in the unit cell arrangement.

[0030] The shape of the first unit cell and the third unit cell correspond in particular to the shape of the second unit cell and the fourth unit cell in such a way that the at least one contacting element of the first unit cell and the third unit cell in the unit cell assembly does not substantially cover the at least one contacting element of the second unit cell and the fourth unit cell.

[0031] At least one contact element of the first unit cell projects from at least one boundary surface of the first unit cell. Additionally or alternatively, a plurality of contact elements can project from the boundary surface of the first unit cell, a further contact element can project from at least one further boundary surface of the first unit cell, and / or at least one contact element can project from each of a plurality of boundary surfaces of the first unit cell, and / or a plurality of contact elements can project from the plurality of boundary surfaces of the first unit cell. The same applies to the second unit cell, the third unit cell, the fourth unit cell, and / or further unit cells.

[0032] Advantageously, unit cells can be implemented as first standard elements, which, for placement at the edge of a printed circuit board, have no contact elements on at least one edge surface and / or on two edge surfaces, and / or as second standard elements, which are designed for placement far from the edge and, in particular, have contact elements on all edge surfaces. This allows for simple production-related manufacturability.

[0033] Further details can be found in the dependent claims.

[0034] In another aspect, the problem is solved by a printed circuit board according to claim 10.

[0035] The printed circuit board comprises, in particular, a plurality of unit cell arrangements according to the invention. The unit cells of adjacent unit cell arrangements, designed as power supply cells, are electrically connected to one another, in particular by means of electrically conductive connecting elements and using contact elements arranged on the unit cells. Additionally or alternatively, the unit cells of adjacent unit cell arrangements, designed as ground cells, are electrically connected to one another, in particular by means of further electrically conductive connecting elements and further contact elements arranged on the unit cells.

[0036] In one application of the printed circuit board, a current source is applied to the board to simulate an external source of interference, thereby initiating a magnetic current Ms at the edges of the board, which, according to Huygens' law, leads to interference emission radiated from the edges of the board. It holds that F→(r→)=μh4Π∫cMs(x',y')⋅e−lk0RRds' Erad→=−1ε∇×F→ Hrad→=−1jωμ∇×Erad→ , where Ms is the magnetic current at the edges of the structure and Erad→ and Hrad→ The corresponding radiated electric and magnetic fields are involved. The simulated external interference source initiates a specific polarity in each unit cell. On a state-of-the-art printed circuit board with essentially parallel current-carrying traces, the interference source generates polarities acting essentially in the same direction, thereby increasing the intensity of the entire electric field and thus the noise or interference emission.

[0037] When a similar interference source is applied to a printed circuit board according to the invention, the "wound" printed circuit board structure, realized by the arrangement of the unit cells, causes a change in the induced polarity between the power supply and ground individual cells in each unit cell from the upper layer to the lower layer. In other words, when an interference source is applied, a different polarity is generated in a main observation unit cell than in all neighboring cells of the main observation unit cell due to the reciprocal arrangement of the power supply and ground plates. The interacting, opposing polarities reduce noise, also called resulting radiation emission. In particular, the radiated emission in the far-field region and / or in the near-field region is reduced.

[0038] It should be noted that the source of interference can act at any position on the circuit board and / or at multiple positions on the circuit board. Additionally or alternatively, the current present at the current-carrying unit cells can be equal to and / or different from the current present as the source of interference.

[0039] Additionally, the direct connection of the decoupling capacitors between the current-carrying and ground-carrying unit cells (without vias) can advantageously reduce the series impedance of capacitors, which lowers the impedance of a power network of the printed circuit board at very high frequencies.

[0040] In this way, a power distribution and supply network of the printed circuit board is realized by means of the structure and arrangement of the unit cell arrangements, resulting in a printed circuit board which advantageously emits low interference emissions and is robust against the influence of external interference emissions.

[0041] Further combinations of features and advantages correspond to the explanations regarding the first-mentioned aspect.

[0042] The invention will now be explained using exemplary embodiments. These will show... Fig. 1 a schematic representation of a first unit cell cluster, Fig. 2 a schematic representation of a side view of a first unit cell arrangement, Fig. 3 a schematic representation of a top view of the first unit cell arrangement, Fig. 4 a schematic representation of a top view of a printed circuit board, Fig. 5 a schematic representation of a side view of the printed circuit board, and Fig. 6 a diagram of a disturbance emission measurement.

[0043] A unit cell assembly 101 comprises a first unit cell 103 and a second unit cell 105. The first unit cell 103 and the second unit cell 105 contain copper, with a copper thickness of 35 µm. The length and width of the first unit cell 103 and the second unit cell 105 are 22 mm.

[0044] The first unit cell 103 is designed to carry current and has six first contact tongues 107a arranged along a right edge. A first bore 109a is arranged at each of the first contact tongues 107a. The second unit cell 105 is designed to carry ground and has five second contact tongues 107b arranged along a left edge. A second bore 109b is arranged at each of the second contact tongues 107b. The shapes of the first unit cell 103 and the second unit cell 105 correspond such that the adjacent unit cells 103 and 105 do not touch each other, but the first bores 109a and second bores 109b essentially intersect a common central axis.

[0045] The first unit cell arrangement 100 comprises the first unit cell assembly 101, a dielectric layer 113 arranged beneath the first unit cell assembly 101, and a second unit cell arrangement 201 arranged beneath the dielectric layer 113. The dielectric layer 113 is an FR4 dielectric with a permeability coefficient of 4.3 and a loss tangent of 0.02. The thickness of the first unit cell arrangement 100 is 1 mm.

[0046] The second unit cell assembly 201 includes a third unit cell 203 and a fourth unit cell 205. The third unit cell 203 has three contact tongues 107c and is essentially designed like the first unit cell 103, and the fourth unit cell 205 has four contact tongues (not shown) and is essentially designed like the second unit cell 105.

[0047] The width and length of each contact tongue 107a, 107b, 107c is substantially 1 mm. The distance between adjacent contact tongues 107a, 107b, 107c is 2.8 mm. The first and second bores 109a, 109b are located substantially centrally on the contact tongues 107a, 107b, 107c. The radius of the first and second bores 109a, 109b is 0.25 mm.

[0048] All dimensions mentioned can vary depending on the application and conditions. The disclosed dimensions correspond in particular to one possible embodiment. Scaling can be carried out, in particular, taking into account a substantially similar ratio between the dimensions, whereby scaling without maintaining the ratios is also not limiting for the invention. In particular, a change in the number of contact tongues can lead to dimensions that deviate significantly from the scaled dimensions of the dimensions shown in the embodiment.

[0049] The first unit cell 103 and the third unit cell 203 are electrically connected by means of first connecting elements 111a at their respective overlapping first contact tongues 107a of the first unit cell 103 and third contact tongues 107c of the third unit cell 203. The plurality of first connecting elements 111a are arranged within the first bore 109a and the third bores (not shown) on the third unit cell 203 and each penetrates the dielectric layer 113 between the first contact tongues 107a of the first unit cell 101 and the third contact tongues 107c of the third unit cell 203.

[0050] The second unit cell 105 and the fourth unit cell 205 are electrically connected to each other at their overlapping third contact tongues 107b and fourth contact tongues (not shown) by means of second connecting elements 111b. The plurality of second connecting elements 111b are arranged within the second bore 109b of the second unit cell 105 and in the fourth bores (not shown) located on the contact tongues of the fourth unit cell 205, and each penetrates the dielectric layer 113 between the second contact tongues 107b of the second unit cell 105 and the four contact tongues of the fourth unit cell 205.

[0051] A printed circuit board 301 comprises an upper layer with 16 unit cells 303, 305, 313, 315, 323, 325, a dielectric layer 113, and a lower layer with 16 unit cells 303, 305, 313, 315, 323, 325. The layers are bonded together. The printed circuit board 301 has a width and length of 88 mm and a thickness of 1 mm. The dimensions of the printed circuit board 301 are the same as those of the unit cell assembly 101.

[0052] The multitude of unit cells 303, 305, 313, 315, 323, 325 are designed as current-carrying corner element unit cell 303, mass-carrying edge element unit cell 305, current-carrying edge element unit cell 313, mass-carrying corner element unit cell 315, current-carrying central element unit cell 323 or mass-carrying central element unit cell 325 and are arranged to each other in such a way that in a layer each current-carrying unit cell 303, 313, 323 is only adjacent to mass-carrying unit cells 305, 315, 325 and each mass-carrying unit cell 305, 315, 325 is only adjacent to current-carrying unit cells 303, 313, 323. In addition, the unit cells 303, 305, 313, 315, 323, 325 of the lower layer are arranged such that a mass-carrying unit cell 305, 315, 325 is located under a current-carrying unit cell 303, 313, 323 and a current-carrying unit cell 303, 313, 323 is located under a mass-carrying unit cell 305, 315, 325.Finally, the unit cells 303, 305, 313, 315, 323, 325 are arranged such that contact tongues 107a, 107b, 107c are present at the edges of adjacent unit cells 303, 305, 313, 315, 323, 325 and no contact tongues protrude from the outer edge of the circuit board 301.

[0053] In particular, at all contact tongues of the unit cells 303, 305, 313, 315, 323, 325 of the printed circuit board 301, the respective current-carrying unit cells 303, 313, 323 are electrically connected to each other, and the respective ground-carrying unit cells 305, 315, 325 are electrically connected to each other by means of connecting elements that penetrate the dielectric layer 113. In this way, current is conducted along a predefined path through the printed circuit board 301.

[0054] The effectiveness of the printed circuit board 301 according to the invention can be seen from the diagram in Fig.6. The ordinate shows the sensor-determined maximum noise E at a distance of 3 meters (far field) in dB, and the abscissa shows the frequency in Hz. Graph 1 shows the measurement results of a printed circuit board 301 subjected to an interference source generated by a CST Studio Suite 3D full-wave electromagnetic simulator. Graph 2 shows the measurement results of a conventional printed circuit board according to the prior art, subjected to the same interference source generated by a CST Studio Suite 3D full-wave electromagnetic simulator as printed circuit board 301. The diagram demonstrates a reduction in interference emissions from the printed circuit board according to the invention. Reference symbol list 100 first unit cell arrangement 101 unit cell cluster 103 first unit cell 105 second unit cell 107a first contact tongue 107b second contact tongue 107c third contact tongue 109a first borehole 109b second borehole 111a first connecting element 111b second connecting element 113 dielectric layer 201 Unit cell arrangement 203 third unit cell 205 fourth unit cell 301 circuit board 303 current-carrying corner element unit cell 305 mass-carrying edge element unit cell 313 current-carrying edge element unit cell 315 grounded corner element unit cell 323 current-carrying central element unit cell 325 mass-carrying central element unit cell QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] DE 10 2006 031 037 B3

[0011] DE 10 2007 036 698 B4

[0011] US 7 674 988 B2

[0011] US 7 786 621 B2

[0011] DE 10 2005 050 147 B4

[0011] DE 10 2005 050 147 B8

[0011]

Claims

[1] Unit cell arrangement (100) comprising a first unit cell assembly (101), a dielectric layer (113) arranged in a vertical direction contacting the first unit cell assembly (101), and a second unit cell assembly (201) arranged in a vertical direction contacting the dielectric layer (113), wherein the first unit cell assembly (101) comprises a first unit cell (103) configured as a power supply cell and a second unit cell (105) configured as a ground cell spaced laterally next to the first unit cell (103), wherein the second unit cell assembly (201) comprises a third unit cell (203) configured as a power supply cell and a fourth unit cell (205) configured as a ground cell spaced laterally next to the third unit cell (203),wherein the first unit cell (103) is arranged vertically above the fourth unit cell (205) and the second unit cell (105) is arranged vertically above the third unit cell (203), characterized by , that the first unit cell (103) is electrically connected to the third unit cell (203) by means of at least one first electrically conductive connecting element (111a) on a first contacting element (107a, 107c) arranged on the first unit cell (103) and the third unit cell (203), and that the second unit cell (105) is electrically connected to the fourth unit cell (205) by means of at least one second electrically conductive connecting element (111b) on a second contacting element (107b) arranged on the second unit cell (105) and the fourth unit cell (205). [2] Unit cell arrangement (100) according to the preceding claim, wherein each of the first unit cell (103), the second unit cell (105), the third unit cell (203) and the fourth unit cell (205) each has a base plate with at least three edges, wherein at least one sub-element of the first contacting element (107a, 107c) is arranged to project from at least a first edge of the base plate of the first unit cell (103) and from a first edge of the base plate of the third unit cell (203), and wherein at least one sub-element of the second contacting element (107b) is arranged to project from a first edge of the base plate of the second unit cell (105) and from a first edge of the base plate of the fourth unit cell (205), wherein the sub-elements of the first contacting element (107a,107c) in the unit cell arrangement (100) are each facing each other and at least partially overlapping each other, and the sub-elements of the second contacting element (107b) in the unit cell arrangement (100) are each facing each other and at least partially overlapping each other. [3] Unit cell arrangement (100) according to the preceding claim, wherein a contour of the first unit cell (103) corresponds to a contour of the second unit cell (105) such that a first slot with a predefined shape is realized between the first unit cell (103) and second unit cell (105) arranged side by side, and wherein a contour of the third unit cell (203) corresponds to a contour of the fourth unit cell (205) such that a second slot with a predefined shape is realized between the third unit cell (203) and fourth unit cell (205) arranged side by side. [4] Unit cell arrangement (100) according to the preceding claim, wherein the first slot and / or the second slot has a width of 0.001 mm to 0.01 mm and is in particular zigzag-shaped. [5] Unit cell arrangement (100) according to claim 2, wherein the respective base plate of the first unit cell (103), the second unit cell (105), the third unit cell (203) and the fourth unit cell (205) comprises an electrically conductive material, in particular copper. [6] Unit cell arrangement (100) according to claim 2 or 5, wherein the respective base plate of the first unit cell (103), the second unit cell (105), the third unit cell (203) and / or the fourth unit cell (205) is square, in particular with an edge length of 15 mm to 30 mm, in particular 21.25 mm, and has a thickness of 20 µm to 50 µm, in particular 35 µm. [7] Unit cell arrangement (100) according to claim 2, wherein the sub-elements of the first contacting element (107a, 107c) and / or the sub-elements of the second contacting element (107b) each have a width of 0.5 mm to 2 mm, in particular 1 mm and a length of 0.5 mm to 2 mm, in particular 1 mm, and a through-hole (109a, 109b) with a radius of 0.1 mm to 0.5 mm, in particular 0.25 mm. [8] Unit cell arrangement (100) according to claim 2 or 7, wherein at least on the first edge of the first unit cell (103) and / or at least on the first edge of the third unit cell (203) more than three, in particular more than five, possibly exactly nine sub-elements of the first contacting element (107a, 107b) project and / or wherein at least on the first edge of the second unit cell (105) and / or at least on the first edge of the fourth unit cell (205) more than three, in particular more than five, possibly exactly nine sub-elements of the first contacting element (107c) project. [9] Unit cell arrangement (100) according to the preceding claim, wherein the partial elements of the first contacting element (107a, 107b) or the second contacting element (107c) arranged at the respective first edge of the first unit cell (103), the second unit cell (105), the third unit cell (203) and / or the fourth unit cell (205) have a distance from each other of 1 mm to 2 mm, in particular 1.35 mm. [10] Printed circuit board (301) comprising a plurality of unit cell arrangements (100) according to one of the preceding claims, wherein unit cells (103, 203) designed as power supply cells of adjacent unit cell arrangements (100) are electrically connected to each other by means of electrically conductive connecting elements (111a, 111b) and contacting elements (107a, 107b) and wherein unit cells (105, 205) designed as ground cells of adjacent unit cell arrangements (100) are electrically connected to each other by means of further electrically conductive connecting elements (111c) and further contacting elements (107c).

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