MODE REGISTER UPDATE (MRUPD)-MODUS

Abstract

A configuration register update mode can be implemented as MRUPD (Mode Register Update) mode for a DRAM (Dynamic Random Access Memory) device. In one example, MRUPD can also be used to update a RCD (Registering Clock Driver). In update mode, the memory device (either the RCD or the DRAM) can configure any number of configuration registers using in-band register write operations. These in-band register write operations can be used to configure the DFE (Decision Feedback Equalization) settings, as well as other configuration settings for non-DFE configurations of a memory device interface.

Description

PRIORITY

[0001] This application is a non-provisional application of U.S. Provisional Application No. 63 / 596,257, filed November 4, 2023, and claims priority thereto. TECHNICAL FIELD

[0002] The descriptions refer generally to computer memory and specifically to the training of memory interfaces. BACKGROUND OF THE INVENTION

[0003] A memory controller can use MRW (Mode Register Writes) to set the DRAM device configuration and perform some training. The memory controller must traditionally train the CA bus before a command such as MRW can be reliably sent to the DRAM device. Therefore, programming the DRAM (Dynamic Random Access Memory) before the CA bus (Command / Address Bus) and DQ bus (Data Bus) are trained is performed using a sideband bus such as the SMBus (System Management Bus). Sideband buses operate at a very slow speed (on the order of megahertz (MHz)) compared to the CA bus and DQ bus (on the order of gigahertz (GHz)). Using a sideband bus for training can introduce significant training delays.

[0004] Available DRAM devices have multiple training phases. Training is performed using the MPC (Multipurpose Command) operation, which requires an MPC opcode table. The MPC instruction has access to a limited number of mode registers in DRAM, as the MPC instructions are not flexible enough to access all DRAM mode registers. Training with MPC is slow and is typically limited to training the DFE (Decision Feedback Equalization) registers. The MPC operation is expected to become increasingly widely used, increasing the number of required MPC opcodes. The increase in MPC opcodes and training is not scalable for all possible future training. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The following description includes a discussion of figures with illustrations that serve as an example of one implementation. The drawings are to be considered as examples and not as limitations. When reference is made herein to one or more examples, it is to be understood as a description of a particular feature, structure, or characteristic included in at least one embodiment of the invention. Terms such as "in an example" or "in an alternative example" are examples of embodiments of the invention and do not necessarily all refer to the same implementation. Nor are they necessarily mutually exclusive. Fig. Figure 1A is a block diagram of an example system with a memory module. Fig. Figure 1B is a block diagram of an example system with an unregistered memory module. Fig. Figure 2 is a block diagram of an example memory module with an RCD having an in-band configuration mode via MRUPD. Fig. Figure 3 is a block diagram of an example memory module with memory devices that have an in-band configuration mode via MRUPD. Fig. 4A-4B are example timing diagrams for MRUPD instructions. Fig. Figure 5A is an example table of register fields for training modes available through an MRUPD mode. Fig. Figure 5B is a first example table for an MRUPD instruction based on seven CA pins. Fig. Figure 5C is a second example table for an MRUPD instruction based on seven CA pins. Fig. Figure 6 is a timing diagram of an example of multi-cycle MRUPD instructions followed by single-cycle MRUPD instructions. Fig. Figure 7A is an example mode register access instruction table. Fig. Figure 7B is an example timing diagram for mode register access instructions. Fig. Figure 8 is a flowchart of an example MRUPD method. Fig. Figure 9 is a state diagram of an example of MRUPD. Fig. 10 is a block diagram of an example storage subsystem in which an in-band configuration mode may be implemented. The Fig. Figures 11A-11B are block diagrams of an example CAMM system in which alarm signal testing can be performed. Fig. 12 is a block diagram of an example computer system in which the in-band configuration mode may be implemented. Fig. Figure 13 is a block diagram of an example multi-node network in which the in-band configuration mode can be implemented.

[0006] Descriptions of specific details and implementations follow, including non-limiting descriptions of the figures, which may depict some or all of the examples, as well as other possible implementations. DETAILED DESCRIPTION OF THE INVENTION

[0007] As described here, a configuration register update mode can be implemented as a mode register update (MRUPD) mode for a dynamic random access memory (DRAM) device. In one example, MRUPD can also be used to update a registering clock driver (RCD). In one example, MRUPD can be applied to the RCD by selectively placing the RCD in a non-pass-through mode. In one example, MRUPD can be applied to the RCD by setting a field in the instructions that indicates whether the instruction applies to the RCD or the DRAM. In update mode, the memory device (either the RCD or the DRAM) can perform the configuration of any number of configuration registers using in-band register write operations.In-band register write operations can be used to configure the Decision Feedback Equalization (DFE) settings as well as other configuration settings for non-DFE configurations of a storage device interface.

[0008] As described here, in-band communication can be used to train any DRAM register or RCD register before training the CS (Chip Select). Using MRUPD mode can be used to update other registers, avoiding the use of the SMBus (System Management Bus), which increases the speed of training and setup. MRUPD extends the concept of register updates to include in-band communication. Using MRUPD can replace at least some MPC (Multipurpose Command) operations. If the buses are not fully trained, the system can use in-band communication for training.

[0009] What is described here can be used for all training steps and extended to MRUPD to accelerate training algorithms and enable the updating of any MRs (mode registers) through MRUPD mode. The following information describes examples of applying an MR update mode. After exiting MRUPD mode, the system can execute a regular single-cycle MRW (Mode Register Write) or MRUPD instruction to update any register. The ability to update registers with MRUPD simplifies host instructions. Furthermore, the system does not require different instructions for different operations before training or after training and during runtime for setting the mode registers; instead, all states can use the same instructions, simplifying instruction handling for the host.

[0010] The described MRUPD mode can replace operations currently performed using MPC instructions with MRUPD operations and mode register accesses. The ability to replace MPC operations with MRUPD operations can alleviate the growing demand for MPC opcodes; otherwise, the opcode table could quickly become exhausted. In one example, MRUPD operation can be used to set CA DFE (command / address decision feedback equalization), CS DFE (chip select decision feedback equalization), and CS / CA Vref (chip select / command / address voltage reference) sweeps. The Vref sweep applies different values ​​of the Vref settings to adjust the voltage that provides the best system performance.

[0011] In one example, MRUPD mode allows the system to access registers that are only accessible via MRW (Mode Register Write). This expanded access to the registers improves the capabilities for future DRAM architectures, where CA / CS DFE / Vref sweeps are expected, requiring a larger number of registers to be configured during the training phases. For example, with 10-20 CA DFE 1-tap settings times 10-20 Vref settings times 2 gain settings for 8 pattern registers, the system can have approximately 800 register accesses as a starting point. It is expected that there will be similar significant register access sequences for CS Vref sweeps and CS DFE, which will currently significantly increase the size of the MPC opcode table. The ability to access the registers via MRUPD, and the faster access compared to MPC operation, can significantly improve training time and efficiency.

[0012] MRUPD mode can reduce the total number of instructions required by the host system for the instruction truth table. The ability to train via MRUPD can, for example, eliminate the need for instructions such as Vref CA, Vref CS, and MPC. Removing these instructions saves coding options for future instruction uses. In one example, the functions provided by the instructions can be moved to the MR register configuration so that the DRAM knows the exact operation to be performed. In one example, the system has no restriction on accessing MRs with MRUPD or MRW.

[0013] MRUPD mode can improve the time and efficiency of initialization and training. In one example, the host can implement a ZQCAL (impedance calibration) at runtime through a single MRW cycle instead of sending an MPC. MRUPD is an in-band command that avoids the use of a sideband. In one example, the system can have default settings (e.g., DFE, ODT (on-die termination), Vref) for higher-speed operation in normal mode. The system can write the default settings to the mode registers using MRUPD mode and optionally use the M3C (Memory Module Management Control) bus for debugging.

[0014] In one example, the system can apply MRUPD mode to DRAM to automate any DFE or Vref sweep using built-in logic. Currently, MRW cannot be used to access MPC-bound registers, which refers to registers associated with access via an MPC operation. Eliminating the MPC operation for the register allowed the registers to be accessed using MRW instructions via MRUPD mode.

[0015] In one example, the system can combine RWUPD (register word update) and MRUPD. Instead of requiring a separate RWUPD for the RCD, the system can selectively apply the MRUPD instructions to either the RCD or DRAM, depending on the target device selected in the instruction (e.g., by using a bit in the instruction). In one example, the system integrates MRUPD and MRW as multi-cycle instructions during initialization and training, and after training, the system can use a single-cycle MRUPD instruction that can also perform the MRW work, reducing the number of instructions.

[0016] Fig. Figure 1A is a block diagram of an example system with a memory module. System 102 includes a socket 110 connected to a DIMM (Dual Inline Memory Module) 120. Socket 110 represents a CPU (Central Processing Unit) socket, which may contain CPU 112 and memory controller 114. DIMM 120 contains multiple DRAM devices. DIMM 120 represents any type of memory module, which may be a DIMM or a CAMM (Compression Attached Memory Module).

[0017] System 102 shows an example of a system with memory devices sharing a control bus or command bus (CA bus 126[0] for one channel and CA bus 126[1] for the other channel) and data buses (data bus 116[0] for one channel and data bus 116[1] for the other channel). The memory devices are represented as dynamic random access memory (DRAM) devices. Each channel has N DRAM devices, DRAM 132[1:N] (collectively, DRAM devices 132) for one channel and DRAM 134[1:N] (collectively, DRAM devices 134) for the other channel, where N can be any integer. In one example, N includes one or more error check and correction (ECC) DRAM devices in addition to the data devices. Each DRAM device 132 and each DRAM device 134 may represent a memory chip with a command bus interface to the memory controller 114, wherein the interface may be via RCD 128.

[0018] In one example, the two separate channels share the CA bus 124 connection between the memory controller 114 and the RCD 128. In one example, the individual channels are equipped with separate CA buses. The DRAM devices can be accessed individually with device-specific commands and in parallel with parallel commands.

[0019] RCD (Registering Clock Driver) 128 (which may also be referred to as a registered clock) represents a controller for DIMM 120. In one example, RCD 128 receives information from memory controller 114 and buffers the signals for the various DRAM devices. By buffering the input command signals from memory controller 114, the controller only sees the load of RCD 128 on the command / address bus (CA bus 124), which can then control the timing and signaling to the DRAM devices.

[0020] In one example, the RCD 128 controls the command signals to the DRAM devices 132 via the CA bus 126[0] and the signals to the DRAM devices 134 via the CA bus 126[1]. In one example, the RCD 128 has independent command pins for separate channels. In one example, the DIMM 120 includes data buffers to buffer the data bus signals between the DRAM devices of the DIMM 120 and the memory controller 114.

[0021] Data bus 116[0] provides a data bus for DRAM devices 132, which are buffered with DB (data buffer) 142[1:N] (collectively, DBs 142). Data bus 116[1] provides a data bus for DRAM devices 134, which are buffered with DB 144[1:N] (collectively, DBs 144). System 102 illustrates a one-to-one relationship between data buffers and DRAM devices. In one example, there are fewer data buffers than DRAM devices, with DRAM devices sharing a data buffer.

[0022] CA bus 126[0] and CA bus 126[1] (collectively, CA buses 126) are typically unilateral or unidirectional buses for transferring command and address information from memory controller 114 to the DRAM devices. CA buses 126 can therefore be used as multi-drop buses. Data bus 116[0] and data bus 116[1], collectively, data buses 116, are traditionally bidirectional, point-to-point buses.

[0023] In one example, memory controller 114 includes one or more sideband bus connections to other devices in system 102. Sideband buses refer to buses other than CA bus 124 and data buses 116. As illustrated, memory controller 114 has an SMBus (System Management Bus, referred to simply as "SMB" in system 102) for connection to RCD 128. In one example, memory controller 114 has an SMBus connection or another SBB (Sideband Bus) for connection to the DRAM devices. In one example, the SBB connection represents a Memory Module Management Control (M3C) bus. Both the SMBus and SBB connections represent sideband bus communication in system 102.

[0024] The sideband bus allows the memory controller 114 to send a command to a device over a connection other than the CA bus. Communication over a sideband bus is not in-band communication because the command is not received over the CA bus. In one example, communication on the sideband bus allows the memory controller 114 to send commands to place a device into a pre-training update mode, which uses in-band communication to perform configuration updates.

[0025] In one example, DIMM 120 includes a PMIC (Power Management Integrated Circuit) 154 to manage the memory's power state and power consumption. The power states can affect the use of the interface between memory controller 114 and DIMM 120.

[0026] In one example, DIMM 120 includes SPD (serial presence detect) 152. SPD 152 contains information about the components of DIMM 120. SPD 152 enables memory controller 114 to automatically access information about the components. The system can adjust the configuration of the components as needed to improve communication between memory controller 114 and the memory devices.

[0027] In one example, system 102 supports an RWUPD mode for configuring the RCD interface to the CA bus 124. In one example, system 102 supports an MRUPD mode for configuring the DRAM devices. Configuring the DRAM devices may include configuring the data bus interface, configuring the CA bus interface, or configuring both the CA bus interface and the data bus interface. Using the update modes, system 102 supports writing configuration parameters in-band before training the CS (chip select).

[0028] In one example, using update modes, system 102 can accelerate back-end and front-end training for all parametric sweeps. By increasing the number of in-band commands to perform configuration, system 102 can reduce sideband bus usage. Due to the significant speed difference between in-band communication and out-of-band communication (e.g., using the sideband bus), where in-band communication can be orders of magnitude faster, using in-band communication for configuration updates can improve system boot time.

[0029] The CA bus 124 provides a connection for the memory controller 114 to provide command and address information to identify an instruction to be executed and the address for executing the instruction. Of course, the interface to the command bus (e.g., CA bus 124) can be trained to recognize preferred settings to ensure proper reception of commands at the RCD 128. During training, various configuration settings can be cycled through to determine a setting with the best performance, which may vary from system to system.

[0030] With the introduction of DDR (double data rate) mode for command buses, the command bus interface can include DFE (Decision Feedback Equalization) with multiple taps (e.g., 2 or 4 taps) to ensure proper data eye alignment on the CA signal lines. DFE refers to a nonlinear equalization circuit that uses information about previously received bits to determine a currently received and processed bit. Other configuration settings can include reference voltage, current, and other configuration settings. Training establishes the parameters that ensure proper communication on the command bus.

[0031] In one example where system 102 supports an MRUPD mode, the update mode may reduce or eliminate the need for general-purpose instructions (MPC instructions) for configuration. In one implementation, system 102 may replace MPC instructions, the Voltage Reference for Chip Select (VrefCS) instruction, and the Voltage Reference for Command / Address (VrefCA) instruction. Full use of MRUPD mode for all training may enable the elimination of the MPC-encoded opcode table. Alternatively, a system may limit the opcode to a few instructions. Both removing and reducing MPC opcodes may conserve hardware logic within the DRAM devices.

[0032] In one example, MRUPD mode can be applied to either the DRAMs or the RCD. The RCD can receive the command and determine whether the command applies to the DRAM configuration or the RCD configuration. If the command applies to the RCD, the RCD can apply the commands to its own configuration. If the command applies to the DRAM, the RCD can forward the command to the selected DRAM.

[0033] The described MRUPD mode can enable configuration for all possible training modes. In one example, enabling configuration for all training modes involves the following: When the device enters update mode, configuration write operations are performed using two instructions, one for the register address and another for the configuration data value. The register write operations are in-band instructions, which speeds up configuration setup.

[0034] What is described above can work for the CA bus in DDR mode at double the data rate. If the DRAM enters MRUPD mode / state immediately after power-on, the system can perform MRUPD before CSTM (Chip Select Training Mode) and before CATM (Command / Address Training Mode). With such operation, the timing and Vref values ​​can be set using an in-band command instead of using sideband communication. While MRUPD can replace MPC with a single-cycle command, it may require a multi-cycle chip select function.

[0035] In one example, the MRUPD can apply to either a DRAM device or an RCD. This allows the system to use an MRUPD instruction where an RWUPD instruction would normally be used. For example, if the system includes an RCD, the memory controller can signal whether the MRUPD instruction is intended for the RCD or the DRAM. The MRUPD could potentially replace the MRW (Mode Register Write) and MRR (Mode Register Read) instructions. In such a case, a single-cycle MRUPD could be used instead of an MRW instruction.

[0036] A multi-cycle / phase MRUPD instruction can be used instead of multipurpose (MPC) instructions. For example, a system enabled for MRUPD would not need to send multiple MPC commands to update configuration settings. Instead, the storage controller would need to send only an MRUPDE to enter MRUPD mode and then continue sending data until it sends an MRUPDX to exit MRUPD mode. For example:

[0037] Fig. Figure 1B is a block diagram of an example system with an unregistered memory module. System 104 includes several components identical to those of system 102. While system 102 includes RCD 128, which is an RDIMM (registered DIMM), system 104 includes DIMM 160, which is a UDIMM (unregistered DIMM), or CAMM.

[0038] In system 104, the CA bus 124 connects the memory controller 114 directly to the DRAM devices. In one example, a single CA bus 124 is used, as shown, with different channels able to use different time slices of the CA bus. In one example, instead of a single CA bus, the system may use separate system buses for each channel.

[0039] Fig. Figure 2 is a block diagram of a memory module with an RCD having an in-band configuration mode. System 200 illustrates a system according to an example of system 102 or system 104.

[0040] System 200 includes a dual inline memory module (DIMM) 210, which represents a memory module with a module controller. RCD 220 represents the module controller. RCD 220 is connected to a host (not shown) via CA bus 224. RCD 220 has an interface to CA bus 224, which can be configured by setting values ​​in registers 222.

[0041] Registers 222 may include, among other things, DFE settings and termination settings. Each register may contain one or more configuration settings. Specifically, registers 222 illustrate DFE to represent configuration settings for the DFE for the CA bus 224, VREF to represent Vref configuration settings, and CA to represent other settings such as termination settings or other configurations for the CA bus 224.

[0042] The RCD 220 can be connected to DRAM devices 232 via the CA bus 244[0] and to DRAM devices 234 via the CA bus 244[1]. In one example, the configuration of registers 222 applies to the interface to the CA bus 224, and the DRAM devices have a separate configuration for the CA bus connection from the RCD 220.

[0043] Applying an MRUPD mode to the RCD 220 may enable the system 200 to exit DCSTM using the MRUPD mode, using in-band communication to set the configuration. In one example, the RCD 220 enters MRUPD using SMBus communication and exits MRUPD in response to a CS assertion. In one example, the system 200 has a setup / configuration qualifier when the RCD 220 is in MRUPD. The qualifier may be a chip select (e.g., DCS0 / 1), where the activation of the chip select may determine which channel is configured. In one example, each training mode may specify which qualifier is used for the particular training.

[0044] In one example, the host may send the register address (e.g., RW address) and opcode for the MRUPD operation and internally loop through the update operations (e.g., with hardware acceleration) using an MRUPD qualifier. In one example, system 200 causes RCD 220 to exit MRUPD through a write to an RCD register (RW32) or through an SMBus command. In one example, registers 222 may include the RW32 RCD register.

[0045] Fig. 3 is a block diagram of an example memory module with memory devices having an in-band configuration mode. System 300 illustrates a system according to an example of system 102 or an example of system 200.

[0046] System 300 includes a dual inline memory module (DIMM) 310, which represents a memory module with a module controller. RCD 320 represents the module controller. RCD 320 connects to a host (not specifically shown). RCD 320 can connect to DRAM devices 332 via CA bus 344[0] and to DRAM devices 334 via CA bus 344[1].

[0047] In one example, DRAM devices 332 include registers 336, and DRAM devices 334 include registers 338. In one example, the configuration of registers 336 applies to the interface of DRAM devices 332 to CA bus 344[0]. In one example, the configuration of registers 338 applies to the interface of DRAM devices 334 to CA bus 344[1].

[0048] Registers 336 and 338 may contain, among other things, DFE settings and termination settings. Specifically, registers 336 and 338 illustrate that DFE represents a DFE configuration register to store one or more configuration settings for the DFE for the CA buses, VREF represents the Vref configuration settings, and CA represents other settings such as termination settings or other configurations for the CA buses. In one example, MRUPD may apply to all configuration settings in the DRAM devices for the CA buses. MRUPD may provide a training mode for all configuration register training for the CA bus. Thus, system 300 may include one DFE configuration register and several additional configuration registers for additional configuration settings.

[0049] The system 300 enables a DRAM mode register update (MRUPD) mode. In one example, the MRUPD mode has an MRUPDE (MRUPD input) and an MRUPDX (MRUPD output). In one example, MRUPD applies to DDR6 (Double Data Rate Version 6). In one example, MRUPD is used in conjunction with an M3C bus. An MRUPD mode application can replace MPC, VrefCA, and VrefCS instructions. Without such instructions, the MPC opcode table would not be required. Removing the table saves logic in DRAM and allows access to the mode register at any time and without restriction to one set.

[0050] In one example, MRUPD provides an update mode in DRAM that the DRAM uses for all training steps. With the proposed MRUPD, the system does not need to perform SMBus access to sweep any parameter, which is significantly slower than in-band commands. Performing training via in-band access accelerates backside training steps such as the CSTM, CATM, and DFE training algorithms and improves system startup time.

[0051] In one example, the in-band register writes are MRWs (Mode Register Writes) based on instructions on the instruction bus prior to the execution of a CATM. In one example, system 300 provides a first MPC to enter MRUPD mode. A second MPC may trigger an exit from MRUPD mode.

[0052] Fig. Figure 4A is an example timing diagram for the MRUPD instruction. Diagram 402 illustrates a timing diagram for the MRUPD instruction. Diagram 402 illustrates various signals and example sequences over time. The thick dashed lines represent timing interruptions, indicating that the number of clock cycles involved in signaling may vary from the figure.

[0053] Signal 410 represents the host clock (CLK), which has the CK_t (primary clock) and CK_c (complementary clock) signals representing timing signals. Signal 420 represents the command and address signal lines CA[6:0] (command / address bits 6 through 0), which represent a command sent from the host. Signal 430 represents the internal command signal CMD (command). The CMD signal represents the decoded operation within the DRAM device in response to the host command. Signal line 440 represents the chip select. CS0_n (Chip Select 0, enumerated for each individual DRAM device) represents a chip select for the target DRAM device, which is configured using the MRUPD.

[0054] The CA signal indicates the MRUPD command 0, MRUPD command 1, and MRUPD command 2 for the training sequence. After training, the CA signal can send any valid command. After training, the CMD can similarly generate any valid command, with the CS signal asserted in one cycle.

[0055] In a response to MRUPD command 0, CMD can be MRUPD ADDR (address or MRA (MRUPD address)), while the CS signal can assert the CS signal for a time of tMRUPD_CS (timing for a CS signal in MRUPD mode). MRUPD command 0 can be an MRUPD mode command that triggers entry into MRUPD mode. In one example, there is a time of tMRUPD_setup (MRUPD mode setup time) before the CS assertion and a time of tMRUPD_hold (MRUPD mode hold time) after the CS assertion.

[0056] In a response to MRUPD command 1, the CMD MRUPD Data can be 0, such as a ZQCALS (impedance calibration start) or any other training mode, while the CS signal can activate the CS signal for a time of tMRUPD_CS. Similarly, in a response to MRUPD command 2, the CMD MRUPD Data can be 1, such as a ZQCALS or any other training mode, while the CS signal can activate the CS signal for a time of tMRUPD_CS.

[0057] Diagram 402 illustrates the use of a multi-cycle CS used in MRUPD mode. The multi-cycle CS is used to give the DRAM time to latch the signal, since there is no Vref CS, no Vref CA, or other training. After training, the CS0_n signal line represents a normal single-cycle CS. The multi-cycle CS signal allows the system to clearly identify whether the DRAM is in MRUPD mode (until CS / CA are trained) or in normal mode.

[0058] In diagram 402, in one example, the host writes to an MR register field MRUPDX using MRUPD to exit. The DRAM can exit MRUPD to execute any valid CS-based one-cycle commands (e.g., a read with a timing of tMRD (time to read memory)) and MRUPD one-cycle commands. This allows the system to perform configuration updates for both the CS and the CA.

[0059] Fig. Figure 4B is an example timing diagram for the MRUPD instruction. Figure 404 shows another timing diagram for the MRUPD output time. Figure 404 illustrates various signals and example sequences over time. The thick dashed lines represent timing interruptions, indicating that the number of clock cycles involved in signaling may vary from the figure.

[0060] Signal 450 represents the host clock (CLK), which has the CK_t (primary clock) and CK_c (complementary clock) signals representing timing signals. Signal 460 represents the command and address signal lines CA[6:0] (command / address bits 6 through 0), which represent a command sent from the host. Signal 470 represents the internal command signal CMD (command). The CMD signal represents a signal for the DRAM device. Signal line 480 represents chip select. CS0_n (Chip Select 0, enumerated for each individual DRAM device) represents a chip select for the target DRAM device, which is configured using the MRUPD.

[0061] The CA signal indicates MRUPD command 0, MRUPD command 1, and MRUPD command 2 for the training sequence. After training, the CA signal can send any valid command. After training, the CMD can similarly generate any valid command, with the CS signal asserted in one cycle. Diagram 402 illustrates the timing for various phases of MRUPD, showing the timing of tMRUPD_PxDelay (timing between MRUPD commands) between MRUPD command 0 and MRUPD command 1.

[0062] In a response to MRUPD command 0, CMD can be MRUPD ADDR (address or MRA (MRUPD address)), while the CS signal can assert the CS signal for a time of tMRUPD_CS (timing for a CS signal in MRUPD mode). In one example, there is a time of tMRUPD_setup (setup time for MRUPD mode) before the CS assertion and a time of tMRUPD_hold (hold time for MRUPD mode) after the CS assertion. Diagram 404 illustrates the timing for the MRUPD operation, illustrating the timing of tMRUPD_Delay (timing for MRUPD mode) from MRUPD command 0 to the valid command after training.

[0063] In a response to MRUPD command 1, the CMD may be an MRUPD exit command, represented as MRUPD data 0, while the CS signal may activate the CS signal for a time of tMRUPD_CS. Similarly, in a response to MRUPD command 2, the CMD may be MRUPD data 1, which may be the extension of the exit command, while the CS signal may activate the CS signal for a time of tMRUPD_CS.

[0064] Diagram 404 illustrates the use of a multi-cycle CS used in MRUPD mode. The multi-cycle CS is used to give the DRAM time to latch the signal, since there is no Vref CS, no Vref CA, or other training. After training, the CS0_n signal line represents a normal single-cycle CS. The multi-cycle CS signal allows the system to clearly identify whether the DRAM is in MRUPD mode (until CS / CA are trained) or in normal mode.

[0065] In diagram 404, in one example, the host writes to an MR register field MRUPDX using MRUPD to exit. The DRAM can exit MRUPD to execute any valid CS-based one-cycle instructions (e.g., a read with a timing of tMRD (time to read memory)) and MRUPD one-cycle instructions.

[0066] Fig. Figure 5A is an example table of register fields for training modes available via an MRUPD mode. Figure 502 shows an example of DRAM mode register fields of encoded MPC opcodes. Instead of accessing the modes through an MPC operation, the modes can be triggered by MR access with an MRUPD instruction.

[0067] Consider a register bit field with an address or identifier of MRxx 510, with line 512. Line 512 contains the fields CSTME (Chip Select Training Mode Enter), CSTMX (Chip Select Training Mode Exit), CATME (Command / Address Training Mode Enter), CATMX (Command / Address Training Mode Exit), MRUPDE (Mode Register Update Enter), and MRUPDX (Mode Register Update Exit), as well as other bit fields that are RFU (Reserved for Future Use). These are only examples, and other mode combinations can be identified in the same mode register.

[0068] Consider a register bit field MRyy 520 with line 522. Line 522 contains the fields ZQCALS (impedance calibration start), ZQCALL (impedance calibration latch), 1N, which refers to 1N mode, where the first half of a two-cycle instruction is sampled at the clock on which CS is asserted, and the second half of the instruction is sampled on the next clock edge, and 2N, which refers to 2N mode, where the first half of a two-cycle instruction is sampled at the clock on which CS is asserted, and the second half of the instruction is sampled two clocks after the first half, DLL (delay lock loop) reset, and MECS, also with RFU fields.

[0069] In one example, the MRUPDX provides an exit from MRUPD mode. MRUPD training can be characterized by a multi-cycle CS and a 3-phase instruction, where the address and two data cycles represent the 3 phases. The separation into multi-cycle CS and 3 phases of the MRUPD instruction helps the DRAM reliably sample the contents. In one example, MRUPD mode is initiated using the MR bit fields of diagram 502 and can trigger other training modes via the MRs.

[0070] Although not specifically shown, there may be registers designated as MRzz with settings of RTT_CS (read abort target for CS), RTT_CA (read abort target for CA), RTT_CK (read abort target for CK (clock)), RTT_PARK (read abort target for Park), and Vref. In one example, the MRUPD modes start using MR bit fields, shown in diagram 502 similar to EXIT mode, to start the DRAM in various modes. In one example, the system scans DRAM mode register fields instead of encoded MPC opcodes from a table.

[0071] Fig. Figure 5B is a first example table for an MRUPD instruction based on seven CA pins. Diagram 504 illustrates table 530, which is a first example of a three-phase MRUPD instruction based on seven CA pins (CA[6:0]. By reducing the number of CA pins, the number of commands can be increased to allow multiple transmission.

[0072] Line 532 illustrates the first phase, Phase 0. In one example, the first phase instruction sends MRP[4:0] (five bits of the mode register paging) and MRA[7:6] (mode register address bits 7 and 6). Line 534 illustrates the second phase, Phase 1. The second phase instruction may send MRA[5:0] (the six least significant bits of the mode register address) and OP0 (the least significant opcode bit). Line 536 illustrates the third phase, Phase 2. The third phase instruction may send OP[7:1] (the most significant bits of the opcode). In one example, paging information may be passed via MRA[0:X], where X is an integer to store a user interface for each instruction. The number of bits may be the same as shown in Figure 504 or may vary depending on the system configuration.

[0073] In an example, there might be 32 pages, 256 registers within a page, 8-bit opcodes (data bits in the instruction), and 128 directly addressable registers. Each of these values ​​can vary, with different numbers of pages, registers per page, opcode sizes, and directly addressable registers. Different configurations are available for different DRAM device implementations.

[0074] In one example, the RCD is placed in pass-through mode so that the commands can be forwarded to the DRAMs. In one example, the RCD can be selectively placed in pass-through mode and forward the MRUPD commands to the DRAMs. In one example, the RCD is selectively not in pass-through mode and receives the MRUPD commands as RWUPD commands for its configuration.

[0075] Fig. Figure 5C is a second example table for an MRUPD command based on seven CA pins. Diagram 506 illustrates table 540, which is an example of a 3-phase MRUPD command based on seven CA pins (CA[6:0]). Reducing the number of CA pins allows the number of commands to be increased to allow multiple transmissions.

[0076] Line 542 illustrates the first phase, Phase 0. In one example, the first phase instruction sends MA[5:0] (six bits of the mode register address) and one valid bit (V). Line 544 illustrates the second phase, Phase 1. The second phase instruction may send MA[7:6] (the most significant mode register address bits) and OP[3:0] (the four least significant opcode bits). Line 546 illustrates the third phase, Phase 2. The third phase instruction may send OP[7:4] (the most significant bits of the opcode) and valid bits. In one example, a swap point is available in one of the MR bits and adds a data integrity check (per phase / step) instead of V.

[0077] In an example, there might be 32 pages, 256 registers within a page, 8-bit opcodes (data bits in the instruction), and 128 directly addressable registers. Each of these values ​​can vary, with different numbers of pages, registers per page, opcode sizes, and directly addressable registers. Different configurations are available for different DRAM device implementations.

[0078] In one example, the RCD is placed in pass-through mode so that the commands can be forwarded to the DRAMs. In one example, the RCD can be selectively placed in pass-through mode and forward the MRUPD commands to the DRAMs. In one example, the RCD is selectively not in pass-through mode and receives the MRUPD commands as RWUPD commands for its configuration.

[0079] Fig. Figure 6 is a timing diagram of an example of multi-cycle MRUPD instructions followed by single-cycle MRUPD instructions. Diagram 600 shows another timing diagram for the MRUPD output time. Diagram 600 illustrates various signals and example sequences over time. The thick dashed lines represent timing interruptions, indicating that the number of clock cycles involved in signaling may vary from the figure.

[0080] Signal 610 represents the host clock (CLK), which has the CK_t (primary clock) and CK_c (complementary clock) signals representing the timing signals. Signal 620 represents the command and address signal lines CA[6:0] (command / address bits 6 through 0), which represent a command sent from the host. Signal 630 represents the internal command signal CMD (command). The CMD (command) is a signal for the DRAM device. Signal line 640 represents the chip select. CS0_n (Chip Select 0, enumerated for each individual DRAM device) represents a chip select for the target DRAM device, which is configured using the MRUPD.

[0081] The CA signal indicates MRUPD command 0, MRUPD command 1, and MRUPD command 2 for the training sequence. After training, the CA signal can send any valid command. After training, the CMD can similarly generate any valid command, with the CS signal asserted in a single cycle. Diagram 600 illustrates the timing for various phases of MRUPD, showing the timing of tMRUPD_PxDelay (timing between MRUPD commands) between MRUPD command 0 and MRUPD command 1.

[0082] In a response to MRUPD command 0, CMD can be MRUPD ADDR (address or MRA (MRUPD address)), while the CS signal can assert the CS signal for a time of tMRUPD_CS (timing for a CS signal in MRUPD mode). In one example, there is a time of tMRUPD_setup (setup time for MRUPD mode) before the CS assertion and a time of tMRUPD_hold (hold time for MRUPD mode) after the CS assertion. Diagram 600 illustrates the timing for the MRUPD operation, illustrating the timing of tMRUPD_Delay (timing for MRUPD mode) from MRUPD command 0 to the valid command after training.

[0083] In a response to MRUPD command 1, the CMD may be an MRUPD exit command, represented as MRUPD data 0, while the CS signal may activate the CS signal for a time of tMRUPD_CS. Similarly, in a response to MRUPD command 2, the CMD may be MRUPD data 1, which may be the extension of the exit command, while the CS signal may activate the CS signal for a time of tMRUPD_CS.

[0084] Diagram 600 illustrates the use of a multi-cycle CS used in MRUPD mode. The multi-cycle CS is used to give the DRAM time to latch the signal since there is no Vref CS, no Vref CA, or other training. After training, the signal line CS0_n represents a normal single-cycle CS.

[0085] In diagram 600, in one example, the host writes to an MR register field MRUPDX using MRUPD to exit. In one example, the DRAM may exit MRUPD to execute any single-cycle MRUPD or MRW instructions. The MRUPD or MRW instruction may identify an address, resulting in a flipping of a bit in the MRA. In one example, the timing from MRUPD instruction 2 to the one-cycle instructions has timing tMRD (mode register delay timing).

[0086] In one example, by not sending two different commands, the system can align the MRW with a single MRUPD cycle, simplifying the overall logic. In one example, the multi-cycle CS commands can be part of the MRUPD mode until the DRAM is trained, which establishes DRAM VrefCA, VrefCS, CS, and CA.

[0087] In one example, after exiting MRUPD mode, the DRAM enters a single-cycle MRUPD mode, where it can send MRWs from the host to the DRAM. In single-cycle MRUPD mode, MRUPD and MRW can be combined because they are single-cycle commands. Because CA has a limited number of pins, MRUPD or MRW may need to be sent with more than one command (see above).

[0088] Fig. Figure 7A is an example table for mode register access instructions. Figure 702 shows table 710, which is a different option than the one shown above. Table 710 shows an example of MRW / MRR (Mode Register Write / Mode Register Read) instructions based on CA[6:0]. In one example, the system may have fewer command signal lines, such as four signal lines.

[0089] In Table 710, MRW-1 is shown in row 712 (rising edge R) and row 714 (falling edge F). In Table 710, MRW-2 is shown in row 716 (rising edge R) and row 718 (falling edge F). Table 710 shows the MRR in row 720 (rising edge R) and row 722 (falling edge F). Row 712, row 716, and row 720 illustrate an enabled chip select, and row 714, row 718, and row 722 illustrate a "don't care" for the chip select.

[0090] MRW-1 with CA[6:0] or non-shared CA[3:0] / CA[7:0] or shared CA[7:0] to send multiple MRW command encodings. As shown in the figure, MRW-1 has a low CS value for the rising edge and a "do not care" on the CS value for the falling edge. For CA[0:6] on the rising edge (line 712), the bits can be the encoding (H / L, H / L, H / L, H / L), a TBD bit, or MA[0:1], respectively. For CA[0:6] on the falling edge (line 714), the bits can be MA[2:7] and a valid bit. The MRW-1 can contain the command encoding and address information.

[0091] As shown in the figure, MRW-2 has a low CS value for the rising edge and a "do not care" on the CS value for the falling edge. For CA[0:6] on the rising edge (line 716), the bits can be the encoding (H / L, H / L, H / L, H / L), a TBD bit, or OP[0:1]. For CA[0:6] on the falling edge (line 718), the bits can be OP[2:7] and a valid bit. Thus, MRW-2 can contain the instruction encoding and the opcode data.

[0092] As shown in the figure, MRR has a low CS value for the rising edge (line 720) and a "do not care" value for the CS value of the falling edge. For CA[0:6], the bits on the rising edge can be the encoding (H / L, H / L, H / L, H / L), a TBD bit, or MA[0:1]. For CA[0:6] on the falling edge (line 722), the bits can be MA[2:7] and a valid bit. Thus, MRR can contain the instruction encoding and the register address.

[0093] Fig. Figure 7B is an example timing diagram for mode register access instructions. Timing diagram 704 illustrates various signals and example sequences over time. The thick dashed lines represent timing interruptions, indicating that the number of clock cycles involved in signaling may vary from the figure.

[0094] Signal 730 represents the host clock (CLK), which has the CK_t (primary clock) and CK_c (complementary clock) signals representing timing signals. Signal 740 represents chip select. CS0_n (Chip Select 0, enumerated for each individual DRAM device) represents a chip select for the target DRAM device being configured with the MRUPD. Signal 750 represents the command and address signal lines CA[6:0] (command / address bits 6 through 0), which represent a command sent from the host. Signal line 760 represents the internal command signal CMD (command). The CMD signal represents a signal for the DRAM device.

[0095] Signal 740 illustrates that Chip Select is enabled at ta0R (time a0, rising edge), with a valid command present on signal 750 and MRW-1 present on signal 760. The signals continue with ta0F (time a0, falling edge). At time ta1R, signal 760 indicates MRW-2. At time ta1F, signal 740 indicates an edge transition for CS. Time ta2R indicates a disabled CS and a deselection command (DES) on signal 760.

[0096] At time tb0R, signal 760 indicates DES, with CS deasserted. At time tb0F, signal 740 indicates an edge transition for the CS assertion and another DES on signal 760. Time tb1R indicates that CS is asserted, a valid command is present on signal 750, and MRW-1 is present on signal 760. Time tb1F indicates that CS is asserted, a valid command is present on signal 750, and MRW-1 is present on signal 760.

[0097] Time tb2R indicates that CS is asserted, a valid command is present on signal 750, and MRW-2 is present on signal 760. Time tb2F illustrates an edge transition for CS, a valid command is present on signal 750, and MRW-2 is present on signal 760. At times tb3R, tb3F, tb4R, tb4F, and tc0R, CS is asserted and DES is present on signal 760. At time tc0F, signal 740 indicates a CS transition with DES present on signal 760. At time tc1R and time tc1F, signal 740 indicates that CS is asserted, signal 750 is valid, and signal 760 contains any command (CMD).

[0098] Chip Select is enabled for MRW instructions. The CA signal line only needs to be valid for the mode register instructions to be transmitted. The CMD signal line represents MRW-1 and MRW-2 instructions, which are sent sequentially when CS is enabled. The time for MRW (tMRW) ranges from ta1R to tb2R, and the time for MRD (tMRD) ranges from tb2R to tc1R.

[0099] Fig. Figure 8 is a flowchart of an example MRUPD procedure. Process 800 represents a process flow for in-band DRAM configuration using MRUPD. After the system powers on (PON), the host can begin communicating, at 802. In one example, the system powers on the DRAM (PON) and defaults to MRUPD mode, which may be part of the reset procedure. The system can optionally perform an M3C operation to enter MRUPDE / MRUPDX mode during debugging.

[0100] The system can perform operations to read the SPD and power up the PMIC (804). The system can follow a standards-based initialization sequence, including initiating the M3C bus, deasserting the Reset_n signal, and waiting for an initialization period (e.g., tINIT3) at 806.

[0101] In one example, the system determines whether a strap pin is present at 808. On a YES branch (810), an optional M3C RW (register word) update (e.g., for an RCD or a mode register update for DRAM) is performed for CS / CA and for ODT / Vref (812). If no strap pin is present, on a NO branch 810, in one example, the M3C register write is required at 814.

[0102] In one example, MRUPD mode follows three operations: MRUPD Entry / Idle, MRUPD Operation with Address and Data, and MRUPD Exit to perform a regular MRUPD. The system can perform MRUPD in idle mode (816). The system can send an MRUPD address command (818), an MRUPD command with a first portion of data (820), and a second MRUPD command with a second portion of data (822).

[0103] The system can use the MRUPD mode operations to set up the DLL and train ZQCal, ODT, and Vref. The MRUPD mode operations can also be used for CSTM Entry, CATM Entry, and DFE training. In one example, after setting a parameter, the system determines if there are any more parameters to be set (824). If there are any more parameters to configure, the system can return to MRUPD Idle (816) at branch 826 YES. If there are no more parameters to configure, the system can trigger MRUPD exit at branch 826 NO. After MRUPD exits, the system supports the regular MRW to set the configuration (830).

[0104] In one example, the system uses MRUPD to configure all required DRAM mode registers, using the same DRAM CS as the qualifier for MRUPD. In one example, the system applies a multi-cycle CS for MRUPD to enter CSTM training (writing to the MR field) and CA with all zeros (0) to exit CSTM. Optionally, M3C can be used for initialization / debugging for terminations, Vref, and other parameters. The M3C can initiate the terminations and Vref settings, and MRUPD in-band instructions can be used for arbitrary parameter sweeps to accelerate them using DRAM sweep acceleration logic. Similarly, the system can use an identifier for the RCD to set RCD configuration registers.

[0105] Fig. 9 is a state diagram of an example MRUPD. System 900 illustrates various states in an example MRUPD flow. In one example, in response to a power-on reset, the memory transitions to the MRUPD idle state 902, a state in which the memory can perform in-band training with MRUPD but is idle because it currently has no operations to perform.

[0106] In one example, as an alternative to entering MRUPD idle during power-on reset, commands may be entered on the M3C bus (which may be a subset of I3C basic) during debugging time. In one example, with a multi-cycle Chip Select (CS) assertion, the memory may transition to the MRUPD ADDR state 904. In response to a CS assertion, the selected memory device may look for an MRUPD address for a configuration update. With another CS assertion, which may also be a multi-cycle assertion, the memory transitions to the MRUPD data state 906, where the memory device acquires the data for writing to the address of the previous state.

[0107] In one example, the written mode register update may be an update that disables MRUPD mode. In response to such an update, memory may transition to the MRUPD exit state 908 and exit MRUPD mode.

[0108] In one example, 902 and 906 can represent states for general mode register updates. Such general updates are not necessarily associated with the activation of a training mode. The update can be used, for example, for Vref configuration. If Vref is out of range, the system can, for example, use the M3C bus to recover.

[0109] In one example, MRUPD data 906 may trigger CSTM entry 910 with a mode register configuration write to enable CSTM. In one example, upon a CS assertion, the memory transitions to the CSTM state 912 with all CA pins high (e.g., to a high logic state) to perform chip select training. In one example, the CA pins may be held high during CS training. In one example, no instructions are supported during CSTM. Alternatively, the DRAM device may be disabled from decoding instructions.

[0110] In one example, in response to a CS assertion with all CA pins low, the memory may transition to the CSTM exit state 914. In response to exiting CSTM mode, the memory may return to the MRUPD idle state 902.

[0111] In one example, MRUPD data 906 may trigger CATM entry 920 with a mode register configuration write to enable CATM. In one example, upon a CS assertion with an appropriate CA pattern on the CA pins (e.g., CA encoding or a CATM command), the memory transitions to CATM state 922 to perform CA bus training. In one example, the CA pins may be held at the CA encoding during CA bus training, triggering entry into CATM.

[0112] In one example, in response to a multi-cycle CS assertion with all CA pins high, the memory may transition to the CATM exit state 924. In response to exiting CATM mode, the memory may return to the MRUPD idle state 902.

[0113] Fig. 10 is a block diagram of an example storage subsystem in which an in-band configuration mode may be implemented. System 1000 includes a processor and elements of a storage subsystem in a computing device. System 1000 represents a system having a storage subsystem according to an example of system 102, an example of system 200, or an example of system 300.

[0114] In one example, system 1000 includes RCD 1072 in memory module 1070. The configuration of RCD 1072 may be programmable using in-band register write operations as described herein. Memory device 1040 may be a DRAM device whose configuration may be programmable using in-band register write operations as described herein.

[0115] The processor 1010 represents a processing unit of a computer platform that can execute an operating system (OS) and applications, which may collectively be referred to as a host or user of the memory. The operating system and applications perform operations that result in memory accesses. The processor 1010 may include one or more separate processors. Each individual processor may include a single processing unit, a multi-core processing unit, or a combination thereof. The processing unit may be a primary processor such as a CPU (Central Processing Unit), a peripheral processor such as a GPU (Graphics Processing Unit), or a combination thereof. Memory accesses may also be initiated by devices such as a network controller or a disk controller. Such devices may, in some systems, be integrated with the processor or may be accessible via a bus (e.g.,PCI Express) connected to the processor, or a combination of both. The System 1000 can be implemented as a SOC (System on a Chip) or with standalone components.

[0116] Reference to memory devices can refer to various memory types. Memory devices often refer to volatile memory technologies. Volatile memory is memory whose state (and therefore the data stored on it) is indeterminate when the device's power supply is interrupted. Non-volatile memory is memory whose state is retained even when the device's power supply is interrupted. Dynamic volatile memory requires the data stored in the device to be refreshed to maintain its state. An example of dynamic volatile memory is DRAM (Dynamic Random-Access Memory) or a variant such as synchronous DRAM (SDRAM). A memory subsystem described herein may be compatible with a number of memory technologies, such as DDR4 (Double Data Rate Version 4, JESD79-4,originally released in September 2012 by JEDEC (Joint Electron Device Engineering Council, now JEDEC Solid State Technology Association)), LPDDR4 (Low Power DDR Version 4, JESD209-4, originally released by JEDEC in August 2014), WIO2 (Wide I / O 2 (WidelO2), JESD229-2, originally released by JEDEC in August 2014), HBM (High Bandwidth Memory DRAM, JESD235A, originally released by JEDEC in November 2015), DDR5 (DDR Version 5, originally released by JEDEC in July 2020), LPDDR5 (LPDDR Version 5, JESD209-5, originally released by JEDEC in February 2019), HBM2 (HBM Version 2, JESD235C, originally released by JEDEC in January 2020), HBM3 (HBM Version 3, JESD238, originally published by JEDEC in January 2022), DDR6 (DDR version 6, under discussion), GDDR7 (graphics DDR version 7, under discussion) or other or combinations of memory technologies as well as technologies,based on derivatives or extensions of these specifications.

[0117] The memory controller 1020 represents one or more memory controller circuits or devices for the system 1000. In one example, the memory controller 1020 is located on the same semiconductor substrate as the processor 1010. The memory controller 1020 represents control logic that generates memory access commands in response to the execution of operations by the processor 1010. The memory controller 1020 accesses one or more memory devices 1040. The memory devices 1040 may be DRAM devices according to the devices mentioned above. In one example, the memory devices 1040 are organized and managed as different channels, with each channel connected to buses and signal lines that connect to multiple memory devices in parallel. Each channel is independently operable.In this way, each channel is accessed and controlled independently, and timing, data transfer, command and address exchange, and other operations are separate for each channel. Coupling can refer to electrical coupling, communicative coupling, physical coupling, or a combination thereof. Physical coupling can involve direct contact. Electrical coupling includes an interface or connection that allows electrical flow between components or signal transmission between components, or both. Communicative coupling includes connections, including wired or wireless, that allow components to exchange data.

[0118] In one example, the settings for each channel are controlled by separate mode registers or other register settings. In one example, each memory controller 1020 manages a separate memory channel, although the system 1000 can be configured to have multiple channels managed by a single controller or to have multiple controllers operating on a single channel. In one example, the memory controller 1020 is part of the host processor 1010, e.g., as logic implemented on the same chip or in the same package as the processor.

[0119] The memory controller 1020 includes I / O interface logic 1022 for coupling to a memory bus, e.g., a memory channel (see above). The I / O interface logic 1022 (as well as the I / O interface logic 1042 of the memory device 1040) may include pins, pads, connectors, signal lines, traces, wires, or other hardware for connecting the devices, or a combination thereof. The I / O interface logic 1022 may include a hardware interface. As shown, the I / O interface logic 1022 includes, at a minimum, drivers / transceivers for signal lines. Typically, wires within an integrated circuit interface are connected to a pad, pin, or connector to connect signal lines, traces, or other wires between the devices.The I / O interface logic 1022 may include drivers, receivers, transceivers, termination, or other circuitry or combinations of circuitry to exchange signals on the signal lines between the devices. The exchange of signals includes at least one of sending and receiving. While I / O 1022 from the memory controller 1020 is shown coupled to I / O 1042 of the memory device 1040, it should be understood that in an implementation of the system 1000 in which groups of memory devices 1040 are accessed in parallel, multiple memory devices may include I / O interfaces to the same interface of the memory controller 1020. In an implementation of the system 1000 with one or more memory modules 1070, I / O 1042 may include interface hardware on the memory device itself in addition to the memory module interface hardware.Other memory controllers 1020 have separate interfaces to other memory devices 1040.

[0120] The bus between the memory controller 1020 and the memory devices 1040 may be implemented as multiple signal lines connecting the memory controller 1020 to the memory devices 1040. The bus may typically include at least clock (CLK) 1032, command / address (CMD) 1034, data (DQ) 1036, and zero or more other signal lines 1038. In one example, a bus or connection between the memory controller 1020 and the memory may be referred to as a memory bus. In one example, the memory bus is a multi-drop bus. The signal lines for CMD may be referred to as the "C / A bus" (or ADD / CMD bus, or another designation indicating the transfer of commands (C or CMD) and address information (A or ADD)), and the signal lines for writing and reading DQ may be referred to as the "data bus." In one example, independent channels have different clock signals, C / A buses, data buses, and other signal lines.Thus, system 1000 can be considered a system with multiple "buses," in the sense that an independent interface path can be considered a separate bus. It should be understood that, in addition to the lines explicitly shown, a bus may include at least one of strobe signal lines, alarm lines, auxiliary lines, or other signal lines, or a combination thereof. It should also be understood that serial bus technologies may be used for the connection between memory controller 1020 and memory devices 1040. An example of a serial bus technology is 8B10B encoding and transfer of high-speed data with embedded clock over a single differential signal pair in each direction. In one example, CMD 1034 represents signal lines shared by multiple memory devices in parallel.In one example, multiple memory devices share the encode command signal lines of CMD 1034, and each has a separate Chip Select (CS_n) signal line to select individual memory devices.

[0121] It should be understood that in the example of system 1000, the bus between memory controller 1020 and memory devices 1040 includes an auxiliary command bus CMD 1034 and an auxiliary bus for transferring write and read data, DQ 1036. In one example, the data bus may include bidirectional lines for read data and for write / command data. In another example, the auxiliary bus DQ 1036 may include unidirectional write signal lines for writing and data from the host to memory and unidirectional lines for reading data from memory to the host. Depending on the chosen memory technology and system design, other signals 1038 may accompany a bus or subbus, such as strobe lines DQS. Depending on the design of system 1000 or the implementation, if a design supports multiple implementations, the data bus may have more or less bandwidth per memory device 1040.For example, the data bus can support memory devices that have either a x4 interface, an x8 interface, a x16 interface, or another interface. The convention is "xW," where W is an integer referring to an interface size or width of the memory device 1040 interface, which represents a number of signal lines for data exchange with the memory controller 1020. The interface size of the memory devices is a determining factor in how many memory devices can be used simultaneously per channel in the system 1000 or connected in parallel to the same signal lines.In one example, high-bandwidth memory devices, wide interface devices, or stacked memory configurations, or combinations thereof, may enable wider interfaces, such as an x128 interface, an x256 interface, an x512 interface, an x1024 interface, or other data bus interface width.

[0122] In one example, memory devices 1040 and memory controller 1020 exchange data over the data bus in a burst or a sequence of consecutive data transfers. The burst corresponds to a number of transfer cycles related to a bus frequency. In one example, the transfer cycle may be an entire clock cycle for transfers that occur on the same clock or strobe signal edge (e.g., on the rising edge). In one example, each clock cycle, which relates to a cycle of the system clock, is divided into multiple unit intervals (UI), where each UI is a transfer cycle. For example, double-data-rate transfers are triggered on both edges of the clock signal (e.g., rising and falling). A burst may last for a configured number of UIs, which may be stored in a register or triggered spontaneously.For example, a sequence of eight consecutive transfer periods can be considered a burst length of eight (BL8), and each memory device 1040 can transfer data in each UI. Thus, an x8 memory device operating at BL8 can transfer 64 bits of data (8 data signal lines times 8 data bits transferred per line over the burst). It should be understood that this simple example is for illustrative purposes only and is not limiting.

[0123] The memory devices 1040 represent memory resources for the system 1000. In one example, each memory device 1040 is a separate memory chip. In one example, each memory device 1040 can be connected to multiple (e.g., 2) channels per device or chip. Each memory device 1040 includes I / O interface logic 1042, the bandwidth of which is determined by the device implementation (e.g., x16 or x8 or another interface bandwidth). The I / O interface logic 1042 enables the memory devices to communicate with the memory controller 1020. The I / O interface logic 1042 can include a hardware interface and can be the same as the memory controller's I / O 1022, but on the memory device side. In one example, multiple memory devices 1040 are connected in parallel to the same command and data buses.In another example, multiple memory devices 1040 are connected in parallel to the same command bus and to different data buses. For example, system 1000 may be configured with multiple memory devices 1040 connected in parallel, with each memory device responding to a command and accessing internal memory resources 1060. During a write operation, a single memory device 1040 may write a portion of the overall data word, and during a read operation, a single memory device 1040 may retrieve a portion of the overall data word. The remaining bits of the word are provided or received in parallel from other memory devices.

[0124] In one example, memory devices 1040 are disposed directly on a motherboard or host system platform (e.g., a printed circuit board (PCB) or substrate on which processor 1010 is disposed) of a computing device. In one example, memory devices 1040 may be organized into memory modules 1070. In one example, memory modules 1070 represent dual in-line memory modules (DIMMs). In one example, memory modules 1070 represent another organization of multiple memory devices to share at least some access or control circuitry, which may be a separate circuit, a separate device, or a separate board of the host system platform. Memory modules 1070 may include multiple memory devices 1040, and the memory modules may provide support for multiple separate channels to the memory devices thereon.In another example, the memory devices 1040 may be integrated into the same package as the memory controller 1020, for example, using techniques such as multi-chip module (MCM), package-on-package, through-silicon via (TSV), or other techniques or combinations. Similarly, in one example, multiple memory devices 1040 may be integrated into memory modules 1070, which may in turn be integrated into the same package as the memory controller 1020. In these and other implementations, the memory controller 1020 may be part of the host processor 1010.

[0125] The memory devices 1040 each include one or more memory arrays 1060. The memory array 1060 represents addressable memory locations or storage locations for data. Typically, the memory array 1060 is managed as rows of data accessed via word line (rows) and bit line (individual bits within a row) control. The memory array 1060 may be organized as separate memory channels, ranks, and banks. Channels may refer to independent control paths to memory locations within the memory devices 1040. Ranks may refer to common memory locations across multiple parallel memory devices (e.g., same row addresses across different devices). Banks may refer to subsets of memory locations within a memory device 1040. In one example, the memory banks are divided into subbanks, where at least a portion of the circuitry (e.g.,Drivers, signal lines, control logic) are shared across the subbanks, allowing separate addressing and access. It goes without saying that channels, ranks, banks, subbanks, bank groups, or other organizations of memory locations and combinations of organizations may overlap in their application to physical resources. For example, a particular channel may access the same physical memory locations as a particular bank, which may also belong to a rank. The organization of memory resources is therefore understood as inclusive, not exclusive.

[0126] In one example, the memory devices 1040 include one or more registers 1044. The register 1044 represents one or more memory devices or memory locations that provide the configuration or settings for the operation of the memory device. In one example, the register 1044 may provide a memory location for the memory device 1040 to store data for access by the memory controller 1020 as part of a control or management operation. In one example, the register 1044 includes one or more mode registers. In one example, the register 1044 includes one or more general-purpose registers. The configuration of memory locations within the register 1044 may configure the memory device 1040 to operate in different "modes" in which command information may trigger different operations within the memory device 1040 depending on the mode.Additionally or alternatively, the different operating modes can also trigger different operations from address information or other signal lines depending on the operating mode. The settings of register 1044 can indicate the configuration for I / O settings (e.g., timing, termination or ODT (on-die termination) 1046, driver configuration, or other I / O settings).

[0127] In one example, memory device 1040 includes ODT 1046 as part of the interface hardware connected to I / O 1042. ODT 1046 can be configured as described above and provides settings for the impedance to be applied to the interface to specific signal lines. In one example, ODT 1046 is applied to DQ signal lines. In one example, ODT 1046 is applied to command signal lines. In one example, ODT 1046 is applied to address signal lines. In one example, ODT 1046 can be applied to any combination of the foregoing. The ODT settings can be changed depending on whether a memory device is a selected target of an access operation or a non-target device. The ODT 1046 settings can affect the timing and reflections of signaling on the terminated lines.Careful control of the ODT 1046 can enable higher-speed operation with better matching of the applied impedance and load. The ODT 1046 can be applied to specific signal lines of the I / O interface 1042, 1022 (e.g., ODT for DQ lines or ODT for CA lines) and does not necessarily need to be applied to all signal lines.

[0128] The storage device 1040 includes a controller 1050, which represents control logic within the storage device to control internal operations within the storage device. For example, the controller 1050 decodes the commands sent from the storage controller 1020 and generates internal operations to execute or satisfy the commands. The controller 1050 may be referred to as an internal controller and is separate from the host storage controller 1020. The controller 1050 may determine which mode is selected from the register 1044 and configure the internal execution of operations for accessing storage resources 1060 or other operations based on the selected mode.Control unit 1050 generates control signals to control the routing of bits within memory device 1040, to provide an appropriate interface for the selected mode, and to route a command to the correct memory locations or addresses. Control unit 1050 includes command logic 1052, which can decode the command encoding received on the command and address signal lines. Thus, command logic 1052 can be or include an instruction decoder. Command logic 1052 allows the memory device to recognize instructions and generate internal operations to execute the requested instructions.

[0129] Returning to the memory controller 1020, the memory controller 1020 includes command logic (CMD) 1024, which is logic or circuitry for generating commands to be sent to the memory devices 1040. Command generation may refer to the command before scheduling or to preparing queued commands that may then be sent. Generally, signaling in memory subsystems includes address information within or accompanying the command to specify or select one or more memory locations where the memory devices should execute the command. In response to scheduling transactions for the memory device 1040, the memory controller 1020 may issue commands via I / O 1022 to cause the memory device 1040 to execute the commands.In one example, controller 1050 of storage device 1040 receives and decodes command and address information obtained from storage controller 1020 via I / O 1042. Based on the received command and address information, controller 1050 can control the timing of the operations of the logic and circuitry within storage device 1040 to execute the commands. Controller 1050 is responsible for ensuring compliance with standards or specifications within storage device 1040, such as timing and signaling requirements. Storage controller 1020 can enforce compliance with standards or specifications through access scheduling and control.

[0130] The memory controller 1020 includes the scheduler 1030, which represents logic or circuitry for generating and ordering transactions to be sent to the memory device 1040. From one perspective, one could say that the primary function of the memory controller 1020 is to schedule memory access and other transactions for the memory device 1040. Such scheduling may include generating the transactions themselves to implement the data requests of the processor 1010 and maintain data integrity (e.g., with update commands). Transactions may include one or more commands and result in the transfer of commands or data, or both, over one or more time cycles, such as clock cycles or unit intervals.The transactions may be access commands such as read or write commands or related commands or a combination thereof, and other transactions may include memory management commands for configuration, settings, data integrity or other commands or a combination thereof.

[0131] The memory controller 1020 typically includes logic such as the scheduler 1030 to enable the selection and ordering of transactions to improve the performance of the system 1000. In this way, the memory controller 1020 can select which of the pending transactions should be sent to the memory device 1040 and in what order, which is typically achieved with much more complex logic than a simple first-in, first-out algorithm. The memory controller 1020 manages the transmission of the transactions to the memory device 1040 and controls the timing associated with the transaction. In one example, transactions have deterministic timing, which can be managed by the memory controller 1020 and used in determining the scheduling of the transactions with the scheduler 1030.

[0132] In one example, memory controller 1020 includes refresh logic (REF) 1026. Refresh logic 1026 may be used for memory resources that are volatile and need to be refreshed to maintain a deterministic state. In one example, refresh logic 1026 specifies a location for the refresh and a type of refresh to be performed. Refresh logic 1026 may trigger a self-refresh within memory device 1040 or perform external refreshes by sending refresh commands, or a combination thereof. In one example, controller 1050 within memory device 1040 includes refresh logic 1054 to perform the refresh within memory device 1040.In one example, refresh logic 1054 generates internal operations to perform a refresh in accordance with an external refresh received from memory controller 1020. Refresh logic 1054 may determine whether a refresh is directed to memory device 1040 and which memory resources 1060 should be refreshed in response to the command.

[0133] The Fig. Figures 11A-11B are block diagrams of an example CAMM system in which alarm signal testing can be performed.

[0134] As in Fig. As shown in Figure 11A, system 1102 includes a memory stack architecture monitored by a memory fault tracker capable of mirroring. System 1102 is an example of a system corresponding to an example of system 102, system 200, or system 300.

[0135] The substrate 1110 represents a SOC packaging substrate or a motherboard or system board. The substrate 1110 includes contacts 1112 that represent contacts for connecting to the memory. The CPU 1114 is a processor, or a central processing unit (CPU) or graphics processing unit (GPU) chip, that is disposed on the substrate 1110. The CPU 1114 performs the computational operations in the system 1102. In one example, the CPU 1114 includes multiple cores (not specifically shown) that may generate operations requesting reading data from and writing data to the memory. The CPU 1114 may include a memory controller to manage access to the memory devices.

[0136] The Compression-Attached Memory Module (CAMM) 1130 is a module with memory devices not specifically shown in the system 1102. The substrate 1110 is connected to the CAMM 1130 and its memory devices via the Compression Mount Technology (CMT) connector 1120. The connector 1120 includes contacts 1122 that are compression-based contacts. The compression-based contacts are compressible pins or devices whose shape compresses when pressure is applied to the connector 1120. In one example, the contacts 1122 represent C-shaped pins as shown. In one example, the contacts 1122 represent another compressible pin shape, such as a spring shape, an S-shape, or pins with other shapes that can be compressed.

[0137] CAMM 1130 includes contacts 1132 on one side of the CAMM board, which is connected to connector 1120. Contacts 1132 connect to the memory devices on the CAMM board. Plate 1140 represents a plate or housing that provides a structure for applying pressure to compress contacts 1122 of connector 1120.

[0138] Referring to Fig. 11B, system 1104 is a perspective view of a system consistent with system 1102. System 1104 shows memory controller 1150, which is not specifically illustrated in system 1102. Memory controller 1150 may provide row hammer mitigation to DRAMs 1136. DRAMs 1136 may be connected to memory controller 1150 via an alarm signal line. System 1104 enables DRAMs 1136 to perform an alarm signal test mode with memory controller 1150 in accordance with any example herein.

[0139] The CAMM 1130 is shown with memory chips or memory chips (DRAMs 1136) on one or both sides of the circuit board of the CAMM 1130. DRAMs 1136 are coupled via traces in or on the circuit board to conductive contacts, which in turn are coupled to contacts 1132, which in turn are coupled to contacts 1122 of the connector 1120.

[0140] The system 1104 shows holes 1142 in the plate 1140 for receiving fasteners, represented by screws 1144. Corresponding holes are located in the CAMM 1130, the connector 1120, and the substrate 1110. The screws 1144 can compressibly attach the CAMM 1130 to the substrate 1110 via the connector 1120.

[0141] Fig. 12 is a block diagram of an example computer system in which the in-band configuration mode may be implemented. System 1200 represents a computing device according to any of the examples provided herein and may be a laptop computer, a desktop computer, a tablet computer, a server, a gaming or entertainment control system, an embedded computing device, or other electronic device. System 1200 represents a system with memory according to an example of system 102, an example of system 200, or an example of system 300.

[0142] In one example, system 1200 includes memory subsystem 1220 with RCD 1224 in a memory module. The configuration of RCD 1224 may be programmable using in-band register write operations as described herein. Memory 1230 may be a DRAM device whose configuration may be programmable using in-band register write operations as described herein. In-band configuration (CONFIG) 1290 represents the components that enable the system to perform in-band register configuration updates using an update mode.

[0143] System 1200 includes a processor 1210, which may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware, or a combination thereof, to enable the processing or execution of instructions for system 1200. Processor 1210 may be a host processor device. Processor 1210 controls the overall operation of system 1200 and may be or include one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or a combination of such devices.

[0144] System 1200 includes boot / configuration area 1216, which stores boot code (e.g., the Basic Input / Output System (BIOS)), configuration settings, security hardware (e.g., the Trusted Platform Module (TPM)), or other system-level hardware operating outside of a host operating system (OS). Boot / configuration 1216 may include a non-volatile storage device, such as read-only memory (ROM), flash memory, or other storage devices.

[0145] In one example, system 1200 includes an interface 1212 connected to processor 1210, which may provide a higher-speed or high-throughput interface for system components requiring higher-bandwidth connections, such as memory subsystem 1220 or graphics interface components 1240. Interface 1212 represents an interface circuit that may be a stand-alone component or integrated into a processor chip. Interface 1212 may be integrated as circuitry on the processor chip or as a component on a system on a chip. If present, graphics interface 1240 provides an interface to graphics components to provide a visual representation to the user of system 1200. Graphics interface 1240 may be a stand-alone component or integrated into the processor chip or system on a chip.In one example, graphics interface 1240 may drive a high-resolution (HD) or ultra-high-resolution (UHD) display that provides output to a user. In one example, the display may be a touchscreen display. In one example, graphics interface 1240 generates a display based on the data stored in memory 1230 or based on the operations performed by processor 1210, or both.

[0146] The memory subsystem 1220 represents the main memory of the system 1200 and provides storage space for the code to be executed by the processor 1210 or for data values ​​used in the execution of a routine. The memory subsystem 1220 may include one or more types of random access memory (RAM), such as DRAM (three-dimensional cross-point memory) or other storage devices, or a combination of such devices. The memory 1230 stores and hosts, among other things, the operating system (OS) 1232 to provide a software platform for executing instructions in the system 1200. In addition, applications 1234 may be executed on the software platform of the operating system 1232 from the memory 1230. The applications 1234 are programs that have their own operating logic to perform one or more functions.Processes 1236 are agents or routines that provide support functions for the operating system 1232 or one or more applications 1234, or a combination thereof. The operating system 1232, the applications 1234, and the processes 1236 provide software logic to provide functions for the system 1200. In one example, the memory subsystem 1220 includes a memory controller 1222 that generates and issues instructions for the memory 1230. It should be understood that the memory controller 1222 may be a physical part of the processor 1210 or a physical part of the interface 1212. For example, the memory controller 1222 may be an integrated memory controller integrated into circuitry with the processor 1210, such as the processor die or a system on a chip.

[0147] Although not specifically shown, system 1200 may include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, interface buses, or others. Buses or other signal lines may communicatively or electrically couple components together, or may couple components both communicatively and electrically. Buses may include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuitry, or a combination thereof. The buses may be, for example, one or more system buses, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB) bus, or other buses, or a combination thereof.

[0148] In one example, system 1200 includes interface 1214, which can be connected to interface 1212. Interface 1214 can be a lower-speed interface than interface 1212. In one example, interface 1214 represents an interface circuit that can include discrete components and integrated circuits. In one example, multiple user interface components or peripheral components, or both, are connected to interface 1214. Network interface 1250 provides system 1200 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface 1250 can represent a network interface circuit (NIC) that enables connection to a remote device over a network connection.The network connection enabled by network interface 1250 may include an Ethernet adapter, wireless connectivity components, cellular network connectivity components, USB (Universal Serial Bus), or other wired or wireless standards-based or proprietary interfaces. Network interface 1250 may exchange data with a remote device, which may include sending data stored in memory or receiving data to be stored in memory.

[0149] In one example, system 1200 includes one or more input / output (I / O) interfaces 1260. I / O interface 1260 may include one or more interface components through which a user interacts with system 1200 (e.g., audio, alphanumeric, tactile / touch, or other interfaces). Peripheral interface 1270 may include any hardware interface not explicitly mentioned above. Peripherals generally refer to devices that connect dependently to system 1200. A dependent connection is one in which system 1200 provides the software or hardware platform, or both, on which operation is performed and with which a user interacts.

[0150] In one example, system 1200 includes a memory subsystem 1280 for storing data in non-volatile form. In one example, in certain system implementations, at least certain components of memory 1280 may overlap with components of memory subsystem 1220. Memory subsystem 1280 includes storage device(s) 1284, which may be or include any conventional medium for storing large amounts of data in non-volatile form, such as one or more magnetic, solid-state, NAND, 3DXP, or optical-based disks, or a combination thereof. Memory 1284 contains code or instructions and data 1286 in a persistent state (i.e., the value persists despite power interruption to system 1200). Memory 1284 may be generally considered "memory," although memory 1230 is typically the execution or operational memory that provides instructions to processor 1210.While memory 1284 is non-volatile, memory 1230 may include volatile memory (i.e., the value or state of the data is indeterminate if power to system 1200 is interrupted). In one example, memory subsystem 1280 includes a controller 1282 as an interface to memory 1284. In one example, controller 1282 is a physical part of interface 1214 or processor 1210, or may include circuitry or logic in both processor 1210 and interface 1214.

[0151] The power source 1202 supplies power to the components of the system 1200. More specifically, the power source 1202 is typically connected to one or more power supplies 1204 within the system 1200 to supply power to the components of the system 1200. In one example, the power supply 1204 includes an AC-to-DC adapter for connection to an electrical outlet. Such an AC power source may be a renewable energy source (e.g., solar power) 1202. In one example, the power source 1202 includes a DC power source, such as an external AC-to-DC converter. In one example, the power source 1202 or the power supply 1204 includes wireless charging hardware for charging near a charging pad. In one example, the power source 1202 may include an internal battery or a fuel cell source.

[0152] Fig.13 is a block diagram of an example multi-node network in which the in-band configuration mode can be implemented. System 1300 represents a network of nodes capable of applying adaptive ECC. In one example, system 1300 represents a data center. In one example, system 1300 represents a server farm. In one example, system 1300 represents a data cloud or a processing cloud.

[0153] System 1300 illustrates a system including memory according to an example of system 102, an example of system 200, or an example of system 300. In one example, storage node 1322 includes memory modules with an RCD (not specifically shown). The configuration of the RCD may be programmed using in-band register writes in accordance with any of the descriptions contained herein, as represented by in-band configuration (CONFIG) 1392. System 1300 may include memory devices in accordance with that described, and in-band configuration (CONFIG) 1390 illustrates the ability to use in-band register writes in accordance with any of the descriptions contained herein to program an RCD and / or a memory device.

[0154] One or more clients 1302 submit requests to system 1300 over network 1304. Network 1304 represents one or more local area networks, wide area networks, or a combination thereof. Clients 1302 may be human or machine clients that submit requests for system 1300 to perform operations. System 1300 executes applications or data computing tasks requested by clients 1302.

[0155] In one example, system 1300 includes one or more racks that provide structural and interconnection resources to house and interconnect multiple compute nodes. In one example, rack 1310 includes multiple nodes 1330. In one example, rack 1310 hosts multiple blade components, blade 1320[0], ..., blade 1320[N-1], collectively blades 1320. Hosting refers to the provision of power, structural or mechanical support, and interconnections. Blades 1320 may refer to compute resources on printed circuit boards (PCBs), where a PCB contains the hardware components for one or more nodes 1330. In one example, blades 1320 do not include a chassis or other "box" other than that provided by rack 1310. In one example, blades 1320 include an exposed-connector chassis for plugging into rack 1310.In one example, the system 1300 does not include a rack 1310, and each blade 1320 includes a chassis or enclosure that can be stacked or otherwise placed in close proximity to other blades and enables interconnection of the nodes 1330.

[0156] System 1300 includes fabric 1370, which represents one or more interconnections for nodes 1330. In one example, fabric 1370 includes multiple switches 1372 or routers or other hardware to route signals between nodes 1330. Furthermore, fabric 1370 may connect system 1300 to network 1304 for access by clients 1302. In addition to the routing equipment, fabric 1370 may also include the cables or ports or other hardware equipment to interconnect nodes 1330. In one example, fabric 1370 has one or more associated protocols to manage the routing of signals through system 1300. In one example, the protocol or protocols depend at least in part on the hardware equipment used in system 1300.

[0157] As shown in the figure, rack 1310 contains N blades 1320. In one example, system 1300 contains rack 1350 in addition to rack 1310. As shown, rack 1350 contains M blade components, blade 1360[0], ..., blade 1360[M-1], collectively blades 1360. M is not necessarily the same as N; therefore, it should be understood that various hardware components can be used and connected through fabric 1370 to form system 1300. Blades 1360 can be the same or similar blades as 1320. Nodes 1330 can be any type of node, and they do not all need to be the same type of node. System 1300 is neither constrained to be homogeneous nor constrained to be non-homogeneous.

[0158] The nodes in system 1300 may include compute nodes, memory nodes, storage nodes, accelerator nodes, or other nodes. Rack 1310 is represented by storage nodes 1322 and storage nodes 1324, which represent shared system storage resources and shared persistent storage, respectively. One or more nodes of rack 1350 may be a storage node or a storage node.

[0159] Nodes 1330 are examples of compute nodes. For simplicity, only the node for computing in blade 1320[0] is shown in detail. However, the other nodes in system 1300 may be the same or similar. At least some nodes 1330 are compute nodes with processor (proc) 1332 and memory 1340. A compute node refers to a node with processing resources (e.g., one or more processors) that runs an operating system and can receive and process one or more tasks. In one example, at least some nodes 1330 are server nodes with a server as processing resources, represented by processor 1332 and memory 1340.

[0160] Storage node 1322 represents an example of a storage node whose system memory is located external to the compute nodes. Storage nodes may include a controller 1382, which represents a processor on the node, to manage access to the memory. The storage nodes include memory 1384 as storage resources shared by multiple compute nodes.

[0161] Storage node 1324 is an example of a storage server, that is, a node with more storage resources than a compute node, which, instead of processors for executing tasks, includes processing resources for managing access to the storage nodes within the storage server. Mass storage nodes may include controllers 1386 that manage access to the mass storage 1388 of the mass storage node.

[0162] In one example, node 1330 includes interface controller 1334, which represents logic for controlling node 1330's access to fabric 1370. The logic may include hardware resources for connecting to the physical interconnect hardware. The logic may include software or firmware logic for managing the connection. In one example, interface controller 1334 is a host fabric interface, which may be a fabric interface according to an example described herein. The interface controllers for storage node 1322 and mass storage node 1324 are not explicitly shown.

[0163] Processor 1332 may include one or more separate processors. Each individual processor may include a single processing unit, a multi-core processing unit, or a combination thereof. The processing unit may be a primary processor such as a central processing unit (CPU), a peripheral processor such as a graphics processing unit (GPU), or a combination thereof. Memory 1340 may consist of or include storage devices represented by memory 1340 and a memory controller represented by controller 1342.

[0164] In view of the descriptions contained herein, in one aspect, an apparatus comprises: a hardware interface for connecting to a command bus, wherein the hardware interface receives a mode register update (MRUPD) mode command to trigger entry into the MRUPD mode; a decision feedback equalization (DFE) configuration register for storing a first configuration setting for the hardware interface to the command bus; and a second configuration register for a configuration setting other than DFE, the second configuration register for storing a second configuration setting for the hardware interface to the command bus; wherein the apparatus updates the second configuration register with mode register write (MRW) commands in the MRUPD mode.

[0165] In one example of the device, the hardware interface comprises a dynamic random access memory (DRAM) hardware interface, wherein the MRUPD mode is to update the configuration for the DRAM device. In accordance with one of the preceding examples of the device, in one example, the hardware interface comprises a registering clock device (RCD) hardware interface, wherein the MRUPD mode is to update the configuration for the RCD. In accordance with one of the preceding examples of the device, in one example, the device is to update the second configuration register to store a configuration setting for on-die termination (ODT) in the MRUPD mode.In accordance with any preceding example of the device, in one example, the device is to update the second configuration register to store a configuration setting for the voltage reference (Vref) in MRUPD mode. In accordance with any preceding example of the device, in one example, the second configuration register comprises a plurality of additional configuration registers for a plurality of additional configuration settings, wherein the device is to update the plurality of additional configuration registers sequentially in MRUPD mode to store the plurality of additional configuration settings and then exit MRUPD mode. In accordance with any preceding example of the device, in one example, the device is to update the configuration for Chip Select (CS) and for Command and Address (CA) sequentially.In accordance with one of the preceding examples of the device, in one example, the device is to update the DFE configuration register in MRUPD mode. In accordance with one of the preceding examples of the device, in one example, the device is to update the second configuration register with mode register write (MRW) commands in MRUPD mode.

[0166] Generally speaking, with respect to the descriptions contained herein, in one aspect, a computer system includes: a memory controller coupled to a command bus; and a memory chip coupled to the command bus with a command bus interface, wherein the memory chip receives an MRUPD mode command from the memory controller to cause the memory chip to enter an MRUPD mode, the memory chip including: a decision feedback equalization (DFE) configuration register for storing a first configuration setting for the command bus interface; and a second configuration register for a configuration setting other than DFE, the second configuration register for storing a second configuration setting for the command bus interface; wherein the memory chip is to update the second configuration register with MRUPD mode write commands.

[0167] In one example of the computer system, the memory chip comprises a dynamic random access memory (DRAM), wherein the MRUPD mode is for updating the configuration for the DRAM. In accordance with any preceding example of the computer system, in one example, the memory chip comprises a registering clock device (RCD), wherein the MRUPD mode is for updating the configuration for the RCD. In accordance with any preceding example of the computer system, in one example, the memory chip is to update the second configuration register to store a configuration setting for the on-die termination (ODT) in the MRUPD mode. In accordance with any preceding example of the computer system, in one example, the memory chip is to update the second configuration register to store a configuration setting for the voltage reference (Vref) in the MRUPD mode.In accordance with any preceding example of the computer system, in one example, the second configuration register comprises a plurality of additional configuration registers for a plurality of additional configuration settings, wherein the memory chip is to sequentially update the plurality of additional configuration registers in MRUPD mode to store the plurality of additional configuration settings and then exit the MRUPD mode. In accordance with any of the preceding examples of the computer system, in one example, the memory chip is to sequentially update the configuration for Chip Select (CS) and for Command and Address (CA). In accordance with any of the preceding examples of the computer system, in one example, the memory chip is to update the DFE configuration register in MRUPD mode.In accordance with any preceding example of the computer system, in one example the computer system includes a multi-core processor unit coupled to the memory controller. In accordance with any preceding example of the computer system, in one example the computer system includes a display communicatively coupled to a processor device. In accordance with any preceding example of the computer system, in one example the computer system includes a battery for powering the system. In accordance with any preceding example of the computer system, in one example the computer system includes network interface circuitry for coupling with a remote device via a network connection.

[0168] In view of the descriptions contained herein, in one aspect, a method for setting a configuration includes: receiving a mode register update (MRUPD) command to trigger entry into MRUPD mode; updating a decision feedback equalization (DFE) configuration register in MRUPD mode; and updating a second configuration register for a configuration setting other than DFE in MRUPD mode.

[0169] In one example of the method, receiving the MRUPD mode command includes receiving the MRUPD command at a dynamic random access memory (DRAM) device, wherein the MRUPD mode is to update the configuration for the DRAM device. In accordance with any preceding example of the method, in one example, receiving the MRUPD mode command includes receiving the MRUPD command at a registering clock device (RCD), wherein the MRUPD mode is to update the configuration for the RCD. In accordance with any of the preceding examples of the method, in one example, updating the second configuration register includes storing a configuration setting for on-die termination (ODT) in MRUPD mode. In accordance with any of the preceding examples of the method, in one example, storing a configuration setting for voltage reference (Vref) in MRUPD mode.In accordance with any preceding example of the method, in one example, the second configuration register comprises a plurality of additional configuration registers for a plurality of additional configuration settings, wherein updating the second configuration register comprises storing the plurality of additional configuration settings sequentially in MRUPD mode and then exiting the MRUPD mode. In accordance with any of the preceding examples of the method, in one example, updating the second configuration comprises updating the configuration for Chip Select (CS) and for Command and Address (CA) sequentially. In accordance with any of the preceding examples of the method, in one example, updating the second configuration comprises updating the DFE configuration register in MRUPD mode.In accordance with any preceding example of the method, in one example, updating the second configuration comprises updating the second configuration register with mode register write (MRW) commands in MRUPD mode. .

[0170] Flowcharts, such as the one shown here, show examples of the sequence of different process steps. The flowcharts can specify both the operations to be performed by a software or firmware routine and the physical operations. A flowchart can illustrate an example implementation of states of a finite state machine (FSM), which can be implemented in hardware and / or software. Unless otherwise stated, the order of actions can be changed even if they are shown in a specific order. The diagrams shown are therefore only examples, and the process can be performed in a different order, and some actions may be executed in parallel. In addition, one or more actions may be omitted, so not all implementations perform all actions.

[0171] To the extent that various operations or functions are described herein, they may be described or defined as software code, instructions, configuration, and / or data. The content may be directly executable (“object” or “executable” form), source code, or difference code (“delta” or “patch” code). The software content described herein may be delivered via an article having the content stored thereon or via a method for operating a communications interface to send data over the communications interface. A machine-readable storage medium can cause a machine to perform the described functions or operations and includes any mechanism that stores information in a form accessible by a machine (e.g., a computer, an electronic system, etc.), such as writable / non-writable media (e.g.,Read-only memory (ROM), random-access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communications interface includes any mechanism that interfaces with a hard-wired, wireless, optical, etc. medium to communicate with another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communications interface can be configured by providing configuration parameters and / or sending signals to prepare the communications interface to provide a data signal describing the software content. Access to the communications interface can be provided through one or more commands or signals sent to the communications interface.

[0172] Various components described herein may be a means of performing the described operations or functions. Each component described herein includes software, hardware, or a combination thereof. The components may be implemented as software modules, hardware modules, special-purpose hardware (e.g., application-specific hardware, application-specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, hard-wired circuits, etc.

[0173] Apart from what is described herein, various changes may be made to what is disclosed and to the embodiments of the invention without departing from its scope. Therefore, the figures and examples herein should be considered in an illustrative rather than a limiting sense. The scope of the invention should be measured solely by reference to the following claims. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 596,257

[0001]

Claims

[1] Device for setting the memory configuration, comprising: a hardware interface for connection to a command bus, the hardware interface receiving a mode register update (MRUPD) command to trigger entry into the MRUPD mode; a DFE (Decision Feedback Equalization) configuration register for storing a first configuration setting for the hardware interface to the command bus; and a second configuration register for a configuration setting other than DFE, the second configuration register for storing a second configuration setting for the hardware interface to the command bus; wherein the device is to update the second configuration register with mode register write (MRW) commands in MRUPD mode. [2] The device of claim 1, wherein the hardware interface comprises a dynamic random access memory (DRAM) hardware interface, wherein the MRUPD mode is to update the configuration for the DRAM device. [3] The apparatus of claim 1, wherein the hardware interface comprises a hardware interface of a registering clock device (RCD), wherein the MRUPD mode is for updating the configuration for the RCD. [4] The apparatus of claim 1, wherein the apparatus is to update the second configuration register to store a configuration setting for on-die termination (ODT) in MRUPD mode. [5] The device of claim 1, wherein the device is to update the second configuration register to store a configuration setting for the voltage reference (Vref) in MRUPD mode. [6] The device of claim 1, wherein the second configuration register comprises a plurality of additional configuration registers for a plurality of additional configuration settings, wherein the device is to update the plurality of additional configuration registers sequentially in the MRUPD mode to store the plurality of additional configuration settings and then exit the MRUPD mode. [7] The apparatus of claim 6, wherein the apparatus updates the configuration for Chip Select (CS) and for Command and Address (CA) sequentially. [8] The apparatus of claim 1, wherein the apparatus is to update the DFE configuration register in MRUPD mode. [9] The apparatus of claim 1, wherein the apparatus is to update the second configuration register with mode register write commands (MRW) in MRUPD mode. [10] A method for setting the memory configuration, comprising: Receiving a mode register update (MRUPD) command to trigger entry into MRUPD mode; Updating a Decision Feedback Equalization (DFE) configuration register in MRUPD mode; and Updating a second configuration register for a configuration setting other than DFE in MRUPD mode. [11] The method of claim 10, wherein receiving the MRUPD mode command comprises receiving the MRUPD command at a dynamic random access memory (DRAM) device, the MRUPD mode being to update the configuration for the DRAM device, or wherein receiving the MRUPD mode command comprises receiving the MRUPD command at a registering clock device (RCD), the MRUPD mode being to update the configuration for the RCD. [12] The method of claim 10, wherein updating the second configuration register comprises storing a configuration setting for on-die termination (ODT) in MRUPD mode or storing a configuration setting for voltage reference (Vref) in MRUPD mode. [13] The method of claim 10, wherein the second configuration register comprises a plurality of additional configuration registers for a plurality of additional configuration settings, wherein updating the second configuration register comprises storing the plurality of additional configuration settings in sequence in MRUPD mode and then exiting the MRUPD mode. [14] An article of manufacture comprising a computer-readable storage medium having content stored thereon, which, when executed, causes a machine to perform a method for setting the memory configuration, comprising: Receiving a mode register update (MRUPD) command to trigger entry into MRUPD mode; Updating a Decision Feedback Equalization (DFE) configuration register in MRUPD mode; and Updating a second configuration register for a configuration setting other than DFE in MRUPD mode. [15] The article of manufacture of claim 14, wherein receiving the MRUPD mode command comprises receiving the MRUPD command at a dynamic random access memory (DRAM) device, the MRUPD mode being to update the configuration for the DRAM device, or wherein receiving the MRUPD mode command comprises receiving the MRUPD command at a registering clock device (RCD), the MRUPD mode being to update the configuration for the RCD. [16] The article of manufacture of claim 14, wherein updating the second configuration register comprises storing a configuration setting for on-die termination (ODT) in MRUPD mode or storing a configuration setting for voltage reference (Vref) in MRUPD mode. [17] The article of manufacture of claim 14, wherein the second configuration register comprises a plurality of additional configuration registers for a plurality of additional configuration settings, wherein updating the second configuration register comprises storing the plurality of additional configuration settings sequentially in MRUPD mode and then exiting the MRUPD mode.

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