DISPLAY SYSTEM, DISPLAY CONTROL METHOD AND VEHICLE

Abstract

The present disclosure relates to a display system (100), a method for controlling the display, and a vehicle (1000). Embodiments of the disclosure may provide a display system (100) comprising a display panel (110) which includes a plurality of subpixel units (Spu) having a first subpixel (SPw) with a first emission angle and a second subpixel (SPn) with a second emission angle, comprising a gate driver circuit (120) configured to supply gate signals (GS) to the display panel (110), and comprising a timing controller (140) configured to control an emission cycle of the first subpixel (SPw) or the second subpixel (SPn) for an emission cycle control range between a first range (A1) in which the first subpixel (SPw) emits light and a second range (A2) in which the second subpixel (SPn) emits light.

Description

CROSS-REFERENCE TO A RELATED REGISTRATION

[0001] This application claims priority over Korean patent application No. 10-2023-0144325, which was filed on October 26, 2023. BACKGROUNDTechnical field

[0002] Embodiments of the disclosure relate to a display system, a method for controlling the display, and a vehicle that is capable of improving a degradation characteristic of the display system in the vehicle. Description of the related technique

[0003] A vehicle is a means of transport that can move people or goods using kinetic energy. Here, "vehicle" can encompass various types of transport that can carry people, such as a car, a truck, a bus, an airplane, and a ship.

[0004] To ensure the safety and comfort of vehicle users, the vehicle can be equipped with various sensors and electronic devices, and the functions of the vehicle are becoming increasingly diverse.

[0005] The functions of the vehicle may include comfort features to promote the convenience of the driver and safety features to promote the safety of drivers or pedestrians.

[0006] Comfort features can include technologies such as infotainment functions (information and entertainment), autonomous driving capabilities, and driver assistance systems for nighttime visibility and blind spot monitoring. Examples of comfort features include active cruise control (ACC), smart parking assist system (SPAS), night vision (NV), head-up display (HUD), around view monitor (AVM), and adaptive headlight system (AHS).

[0007] Safety features can include technologies that ensure the safety of drivers or pedestrians, such as the lane departure warning system (LDWS), the lane keeping assist system (KAS), and the autonomous emergency braking system (AEB), etc.

[0008] Meanwhile, a vehicle can have a display system with various types of display panels. A vehicle control unit can provide the driver or passengers with various comfort and safety functions by controlling the information fed to the internal display panel.

[0009] The different types of display panels can be liquid crystal displays, organic light-emitting display panels, etc.

[0010] Since there may be other passengers in the vehicle at this time besides the driver, various information can be displayed via a number of display panels so that the occupants (driver or front passenger) can recognize it. SHORT SUMMARY

[0011] For this purpose, a plurality of emission regions with different emission angles can be arranged on the display panel. Currently, there is a problem of luminance deviation, which occurs due to the different degradation in the emission regions with different emission angles.

[0012] The inventors of the disclosure have invented a display system, a display control method, and a vehicle capable of improving a degradation characteristic of the display system in the vehicle.

[0013] Embodiments of the disclosure can provide a display system, a display control method and a vehicle that are capable of improving a degradation characteristic by controlling drive cycles of a plurality of emission ranges with different emission angles.

[0014] Embodiments of the disclosure can provide a display system, a method for controlling the display, and a vehicle capable of improving a degradation characteristic by varying control cycles depending on positions based on a boundary region of a plurality of emission regions with different emission angles. Embodiments of the disclosure provide a display system according to claim 1, a method for controlling the display according to claim 17, a vehicle according to claim 20, and a display system according to claim 21. Further embodiments are described in the dependent claims.

[0015] Embodiments of the disclosure provide a display system including a display panel having a plurality of subpixel units including a first subpixel having a first emission angle and a second subpixel having a second emission angle, a gate driver circuit configured to supply gate signals to the display panel, and a timing controller configured to control an emission cycle of the first subpixel or the second subpixel for an emission cycle control range between a first region in which the first subpixel emits light and a second region in which the second subpixel emits light.

[0016] Embodiments of the disclosure provide a display control method for controlling a display panel having a plurality of subpixel units, each having a first subpixel with a first emission angle and a second subpixel with a second emission angle, comprising a step of controlling the first subpixel for a first area of ​​the display panel, a step of controlling the second subpixel for a second area of ​​the display panel, a step of alternately emitting the first subpixel and the second subpixel with a predetermined cycle for a 1-1 area within the first area, and a step of alternately emitting the first subpixel and the second subpixel with a predetermined cycle for a 2-1 area within the second area.

[0017] Embodiments of the disclosure provide a vehicle comprising a display panel having a plurality of subpixel units comprising a first subpixel with a first emission angle and a second subpixel with a second emission angle, a gate driver circuit configured to supply gate signals to the display panel, and a timing controller configured to control an emission cycle of the first subpixel or the second subpixel for an emission cycle control range between a first range in which the first subpixel emits light and a second range in which the second subpixel emits light.

[0018] According to embodiments of the disclosure, it is possible to provide a power-saving display system that is able to reduce power consumption to compensate for characteristic values ​​by improving the degradation characteristics of the display system in the vehicle.

[0019] According to the embodiments of the disclosure, it is possible to improve a degradation characteristic by controlling the drive cycles of a plurality of emission ranges with different emission angles.

[0020] According to embodiments of the disclosure, it is possible to improve a degradation characteristic by varying drive cycles depending on positions based on a boundary region of a plurality of emission regions with different emission angles. DESCRIPTION OF THE DIFFERENT VIEWS OF THE DRAWINGS

[0021] The above and other objects, features, and benefits of the disclosure will be better understood from the following detailed description in conjunction with the accompanying drawings, in which: Fig. 1 is a diagram illustrating the interior of a vehicle according to embodiments of the present disclosure; Fig. Figure 2 is a schematic diagram illustrating a configuration of a display system according to embodiments of the present disclosure; Fig. 3 is an example diagram illustrating a display system according to embodiments of the present disclosure; Fig. Figure 4 is a diagram showing an example of a structure for controlling a plurality of display panels in a display system according to embodiments of the present disclosure; Fig. Figure 5 is a diagram illustrating a display panel with subpixels having different emission angles in a display system according to embodiments of the present disclosure; Fig. Figure 6 is a diagram illustrating various structures of the first subpixel and the second subpixel that form a subpixel unit in the display system according to embodiments of the present disclosure; Fig. Figure 7 is a diagram illustrating a first lens arranged on a first subpixel and a second lens arranged on a second subpixel in the display system according to embodiments of the present disclosure; Fig. 8 is a cross-sectional diagram of a subpixel unit in a display system according to embodiments of the present disclosure; Fig. 9 is a diagram illustrating a case where different images are displayed in the first area and the second area of ​​the display panel in the display system according to embodiments of the present disclosure; Fig. 10 is a diagram illustrating a degradation state when different images are displayed in the first area and the second area of ​​the display panel in the display system according to embodiments of the present disclosure; Fig. 11 is a diagram illustrating a case that controls the emission cycle of a first region and a second region having different viewing angles in a display system according to embodiments of the present disclosure; Fig. 12 is a block diagram illustrating a configuration of a gate driver circuit in a display system according to embodiments of the present disclosure; Fig. 13 is a diagram illustrating a gate signal output from a gate driver circuit in a display system according to embodiments of the present disclosure; Fig. 14 is a diagram illustrating a circuit operation in which the first subpixel of a subpixel unit emits light in a display system according to embodiments of the present disclosure; Fig. 15 is a diagram of signal waveforms controlled by the first subpixel of a unit subpixel in a display system according to embodiments of the present disclosure; Fig. 16 is a diagram illustrating a switching operation in which the second subpixel of a subpixel unit emits light in a display system according to embodiments of the present disclosure; Fig. Figure 17 is a diagram of signal waveforms controlled by the second subpixel of a subpixel unit in a display system according to embodiments of the present disclosure; Fig. Figures 18 to 20 are diagrams illustrating cycle control signals and emission states as a function of the display panel area in the display system according to embodiments of the present disclosure; and Fig. Figure 21 is a diagram illustrating a variation of the emission cycle near the boundary between the first area and the second area in the display system according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0022] The following section describes in detail some embodiments of the disclosure with reference to exemplary drawings. In the following description of examples or embodiments of the disclosure, reference is made to the accompanying drawings, which show specific examples or embodiments that can be implemented for illustrative purposes and in which the same reference numerals and symbols can be used to designate identical or similar components, even if they are shown in different accompanying drawings. Furthermore, the following description of examples or embodiments of the disclosure omits detailed descriptions of known functions and components where it is determined that such a description might make the subject matter unclear in some embodiments of the disclosure.Terms such as "including," "having," "containing," "consisting of," and "consisting of" are generally intended to allow for the addition of other components unless the terms are used with the phrase "only." The singular forms used herein include the plural forms unless the context clearly indicates otherwise.

[0023] Terms such as "first," "second," "A," "B," "(A)," or "(B)" may be used herein to describe elements of the disclosure. Each of these terms is not used to define the nature, order, sequence, or number of the elements, etc., but merely to distinguish the corresponding element from other elements.

[0024] When it is stated that a first element is "connected or coupled" to a second element, "touches or overlaps" it, etc., this is to be understood as meaning not only that the first element can be "directly connected or coupled" to the second element, or that it can "directly touch or overlap," but also that a third element can be "inserted" between the first and second elements, or that the first and second elements can be "connected or coupled," "touch or overlap," etc., via a fourth element. Here, the second element can be contained within at least one of two or more elements that are "connected or coupled," "touch or overlap," etc., with each other.

[0025] When time-related expressions such as "after," "following," "next," "before," and the like are used to describe processes or operations of elements or configurations, or of sequences or steps in methods of operation, processing, and manufacturing, these expressions may be used to describe non-consecutive or non-sequential processes or operations, unless the expression "immediately" or "immediately" is used together.

[0026] Furthermore, when mentioning dimensions, relative sizes, etc., it should be noted that numerical values ​​for elements or characteristics, or corresponding information (e.g., level, range, etc.), include a tolerance or error range that can be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no specific description is provided. Moreover, the term "may" encompasses all meanings of the term "can."

[0027] Hereinafter, various embodiments of the disclosure will be described in detail with reference to the accompanying drawings.

[0028] Fig. 1 is a diagram illustrating an interior of a vehicle according to embodiments of the present disclosure.

[0029] With reference to Fig. 1 The interior of the vehicle 1000 according to embodiments of the present disclosure may comprise a driver's seat, a passenger seat, a dashboard equipped with various instruments for driving, located in front of the driver's and passenger's seats, and a center console with a control panel for electronic devices.

[0030] The instrument panel may include a first display panel 111 for displaying driving information, including a speedometer. The first display panel 111 may be referred to as the instrument panel display panel.

[0031] The first display panel 111 is a display panel that enables safe driving of the vehicle 1000 by providing the driver with information about the driving status of the vehicle 1000 and the operation of various electronic devices installed in the vehicle 1000. The first display panel 111, located behind the steering wheel relative to the driver's seat, may include a speedometer for displaying the driving speed, a trip meter for displaying the driving distance, a tachometer for displaying the engine speed, a fuel gauge, a water temperature gauge, an engine temperature gauge, and various warning lights.

[0032] The center console can be located between the driver and passenger seats and corresponds to the area where the dashboard and gearshift lever meet vertically. The center console may house an audio system, air conditioning, heating controls, a navigation system, air vents, a cigarette lighter, an ashtray, cup holders, etc. Additionally, the center console may include a second display panel.

[0033] The second display panel 112 can show a route to the destination or a map image corresponding to the current location and can display a user interface for controlling various electronic devices in the vehicle 1000. If the vehicle 1000 is connected to a mobile device, a screen provided by the mobile device can also be displayed on the second display panel 112.

[0034] The second display panel 112, located between the driver and passenger seats of the vehicle 1000, may be referred to as a center console display panel.

[0035] Additionally, a third display panel 113 may be arranged at the front of the passenger seat for passenger convenience. The third display panel 113 arranged at the passenger seat may be referred to as a passenger display panel.

[0036] Furthermore, in addition to the first display panel 111 (dashboard display panel), a second display panel 112 (center console display panel), and the passenger display panel 113, the display panel 110 may include at least one of a windshield display panel, a side mirror display panel, a rearview mirror display panel, and a side window display panel. Of course, other types of display panels may also be installed.

[0037] The windshield display panel may be a display panel that projects a virtual image onto a portion of the windshield through which the front of the vehicle 1000 can be seen. By displaying vehicle speed, remaining fuel, and route information via the windshield display panel, the driver's gaze may be reduced from being unnecessarily diverted elsewhere.

[0038] The side mirror display panel may be a display panel that can display a side image captured by a side camera on part or all of a side mirror to view the side of the vehicle 1000. Therefore, the driver can check not only the side image reflected by the side mirror but also the side image captured by the side camera via the side mirror display panel.

[0039] The rearview mirror display panel can be a display panel that can show a rear image captured by a reversing camera on part or all of the rearview mirror to view the rear of the vehicle. Therefore, the driver can check not only the image reflected by the rearview mirror but also the image captured by the reversing camera via the rearview mirror display panel.

[0040] The side window display panel can be used to project a virtual image onto a portion of the side window, allowing the view through the side of the vehicle. Various vehicle information can be displayed via the side window display panel.

[0041] Fig. 2 is a schematic diagram illustrating a configuration of a display system according to embodiments of the present disclosure.

[0042] With reference to Fig. 2, a display system 100 according to embodiments of the present disclosure may include a display panel 110 connected to a plurality of gate lines GL and a plurality of data lines DL, and in which a plurality of subpixels SP are arranged in the form of a matrix, a gate driver circuit 120 that supplies gate signals to the plurality of gate lines GL, a data driver circuit 130 that supplies a data voltage via the plurality of data lines DL, a timing controller 140 for controlling the gate driver circuit 120 and the data driver circuit 130, and a power management circuit 150 that supplies power for the display driving operation.

[0043] The display panel 110 shows an image based on sampling signals transmitted by the gate driver circuit 120 via the plurality of gate lines GL, and on data voltages transmitted by the data driver circuit 130 via the plurality of data lines DL.

[0044] In the case of a liquid crystal display system, the display panel 110 comprises a liquid crystal layer sandwiched between two substrates and can operate in any known mode, such as twisted nematic (TN) mode, vertical alignment (VA) mode, in-plane switching (IPS) mode, or fringe field switching (FFS) mode. In the case of an organic light-emitting display system, the display panel 110 can be implemented using a top-emission process, a bottom-emission process, or a dual-emission process.

[0045] In the display panel 110, a plurality of subpixels SP can be arranged in the form of a matrix, wherein each subpixel SP can be formed from subpixels SP with different colors, e.g. a white subpixel, a red subpixel, a green subpixel and a blue subpixel, and each subpixel SP can be defined by the plurality of data lines DL and the plurality of gate lines GL.

[0046] A subpixel SP can include a thin-film transistor (TFT), a light-emitting element that emits light according to the data voltage, and a storage capacitor that is electrically connected to the light-emitting element to maintain a voltage, arranged in an area formed by a data line DL and a gate line GL.

[0047] For example, if the display system 100 with a resolution of 2,160 x 3,840 is formed from four subpixels SP, comprising a white subpixel, a red subpixel, a green subpixel, and a blue subpixel, because there are 2,160 gate lines GL and 3,840 data lines DL connected to the four subpixels SP, a total of 3,840 x 4 = 15,360 data lines DL can be provided, and the subpixels SP can be arranged in areas formed by the gate lines GL and the data lines DL.

[0048] The gate driver circuit 120 is controlled by the timing controller 140 and successively outputs sampling signals to the majority of gate lines GL arranged in the display panel 110 in order to control the control timing of the majority of subpixels SP.

[0049] Depending on the application, the gate driver circuit can generate 120 sampling signals that control the drive timing of subpixel SP, and generate light emission signals that control the light emission timing of subpixel SP. In this case, the gate signal generated by the gate driver circuit can contain both sampling signals and light emission signals. A circuit that generates the sampling signals and a circuit that generates the light emission signals can be implemented as separate circuits or as a single circuit.

[0050] If the circuit that generates the sampling signals and the circuit that generates the light emission signals are implemented as separate circuits, the gate driver circuit 120 can include a sampling driver circuit that generates the sampling signals and a light emission driver circuit that generates the light emission signals.

[0051] In the display system 100 with a resolution of 2160 x 3840, a case where scanning signals are sequentially output from the first gate line to the 2160th gate line with respect to the 2160 gate lines GL may be referred to as 2160-phase drive. Alternatively, as in a case where scanning signals are sequentially output from the first gate line to the fourth gate line and then sequentially from the fifth gate line to the eighth gate line, a case where scanning signals are sequentially output based on four gate lines may be referred to as four-phase drive. That is, a case where scanning signals are sequentially output for every N gate lines GL may be referred to as N-phase drive.

[0052] In this case, the gate driver circuit 120 can comprise one or more integrated gate driver circuits (GDICs), and depending on the control method, the gate driver circuit 120 can be located on only one side or on both sides of the display panel 110. Alternatively, the gate driver circuit 120 can be formed directly within a frame area of ​​the display panel 110 to be implemented as a gate-in-panel (GIP).

[0053] The data driver circuit 130 receives digital image data DATA from the timing controller 140 and converts the received digital image data DATA into an analog data voltage. The data voltage is then output to each data line DL at a specific time when the sampling signal is applied via the gate line GL, and thus each subpixel SP connected to the data line DL displays a light emission signal with a brightness corresponding to the data voltage.

[0054] Similarly, the data driver circuit 130 may include one or more source driver integrated circuits (SDICs), and the source driver integrated circuits (SDICs) may be connected to a bonding pad of the panel 110 or disposed directly on the display panel 110 using a tape automated bonding (TAB) or a chip on glass (COG) process.

[0055] In some cases, each source driver integrated circuit SDIC may be integrated and arranged in the display panel 110. Furthermore, each source driver integrated circuit SDIC may be implemented using a chip-on-film (COF) process. In this case, each source driver integrated circuit SDIC may be mounted on a circuit film and electrically connected to the data lines DL of the display panel 110 via the circuit film.

[0056] The timing controller 140 supplies various control signals to the gate driver circuit 120 and the data driver circuit 130 to control their operation. Specifically, the timing controller 140 controls the gate driver circuit 120 to generate the sampling signals according to a timing implemented in each frame, and conversely, the timing controller 140 controls the data driver circuit 130 to convert image data (DATA) and generate a data voltage.

[0057] In this case, the timing controller 140 can receive various timing signals in addition to the digital image data DATA, including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data release signal DE and a main clock MCLK from an external component (e.g. a host system).

[0058] The host system can include one or more of a TV system (television), a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a portable device.

[0059] Accordingly, the timing controller 140 generates control signals using the various timing signals received from the host system and transmits the control signals to the gate driver circuit 120 and the data driver circuit 130.

[0060] To control the gate driver circuit 120, the timing controller 140 outputs various gate control signals, including a gate start pulse GSP, a gate clock GCLK, and a gate output enable signal GOE. The gate start pulse GSP controls the times at which one or more GDICs, which comprise the gate driver circuit 120, begin operating. Furthermore, the gate clock GCLK is a clock signal typically input to the one or more integrated gate driver circuits GDICs and controls a shift time of the sample signal. Additionally, the gate output enable signal GOE specifies timing information for the one or more integrated gate driver circuits GDICs.

[0061] To control the data driver circuit 130, the timing controller 140 also outputs various data control signals, including a source start pulse SSP, a source sampling clock SCLK, and a source output enable signal SOE. The source start pulse SSP controls the timing at which the one or more SDICs constituting the data driver circuit 130 begin sampling data. The source sampling clock SCLK is a clock signal for controlling the timing at which the SDIC samples data. The source output enable signal SOE controls an output timing of the data driver circuit 130.

[0062] The display system 100 may further include a power management circuit 150 to supply different voltages or currents to the display panel 110, the gate driver circuit 120, or the data driver circuit 130, or to control different voltages or different currents to be supplied.

[0063] The power management circuit 150 can generate the energy required for driving the display panels 110, the gate driver circuit 120 and the data driver circuit 130 by adjusting input DC voltages.

[0064] Fig. 3 is an example diagram illustrating a display system according to embodiments of the present disclosure.

[0065] With reference to Fig. 3 In the display system 100 according to embodiments of the present disclosure, the integrated source driver circuit SDICs, which is included in the data driver circuit 130, can be implemented in the form of a COF method under various methods (TAB, COG and COF), and the gate driver circuit 120 can be implemented in the form of a GIP under various methods (TAB, COG, COF and GIP).

[0066] If the gate driver circuit 120 is implemented as a GIP, the majority of the integrated gate driver circuits (GDICs) contained within the gate driver circuit 120 can be directly located in a non-display area of ​​the display panel 110. In this case, the integrated gate driver circuit (GDIC) can receive various signals (a clock signal, a gate-high signal, and a gate-low signal) required to generate a sample signal via gate-driven signal lines located in the non-display area.

[0067] Similarly, the one or more integrated source driver circuits SDIC contained in the data driver circuit 130 can each be mounted on a source foil SF, and one side of the source foil SF can be electrically connected to the display panel 110. Furthermore, leads for electrically connecting the integrated source driver circuit SDIC to the display panel 110 can be arranged on the source foil SF.

[0068] The display system 100 may include at least one source circuit board SPCB for circuit-connecting the plurality of source driver integrated circuits SDIC to other devices and a control circuit board CPCB for mounting control components and various electrical devices.

[0069] In this case, one side of the source film SF, on which the source driver integrated circuit SDIC is mounted, may be connected to the at least one source circuit board SPCB. That is, one side of the source film SF, on which the source driver integrated circuit SDIC is mounted, may be electrically connected to the display panel 110, and the other side thereof may be electrically connected to the source circuit board SPCB.

[0070] The timing controller 140 and the power management circuit 150 may be mounted on the control board CPCB. The timing controller 140 may control the operation of the data driver circuit 130 and the gate driver circuit 120. The power management circuit 150 may supply a drive voltage or current to the display panel 110, the data driver circuit 130, and the gate driver circuit 120, and control a voltage or current to be supplied.

[0071] At least one source printed circuit board (SPCB) and at least one control printed circuit board (CPCB) can be electrically connected by at least one interconnect, and the interconnect can be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), or the like. Furthermore, the at least one source printed circuit board (SPCB) and the at least one control printed circuit board (CPCB) can be implemented in such a way that they are integrated into a single printed circuit board.

[0072] In the case of the display system 100 with the above configuration, the power management circuit 150 transmits a drive voltage required for driving a display or sensing a characteristic value to the source circuit board SPCB via the flexible printed circuit FPC or the flexible flat cable FFC. The drive voltage transmitted to the source circuit board SPCB is supplied via the source drive integrated circuit SDIC to drive a specific subpixel SP in the display panel 110 to emit light or sense the specific subpixel SP.

[0073] In this case, each subpixel SP arranged in the display panel 110 can have the light emission element and a circuit element such as a driver transistor for controlling the light emission element.

[0074] The type and number of circuit elements that make up each subpixel SP can be defined differently according to a given function and design procedure.

[0075] Fig. Figure 4 is a diagram showing an example of a structure for controlling a plurality of display panels in a display system according to the embodiments of the present disclosure.

[0076] With reference to Fig. 4 The display system 100 according to embodiments of the present disclosure can comprise one or more display panels 111, 112, 113, a timing controller 140 and one or more integrated source driver circuits SDIC1, SDIC2, SDIC3.

[0077] The one or more display panels can be at least one of the first display panel 111, the second display panel 112, and the third display panel 113. The first display panel 111 can be a dashboard display panel, the second display panel 112 can be a center console display panel, and the third display panel 113 can be a passenger-side display panel.

[0078] The first integrated source driver circuit, SDIC1, can supply a first data voltage to the first display panel 111. The second integrated source driver circuit, SDIC2, can supply a second data voltage to the second display panel 112. The third integrated source driver circuit, SDIC3, can supply a third data voltage to the third display panel 113.

[0079] The Timing Controller 140 can receive external timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data release signal DE and a main clock MCLK, etc., as well as image data DATA from the host system via an interface such as the LVDS interface (Low Voltage Differential Signaling).

[0080] The timing controller 140 can generate control signals for the operation of the gate driver circuit 120 and the data driver circuit 130 based on the external timing signals and supply the image data DATA to the integrated source driver circuits SDIC1-SDIC3, which form the data driver circuit 130.

[0081] Meanwhile, the timing controller can receive 140 coordinates of important information from the host system and calculate a checksum to verify the image data DATA for errors based on the coordinates of the important information.

[0082] If the display system shows 100 vehicle-related pieces of information, the important information may include vehicle warnings such as safety check off, temperature warning, anti-lock braking system (ABS), low hydraulic pressure, etc.

[0083] The timing controller 140 transmits the coordinates and checksum of important information to the integrated source driver circuits SDIC1-SDIC3.

[0084] The timing controller 140 can then receive feedback from the source driver circuits SDIC1-SDIC3 via a specific interface regarding whether an error exists in the image data DATA. Furthermore, the timing controller 140 can receive feedback from the source driver circuits SDIC1-SDIC3 regarding whether an error exists in the communication status.

[0085] Based on the feedback results, the timing controller 140 can determine whether an error has occurred in the communication state or whether an abnormal image is displayed in the integrated source driver circuit SDIC1-SDIC3.

[0086] Each integrated source driver circuit SDIC1-SDIC3 converts the image data DATA received from the timing controller 140 into an analog data voltage and delivers it via data lines to the corresponding display panel 111-113.

[0087] The first source driver integrated circuit SDIC1 can supply the data voltage via a data line connected to the first display panel 111, the second source driver integrated circuit SDIC2 can supply the data voltage via a data line connected to the second display panel 112, and the third source driver integrated circuit SDIC3 can supply the data voltage via a data line connected to the third display panel 113.

[0088] Simultaneously, first subpixels and second subpixels with different emission angles can be arranged together in at least one display panel 111-113. The display system 100 can control the viewing angle of the image by selectively controlling the control processes of the first subpixels or the second subpixels.

[0089] Fig. Figure 5 is a diagram illustrating a display panel with subpixels having different emission angles in a display system according to embodiments of the present disclosure.

[0090] With reference to Fig. 5 A plurality of subpixel units SPu can be arranged on the first display panel 111 in the display system 100 according to embodiments of the present disclosure.

[0091] Here, the subpixel unit SPu is a subpixel that emits light of a specific color and can comprise a first subpixel SPw with a first emission angle and a second subpixel SPn with a second emission angle. The subpixel unit SPu can include a subpixel unit that emits red, a subpixel unit that emits green, and a subpixel unit that emits blue.

[0092] The first subpixel SPw can be a wide-angle subpixel with a wide emission angle, and the second subpixel SPn can be a narrow-angle subpixel with a narrow emission angle.

[0093] When the first subpixel SPw, with a wide emission angle, emits light in the subpixel unit SPu, which is located on the first display panel 111, the image of the first display panel 111 is displayed with a wide viewing angle. Therefore, not only the driver but also the passenger in the front seat of the vehicle is able to see the image of the first display panel 111.

[0094] If, on the other hand, the second subpixel SPn emits light with a narrow emission angle in the subpixel unit SPu arranged on the first display panel 111, the image of the first display panel 111 has a narrow viewing angle. Therefore, only the occupant (e.g., the driver) who is located in front of the first display panel 111 in the vehicle can see the image of the first display panel 111.

[0095] At the same time, the area of ​​the first display panel can be subdivided 111, and in each area images with different viewing angles can be displayed.

[0096] For example, the outer part of the first display panel 111 may be designated as the first region A1, and the subpixel unit SPu located in the first region A1 may emit the first subpixel SPw in the first region A1 with a wide emission angle. In this case, the image displayed in the first region A1 may have a wide viewing angle.

[0097] On the other hand, the central part of the first display panel 111 may be defined as the second area A2, and the subpixel unit SPu located in the second area A2 may emit the second subpixel SPn with a narrow emission angle. In this case, the image displayed in the second area A2 may have a narrow viewing angle.

[0098] The size of the second area A2 can be changed depending on the center of the first display panel 111. Accordingly, the first area A1 can be a remaining outer area of ​​the first display panel 111 without the second area A2.

[0099] In this way, the display system 100 of the present disclosure can display images with different viewing angles depending on the position of the first display panel 111 by selectively controlling the subpixels SPw, SPn with different emission angles.

[0100] At the same time, the first subpixel SPw and the second subpixel SPn, which form the subpixel unit SPu, can have the same structure (size, number, position, etc.) or different structures.

[0101] Fig. Figure 6 is a diagram illustrating various structures of the first subpixel and the second subpixel that form a subpixel unit in the display system according to the embodiments of the present disclosure.

[0102] With reference to Fig. 6 can comprise a subpixel unit SPu, which is arranged on the display panel 110 in the display system 100 according to the embodiments of the present disclosure, comprising a first subpixel unit emitting a red color, a second subpixel unit emitting a green color, and a third subpixel unit emitting a blue color.

[0103] The subpixel units SPu of each color may comprise a first subpixel SPw with a wide emission angle and a second subpixel SPn with a narrow emission angle.

[0104] At the same time, the first subpixel SPw may differ in size, number or position from the second subpixel SPn.

[0105] For example, the first subpixel unit that emits red color can comprise one first subpixel SPw and two second subpixels SPn. At the same time, the size of the first subpixel SPw can be larger than that of the second subpixel SPn.

[0106] Furthermore, the second subpixel unit, which emits green color, can comprise a first subpixel SPw and four second subpixels SPn. Simultaneously, the four second subpixels SPn can be arranged in a square structure in the upper region of the first subpixel SPw.

[0107] Furthermore, the third subpixel unit, which emits blue color, can have one first subpixel SPw and four second subpixels SPn. Simultaneously, four second subpixels SPn can be arranged in a row in the upper region of the first subpixel SPw.

[0108] The size and arrangement of the first subpixel SPw and the second subpixel SPn can be determined according to the light yield of the corresponding color and the lifetime of the subpixel.

[0109] At the same time, the emission angles of the first subpixel SPw and the second subpixel SPn can be controlled according to the shape of the lens arranged on an emission surface.

[0110] Fig. 7 is a diagram illustrating a first lens disposed on a first subpixel and a second lens disposed on a second subpixel in the display system according to embodiments of the present disclosure.

[0111] With reference to Fig. 7, the first lens Lz1 arranged on the first subpixel SPw with a wide emission angle may be a semi-cylindrical lens, and the second lens Lz2 arranged on the second subpixel SPn with a narrow emission angle may be a semi-spherical lens in the subpixel unit of the display system 100 according to an embodiment of the present disclosure.

[0112] The first lens Lz1 and the second lens Lz2 can be shaped differently and be of different sizes, but essentially have the same thickness (height).

[0113] The first lens Lz1 and the second lens Lz2 can have different shapes, different sizes and different thicknesses (heights).

[0114] The first lens Lz1 can have a semi-cylindrical shape with a rectangular base. Therefore, the light exit direction can be cut off in a y-y' direction but not in an x-x' direction.

[0115] This means that since the first lens Lz1 has a length that exceeds the width of the first subpixel SPw in the x-axis direction, the first lens Lz1 is not truncated in the x-x' direction. The first lens Lz1 has a curvature, and its width in the x-x' direction becomes narrower as it extends upwards along the z-axis. Therefore, the first lens Lz1 is truncated in the y-y' direction.

[0116] The second lens Lz2 is a hemispherical lens with a circular base. The second lens Lz2 has a curvature, and its width h is narrower in both the x-x' and y-y' directions as it extends upwards along the z-axis.

[0117] Therefore, the direction of light emission can be cut off by the circular base surface and by a width of the second subpixel SPn in both the x-x' direction and the y-y' direction.

[0118] The size of each of the subpixels SPw, SPn, the first lens Lz1 and the second lens Lz2 can vary depending on the angle at which the light is cut off.

[0119] Furthermore, the size of each of the subpixels SPw, SPn, the first lens Lz1 and the second lens Lz2 can vary depending on the light yield and light concentration of the subpixels SPw, SPn.

[0120] Fig. Figure 8 is a cross-sectional diagram of a subpixel unit in a display system according to the embodiments of the present disclosure.

[0121] With reference to Fig. 8 The subpixel unit, which is arranged on the display panel 110 in the display system 100 according to the embodiments of the present disclosure, can comprise a first subpixel SPw with a first emission angle and a second subpixel SPn with a second emission angle.

[0122] The first emission angle emitted by the first subpixel SPw may be larger than the second emission angle emitted by the second subpixel SPn.

[0123] The first subpixel SPw can have a first anode electrode AE1, a first emission layer EL1, and a first cathode electrode CE1. The first anode electrode AE1, the first emission layer EL1, and the first cathode electrode CE1 can form a first light-emitting element.

[0124] Additionally, a first black matrix BM1, a first insulating layer ENCAP1, a first gap filler GF1, and a first lens Lz1 with a first emission angle can be stacked sequentially on the first cathode electrode CE1. An auxiliary gap filler can also be arranged on the first lens Lz1.

[0125] In this case, a part of the area of ​​the first black matrix BM1, which overlaps with the first anode electrode AE1, may be open.

[0126] The second subpixel SPn can have a second anode electrode AE2, a second emission layer EL2, and a second cathode electrode CE2. The second anode electrode AE2, the second emission layer EL2, and the second cathode electrode CE2 can form a second light-emitting element.

[0127] Additionally, a second black matrix BM2, a second insulating layer ENCAP2, a second gap filler GF2, and a second lens Lz2 with a second emission angle can be stacked sequentially onto the second cathode electrode CE2. An auxiliary gap filler can also be arranged on the second lens Lz2.

[0128] Part of the area of ​​the second black matrix BM2, which overlaps with the second anode electrode AE2, may be open.

[0129] The first black matrix BM1 and the second black matrix BM2 can prevent light from falling on the active layer of a driver transistor constituting a subpixel to prevent the generation of leakage current.

[0130] The first anode electrode AE1 of the first subpixel SPw and the second anode electrode AE2 of the second subpixel SPn can be fabricated using the same process, on the same layer, with the same material, and with substantially the same thickness. The first anode electrode AE1 and the second anode electrode AE2 can be formed using a masking process with photoresist.

[0131] The first emission layer EL1 of the first subpixel SPw and the second emission layer EL2 of the second subpixel SPn can be formed with the same material, the same color and the same thickness on the same layer by a same process.

[0132] Each of the first emission layer EL1 and the second emission layer EL2 can include a hole injection layer (HIL), a hole transport layer (HTL), an emitting material layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL).

[0133] The first cathode electrode CE1 of the first subpixel SPw and the second cathode electrode CE2 of the second subpixel SPn can be produced with the same material, the same color and the same thickness on the same layer by the same process.

[0134] The first cathode electrode 3CE1 and the second cathode electrode CE2 can be made of an opaque metallic material, such as at least one from the group consisting of aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti) and alloys of combinations thereof.

[0135] The first gap filler GF1 of the first subpixel SPw and the second gap filler GF2 of the second subpixel SPn may be formed with the same material, the same color and the same thickness on the same layer by a same process.

[0136] The distance between the first emission layer EL1 and the first lens Lz1 can be adjusted depending on the thickness (height) of the first gap filler GF1. Furthermore, the distance between the second emission layer EL2 and the second lens Lz2 can be adjusted depending on the thickness (height) of the second gap filler GF2.

[0137] The first gap filler GF1 or the second gap filler GF2 can be made of acrylic, epoxy, and silicone, or combinations thereof. Furthermore, the first gap filler GF1 or the second gap filler GF2 can be made of an organic material.

[0138] The particle size in the first gap filler GF1 or the second gap filler GF2 can correspond to the wavelength of light or be larger or smaller than the wavelength of light by a certain range. The first gap filler GF1 or the second gap filler GF2 can have a forward diffusion property based on a particle density, a particle size, or a particle shape.

[0139] In this context, the first gap filler GF1 or the second gap filler GF2 can have a lower refractive index than the first insulating layer ENCAP1. That is, the first gap filler GF1 and the second gap filler GF2 can have a lower refractive index than the first insulating layer ENCAP1 due to their particle density, size, or shape.

[0140] The material of the first insulating layer ENCAP1 or the second insulating layer ENCAP2 can be one of the following: TiO2, Al2O3 and SiO2.

[0141] If the material of the first insulating layer ENCAP1 or the second insulating layer ENCAP2 is TiO2, the first insulating layer ENCAP1 or the second insulating layer ENCAP2 can have a refractive index in the range of 2.6 to 2.9. If the material of the first insulating layer ENCAP1 or the second insulating layer ENCAP2 is Al2O3, the refractive index of the first insulating layer ENCAP1 or the second insulating layer ENCAP2 can be in the range of 1.75 to 1.76. If the material of the first insulating layer ENCAP1 or the second insulating layer ENCAP2 is SiO2, the first insulating layer ENCAP1 or the second insulating layer ENCAP2 can have a refractive index in the range of 1.40 to 1.55.

[0142] The first lens Lz1 of the first subpixel SPw and the second lens Lz2 of the second subpixel SPn can be manufactured with the same material, color, and thickness on the same layer using the same process. However, the first lens Lz1 and the second lens Lz2 can be designed to have different shapes and sizes.

[0143] The refractive indices of the first lens Lz1 and the second lens Lz2 can be determined depending on the shape of the lens and the thickness (height) of the gap filler GF1, GF2.

[0144] Fig. Figure 9 is a diagram illustrating a case in which different images are displayed in the first area and the second area of ​​the display panel in the display system according to the embodiments of the present disclosure. Furthermore, Fig. 10 a diagram illustrating a state of degradation when different images are displayed in the first area and in the second area of ​​the display panel in the display system according to the embodiments of the present disclosure.

[0145] First, with reference to Fig. 9, the display system 100 according to embodiments of the present disclosure may include a plurality of display panels (e.g., a first display panel through a third display panel). At least one display panel (e.g., the first display panel) may be aligned with a plurality of regions (e.g., the first region and the second region) having different viewing angles.

[0146] For example, the first area A1 of the first display panel 111 can be displayed with a wide viewing angle because the first subpixel SPw emits light with a wide emission angle in the subpixel unit SPu. Accordingly, not only the driver in the vehicle but also the passenger in the front seat can see the image on the first display panel 111.

[0147] On the other hand, the second area A2 of the first display panel 111 can be displayed with a narrow viewing angle because the second subpixel SPn emits light with a narrow emission angle in the subpixel unit SPu. Accordingly, only the driver located in the vehicle in front of the first display panel 111 will be able to see the image of the first display panel 111.

[0148] At the same time, the size of the first area A1 can be variable with a narrow viewing angle.

[0149] However, if the first subpixel SPw emits light in the first area A1 and the second subpixel SPn emits light in the second area A2 for a longer period of time, there will be a difference in the degree of degradation of the first area A1 and the degree of degradation of the second area A2.

[0150] As a result, as in Fig. 10, a problem may occur in which a luminance deviation is detected at the edge area between the first area A1 and the second area A2.

[0151] The display system 100 of the present disclosure can reduce image defects caused by luminance deviation by reducing the degradation deviation between the first area A1 and the second area A2.

[0152] For this purpose, the display system 100 of the present disclosure can reduce the degradation deviation between the first region A1 and the second region A2 by controlling the emission cycle of the first subpixel SPw and the second subpixel SPn at the edge region between the first region A1 and the second region A2 with different viewing angles.

[0153] Fig. 11 is a diagram illustrating a case of controlling the emission cycle of a first region and a second region having different viewing angles in a display system according to embodiments of the present disclosure.

[0154] With reference to Fig. 11. The display system 100 of the present disclosure can reduce the degradation deviation of the display panel by controlling the emission cycle of subpixels in an area with a high degradation deviation with respect to the first area A1 and the second area A2, which display images at different viewing angles.

[0155] For example, the first area A1 of the first display panel 111 can have a wide viewing angle because the first subpixels SPw emit with a wide emission angle in the subpixel unit SPu. The second area A2 of the first display panel 111 can have a narrow viewing angle because the second subpixels SPn emit with a narrow emission angle in the subpixel unit SPu.

[0156] Since in this case the first subpixel SPw emits light in the first area A1 and the second subpixel SPn emits light in the second area A2 over a longer period of time, the deviation between the degree of degradation in the first area A1 and the degree of degradation in the second area A2 increases.

[0157] Therefore, a region near the boundary can be set as an emission cycle control region starting from the boundary between the first region A1 and the second region A2.

[0158] For example, the 1-1 range A1-1 near the boundary within the first range A1 and the 2-1 range A2-1 near the boundary within the second range A2 can be defined as the emissions cycle control range.

[0159] The emission cycle control region may have two or more subpixel lines from the boundary.

[0160] The 1-2 area A1-2, unlike the 1-1 area A1-1, which corresponds to the emission cycle control area within the first area A1, may be an emission area in which the emission cycle is not variable.

[0161] Likewise, the 2-2 region A2-2, unlike the 2-1 region A2-1, which corresponds to the emission cycle control region within the second region A2, may be an emission region in which the emission cycle is not variable.

[0162] The display system 100 of the present disclosure may control gate signals generated in the gate driver circuit 120 to control the emission cycle of the subpixel located in the emission cycle control region.

[0163] Fig. Figure 12 is a block diagram illustrating a configuration of a gate driver circuit in a display system according to embodiments of the present disclosure.

[0164] With reference to Fig. 12, the gate driver circuit 120 in the display system 100 according to embodiments of the present disclosure may be arranged in the lateral edge region of the display panel 110.

[0165] Gate driver circuit 120 may consist of n stages STG1-STGn, to which n (a natural number of 2 or more) gate driver integrated circuits GDIC #1-GDIC #n are connected in a dependent manner. Each of the gate driver integrated circuits GDIC #1-GDIC #n receives a gate high voltage VGH and a gate low voltage VGL as drive voltages and is driven by gate clock signals GCLKs.

[0166] A first gate driver integrated circuit GDIC #1 starts operation by a gate start signal GVST, and a second gate driver integrated circuit GDIC #2 to the n-th gate driver integrated circuit GDIC #n can receive gate signals GS1-GS(n-1) output from preceding output terminals as start signals.

[0167] For example, a first gate signal GS1 output from the output terminal of the first gate driver integrated circuit GDIC #1 corresponding to the first stage STG1 may be supplied to a first subpixel line SPL1 arranged in the first row and a start signal input terminal of the second gate driver integrated circuit GDIC #2 of the second stage STG2.

[0168] Accordingly, the first gate driver integrated circuit GDIC #1 of the first stage STG1 may use the gate start signal GVST as a start signal, but each of the second gate driver integrated circuit GDIC #2 of the second stage STG2 to the n-th gate driver integrated circuit GDIC #n of the n-th stage STGn may use the gate signal output from the output terminal of the preceding gate driver integrated circuit as a start signal.

[0169] The expression that the first gate signal GS1 output from the output terminal of the first integrated gate driver circuit GDIC #1 is the first start signal START1 is intended to show that the first gate signal GS1 generated in the first stage STG1 is used as the start signal for the next stage.

[0170] Dependentally connected stages and the configuration in which the gate signal of the front stage is used as the start signal of the next stage can be applied equally to all stages STG1-STGn, as shown in the relationship between the (n-1)th stage STG(n-1) and the nth stage STGn.

[0171] Meanwhile, a gate signal output by a stage (an integrated gate driver circuit) can contain one or more sampling signals and one or more emission signals. For example, two sampling signals and one emission signal can be generated by a single stage (an integrated gate driver circuit).

[0172] Furthermore, the gate driver circuit 120 in the display system 100 of the present disclosure can additionally generate an emission cycle control signal for controlling emission cycles in areas near a boundary between the first area A1 with the first emission angle and the second area A2 with the second emission angle.

[0173] Fig. Figure 13 is a diagram illustrating a gate signal output by a gate driver circuit in a display system according to embodiments of the present disclosure.

[0174] With reference to Fig. 13 Each of a plurality of integrated gate driver circuits GDIC, which form the gate driver circuit 120 in the display system 100 according to embodiments of the present disclosure, can generate a gate signal for controlling subpixels of the display panel 110.

[0175] At the same time, the gate signal GS, which is output by the integrated gate driver circuit GDIC, can include a sampling signal SC, which controls the drive timing of the subpixel, an emission signal EM, which controls the emission timing of the subpixel, and a cycle control signal PS, which controls the emission cycle of a specific subpixel.

[0176] Depending on the circuit configuration of the subpixel, the sampling signal SC can have one or more sampling signals.

[0177] Depending on the circuit configuration of the subpixel, the emission signal EM can have one or more emission signals.

[0178] The cycle control signal PS can have a first cycle control signal PS1, which controls the emission cycle of the first subpixel SPw with a first emission angle, and a second cycle control signal PS2, which controls the emission cycle of the second subpixel SPn with a second emission angle.

[0179] Fig. 14 is a diagram illustrating a circuit operation in which the first subpixel of a subpixel unit emits light in a display system according to embodiments of the present disclosure, and Fig. Figure 15 is a diagram of signal waveforms controlled by the first subpixel of a subpixel unit in a display system according to embodiments of the present disclosure.

[0180] With reference to Fig. 14 and Fig. 15, a subpixel unit according to embodiments of the present disclosure may comprise a first light-emitting element ED1, a second light-emitting element ED2, a driver transistor DRT and an internal compensation circuit.

[0181] The first light-emitting element ED1 can be located in the first subpixel SPw and the second light-emitting element ED2 in the second subpixel SPn.

[0182] The first lens Lz1 can be arranged on the first light-emitting element ED1 and the second lens Lz2 on the second light-emitting element ED2.

[0183] The transistors T1-T8, DRT, which are arranged in a subpixel unit, can be implemented as PMOS transistors of the LTPS (Low Temperature Poly Silicon) type, and the desired response characteristics can be obtained from these.

[0184] For example, at least one transistor among the switching transistors T1-T8 may be implemented as an NMOS or PMOS type oxide transistor with good off-state leakage current characteristics, and the remaining transistors may be implemented as a PMOS type LTPS transistor with good response characteristics.

[0185] The subpixel unit may comprise a first transistor T1 connected to the data line and transmitting the data voltage Vdata by means of the second scanning signal SC2.

[0186] The subpixel unit may comprise a second transistor T2 connected to a drive voltage VDD and transmitting the drive voltage VDD by means of the emission signal EM.

[0187] The driver transistor DRT connects the first node N1, which is shared by the first transistor T1 and the second transistor T2, with the third node N3 and receives the voltage charged in the storage capacitor Cst via the second node N2 as the gate voltage.

[0188] A fourth transistor T4, controlled by the emission signal EM, and a sixth transistor T6, controlled by the first cycle control signal PS1, are connected between the third node N3 and the first light-emitting element ED1.

[0189] The fourth transistor T4, controlled by the emission signal EM, and an eighth transistor T8, controlled by the second cycle control signal PS2, are connected between the third node N3 and the second light-emitting element ED2. The eighth transistor T8 is connected to a fourth node N4 of the fourth transistor T4.

[0190] Accordingly, the first light-emitting element ED1 or the second light-emitting element ED2 can emit light by means of the first cycle control signal PS1 and by means of the second cycle control signal PS2 in a state in which the fourth transistor T4 is switched on by the emission signal EM.

[0191] A third transistor T3, controlled by the second sampling signal SC2, may connect the second node N2 to the third node N3.

[0192] The fifth transistor T5 is connected between the second node N2 and a line supplying the second initialization voltage Vini2 and can be controlled by the first sampling signal SC1. Accordingly, the fifth transistor T5 can initialize the gate node of the driver transistor DRT to the second initialization voltage Vini2 using the first sampling signal SC1.

[0193] The seventh transistor T7 is connected between the anode electrode of the first light-emitting element ED1 and a line that supplies the first initialization voltage Vini1, and can be controlled by the second sampling signal SC2. Accordingly, the seventh transistor T7 can initialize the anode electrode of the first light-emitting element ED1 to the first initialization voltage Vini1 by means of the second sampling signal SC2.

[0194] At the same time, the first to eighth transistors T1 to T8 can be referred to as the first to eighth switching transistors.

[0195] The first light-emitting element ED1 and the second light-emitting element ED2 emit light with a current controlled by the voltage Vgs between the gate node and the source node of the driver transistor DRT.

[0196] The first light-emitting element ED1 can be connected to the driver transistor DRT via the fourth transistor T4 and the sixth transistor T6. The second light-emitting element ED2 can be connected to the driver transistor DRT via the fourth transistor T4 and the eighth transistor T8.

[0197] The cathode electrodes of the first light-emitting element ED1 and the second light-emitting element ED2 are connected to the low-potential voltage VSS.

[0198] The driver transistor DRT can control a driver current Id flowing through the first light-emitting element ED1 or the second light-emitting element ED2 as a function of the voltage Vgs between the gate node and the source node.

[0199] The compensation circuit can sample the voltage Vgs between the gate node and the source node of the driver transistor DRT to compensate for the change in the threshold voltage of the driver transistor DRT. The compensation circuit can include the first to eighth transistors T1-T8 and a storage capacitor Cst. Alternatively, the rest, except for the first transistor T1 for supplying the data voltage Vdata, can also be referred to as a compensation circuit.

[0200] Accordingly, the subpixel unit that forms the display system 100 of the present disclosure can control the emission cycle of the first light-emitting element ED1 by means of the first cycle control signal PS1 and control the emission cycle of the second light-emitting element ED2 by means of the second cycle control signal PS2.

[0201] For example, the first cycle control signal PS1 is supplied with a switch-on level (e.g. low level) and the second cycle control signal PS2 with a switch-off level (e.g. high level) during a period in which the first light-emitting element ED1 emits light.

[0202] With reference to Fig. 15, the gate node of the driver transistor DRT is initialized to the second initialization voltage Vini2 by means of the first sampling signal SC1 in the first period P1.

[0203] In the second period P2, the data voltage Vdata is applied to the driver transistor DRT via the second sampling signal SC2, and the anode electrode of the first light-emitting element ED1 can be initialized with the first initialization voltage Vini1.

[0204] In the third period P3, the first light-emitting element ED1 emits light by means of the first cycle control signal PS1, and the second light-emitting element ED2 turns off by means of the second cycle control signal PS2.

[0205] Fig. 16 is a diagram illustrating a circuit operation in which the second subpixel of a subpixel unit emits light in a display system according to embodiments of the present disclosure, and Fig. 17 is a diagram of signal waveforms driven by the second subpixel of a subpixel unit in a display system according to embodiments of the present disclosure.

[0206] There Fig. 16 the same configuration as that of Fig. Since 14 is identical, a description of the configuration is omitted.

[0207] However, during a period in which the second light-emitting element ED2 emits, the second cycle control signal PS2 can be supplied with a turn-on level (e.g. a low level) and the first cycle control signal PS1 with a turn-off level (e.g. a high level).

[0208] With reference to Fig. 17, the gate node of the driver transistor DRT is initialized to the second initialization voltage Vini2 by means of the first sampling signal SC1 in the first period P1.

[0209] In the second period P2, the data voltage Vdata can be supplied to the driver transistor DRT by means of the second sampling signal SC2, and the anode electrode of the first light-emitting element ED1 can be initialized with the first initialization voltage Vini1.

[0210] In the third period P3, the second light-emitting element ED2 emits light by means of the second cycle control signal PS2, and the first light-emitting element ED1 switches off by means of the first cycle control signal PS1.

[0211] Fig. Figures 18 to 20 are diagrams illustrating cycle control signals and emission states as a function of the area of ​​the display panels in the display system according to embodiments of the present disclosure.

[0212] With reference to Fig. 18 to 20, at least one display panel 110 in the display system 100 according to embodiments of the present disclosure can have an emission cycle control area near the boundary between the first area A1 with a first emission angle and the second area A2 with a second emission angle.

[0213] For example, the 1-1 area A1-1 near the boundary of the first area A1 and the 2-1 area A2-1 near the boundary of the second area A2 may be set as the emission cycle control area.

[0214] On the other hand, the region 1-2 A1-2, which is different from the region 1-1 A1-1 whose emission cycle is variable in the first region A1, may be a fixed emission region.

[0215] Similarly, the region A2-2, which differs from the region A2-1, whose emission cycle is variable within the second region A2, may be a fixed emission region.

[0216] Fig. 18 illustrates the signals supplied to the region A1-2 in which the first light-emitting element ED1 constantly emits light in the first region A1, and its emission states.

[0217] To illustrate, the case where the high-level signal is the turn-on level is presented to facilitate understanding.

[0218] With reference to Fig. 18, the area 1-2 A1-2 of the display panel 110 corresponds to a fixed emission area in which the first light-emitting element ED1 emits light at a first emission angle.

[0219] The first cycle control signal PS1, with an on-level that turns on the first light-emitting element ED1, is applied to the area 1-2 A1-2 every frame according to a vertical synchronization signal Vsync that defines the frame. The second cycle control signal PS2, on the other hand, maintains the off-level.

[0220] Accordingly, the first light-emitting element ED1 emits light in every frame, and the second light-emitting element ED2 remains in the off state.

[0221] Similarly, the second cycle control signal PS2 having the on-level that turns on the second light-emitting element ED2 is supplied to the area A2-2 in which the second light-emitting element ED2 constantly emits light every frame, and the first cycle control signal PS1 maintains the off-level.

[0222] Fig. Figure 19 illustrates the signal applied to the region A1-1 near the boundary in the first region A1 and the emission states.

[0223] With reference to Fig. 19, the 1-1 area A1-1 of the display panel 110 corresponds to an area near the second area A2 in which the second light-emitting element ED2 emits light.

[0224] Therefore, since the first light-emitting element ED1 and the second light-emitting element ED2 alternately emit light into the first region A1-1, the degradation deviation with respect to the second region A2 can be reduced.

[0225] At the same time, the cycle in which the first light-emitting element ED1 and the second light-emitting element ED2 alternately emit light can vary depending on the distance from the boundary. For example, the emission cycle of the first light-emitting element ED1 can increase with increasing distance from the boundary in the region A1-1.

[0226] In this case, the user can naturally perceive the luminance change near the boundary, and the luminance degradation near the boundary may be gradually reduced.

[0227] Fig. Figure 19 illustrates a case in which the first light-emitting element ED1 and the second light-emitting element ED2 alternately emit light in a 1:1 ratio.

[0228] In this case, the first cycle control signal PS1, with a switch-on level for the first light-emitting element ED1, can be supplied at each odd frame according to the vertical synchronization signal Vsync, which defines the frame. Conversely, the second cycle control signal PS2, with a switch-on level, can be supplied at each even frame.

[0229] Accordingly, the first light-emitting element ED1 and the second light-emitting element ED2 emit light alternately in each frame.

[0230] Fig. Figure 20 illustrates a case in which the first light-emitting element ED1 and the second light-emitting element ED2 alternately emit light in a 2:1 ratio.

[0231] In this case, the first cycle control signal PS1, which turns on the first light-emitting element ED1, may be continuously supplied at the on level for two frames according to the vertical synchronization signal Vsync defining the frame, and may be supplied at the off level during a subsequent frame. On the other hand, the second cycle control signal PS2 may be supplied at an on level for each frame, while the first cycle control signal PS1 is supplied at an off level.

[0232] Accordingly, the first light-emitting element ED1 and the second light-emitting element ED2 alternately emit light in frames with a ratio of 2:1.

[0233] Since the emission rate of the first light-emitting element ED1 increases as the first light-emitting element ED1 moves away from the boundary to the first region A1, the degradation deviation can be reduced in this way, while the luminance change is naturally preserved.

[0234] Fig. Figure 21 is a diagram illustrating a variation of the emission cycle near the boundary between the first area and the second area in the display system according to embodiments of the present disclosure.

[0235] With reference to Fig. 21 at least one display panel 110 in the display system 100 according to embodiments of the present disclosure can comprise an emission cycle control area near the boundary between the first area A1 with a first emission angle and the second area A2 with a second emission angle.

[0236] For example, the 1-1 range A1-1 near the boundary in the first range A1 and the 2-1 range A2-1 near the boundary in the second range A2 can be defined as the emissions cycle control range.

[0237] The emission cycle control area is an area in which the first light-emitting element ED1 and the second light-emitting element ED2 alternately emit light according to a predetermined cycle.

[0238] For example, the first light-emitting element ED1 and the second light-emitting element ED2 can alternately emit light into the region A1-1. With increasing distance from the boundary, the emission cycle of the first light-emitting element ED1 can increase.

[0239] Furthermore, the first light-emitting element ED1 and the second light-emitting element ED2 can alternately emit light in the region A2-1. As the distance from the boundary increases, the emission cycle of the second light-emitting element ED2 can increase.

[0240] In this way, with increasing distance from the boundary, the degradation deviation can be reduced while naturally maintaining the luminance variation by increasing the emission ratio of the light-emitting element corresponding to the area.

[0241] The aforementioned points are briefly described below.

[0242] An embodiment of the present disclosure can provide a display system comprising a display panel having a plurality of subpixel units comprising a first subpixel with a first emission angle and a second subpixel with a second emission angle, a gate driver circuit configured to supply gate signals to the display panel, and a timing controller configured to control an emission cycle of the first subpixel or the second subpixel for an emission cycle control range between a first range in which the first subpixel emits light and a second range in which the second subpixel emits light.

[0243] In an example implementation, the display panel includes an instrument panel display panel located in a driver seat, a center console display panel located between the driver seat and the front passenger seat, and a front passenger display panel located on the front passenger seat.

[0244] In an example implementation, the second emission angle is smaller than the first emission angle and is a viewing angle that is only recognized by an occupant of a seat where the display panel is located.

[0245] In an exemplary implementation, the first subpixel comprises a first light-emitting element, a first black matrix having an opening above the first light-emitting element, a first insulating layer formed on the first black matrix, a first gap filler formed on the first insulating layer, and a first lens formed on the first gap filler with a first emission angle.

[0246] In one exemplary implementation, the first lens is a semi-cylindrical lens with a rectangular base.

[0247] In an exemplary implementation, the second subpixel includes a second light-emitting element, a second black matrix having an opening above the second light-emitting element, a second insulating layer formed on the second black matrix, a second gap filler formed on the second insulating layer, and a second lens having a second emission angle formed on the second gap filler.

[0248] In one example implementation, the second lens is a hemispherical lens with a circular base. As such, the second lens differs structurally from the first lens.

[0249] In an example implementation, the subpixel unit includes a number of second subpixels that is greater than a number of the first subpixels.

[0250] In an example implementation, the first area is located on the outside of the second area.

[0251] In an example implementation, the second area has a variable size.

[0252] In an example implementation, the first region includes a 1-1 region in which the first subpixel and the second subpixel alternately emit light, and a 1-2 region in which only the first subpixel emits light.

[0253] In an example implementation, the emission cycle of the first subpixel increases the further the first subpixel is from the boundary between the first region and the second region.

[0254] In an example implementation, the second region includes a 2-1 region in which the first subpixel and the second subpixel alternately emit light, and a 2-2 region in which only the second subpixel emits light.

[0255] In an exemplary implementation, the emission cycle of the second subpixel increases the further the second subpixel is from the boundary between the first area and the second area.

[0256] In an exemplary implementation, the gate driver circuit outputs a sampling signal that controls the drive time of the subpixel unit, an emission signal that controls the emission time of the subpixel unit, a first cycle control signal that controls an emission cycle of the first subpixel, and a second cycle control signal that controls an emission cycle of the second subpixel.

[0257] In an exemplary implementation, the subpixel unit comprises a first light-emitting element, a second light-emitting element, a first transistor that transmits a data voltage depending on a second sampling signal, a second transistor that transmits a driver voltage depending on the emission signal, a driver transistor that connects a first node, shared by the first and second transistors, to a third node and receives a voltage charged in a storage capacitor as a gate voltage via a second node, a third transistor that connects the second node to the third node and is controlled by the second sampling signal, a fourth transistor that is connected to the third node and controlled by the emission signal, and a fifth transistor that is connected between the second node and a line.a sixth transistor, which provides a second initialization voltage and is controlled by a first sampling signal; a seventh transistor, which is connected between the anode electrode of the first light-emitting element and a line that provides a first initialization voltage and is controlled by the second sampling signal; and an eighth transistor, which is connected between the fourth node of the fourth transistor and an anode electrode of the second light-emitting element and is controlled by the second cycle control signal.

[0258] An embodiment of the present disclosure can provide a display control method for controlling a display panel having a plurality of subpixel units comprising a first subpixel with a first emission angle and a second subpixel with a second emission angle, wherein the method comprises a step of controlling the first subpixel for a first area of ​​the display panel, a step of controlling the second subpixel for a second area of ​​the display panel, a step of alternately emitting the first subpixel and the second subpixel with a predetermined cycle for a 1-1 area within the first area, and a step of alternately emitting the first subpixel and the second subpixel with a predetermined cycle for a 2-1 area within the second area.

[0259] In an exemplary implementation, the emission cycle of the first subpixel in the 1-1 region increases the further the first subpixel is from the boundary between the first region and the second region.

[0260] In an exemplary implementation, the emission cycle of the second subpixel in the 2-1 region increases the further the second subpixel is from the boundary between the first region and the second region.

[0261] An embodiment of the present disclosure may provide a vehicle having a display panel including a plurality of sub-pixel units including a first sub-pixel having a first emission angle and a second sub-pixel having a second emission angle, a gate drive circuit configured to supply gate signals to the display panel, and a timing controller configured to control an emission cycle of the first sub-pixel or the second sub-pixel for an emission cycle control range between a first region in which the first sub-pixel emits light and a second region in which the second sub-pixel emits light.

[0262] An embodiment of the present disclosure may provide a display panel having a plurality of subpixel units, wherein a subpixel unit of the plurality of subpixel units includes a first subpixel configured to emit light in a first region and a second subpixel configured to emit light in a second region; a gate driver circuit configured to provide gate signals to the display panel; and a timing controller configured to control an emission cycle of at least one of the first subpixel and the second subpixel based on a distance from the respective first subpixel and / or second subpixel to a boundary between the first region and the second region.

[0263] In an exemplary implementation, the first subpixel has a first emission angle and the second subpixel has a second emission angle that differs from the first emission angle.

[0264] In an exemplary implementation, the first subpixel has a first lens and the second subpixel has a second lens, which is structurally different from the first lens.

[0265] In an exemplary implementation, the first lens is a semi-cylindrical lens with a rectangular base, and the second lens is a hemispherical lens with a circular base.

[0266] In an example implementation, the first subpixel and the second subpixel are configured to emit light of the same color.

[0267] The above description is presented to enable any person skilled in the art to produce and utilize the technical idea of ​​the disclosure and is provided in connection with a specific application and its requirements. Various modifications, additions, and substitutions of the described embodiments are readily apparent to the person skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the scope of the disclosure. The above description and the accompanying drawings represent an example of the technical idea of ​​the disclosure and serve only for illustration. That is to say, the disclosed embodiments are intended to illustrate the scope of the technical idea of ​​the disclosure.

[0268] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to utilize concepts from the different embodiments to provide yet more embodiments.

[0269] These and other modifications may be made to the embodiments in light of the detailed description above. In general, the terms used in the following claims should not be interpreted as limiting the claims to the specific embodiments disclosed in the description and the claims, but rather as encompassing all possible embodiments. Accordingly, the claims are not limited by the disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] KR 10-2023-0144325

[0001]

Claims

[1] Display system (100) comprising: a display panel (110) having a plurality of subpixel units (SPu), wherein a subpixel unit (SPu) has a first subpixel (SPw) with a first emission angle and a second subpixel (SPn) with a second emission angle; a gate driver circuit (120) configured to provide gate signals to the display panel (110); and a timing controller (140) configured to control an emission cycle of one or more of the first subpixel (SPw) or the second subpixel (SPn) for an emission cycle control range between a first region (A1) in which the first subpixel (SPw) is configured to emit light and a second region (A2) in which the second subpixel (SPn) is configured to emit light. [2] The display system (100) of claim 1, wherein the display panel (110) comprises: an instrument panel display panel (111) arranged facing the driver's seat; a center console display panel (112) disposed between the driver's seat and the passenger seat; and a passenger display panel (113) arranged facing the passenger seat. [3] The display system (100) according to claim 1 or 2, wherein the second emission angle is narrower than the first emission angle and is a viewing angle configured to be recognized only by an occupant of a seat facing the display panel (110). [4] The display system (100) according to any one of claims 1 to 3, wherein the first subpixel (SPw) comprises: a first light-emitting element (AE1, EL1, CE1); a first black matrix (BM1) having an opening above the first light-emitting element (AE1, EL1, CE1); a first insulating layer (ENCAP1) formed on the first black matrix (BM1); a first gap filler (GF1) formed on the first insulating layer (ENCAP1); and a first lens (Lz1) having the first emission angle formed on the first gap filler (GF1). [5] The display system (100) of claim 4, wherein the first lens (Lz1) is a semi-cylindrical lens having a rectangular bottom. [6] Display system (100) according to one of claims 1 to 5, wherein the second subpixel (SPn) comprises: a second light-emitting element (AE2, EL2, CE2); a second black matrix (BM2) having an opening above the second light-emitting element (AE2, EL2, CE2); a second insulating layer (ENCAP2) formed on the second black matrix (BM2); a second gap filler (GF2) formed on the second insulating layer (ENCAP2); and a second lens (Lz2) having the second emission angle formed on the second gap filler (GF2). [7] The display system (100) of claim 6, wherein the second lens (Lz2) is a hemispherical lens with a circular bottom. [8] Display system (100) according to one of claims 1 to 7, wherein the subpixel unit (SPu) comprises a second number of second subpixels (SPn) and a first number of first subpixels (SPw), the second number being greater than the first number. [9] Display system (100) according to one of claims 1 to 8, wherein the first region (A1) is arranged on an outer side of the second region (A2). [10] Display system (100) according to one of claims 1 to 9, wherein the second area (A2) has a variable size. [11] Display system (100) according to one of claims 1 to 10, wherein the first area (A1) comprises: a 1-1 region (A1-1) in which the first subpixel (SPw) and the second subpixel (SPn) are configured to alternately emit light; and an area 1-2 (A1-2) in which only the first subpixel (SPw) is configured to emit light. [12] The display system (100) of claim 11, wherein the emission cycle of the first subpixel (SPw) increases with increasing distance between the first subpixel (SPw) and a boundary between the first region (A1) and the second region (A2). [13] Display system (100) according to one of claims 1 to 12, wherein the second area (A2) comprises: a 2-1 region (A2-1) in which the first subpixel (SPw) and the second subpixel (SPn) are configured to alternately emit light; and a 2-2 area (A2-2) in which only the second subpixel (SPn) is configured to emit light. [14] The display system (100) of claim 13, wherein the emission cycle of the second subpixel (SPn) increases with increasing distance between the second subpixel (SPn) and a boundary between the first region (A1) and the second region (A2). [15] The display system (100) according to any one of claims 1 to 14, wherein the gate driver circuit (120) is configured to output: a scanning signal (SC) that controls the drive timing of the subpixel unit (SPu); an emission signal (EM) that controls the emission timing of the subpixel unit (SPu); a first cycle control signal (PS1) that controls an emission cycle of the first subpixel (SPw); and a second cycle control signal (PS2) that controls an emission cycle of the second subpixel (SPn). [16] The display system (100) of claim 15, wherein the subpixel unit (SPu) comprises: a first light-emitting element (ED1); a second light-emitting element (ED2); a first transistor (T1) configured to transmit a data voltage (Vdata) based on a second strobe signal (SC2); a second transistor (T2) configured to transmit a drive voltage (VDD) based on the emission signal (EM); a driver transistor (DRT) connected between a first node (N1) shared by the first transistor (T1) and the second transistor (T2) and a third node (N3), and connected to receive a voltage charged in a storage capacitor (Cst) as a gate voltage via a second node (N2); a third transistor (T3) connected between the second node (N2) and the third node (N3) and connected to be controlled by the second sampling signal (SC2); a fourth transistor (T4) connected to the third node (N3) and controlled by the emission signal (EM); a fifth transistor (T5) connected between the second node (N2) and a line supplying a second initialization voltage (Vini2) and connected to be controlled by a first sampling signal (SC1); a sixth transistor (T6) connected between a fourth node (N4) of the fourth transistor (T4) and an anode electrode of the first light-emitting element (ED1) and connected to be controlled by the first cycle control signal (PS1); a seventh transistor (T7) connected between the anode electrode of the first light-emitting element (ED1) and a line supplying a first initialization voltage (Vini1) and connected to be controlled by the second scanning signal (SC2); and an eighth transistor (T8) connected between the fourth node (N4) of the fourth transistor (T4) and an anode electrode of the second light-emitting element (ED2) and connected to be controlled by the second cycle control signal (PS2). [17] A display control method for controlling a display panel (110) having a plurality of subpixel units (Spu), each having a first subpixel (SPw) with a first emission angle and a second subpixel (SPn) with a second emission angle, the method comprising: Controlling the first subpixel (SPw) for a first area (A1) of the display panel (110); Controlling the second subpixel (SPn) for a second area (A2) of the display panel (110); Controlling light emission alternately by the first subpixel (SPw) or the second subpixel (SPn) in a cycle for a 1-1 area within the first area (A1); and Controlling light emission alternately by the first subpixel (SPw) or the second subpixel (SPn) in a cycle for a 2-1 area within the second area (A2). [18] A display driving method according to claim 17, wherein an emission cycle of the first sub-pixel (SPw) in the 1-1 region increases with increasing distance of the first sub-pixel (SPw) to a boundary between the first region (A1) and the second region (A2). [19] A display driving method according to claim 17 or 18, wherein an emission cycle of the second subpixel (SPn) in the 2-1 region increases with increasing distance of the second subpixel (SPn) to a boundary between the first region (A1) and the second region (A2). [20] Vehicle (1000), comprising: a display panel (110) having a plurality of subpixel units (SPu), each subpixel unit (SPu) having a first subpixel (SPw) with a first emission angle and a second subpixel (SPn) with a second emission angle; a gate driver circuit (120) configured to supply gate signals (GS) to the display panel (110); and a timing controller (140) configured to control an emission cycle of one or more of the first subpixel (SPw) or the second subpixel (SPn) for an emission cycle control range between a first region (A1) in which the first subpixel (SPw) is configured to emit light and a second region (A2) in which the second subpixel (SPn) is configured to emit light.

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