Double-edge multi-phase clock generator and control method thereof

Abstract

The invention discloses a double-edge multi-phase clock generator and a control method thereof, and belongs to the technical field of integrated circuit design. According to the method, the waveform freedom degree is improved through a three-stage time division architecture of'time period-round-period 'and in combination with a configuration mechanism of a plurality of programmable event points in each time period; configuration parameters are pre-stored in a register file module, and mode switching only needs to directly call pre-stored configuration, so that the real-time response capability is improved; the time control resolution is improved through double-edge counting, so that the sub-clock cycle control precision is achieved, and the method is suitable for high-precision application sensitive to power consumption and complex scene application.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a double-edge multi-phase clock generator and its control method. Background Technology

[0002] Multi-Phase Clock Generators (MPCGs) are key fundamental modules in modern integrated circuit systems, widely used in system-on-chips (SoCs), motor control systems, digital power management, high-speed communication interfaces, and analog front-ends. Their core function is to generate one or more clock or control signals with specific frequencies, phases, and duty cycles, providing a precise time base and switching control logic for the entire digital system. The accuracy, stability, and flexibility of the MPCG output signal directly determine the performance, efficiency, and functionality of the upper-level system.

[0003] As electronic devices continue to evolve towards higher precision, higher integration, lower power consumption, and multi-task parallel processing, the system's requirements for MPCG (Multi-Clock Controller) have also undergone profound changes. The demand has evolved from generating a single-frequency clock to simultaneously generating multiple independently controllable, complex, configurable clock signals with real-time, delay-free mode switching. This requires MPCG to possess unprecedented timing control flexibility and extremely high response speed.

[0004] Currently, mainstream MPCG technology solutions mainly rely on the following technical routes: A fixed-frequency reference clock is generated based on a crystal oscillator. Frequency synthesis and phase adjustment are performed based on phase-locked loops (PLLs) to achieve frequency multiplication and limited phase shift. The reference clock is divided using a digital divider / counter to generate multiple signals of different frequencies or simple phases. In multi-output applications, traditional architectures typically employ a "single reference clock + multiple frequency divider / multiplier circuits" approach. While this architecture can achieve basic multi-clock output, its inherent limitations are becoming increasingly apparent, making it difficult to meet the stringent requirements of emerging applications. Specifically, existing multi-phase clock generation technologies face the following pressing technical challenges: Fixed phase configuration and low waveform freedom: The phase interval and waveform cannot be dynamically adjusted. Traditional solutions, such as simple frequency dividers, generate signals whose phase relationships and waveforms are fixed during circuit design and cannot be dynamically adjusted according to different application scenarios. The programmability of the output signal waveform is severely insufficient, making it impossible to set multiple level switching points and perform fine-grained (such as sub-clock cycle level) timing control within a basic clock cycle. This greatly limits the ability to generate complex waveforms (such as asymmetric PWM, dead-time controllable drive signals, and multi-pulse waveforms).

[0005] Significant mode switching latency and poor real-time performance: Most existing modules lack pre-configured mode storage functionality. When the system needs to switch clock waveforms between different operating scenarios, the main controller must rewrite a large number of register configuration parameters via a low-speed serial interface (such as I2C or SPI). This process is time-consuming, introduces significant switching latency, causes clock output pauses or irregularities, fails to achieve "seamless switching," and severely impacts the system's real-time response performance.

[0006] Inefficient data transmission for configuration: The pursuit of waveform flexibility inevitably leads to a surge in the number of configuration parameters, such as storing a large amount of detailed event point information for multiple modes of multiple signals. However, existing solutions heavily rely on low-speed universal serial interfaces for configuration, whose transmission rates are significantly lower than those of high-speed on-chip buses (such as APB and AHB). When there are many configuration parameters, the lengthy configuration time becomes a bottleneck for system startup and mode switching.

[0007] Analog circuit design is complex: schemes relying on analog PLLs for fine phase adjustment are highly sensitive to changes in semiconductor process, voltage, and temperature (PVT). To maintain stable performance, complex calibration circuits are often required, which not only significantly increases design complexity and chip area but also contradicts the development trend of modern digital nanotechnology, hindering technology scaling and portability.

[0008] Synchronization and coordination of multiple complex signals: Achieving precise synchronous output among multiple complex signals requires complex scheduling and nanosecond-level configuration. This typically relies on additional delay-locked loops (DLLs) or precision calibration circuitry, further increasing system area and power consumption.

[0009] Limited timing control precision: The time resolution of traditional digital control schemes is usually limited by the period of the system reference clock, making it difficult to achieve precise control of sub-clock periods at the nanosecond or even picosecond level, and thus failing to meet the extreme timing precision requirements of high-end applications.

[0010] Limited number of output channels: Due to architectural complexity and resource overhead, many traditional MPCG designs only support a small number of output channels (such as 4 or 8), which makes it difficult to meet the growing demand of multi-channel parallel control systems (such as multiphase motor drives and large-scale antenna arrays).

[0011] In summary, there is an urgent need in this field for a novel MPCG solution that can overcome many of the shortcomings of the existing technologies and achieve high-degree-of-freedom, high-precision, and delay-free switching of multiple clock signals to meet the stringent timing control requirements of next-generation electronic systems. Summary of the Invention

[0012] This invention proposes a double-edge multi-phase clock generator and its control method, which solves the problems of fixed phase configuration, low waveform freedom, mode switching delay, low data transmission efficiency, complex coordination of multiple clock signals, and limited timing control accuracy.

[0013] The core technical solution of this invention is as follows: through three-level time division and multiple event point configuration, multiple signal state reversals can be achieved in each period, supporting custom high and low level duty cycles and multi-segment waveforms to meet the waveform customization requirements in complex scenarios. The mode pre-configuration mechanism only needs to call the pre-stored data when switching, without rewriting the register, and the switching delay is reduced to the "clock cycle level" to ensure the real-time performance of the system.

[0014] The specific solution of the present invention is as follows: A dual-edge multi-phase clock generator includes a bus interface module, a register file module, a counter module, and an output signal module. The bus interface module is mounted in the bus architecture and is used for data transmission. The register file module includes an event register, an initial state register, and a control register. The event register stores event point configuration data, and the initial state register stores the initial state configuration data of the clock signal. The counter module includes a round counter and a period counter. The period counter includes a rising edge clock counter and a falling edge clock counter to achieve double-edge operation. The output signal module includes an output arbitrator. The output signal module is used to read data from the counter module and the register file module in real time to generate a clock signal, and to control the output of the clock signal through the output arbitrator. The length of a complete clock signal is a time period, a time period includes R rounds, and a round includes T periods.

[0015] Furthermore, within one of the time periods, the event register is configured with E event points, each event point containing a set of {round, period} data.

[0016] Furthermore, the output signal module includes a clock rising edge sub-signal register and a clock falling edge sub-signal register, the clock rising edge sub-signal register and the clock rising edge counter are electrically connected, and the clock falling edge sub-signal register and the clock falling edge counter are electrically connected.

[0017] Furthermore, the clock rising edge sub-signal register outputs a rising edge sub-signal, and the clock falling edge sub-signal register outputs a falling edge sub-signal. The clock rising edge sub-signal register and the clock falling edge sub-signal register are respectively electrically connected to the output arbitrator. The output arbitrator outputs the rising edge sub-signal or the falling edge sub-signal by determining whether to use the rising edge sub-signal or the falling edge sub-signal.

[0018] A control method for a double-edge multi-phase clock generator, the method comprising: S1 performs multi-level time division and multi-event point configuration on the clock signal; S2 writes data to the register file module through the bus interface module; After the S3 module is enabled, the counter module starts counting from 0; The S4 output signal module reads data from the counter module and register file module in real time, generates rising edge sub-signals or falling edge sub-signals, and outputs them through the output arbitrator.

[0019] Furthermore, the S1 configuration of the clock signal for multi-level time division and multi-event point configuration includes: the length of a complete clock signal is a time period, a time period includes R rounds, a round includes T periods, and within a time period, the event register is configured with E event points, each event point containing a set of {round, period} data.

[0020] Furthermore, the step of S2 writing data to the register file module through the bus interface module includes writing event point configurations, initial states, and control instructions for M modes of N clock signals to the register file module.

[0021] Furthermore, after the S3 module is enabled, the counter module starts counting from 0, including: The S31 round counter counts from 0 to r, and the period counter counts from 0 to t. The period counter counts according to the double-edge rule. The S32 counts for even periods are triggered by the rising edge of the clock, and the counts for odd periods are triggered by the falling edge of the clock, or the counts for even periods are triggered by the falling edge of the clock, and the counts for odd periods are triggered by the rising edge of the clock. When the count value of the current period is t, the count value of the current period is reset to zero on the next rising edge of the clock, and the value of the cycle counter is incremented by one. When the value of the cycle counter reaches r and the value of the current period counter is t, it indicates that a complete clock signal has been output.

[0022] Furthermore, the S4 output signal module reads data from the counter module and the register file module in real time, generates rising edge sub-signals or falling edge sub-signals, and outputs them through the output arbitrator, including: When the values ​​of the round counter and the rising edge counter reach the set event point, the rising edge sub-signal of the clock is inverted; when the values ​​of the round counter and the falling edge counter reach the set event point, the falling edge sub-signal of the clock is inverted. When the value of the round counter is the round number set by the event point, the output arbitrator performs parity judgment on the values ​​of the clock rising edge counter and the clock falling edge counter, and outputs the corresponding clock rising edge sub-signal or clock falling edge sub-signal.

[0023] Furthermore, when switching to S5 mode, the register file module directly calls the pre-configured event point data without rewriting, achieving seamless mode switching.

[0024] The present invention has the following technical effects: 1. Significantly improved degrees of freedom and complexity in waveform generation. By employing an innovative three-level time division architecture of "Slot-Round-Term" and combining it with a configuration mechanism for multiple programmable event points within each slot, the limitations of traditional clock generators, which can only control 1-2 edges, are broken. This allows each clock signal to support multiple precise level state transitions within a basic cycle, thereby enabling the generation of extremely complex customized waveforms such as asymmetric PWM, drive signals with dead time, and multi-pulse waveforms.

[0025] 2. Achieves seamless mode switching, greatly improving system real-time performance. Addressing the core pain point of large mode switching latency in existing technologies, this invention pioneers a multi-channel, multi-mode pre-configuration architecture. Configuration parameters for all waveform modes are pre-stored in a register file module. In actual operation, mode switching only requires directly calling the pre-stored configuration, eliminating the need to rewrite large amounts of data through external interfaces. This mechanism reduces mode switching latency from milliseconds (low-speed serial configuration time) to several system clock cycles, achieving near-zero latency seamless switching and greatly ensuring the real-time response capability of the control system in dynamically changing scenarios.

[0026] 3. Configuration efficiency and system integration are significantly improved. The invention replaces traditional low-speed serial interfaces such as I2C / SPI with an APB high-speed bus interface module. The APB interface offers higher transmission bandwidth, enabling extremely fast loading of numerous configuration parameters during the initialization phase, significantly reducing system startup and batch configuration time. Furthermore, APB is the standard bus for System-on-a-Chip (SoC), making this invention easier to integrate into complex SoCs, achieving seamless connectivity with the processor core, reducing processor load, simplifying software driver design, and improving the overall system's collaborative efficiency and reliability.

[0027] 4. High-precision timing control at the sub-clock cycle level was achieved without increasing power consumption. Double-edge counting, by splitting the period counter into a rising-edge counter and a falling-edge counter, and performing counting operations on both the rising and falling edges of the clock, doubles the time control resolution without increasing the system core clock frequency, thus achieving sub-clock cycle control accuracy. Doubling the accuracy without increasing power consumption perfectly balances the requirements of high performance and low power consumption, making it particularly suitable for power-sensitive, high-precision applications.

[0028] 5. High reliability, strong robustness, and minimal susceptibility to external environmental influences. The fully digital logic control uses a purely digital method of "double-edge counting" and "event point comparison" to generate the clock signal, rather than traditional analog delay units (such as voltage-controlled delay lines in DLLs). Therefore, its performance is extremely insensitive to external factors such as process variations, power supply voltage fluctuations, and physical temperature variations (PVT). It can output a stable and accurate clock signal under various operating conditions without the need for complex calibration circuits, improving system reliability and consistency while reducing chip area, design complexity, and risk.

[0029] 6. Supports multiple independent high-precision outputs, with strong expandability. It supports multiple independently controllable output channels, each of which can be independently configured with its operating mode and initial state, meeting the synchronous control requirements of multi-task parallel systems. The architecture exhibits good scalability; the number of output channels and pre-configured modes can be further expanded by increasing the capacity of the register file module and the output arbitration logic to adapt to more complex future application scenarios. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of a double-edge multi-phase clock generator structure in one embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the relationship between time period, round, and period in one embodiment of the present invention; Figure 3 This is a schematic diagram of the output signal module structure in one embodiment of the present invention.

[0031] Explanation of reference numerals in the attached figures Bus interface module 1; Register file module 2; Event register 21; Initial state register 22; Control register 23; Counter module 3; Round counter 31; Period counter 32; Clock falling edge counter 321; Clock rising edge counter 322; Output signal module 4; Output arbiter 41; Clock rising edge sub-signal register 42; Clock falling edge sub-signal register 43; Rising edge sub-signal 5; Falling edge sub-signal 6. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] In this specification, identical components are represented by the same reference numerals. It should be noted that the terms "front," "rear," "left," "right," "upper," and "lower" used in the following description refer to directions in the accompanying drawings, while the terms "bottom surface," "top surface," "inner," and "outer" refer to directions towards or away from a specific component, respectively. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this specification, "multiple" means two or more.

[0034] Example 1 This invention provides a double-edge multi-phase clock generator. Figure 1This is a schematic diagram of a dual-edge multi-phase clock generator structure in one embodiment, including a bus interface module 1, a register file module 2, a counter module 3, and an output signal module 4. The bus interface module 1 is mounted in the bus architecture for data transmission. The register file module 2 includes an event register 21, an initial state register 22, and a control register 23. The event register 21 is used to store event point configuration data, and the initial state register 22 is used to store the initial state configuration data of the clock signal. The counter module 3 includes a round counter 31 and a period counter 32. The period counter 32 includes a clock rising edge counter 322 and a clock falling edge counter 321 to implement dual-edge operation. The output signal module 4 includes an output arbitrator 41. The output signal module 4 is used to read the data from the counter module 3 and the register file module 2 in real time to generate a clock signal, and controls the clock signal output through the output arbitrator 41. The length of a complete clock signal is a time period, a time period includes R rounds, a round includes T periods, and within a time period, the event register 21 configures E event points, each event point containing a set of {round, period} data.

[0035] The bus interface module 1 is an APB interface, mounted on the internal bus architecture of the system. It serves as a high-speed data channel for external connections, responsible for receiving and parsing read / write instructions and configuration data, and for data transmission with the processor. For example, it receives data for configuring the register file module 2 and provides feedback on the current operating status of the register file module 2. Because this invention can be mounted on the bus architecture via the APB interface, data transmission with the processor is much faster than conventional communication methods (such as I2C, SPI, etc.), allowing for more rapid control of the clock signal. The use of the APB high-speed bus interface significantly improves the transmission efficiency of a large number of configuration parameters. In other embodiments, AHB, AXI, or other types of on-chip bus interfaces can also be used.

[0036] The register file module 2 is the storage center for the configuration data of this invention, and it includes: Event Register 21: Used to store waveform event point configuration data for all clock signals. In a preferred embodiment, Event Register 21 provides 16 pre-configurable operating patterns for each clock signal, each pattern capable of storing up to 4 event points. Each event point is uniquely identified by a set of {Round, Term} data, representing the precise moment when the clock signal's level state reverses within a slot.

[0037] Initial State Register 22: A multi-bit register used to configure the initial level state (high or low) of each clock signal at the start of a slot.

[0038] Control Register 23: Used to implement global control of the module, it includes functional fields such as global enable bit, enable bit for each output channel, mode selection field (used to select the currently active pre-configured mode for each output channel), interrupt enable, and status flag bit.

[0039] Counter module 3 is the timing reference generation unit of this invention. It is activated after the enable bit of control register 23 is set, and is used to generate the coordinates of the current moment on the three-level time scale of "segment period - round - period". This module includes: Round counter 31: Circularly counts the rounds within a slot. Assuming a slot contains R rounds (e.g., R=32), the round counter 31 will count from 0 to (R-1).

[0040] Period counter 32: Circularly counts the terms within a round. One of the key innovations of this invention is that the period counter 32 is implemented by two sub-counters: a rising edge counter 322 and a falling edge counter 321. The rising edge counter increments on each rising edge of the system clock (CLK); the falling edge counter increments on each falling edge of the system clock (CLK). The two counters work together to complete two counting operations within one system clock cycle, thereby doubling the time resolution without increasing the system clock frequency, achieving precise sub-clock cycle control. Assuming a round contains T terms (e.g., T=16), the counting range of the period counter 32 is 0 to (T-1).

[0041] The above structure can be easily modified to use a "single-edge counter + frequency multiplier clock" approach. This means doubling the clock frequency halves the number of counter units, effectively achieving double-edge precision. However, the frequency multiplier clock increases module power consumption; doubling the clock frequency nearly doubles the dynamic power consumption.

[0042] The output signal module 4 includes a clock rising edge sub-signal register 42 and a clock falling edge sub-signal register 43. The clock rising edge sub-signal register 42 is electrically connected to the clock rising edge counter 322, and the clock falling edge sub-signal register 43 is electrically connected to the clock falling edge counter 321. The clock rising edge sub-signal register 42 outputs a rising edge sub-signal 5, and the clock falling edge sub-signal register 43 outputs a falling edge sub-signal 6. The clock rising edge sub-signal register 42 and the clock falling edge sub-signal register 43 are respectively electrically connected to the output arbitrator 41. The output arbitrator 41 outputs either the rising edge sub-signal 5 or the falling edge sub-signal 6 by determining whether to use the rising edge sub-signal 5 or the falling edge sub-signal 6.

[0043] Output signal module 4 is the waveform generation execution unit, such as... Figure 3 As shown, it is used to read the current count value from counter module 3 and the configuration data from register file module 2 in real time, compare and synthesize them, and finally generate the required complex clock waveform. This module includes an output arbitrator 41, which works as follows: the clock signal is logically split into a rising edge sub-signal 5 and a falling edge sub-signal 6. The output arbitrator 41 monitors the parity of the term corresponding to the current event point in real time. Through this mechanism, the high-precision time coordinates generated by the dual-edge counting are accurately mapped to the final clock signal, achieving precise level switching based on event points.

[0044] like Figure 2 As shown, in one embodiment, the present invention defines the length of a complete clock signal as a slot. For precise control of the clock signal, a slot is subdivided into 32 rounds, and a round is further subdivided into 16 periods. Within a slot, the event register 21 is configured with 4 event points. Each event point contains a set of {round, period} data. The number of event points is not limited to 4 and can be increased or decreased. For example, a 2-event-point version can be designed for simpler applications, or an 8-event-point version can be designed for more complex applications. When the clock signal reaches a preset period of a preset round, the state of the clock signal will reverse; that is, if it was originally high, it will become low when passing the event point, and vice versa.

[0045] In other words, the state of the clock signal can change four times within a complete clock signal output time, which gives the clock signal waveform a high degree of freedom. Furthermore, this invention supports the design of the initial state, that is, setting the high / low level of the clock signal at the beginning of each time period, which further enhances the editability and freedom of the clock signal in this invention.

[0046] Example 2 This invention also provides a control method for a dual-edge multi-phase clock generator. In this embodiment, the control method mainly includes: S1 performing multi-level time division and multi-event point configuration on the clock signal; S2 writing data to the register file module 2 through the bus interface module 1; S3 after the module is enabled, the counter module 3 starts counting from 0; S4 the output signal module 4 reads the data from the counter module 3 and the register file module 2 in real time, generates rising edge sub-signal 5 or falling edge sub-signal 6, and outputs it through the output arbitrator 41.

[0047] S1 performs multi-level time division and multi-event point configuration on the clock signal, including: the length of a complete clock signal is a time period, a time period includes R rounds, a round includes T periods, and within a time period, the event register 21 configures E event points, each event point containing a set of {round, period} data.

[0048] The timing subdivision granularity can be adjusted according to actual accuracy and range requirements. In different embodiments, {round number, period number} can be set to {32, 16}, or {64, 8}, {16, 32}. However, it should be noted that changing the round number and period number will change the required bit width of the counter module 3, which will lead to changes in power consumption and area.

[0049] S2 writes data to register file module 2 through bus interface module 1, including writing event point configurations, initial states, and control commands for M modes of N clock signals to register file module 2.

[0050] In one embodiment, 12 clock signals can be output, each of which can be defined with 16 operating modes. The processor can pre-edit the actions of each clock signal under each mode, that is, pre-configure the event register 21 of each clock signal. In this way, when switching modes, it is not necessary to rewrite data into the register file module 2, thereby achieving a seamless switching effect.

[0051] After S3 module is enabled, counter module 3 starts counting from 0, including: S31 round counter 31 counts from 0 to r, period counter 32 counts from 0 to t, and period counter 32 counts according to the double-edge rule; The S32 counts for even periods are triggered by the rising edge of the clock, and the counts for odd periods are triggered by the falling edge of the clock, or the counts for even periods are triggered by the falling edge of the clock, and the counts for odd periods are triggered by the rising edge of the clock. When the count value of the current period is t, the count value of the current period is reset to zero on the next rising edge of the clock, and the value of the cycle counter 31 is incremented by one. When the value of the cycle counter 31 reaches r and the value of the current period counter 32 is t, it indicates that a complete clock signal has been output.

[0052] This invention employs a dual-edge operation mode. In one embodiment, the period counter 32 is divided into an even-numbered clock rising edge counter 322 and an odd-numbered clock falling edge counter 321. That is, both the clock rising edge counter 322 and the clock falling edge counter 321 are used simultaneously to count the periods. The counters start counting from 0; therefore, the counting of even-numbered periods occurs on the clock rising edge, and the counting of odd-numbered periods occurs on the clock falling edge. When the period count is 15, the period count will reset to zero on the next clock rising edge, and the period counter 31 will increment by one. When the period counter 31 reaches 31 and the period counter 32 is 15, it indicates that a complete clock signal has been output, signifying the end of one period. A new clock signal begins from the next clock rising edge.

[0053] In another embodiment, the period counter 32 is divided into an odd-rising-edge clock counter 322 and an even-falling-edge clock counter 321. That is, both the rising-edge clock counter 322 and the falling-edge clock counter 321 are used simultaneously to count the periods. The counters start counting from 0, so the counting of odd-numbered periods occurs on the rising edge of the clock, and the counting of even-numbered periods occurs on the falling edge of the clock. When the period count is 15, the period count resets to zero on the next rising edge of the clock, and the period counter 31 increments by one. When the period counter 31 reaches 31 and the period counter 32 is 15, it indicates that a complete clock signal has been output, signifying the end of one period, and a new clock signal begins from the next rising edge of the clock.

[0054] S4 output signal module 4 reads data from counter module 3 and register file module 2 in real time, generates rising edge sub-signal 5 or falling edge sub-signal 6, and outputs the following through output arbitrator 41: When the values ​​of the round counter 31 and the clock rising edge counter 322 reach the set event point, the clock rising edge sub-signal 5 is reversed; when the values ​​of the round counter 31 and the clock falling edge counter 321 reach the set event point, the clock falling edge sub-signal 6 is reversed. When the value of the round counter 31 is the round number set by the event point, the output arbitrator 41 performs parity judgment on the values ​​of the clock rising edge counter 322 and the clock falling edge counter 321, and outputs the corresponding clock rising edge sub-signal 5 or clock falling edge sub-signal 6.

[0055] The initial states of the clock rising edge sub-signal 5 and the clock falling edge sub-signal 6 are set by the initial state register 22 in the register file module 2. These two signals are updated at the rising edge and falling edge of the clock, respectively.

[0056] For the rising edge sub-signal 5, its state is reversed when the values ​​of the round counter 31 and the rising edge counter 322 reach a set event point. Otherwise, the rising edge sub-signal register 42 continuously samples the output signal, updating the rising edge sub-signal 5 at the rising edge of each clock cycle. That is, if the clock signal changes at the falling edge of the clock, the rising edge sub-signal 5 will update this change at the rising edge of the next clock cycle. Similarly, the falling edge sub-signal 6 is reversed when the values ​​of the round counter 31 and the falling edge counter 321 reach a set event point. Otherwise, it is updated to the clock signal value at the falling edge of each clock cycle.

[0057] The output arbiter 41 ultimately determines whether to output the rising edge sub-signal 5 or the falling edge sub-signal 6. When the round counter 31 returns the round number set by the event point, the output arbiter 41 performs an even / odd check on the set round number. If the set round number is odd, the output terminal outputs the falling edge sub-signal 6 during this round; otherwise, it outputs the rising edge sub-signal 5. When the current round is not an event point round, the output arbiter 41 defaults to outputting the rising edge sub-signal 5. Thus, the module's double-edge operation mode is completed under the combined action of the double-edge round counter 32 and the double-edge sub-signals.

[0058] In another embodiment, the parity judgment and edge correspondence can be interchanged. That is, when the set period is even, the output terminal outputs the falling edge sub-signal 6 during this round; otherwise, it outputs the rising edge sub-signal 5.

[0059] During S5 mode switching, register file module 2 directly calls the pre-configured event point data without rewriting, achieving seamless mode switching. Since the event registers 21 for each clock signal are pre-configured, during mode switching, the processor only needs to write the "target mode number" to control register 23, without needing to rewrite data to register file module 2, thus achieving a seamless switching effect.

[0060] In summary, through a series of innovative designs, this invention brings groundbreaking benefits in terms of waveform freedom, real-time switching, configuration efficiency, timing accuracy, power consumption control, system reliability, and multi-channel expansion capabilities, with overall performance far exceeding that of existing technical solutions.

Claims

1. A double-edge multi-phase clock generator, characterized in that, It includes a bus interface module, a register file module, a counter module, and an output signal module. The bus interface module is mounted in the bus architecture and is used for data transmission. The register file module includes an event register, an initial state register, and a control register. The event register stores event point configuration data, and the initial state register stores initial state configuration data for signals. The counter module includes a round counter and a period counter. The period counter includes a rising edge clock counter and a falling edge clock counter to achieve double-edge operation. The output signal module includes an output arbitrator. The output signal module is used to read data from the counter module and the register file module in real time to generate a clock signal, and to control the output of the clock signal through the output arbitrator. The length of a complete clock signal is a time period, a time period includes R rounds, and a round includes T periods.

2. The double-edge multi-phase clock generator according to claim 1, characterized in that, Within a given time period, the event register is configured with E event points, each event point containing a set of {round, period} data.

3. The double-edge multi-phase clock generator according to claim 2, characterized in that, The output signal module includes a clock rising edge sub-signal register and a clock falling edge sub-signal register. The clock rising edge sub-signal register and the clock rising edge counter are electrically connected, and the clock falling edge sub-signal register and the clock falling edge counter are electrically connected.

4. The double-edge multi-phase clock generator according to claim 3, characterized in that, The clock rising edge sub-signal register outputs a rising edge sub-signal, and the clock falling edge sub-signal register outputs a falling edge sub-signal. The clock rising edge sub-signal register and the clock falling edge sub-signal register are respectively connected to the output arbitrator. The output arbitrator outputs the rising edge sub-signal or the falling edge sub-signal by determining whether to use the rising edge sub-signal or the falling edge sub-signal.

5. The control method for the double-edge multi-phase clock generator according to any one of claims 1 to 4, characterized in that, The method includes: S1 performs multi-level time division and multi-event point configuration on the clock signal; S2 writes data to the register file module through the bus interface module; After the S3 module is enabled, the counter module starts counting from 0; The S4 output signal module reads data from the counter module and register file module in real time, generates rising edge sub-signals or falling edge sub-signals, and outputs them through the output arbitrator.

6. The control method for the double-edge multi-phase clock generator according to claim 5, characterized in that, The S1 process for multi-level time division and multi-event point configuration of the clock signal includes: the length of a complete clock signal is a time period, a time period includes R rounds, a round includes T periods, and within a time period, the event register is configured with E event points, each event point containing a set of {round, period} data.

7. The control method for the double-edge multi-phase clock generator according to claim 6, characterized in that, The process of S2 writing data to the register file module via the bus interface module includes writing event point configurations, initial states, and control commands for M modes of N clock signals to the register file module.

8. The control method for the double-edge multi-phase clock generator according to claim 7, characterized in that, After the S3 module is enabled, the counter module starts counting from 0, including: The S31 round counter counts from 0 to r, and the period counter counts from 0 to t. The period counter counts according to the double-edge rule. The S32 counts for even periods are triggered by the rising edge of the clock, and the counts for odd periods are triggered by the falling edge of the clock, or the counts for even periods are triggered by the falling edge of the clock, and the counts for odd periods are triggered by the rising edge of the clock. When the count value of the current period is t, the count value of the current period is reset to zero on the next rising edge of the clock, and the value of the cycle counter is incremented by one. When the value of the cycle counter reaches r and the value of the current period counter is t, it indicates that a complete clock signal has been output.

9. The control method for a double-edge multi-phase clock generator according to claim 8, characterized in that, The S4 output signal module reads data from the counter module and the register file module in real time, generates rising edge sub-signals or falling edge sub-signals, and outputs them through the output arbitrator, including: When the values ​​of the round counter and the rising edge counter reach the set event point, the rising edge sub-signal of the clock is inverted; when the values ​​of the round counter and the falling edge counter reach the set event point, the falling edge sub-signal of the clock is inverted. When the value of the round counter is the round number set by the event point, the output arbitrator performs parity judgment on the values ​​of the clock rising edge counter and the clock falling edge counter, and outputs the corresponding clock rising edge sub-signal or clock falling edge sub-signal.

10. The control method for a double-edge multi-phase clock generator according to claim 9, characterized in that, When switching to S5 mode, the register file module directly calls the pre-configured event point data without rewriting, achieving seamless mode switching.

Images