Chip encapsulation structure

Abstract

The present invention discloses a chip encapsulation structure (E) comprising a ceramic substrate (1), a copper structure (2), a precious metal layer (3), a chip (3a), and an encapsulation adhesive (4). The copper structure (2) is formed on the ceramic substrate (1), with a recessed recess (2c) being formed on at least one side wall (2a) of the copper structure (2). The precious metal layer (3) is formed on the copper structure (2). The chip (3a) is arranged on the precious metal layer (3). The encapsulation adhesive (4) is formed on the ceramic substrate (1) and encapsulates the copper structure (2), the precious metal layer (3), and the chip (3a).A surface treatment layer (2b) is formed on the exposed copper surface of the copper structure (2), which is not in contact with the ceramic substrate (1) and the precious metal layer (3). The encapsulation adhesive (4) is in contact with the surface treatment layer (2b) and thus bonds with the copper structure (2). The surface treatment layer (2b) extends over the inner surface of the recess (2c), while the encapsulation adhesive (4) also fills and engages with the recess (2c).

Description

[0001] The present invention relates to an encapsulation structure, in particular a chip encapsulation structure.

[0002] Existing chip encapsulation technology typically employs large quantities of precious metal materials such as gold (Au), silver (Ag), palladium (Pd), and the like to improve the reliability and electrical performance of the encapsulation structure. However, the high cost of these precious metals and their limited availability significantly increase manufacturing costs. Furthermore, the extensive use of precious metal layers in the encapsulation structure also increases material waste, further driving up manufacturing costs.

[0003] Furthermore, state-of-the-art chip encapsulation structures often suffer from insufficient heterogeneous bonding between the copper surface and the encapsulation adhesive, which can lead to encapsulation failure at high temperatures or pressures, thus compromising the reliability and lifespan of the encapsulation. According to the state of the art, the heterogeneous bonding of copper surfaces is usually enhanced by physical roughening or chemical treatment, but these methods often require complex process steps and expensive materials.

[0004] Therefore, there is an urgent need in the professional community for an improved chip encapsulation structure that can reduce manufacturing costs while simultaneously increasing the reliability and design flexibility of an encapsulation structure.

[0005] Starting from the disadvantages of the prior art, the present invention aims to offer a chip encapsulation structure that avoids the aforementioned disadvantages.

[0006] According to the invention, the problem is solved by a chip encapsulation structure comprising a ceramic substrate, a copper structure formed on the ceramic substrate (with a recessed recess on at least one side wall of the copper structure), a precious metal layer formed on the copper structure, a chip arranged on the precious metal layer, and an encapsulation adhesive formed on the ceramic substrate that encapsulates the copper structure, the precious metal layer, and the chip. A surface treatment layer is formed on the exposed copper surface of the copper structure, which is not in contact with the ceramic substrate or the precious metal layer. The encapsulation adhesive is in contact with the surface treatment layer and thereby bonds with the copper structure.The surface treatment layer extends over the inner surface of the recess, while the encapsulation adhesive also fills and engages within the recess.

[0007] According to the invention, the problem is further solved by a chip encapsulation structure comprising a ceramic substrate, a copper structure formed on the ceramic substrate, a precious metal layer formed on the copper structure, a chip arranged on the precious metal layer, and an encapsulation adhesive formed on the ceramic substrate that encapsulates the copper structure, the precious metal layer, and the chip. A surface treatment layer is formed on the exposed copper surface of the copper structure, which is not in contact with the ceramic substrate and the precious metal layer. The encapsulation adhesive is in contact with the surface treatment layer and thereby bonds with the copper structure.The copper structure consists of a supporting copper pillar in the form of an elongated column, which is present in multiples, with the several supporting copper pillars spaced apart from each other and arranged upright on the ceramic substrate, and the encapsulating adhesive filling the gap between the several supporting copper pillars.

[0008] The advantageous effect of the present invention is that, in the chip encapsulation structure provided by the present invention, the heterogeneous bond between the encapsulation adhesive and the copper structure can be strengthened and the use of precious metal reduced by the design "on the exposed copper surface of the copper structure, which is not in contact with the ceramic substrate and the precious metal layer, a surface treatment layer is formed, wherein the encapsulation adhesive is in contact with the surface treatment layer and thereby bonds with the copper structure" and the design "a recess is formed on the side wall of the copper structure or the copper structure is formed as several supporting copper columns".

[0009] For a better understanding of the features and technical content of the present invention, reference is made to the following detailed description and the drawings of the present disclosure, which, however, serve only for illustration and are not intended to limit the present invention. Fig. Figure 1 shows a schematic side view of an encapsulation structure of a first embodiment of the present invention. Fig. Figure 2 shows a partially enlarged schematic representation of area II in Fig. 1. Fig. Figure 3 shows a schematic top view of the encapsulation structure of the first embodiment of the present invention. Fig. Figures 4A to 4H show schematic flowcharts of a process for producing an encapsulation structure according to the invention. Fig. Figure 5 shows a schematic side view of an encapsulation structure of a second embodiment of the present invention. Fig. Figure 6A shows a schematic top view of the encapsulation structure of the second embodiment of the present invention. Fig. Figure 6B shows a schematic view from below of the encapsulation structure of the second embodiment of the present invention and Fig. Figure 7 shows a schematic representation of a variant of the encapsulation structure of the second embodiment of the present invention.

[0010] The embodiments disclosed within the scope of the present invention are described below with reference to specific, concrete examples. Those skilled in the art will recognize that the advantages and effects of the present invention can be derived from the disclosures in this description. The present invention can be implemented or applied in other specific embodiments, whereby various modifications or alterations can be made to the details disclosed in this description as needed and depending on the application, without departing from the fundamental ideas of the present invention.

[0011] Furthermore, it should be noted that the individual components of the present invention are not shown in their actual size, but only schematically. The following embodiments serve to further explain the respective configurations of the present invention and in no way limit the scope of protection of the present invention.

[0012] It is understood that the terms "first," "second," "third," etc., used to describe various elements or signals, are not to be interpreted as restrictive. Rather, such terms serve to distinguish one element from another or one signal from another. Furthermore, the term "or" used in this description may, where applicable, encompass any of the listed items or a combination of several such items. [First embodiment]

[0013] With reference to Fig. 1, Fig. 2 to Fig. 3 The first embodiment of the present invention provides a chip encapsulation structure E, in particular a chip encapsulation structure E based on an eDPC stack.

[0014] The aim of the first embodiment of the present invention is to reduce the precious metal surface area of ​​the eDPC stack, to increase the exposed copper area on the surfaces and sidewalls, and to enhance the heterogeneous bond of the encapsulation adhesive to the copper surface by creating a surface treatment layer on the exposed copper surface. Furthermore, the chip encapsulation structure E of the first embodiment of the present invention can strengthen the heterogeneous bond of the copper surface without impairing the reliability of placement on the precious metal surface and also provides a solder stop effect.

[0015] To achieve the above-mentioned goal, the chip encapsulation structure E comprises a ceramic substrate 1, a copper structure 2, a precious metal layer 3, a chip 3a, at least one conductor 3b and an encapsulation adhesive 4.

[0016] The copper structure 2 is formed on a side surface (e.g., the top surface) of the ceramic substrate 1. The precious metal layer 3 is formed on a side surface (e.g., the top surface 2d) of the copper structure 2 facing away from the ceramic substrate 1. The chip 3a is arranged on a side surface of the precious metal layer 3 facing away from the copper structure 2. The at least one conductor 3b is connected between the chip 3a (or its top surface) and the precious metal layer 3 (or its top surface).

[0017] The encapsulation adhesive 4 is formed on the side surface of the ceramic substrate 1 and serves to encapsulate the copper structure 2, the precious metal layer 3, the chip 3a and the conductor 3b. That is, the copper structure 2, the precious metal layer 3, the chip 3a and the conductor 3b are located within the encapsulation adhesive 4 and are surrounded by the encapsulation adhesive 4.

[0018] In some embodiments of the present invention, the ceramic substrate 1 can consist, for example, of aluminium nitride (AlN), aluminium oxide (Al2O3), silicon nitride (SiN) or silicon carbide (SiC).

[0019] Furthermore, the ceramic substrate 1 is formed on its inner surface with at least one continuous copper column 1a extending from the top to the bottom and on its underside with an underside copper layer 1b. The at least one continuous copper column 1a is electrically connected between the copper structure 2 and the underside copper layer 1b. In the present embodiment, the at least one continuous copper column 1a is present in plurality and arranged spaced apart from one another. The underside copper layer 1b substantially covers the underside of the ceramic substrate 1, but the present invention is not limited thereto.

[0020] Furthermore, as can be seen from Fig. 1 and Fig. In the present embodiment, a surface treatment layer 2b is formed on the exposed copper surface of the copper structure 2, which is not in contact with the ceramic substrate 1 and the precious metal layer 3. The encapsulation adhesive 4 is in contact with the surface treatment layer 2b and thereby bonds with the copper structure 2 to strengthen the heterogeneous bond between the encapsulation adhesive 4 and the copper structure 2. In the present embodiment, the surface treatment layer 2b is formed on at least one side wall 2a of the copper structure 2 that is not in contact with the ceramic substrate 1 and the precious metal layer 3, and in certain areas on a top surface 2d that is connected to the side wall 2a.In contrast, the top surface of the precious metal layer 3 is not provided with the surface treatment layer 2b in order to increase the heterogeneous bonding of the copper surface without affecting the reliability of assembly on the precious metal surface.

[0021] The surface treatment layer 2b can, for example, be a roughened surface treatment layer that has a greater surface roughness (e.g., arithmetic mean of roughness Ra) than the precious metal layer 3, but the present invention is not limited to this.

[0022] In another embodiment of the present invention, the surface treatment layer 2b can, for example, also be a functionalized surface treatment layer, which may be, for example, a functionalized surface treatment layer with a functional silane group and / or a functional siloxane group. In a further embodiment of the present invention, the surface treatment layer 2b can, for example, also be a chemically bonded surface treatment layer, which may be, for example, a copper oxide (CuO) surface treatment layer with an oxidized surface, but the present invention is not limited thereto.

[0023] Furthermore, in the present embodiment, a recessed recess 2c is formed on the side wall 2a of the copper structure 2, over the inner surface of which the surface treatment layer 2b extends, wherein the encapsulation adhesive 4 also fills the recess 2c of the copper structure 2 and is thereby in contact with the surface treatment layer 2b inside the recess 2c.

[0024] By having the encapsulating adhesive 4 fill the recess 2c of the copper structure 2, a structure can be created in which the encapsulating adhesive 4 and the copper structure 2 interlock to increase the contact area between the encapsulating adhesive 4 and the copper structure 2 and thus increase the bonding force between the encapsulating adhesive 4 and the copper structure 2.

[0025] In the present embodiment, the precious metal layer 3 is formed on the top surface 2d of the copper structure 2 and occupies an area that is smaller than the area of ​​the top surface 2d of the copper structure 2.

[0026] This means that the precious metal layer 3 is only formed in certain areas on the top surface 2d of the copper structure 2, so that at least one other area of ​​the top surface 2d of the copper structure 2 is exposed and covered by the surface treatment layer 2b.

[0027] According to the configuration above, the chip encapsulation structure E according to the embodiment of the present invention can reduce the precious metal area of ​​the eDPC stack, increase the exposed copper area on the surfaces and sidewalls, and enhance the heterogeneous bond of the encapsulation adhesive to the copper surface by creating a surface treatment layer on the exposed copper surface. Furthermore, the heterogeneous bond of the copper surface can be strengthened without compromising the reliability of placement on the precious metal surface.

[0028] In particular, attention is drawn to Fig. Reference is made to Figure 2, which schematically shows a partially enlarged side view of the copper structure 2 of the embodiment of the present invention. The copper structure 2 comprises a first copper layer 21, a second copper layer 22, and a third copper layer 23, which are stacked one above the other on the side surface of the ceramic substrate 1. The side wall of the second copper layer 22 is recessed both with respect to the side wall of the first copper layer 21 and with respect to the side wall of the third copper layer 23 in order to create the recess 2c.

[0029] In other words, the side wall of the third copper layer 23 projects relative to the side wall of the second copper layer 22, thus forming an eaves structure, the length over which the side wall of the third copper layer 23 projects relative to the side wall of the second copper layer 22 is defined as the first projection length W1. Furthermore, the side wall of the first copper layer 21 also projects relative to the side wall of the second copper layer 22, the length over which the side wall of the first copper layer 21 projects relative to the side wall of the second copper layer 22 is defined as the second projection length W2.

[0030] The first protrusion length W1 is less than the second protrusion length W2, wherein the first protrusion length W1 is not greater than 50 micrometers and preferably between 15 micrometers and 50 micrometers.

[0031] Accordingly, the recess 2c can provide sufficient space for the encapsulation adhesive 4 to engage more securely in the recess 2c of the copper structure 2 in order to increase the bonding force. However, this does not constitute a limitation of the present invention.

[0032] In Fig. Figure 3 shows a schematic top view of the encapsulation structure E of the embodiment of the present invention. In the copper structure 2, the projecting eaves structure of the side wall of the third copper layer 23, in relation to the side wall of the second copper layer 22, can, for example, be rectangular, but the present invention is not limited to this. The projecting shape of the third copper layer 23 can also be, for example, a semicircle, a triangle, or another physical shape.

[0033] Furthermore, the aforementioned eaves structure of the third copper layer 23 can be provided, for example, in a number of four, wherein the aforementioned eaves structures are arranged in pairs opposite each other on the four edges of the third copper layer 23.

[0034] In addition, the four corner edges of the first copper layer 21 can, for example, each be designed as a rounded corner edge 2e, replacing the conventional right-angled design, thereby reducing the concentration of stresses that can cause the copper layer to detach from the ceramic substrate or to warp.

[0035] Dating back to Fig. Figure 1 shows that the precious metal layer 3 is formed on a side surface of the copper structure 2 facing away from the ceramic substrate 1 (e.g., the top surface 2d of the third copper layer 23). The thickness of the precious metal layer 3 is less than the total thickness of the copper structure 2 (i.e., the sum of the thicknesses of the first copper layer 21, the second copper layer 22, and the third copper layer 23) and is not more than one-third of the total thickness of the copper structure 2, but the present invention is not limited thereto.

[0036] The material of the precious metal layer 3 can, for example, contain at least one of the following metals: gold (Au), silver (Ag), palladium (Pd), and nickel (Ni). The precious metal layer 3 can be produced, for example, by electroplating, electroless deposition, physical vapor deposition (PVD), or chemical vapor deposition (CVD).

[0037] In some embodiments of the present invention, the precious metal layer 3 can be electroplated nickel-palladium-gold, electroplated ultrathin nickel-palladium-gold (e.g., Ni < 3 µm, Pd < 0.076 µm, Au < 0.076 µm), electroplated nickel-gold, electroplated nickel-silver, electroplated nickel, electroless nickel-palladium-gold, electroless ultrathin nickel-palladium-gold (Ni < 0.25 µm, Pd < 0.12 µm, Au < 0.07 µm), electroless nickel-gold, electroless silver, electroless nickel, gas-phase titanium-platinum-gold (PVD Ti / Pt / Au), or gas-phase gold-tin (PVD) Au / Sn).

[0038] Furthermore, the encapsulation adhesive 4 can be made, for example, from at least one of the following materials: epoxy resin, polyimide resin, silicone resin and polyurethane resin, preferably epoxy resin.

[0039] According to the configuration described above, the chip encapsulation structure E of the embodiment of the present invention can exhibit improved reliability and avoid an excessively rough surface treatment of the precious metal layer 3, which can lead to poor placement or melting quality. It is also possible to increase the heterogeneous bond between the copper surface area and the encapsulation adhesive, thereby also increasing the bond strength of the copper sidewalls (better than with normal physical roughening). Furthermore, since the chip encapsulation structure E of the embodiment of the present invention does not require a full-surface surface treatment of the precious metal, it is cost-effective to manufacture.

[0040] Furthermore, the chip encapsulation structure E of the embodiment of the present invention can be designed with different exposed copper surfaces according to the respective product, wherein the shape of the exposed copper surface can also be varied according to the design requirements, thereby ensuring design flexibility.

[0041] In Fig. Figures 4A to 4H show a method for manufacturing the chip encapsulation structure E of the first embodiment of the present invention; however, the chip encapsulation structure E of the present invention is not limited to being manufactured by this method. The method for manufacturing the chip encapsulation structure comprises steps S110, S120, S130, S140, S150, S160, S170, and S180.

[0042] As in Fig. As shown in Figure 4A, step S110 consists of performing a copper coating process for a ceramic substrate, which includes providing a ceramic substrate 1 and producing a first copper layer 21 and a second copper layer 22 on the top of the ceramic substrate 1 with a first photoresist film df1 and a second photoresist film df2 successively by a photolithographic process.

[0043] The ceramic substrate 1 is formed on its inner side with at least one continuous copper column 1a and on its underside with an underside copper layer 1b, wherein the continuous copper column 1a is electrically connected to the first copper layer 21 and the underside copper layer 1b.

[0044] As in Fig. As shown in Figure 4B, step S120 consists of creating a third photoresist film df3 on the second photoresist film df2 and a defilming space df3' within the third photoresist film df3, the defilming space being located above the second copper layer 22.

[0045] As in Fig. As shown in Figure 4C, step S130 consists of creating a third copper layer 23 (e.g., by electroplating) on ​​the second copper layer 22, such that the first copper layer 21, the second copper layer 22, and the third copper layer 23 together form a copper structure 2. The side wall of the second copper layer 22 is recessed relative to both the side wall of the first copper layer 21 and the side wall of the third copper layer 23 to create a recess 2c on a side wall 2a of the copper structure 2. Furthermore, the projecting eaves structure of the side wall of the third copper layer 23, relative to the side wall of the second copper layer 22, contributes to increasing the exposed area of ​​the copper surface.

[0046] As in Fig. As shown in 4D, step S140 consists of creating a fourth photoresist film df4 on the third photoresist film df3 and a precious metal layer 3 within the fourth photoresist film df4, wherein the precious metal layer 3 is connected to the third copper layer 23 from above and only partially covers the top 2d of the third copper layer 23.

[0047] As in Fig. As shown in Figure 4E, step S150 consists of performing a photoresist film removal process to remove the first photoresist film df1, the second photoresist film df2, the third photoresist film df3 and the fourth photoresist film df4 from the ceramic substrate 1, thereby exposing the copper structure 2 (comprising the first copper layer 21, the second copper layer 22 and the third copper layer 23) and the precious metal layer 3 to the external environment.

[0048] As in Fig. As shown in Figure 4F, step S160 consists of performing a surface treatment process to create a surface treatment layer 2b on the exposed copper surface of the copper structure 2 that is not in contact with the ceramic substrate 1 and the precious metal layer 3.

[0049] In the present embodiment, the surface treatment layer 2b is formed on the side wall 2a of the copper structure 2, which is not in contact with the ceramic substrate 1 and the precious metal layer 3, and in certain areas on the top surface 2d, which is connected to the side wall 2a, and also extends over the inner surface of the recess 2c. In contrast, the top surface and the side wall of the precious metal layer 3 are not provided with the surface treatment layer 2b in order to increase the heterogeneous bonding of the copper surface without impairing the reliability of assembly on the precious metal surface.

[0050] It is worth mentioning that the surface treatment process carried out in step S160 can, for example, be a direct surface treatment of the exposed copper surface of the copper structure 2 without additional protection of the precious metal layer 3 in order to simplify the manufacturing process, but the present invention is not limited to this.

[0051] As in Fig. As shown in Figure 4G, step S170 consists of arranging a chip 3a on a side surface of the precious metal layer 3 facing away from the copper structure 2 and connecting at least one conductor 3b between the top of the chip 3a and the top of the precious metal layer 3.

[0052] As in Fig. As shown in Figure 4H, step S180 consists of performing an encapsulation process that includes generating an encapsulation adhesive 4 on the ceramic substrate 1. This adhesive serves to encapsulate the copper structure 2, the precious metal layer 3, the chip 3a, and the conductor 3b to form a chip encapsulation structure E. The encapsulation adhesive 4 is in contact with the surface treatment layer 2b and fills the recess 2c to engage with the copper structure 2, thereby improving the heterogeneous bond between the encapsulation adhesive 4 and the copper structure 2. [Second embodiment]

[0053] With reference to Fig. 5, Fig. 6 to Fig. Figure 7 of the second embodiment of the present invention also provides an encapsulation structure E' for chips that can be applied to chip encapsulation based on a copper pillar or an RDL stack. The purpose of the second embodiment of the present invention is to increase the exposed copper area on the surfaces and sidewalls and to enhance the heterogeneous bond of the encapsulation adhesive to the copper surface by creating a surface treatment layer on the exposed copper surface.

[0054] To achieve the above-mentioned purpose, the encapsulation structure E' of the second embodiment of the present invention comprises, as shown in Fig. 5 shown, a ceramic substrate 1', at least one copper structure 2', at least one precious metal layer 3', a chip 3a', at least one solder ball 3b' and an encapsulation adhesive 4'.

[0055] The copper structure 2' is formed on a side surface (e.g., the top surface) of the ceramic substrate 1'. The precious metal layer 3' is formed on a side surface (e.g., the top surface) of the copper structure 2' facing away from the ceramic substrate 1'. The chip 3a' is arranged on a side surface of the precious metal layer 3' facing away from the copper structure 2' by means of the solder ball 3b'. The encapsulating adhesive 4' is formed on the ceramic substrate 1' and serves to encapsulate the copper structure 2', the precious metal layer 3', the chip 3a', and the solder ball 3b'. Furthermore, at least one underside copper pad 1b' is formed on the underside of the ceramic substrate 1', but the present invention is not limited thereto.

[0056] What's next? Fig. As shown in Figure 5, a surface treatment layer 2b' is formed on the exposed copper surface of the copper structure 2', which is not in contact with the ceramic substrate 1' and the precious metal layer 3', wherein the encapsulation adhesive 4' is in contact with the surface treatment layer 2b' and thereby bonds with the copper structure 2' in order to strengthen the heterogeneous bond between the encapsulation adhesive 4' and the copper structure 2'.

[0057] In the present embodiment, the surface treatment layer 2b' is formed on at least one side wall 2a' of the copper structure 2' which is not in contact with the ceramic substrate 1' and the precious metal layer 3'.

[0058] The surface treatment layer 2b' can be, for example, one of the following: a roughened surface treatment layer, a functionalized surface treatment layer, and a chemically bonded surface treatment layer.

[0059] More precisely, in the present embodiment, the copper structure 2' is a supporting copper pillar 21' in the form of an elongated column, wherein the supporting copper pillar 21' is present in a plurality (i.e. multiple times).

[0060] The multiple supporting copper columns 21' are spaced apart and arranged upright on the ceramic substrate 1'. Corresponding to the number of supporting copper columns 21', the precious metal layer 3', the solder ball 3b', and the underside copper pad 1b' are each present in multiples (i.e., several times).

[0061] In other words, the multiple precious metal layers 3' are formed on the multiple supporting copper columns 21' and the multiple solder balls 3b' are formed on the multiple precious metal layers 3', wherein the chip 3a' is spaced apart on the ceramic substrate 1' by means of the multiple supporting copper columns 21', the multiple precious metal layers 3' and the multiple solder balls 3b'.

[0062] Furthermore, the multiple underside copper pads 1b' are arranged below the multiple supporting copper columns 21' in relation to the ceramic substrate 1' and are electrically connected to each other, but the present invention is not limited thereto.

[0063] In the present embodiment, the surface treatment layer 2b' is formed on the surface of the side walls 2a' of the several supporting copper columns 21', wherein the encapsulation adhesive 4' also fills the gap between the several supporting copper columns 21' and is in contact with the surface treatment layer 2b' in order to increase the contact area between the encapsulation adhesive 4' and the supporting copper columns 21' and thereby increase the heterogeneous bond between the encapsulation adhesive and the copper surfaces.

[0064] Furthermore, the Fig. Figure 6A shows a schematic view of the top of the encapsulation structure E' of the present embodiment, showing the manner in which the multiple supporting copper columns 21' are arranged, and the Fig. 6B a schematic view of the underside of the encapsulation structure E' of the present embodiment, showing the manner in which the multiple underside copper pads 1b' are arranged, to which, however, the present invention is not limited.

[0065] According to the above configuration, in the chip encapsulation structure E' of the second embodiment of the present invention, the heterogeneous bond between the encapsulation adhesive 4' and the copper structure 2' can be increased by forming a surface treatment layer 2b' on the exposed copper surface of the copper structure 2' which is not in contact with the ceramic substrate 1' and the precious metal layer 3', and by having the encapsulation adhesive 4' in contact with the surface treatment layer 2b' and thereby bonding with the copper structure 2'.

[0066] It will continue on Fig. Reference is made to Figure 7, which shows a schematic representation of a variant of the chip encapsulation structure E' of the second embodiment of the present invention. On the side wall 2a' of each of the supporting copper columns 21' of the chip encapsulation structure E' in Fig. 7 at least one recessed recess 2c' is formed, over whose inner surface the surface treatment layer 2b' also extends, wherein the encapsulation adhesive 4' also fills the recesses 2c' of the supporting copper columns 21' and is thereby in contact with the surface treatment layer 2b'.

[0067] By having the encapsulating adhesive 4' fill the recesses 2c, a structure can be created in which the encapsulating adhesive 4' and the supporting copper columns 21' interlock to increase the contact area between the encapsulating adhesive 4' and the copper structure 2' and thus improve the heterogeneous bond between the encapsulating adhesive 4' and the copper structure 2'. [Advantageous effects of the exemplary embodiments]

[0068] The advantageous effect of the present invention is that, in the chip encapsulation structure provided by the present invention, the heterogeneous bond between the encapsulation adhesive and the copper structure can be strengthened and the use of precious metal reduced by the design "on the exposed copper surface of the copper structure, which is not in contact with the ceramic substrate and the precious metal layer, a surface treatment layer is formed, wherein the encapsulation adhesive is in contact with the surface treatment layer and thereby bonds with the copper structure" and the design "a recess is formed on the side wall of the copper structure or the copper structure is formed as several supporting copper columns".

[0069] The above disclosures do not constitute a limitation of the scope of protection of the claims of the present invention, but merely serve to illustrate possible preferred embodiments of the present invention. Any equivalent modification that can be derived from the description or the drawings of the present invention therefore falls within the scope of protection of the claims of the present invention. Reference symbol list

[0070] [First embodiment] E encapsulation structure 1 ceramic substrate 1a Continuous copper column 1b Underside copper layer 2 Copper structure 21 First copper layer 22 Second copper layer 23 Third copper layer 2a Side wall 2b Surface treatment layer 2c Exclusion 2D Top 2e rounded corner edge 3 precious metal layer 3a Chip 3b Line 4 Encapsulation adhesive W1 First lead length W2 Second lead length df1 First photoresist film df2 Second photoresist film df3 Third photoresist film df3' De-filming room df4 Fourth photoresist film [Second embodiment] E' encapsulation structure 1' Ceramic substrate 1b' Underside copper pad 2' copper structure 21' Load-bearing copper column 2a' Side wall 2b' Surface treatment layer 2c' recess 3' precious metal layer 3a' Chip 3b' Plumb bob 4' Encapsulation adhesive

Claims

[1] Chip encapsulation structure (E), comprising: - a ceramic substrate (1); - a copper structure (2) formed on the ceramic substrate (1), wherein at least one side wall (2a) of the copper structure (2) has a recessed recess (2c); - a precious metal layer (3) formed on the copper structure (2); - a chip (3a) arranged on the precious metal layer (3); - an encapsulation adhesive (4) formed on the ceramic substrate (1) and encapsulating the copper structure (2), the precious metal layer (3) and the chip (3a); wherein a surface treatment layer (2b) is formed on the exposed copper surface of the copper structure (2) which is not in contact with the ceramic substrate (1) and the precious metal layer (3), wherein the encapsulation adhesive (4) is in contact with the surface treatment layer (2b) and thereby bonds with the copper structure (2); wherein the surface treatment layer (2b) extends over the inner surface of the recess (2c), while the encapsulation adhesive (4) also fills and engages in the recess (2c). [2] Chip encapsulation structure (E) according to claim 1, wherein the precious metal layer (3) is formed on the top side (2d) of the copper structure (2) and occupies an area that is smaller than the area of ​​the top side (2d) of the copper structure (2). [3] Chip encapsulation structure (E) according to claim 1 or 2, further comprising at least one conductor (3b) connected between the top surface (2d) of the chip (3a) and the top surface (2d) of the precious metal layer (3), wherein the surface treatment layer (2b) is formed on at least one side wall (2a) of the copper structure (2) that is not in contact with the ceramic substrate (1) and the precious metal layer (3) and in certain areas on a top surface (2d) connected with the side wall (2a), while the top surface (2d) of the precious metal layer (3) is not provided with the surface treatment layer (2b). [4] Chip encapsulation structure (E) according to any one of claims 1 to 3, wherein the copper structure (2) comprises a first copper layer (21), a second copper layer (22) and a third copper layer (23) formed successively on the ceramic substrate (1), wherein the side wall (2a) of the second copper layer (22) is recessed in relation to the side wall (2a) of the first copper layer (21) and the side wall (2a) of the third copper layer (23) to create the recess (2c). [5] Chip encapsulation structure (E) according to claim 4, wherein in the copper structure (2) the length over which the side wall (2a) of the third copper layer (23) projects relative to the side wall (2a) of the second copper layer (22) is defined as the first projection length (W1) and the length over which the side wall (2a) of the first copper layer (21) projects relative to the side wall (2a) of the second copper layer (22) is defined as the second projection length (W2), wherein the first projection length (W1) is less than the second projection length (W2). [6] Chip encapsulation structure (E) according to claim 4 or 5, wherein the first projection length (W1) is not greater than 50 micrometers. [7] Chip encapsulation structure (E) according to one of claims 4 to 6, wherein the four corner edges of the first copper layer (21) are each designed as a rounded corner edge (2e). [8] Chip encapsulation structure (E) according to any one of claims 1 to 7, wherein the surface treatment layer (2b) is a roughened surface treatment layer which has a greater surface roughness than the precious metal layer (3). [9] Chip encapsulation structure (E) according to any one of claims 1 to 8, wherein the surface treatment layer (2b) is a functionalized surface treatment layer which is a functionalized surface treatment layer with a functional silane group and / or a functional siloxane group. [10] Chip encapsulation structure (E) according to any one of claims 1 to 9, wherein the surface treatment layer (2b) is a chemically bonded surface treatment layer which is a copper oxide (CuO) surface treatment layer with an oxidized surface. [11] Chip encapsulation structure (E'), comprising: - a ceramic substrate (1'); - a copper structure (2') formed on the ceramic substrate (1'); - a precious metal layer (3') formed on the copper structure (2'); - a chip (3a') arranged on the precious metal layer (3'); - an encapsulation adhesive (4') formed on the ceramic substrate (1') that encapsulates the copper structure (2'), the precious metal layer (3') and the chip (3a'); wherein a surface treatment layer (2b') is formed on the exposed copper surface of the copper structure (2') which is not in contact with the ceramic substrate (1') and the precious metal layer (3'), wherein the encapsulation adhesive (4') is in contact with the surface treatment layer (2b') and thereby bonds with the copper structure (2'); wherein the copper structure (2') is a supporting copper pillar (21') in the form of an elongated column, which is present in plurality, wherein the multiple supporting copper pillars are spaced apart from each other and arranged upright on the ceramic substrate (1') and the encapsulating adhesive (4') fills the gap between the multiple supporting copper pillars (21'). [12] Chip encapsulation structure (E') according to claim 11, wherein the surface treatment layer (2b') is formed on the surface of the side wall (2a') of each of the supporting copper columns (21'). [13] Chip encapsulation structure (E') according to claim 11 or 12, wherein at least one recessed recess (2c') is formed on the side wall (2a') of each of the supporting copper columns (21'), over the inner surface of which the surface treatment layer (2b') extends, wherein the encapsulation adhesive (4') also fills the recesses.

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