SEMICONDUCTOR DEVICE

Abstract

A semiconductor device contains a semiconductor chip with a multitude of layers formed on a surface. These layers include a power supply wiring, to which a power supply voltage is applied; a ground wiring, to which a ground voltage is applied; MOS transistors connected to the power supply and ground wiring; and a trigger circuit, electrically connected to a gate electrode of the MOS transistor via a first wiring connection.The MOS transistors and the trigger circuit are formed in a first layer, the first wiring is formed in a second layer, which is an upper layer of the first layer, and the first wiring contains a first section extending in a first direction, and a second section extending in a second direction which intersects the first direction and is electrically connected to the first section.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The disclosure of Japanese Patent Application No. 2023-187662, filed on November 1, 2023, including the specification, drawings, and abstract, is incorporated herein by reference in its entirety. BACKGROUND

[0002] The present invention relates to a semiconductor device, for example a semiconductor device including an electrostatic discharge (ESD) protection circuit.

[0003] Techniques listed below are disclosed.

[0004] [Patent Document 1] US Patent No. 7,397,642

[0005] For example, Patent Document 1 discloses an ESD protection circuit. Patent Document 1 discloses an ESD protection circuit including a field-effect transistor (hereinafter also referred to as a MOS transistor) having a low withstand voltage. That is, Patent Document 1 discloses an ESD protection circuit having a configuration in which source-drain paths of two N-channel MOSFETs (hereinafter also referred to as NMOS transistors), each having a withstand voltage (3.3 V) lower than a power supply voltage (5 V) supplied to a main discharge wiring to which the ESD protection circuit is connected, are connected in series with the main discharge wiring. SUMMARY

[0006] As will be described later with reference to the drawings, as a result of studies conducted by the present inventors before the present invention, the present inventors have found a problem that, in a semiconductor device including an ESD protection circuit, sufficient wiring resources are not allocated to a wiring in the ESD protection circuit because a large number of wiring resources are allocated to a main discharge wiring connected to the ESD protection circuit, thereby deteriorating an ESD protection function.

[0007] Patent Document 1 does not pay attention to the main discharge wiring and the wiring in the ESD protection circuit, and the problem described above is not stated in Patent Document 1.

[0008] An outline of a typical example of the embodiments disclosed in the present application will be briefly described as follows.

[0009] That is, a semiconductor device according to one embodiment includes a semiconductor chip having a plurality of layers formed on a surface. Here, in the plurality of layers, a first power supply wiring to which a power supply voltage is supplied, a second power supply wiring to which a ground voltage is supplied, a MOS transistor connected to the first power supply wiring and the second power supply wiring and configured to electrically short-circuit the first power supply wiring and the second power supply wiring, and a trigger circuit electrically connected to a first gate electrode of the MOS transistor via a first wiring and configured to output a first control signal for controlling the first gate electrode are formed.the MOS transistor and the trigger circuit are formed in a first layer of the plurality of layers, the first wiring is formed in a second layer which is an upper layer of the first layer, and the first wiring includes a first portion extending in a first direction and a second portion extending in a second direction intersecting the first direction and electrically connected to the first portion.

[0010] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

[0011] According to one embodiment, it is possible to provide the semiconductor device capable of suppressing the deterioration of the ESD protection function. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram illustrating a configuration of a semiconductor device according to a first embodiment. Fig. 2 is a block diagram illustrating a configuration of an ESD protection circuit according to the first embodiment. Fig. 3 is a plan view illustrating a schematic layout of the ESD protection circuit according to the first embodiment. Fig. 4A is a diagram for describing a layer according to the first embodiment. Fig. 4B is a diagram for describing a layer according to the first embodiment. Fig. 4C is a diagram for describing a layer according to the first embodiment. Fig. 4D is a diagram for describing a layer according to the first embodiment. Fig. 4E is a diagram for describing a layer according to the first embodiment. Fig. 5 is a plan view illustrating a wiring layout in a dedicated wiring area according to the first embodiment. Fig. 6A is a diagram for describing a layer according to the first embodiment. Fig. 6B is a diagram for describing a layer according to the first embodiment. Fig. 6C is a diagram for describing a layer according to the first embodiment. Fig. 6D is a diagram for describing a layer according to the first embodiment. Fig. 6E is a diagram for describing a layer according to the first embodiment. Fig. 7 is a plan view illustrating a wiring layout in a dedicated wiring area according to the first embodiment. Fig. 8 is a plan view illustrating a layout of a power supply wiring and a ground wiring according to the first embodiment. Fig. 9A to Fig. 9C are diagrams for describing a discharge switch circuit according to the first embodiment. Fig. 10 is a block diagram illustrating a configuration of an ESD protection circuit according to a second embodiment. Fig. 11 is a plan view illustrating a layout of the ESD protection circuit according to the second embodiment, Fig. 12A and Fig. 12B are diagrams for describing an ESD protection circuit studied by the present inventors prior to the present invention. Fig. 13 is a plan view showing a schematic layout of the Fig. 12A illustrates the ESD protection circuit. DETAILED DESCRIPTION

[0012] Each embodiment of the invention will be described below with reference to the drawings. Otherwise, the disclosure is merely an example, and it is to be understood that any modifications readily conceivable by a person skilled in the art, if necessary, while retaining a gist of the invention are included in the invention.

[0013] Moreover, the same reference numerals are applied to the same elements as those described with reference to the above drawings in the present specification and the respective drawings, and detailed descriptions thereof are appropriately omitted in some cases. <Studien von den vorliegenden Erfindern>

[0014] First, the facts investigated by the present inventors will be described with reference to the drawings. Fig. 12A and Fig. 12B are diagrams for describing an ESD protection circuit studied by the present inventors prior to the present invention. Here, Fig. 12A is a block diagram illustrating a configuration of an ESD protection circuit ESDP, and Fig. Figure 12B is a characteristic diagram illustrating characteristics of the ESD protection circuit ESDP.

[0015] In addition, Fig. 13 is a plan view showing a schematic layout of the Fig. 12A and Fig. 12B. The ESD protection circuit ESDP is formed on a semiconductor chip CHP, which forms a semiconductor device. Although a plurality of circuit blocks including the ESD protection circuit ESDP are formed on the semiconductor chip CHP, Fig. 13 only the schematic layout of the ESD protection circuit ESDP formed on a part of the semiconductor chip CHP to avoid complicating the drawing.

[0016] In Fig. 12A, VCCQ indicates a power supply terminal to which a power supply voltage VCC is supplied, and VSSQ indicates a ground terminal to which a ground voltage VSS is supplied. A power supply wiring (hereinafter also referred to as the first power supply wiring) LVCC is connected to the power supply terminal VCCQ, and a ground wiring (hereinafter also referred to as the second power supply wiring) LVSS is connected to the ground terminal VSSQ. The ESD protection circuit ESDP is connected between the power supply wiring LVCC and the ground wiring LVSS. For example, when a steep high voltage is applied to the power supply terminal VCCQ, current flows through the power supply wiring LVCC, the ESD protection circuit ESDP, and the ground wiring LVSS (discharging is performed).This can prevent circuit blocks (not illustrated) such as a processing circuit connected between the power supply wiring LVCC and the ground wiring LVSS and operating using the power supply voltage VCC as an operating voltage from being destroyed by the steep high voltage.

[0017] The power supply wiring LVCC and the ground wiring LVSS serve as paths at the time of discharge and can thus be considered a single main discharge wiring (main discharge path). The main discharge wiring serves not only as a path at the time of discharge but also as a role for supplying the operating voltage to a large number of circuit blocks, and is thus configured to reduce wiring resistance by utilizing sufficient wiring resources.

[0018] The ESD protection circuit ESDP includes resistors R1 to R4, an NMOS switch circuit NMOS-SW1, time constant circuits (RC circuits) RC-1 and RC-2, inverter circuits INV-1 and INV-2, a discharge switch circuit B-NMOS and a blocking diode REV-D.

[0019] In Fig. Figure 12A shows wirings (internal wiring) in the ESD protection circuit, LINA to LINC, connecting circuits (including elements) that make up the ESD protection circuit ESDP. Resistor R1, NMOS switch circuit NMOS-SW1, time constant circuit RC-1, and inverter circuit INV-1 are connected in parallel between the power supply wiring LVCC and the internal wiring LINC. Additionally, resistor R2, time constant circuit RC-2, and inverter circuit INV-2 are connected in parallel between the internal wiring LINC and the ground wiring LVSS. Additionally, discharge switch circuit B-NMOS is connected between the power supply wiring LVCC and the ground wiring LVSS. The discharge switch circuit B-NMOS includes two NMOS transistors BN1 and BN2. Source-drain paths of the two NMOS transistors BN1 and BN2 are connected in series between the power supply wiring LVCC and the ground wiring LVSS.Further, an output of the inverter circuit INV-1 is supplied to a gate electrode of the NMOS transistor BN1 via the internal wiring LINA, and an output of the inverter circuit INV-2 is supplied to a gate electrode of the NMOS transistor BN2 via the internal wiring LINB.

[0020] For example, when a steep high voltage is applied to the power supply terminal VCCQ (when an ESD event occurs), this voltage increases the voltages of the internal wirings LINC, LINA, and LINB, and both NMOS transistors BN1 and BN2 turn on. As a result, current flows through the B-NMOS discharge switch circuit in the ESD protection circuit ESDP, and the circuit blocks (not shown) connected to the power supply wiring LVCC are protected from the high voltage.

[0021] When viewed from a top view, the circuits (NMOS-SW1, RC-1, RC-2, INV-1, INV-2, B-NMOS and REV-D) forming the ESD protection circuit ESDP are densely arranged on the semiconductor chip, as shown in Fig. 13 illustrates this. Since the wiring resources constituting the internal wirings LINA to LINC of the ESD protection circuit ESDP are smaller than the wiring resources constituting the main discharge wiring, the wiring resistance of the internal wirings LINA to LINC is high. When the wiring resistance of the internal wirings LINA to LINC is high, when a steep high voltage is applied, the gate electrode voltages of the NMOS transistors BN1 and BN2 cannot be sufficiently increased, thus degrading the protection function of the ESD protection circuit ESDP.

[0022] In Fig. In Figure 12B, "V" on the horizontal axis represents a voltage applied to the ESD protection circuit ESDP, that is, a voltage applied to the power supply terminal VCCQ with the ground terminal VSSQ as a reference, and "I" on the vertical axis represents the current flowing through the ESD protection circuit ESDP. The main current flowing through the ESD protection circuit ESDP is the current flowing between a source and a drain of each of the NMOS transistors BN1 and BN2 constituting the B-NMOS discharge switch circuit. When a high voltage VOV is applied to the power supply terminal VCCQ, the current I begins to flow, as shown in Fig. 12B illustrates this. In a case where the wiring resistance of the internal wirings LINA to LINC is high (reference symbol RH), the flowing current I decreases compared to a case where the wiring resistance is low (reference symbol RL). As the flowing current I decreases, the protection function by the ESD protection circuit ESDP deteriorates.

[0023] According to embodiments described below, it is possible to suppress the deterioration of the ESD protection function. (First embodiment)<Konfiguration einer Halbleitervorrichtung>

[0024] Fig. 1 is a block diagram illustrating a configuration of a semiconductor device according to a first embodiment. In Fig. In FIG. 1, a portion CHP illustrated in a dashed line indicates a semiconductor chip constituting the semiconductor device. Although not particularly limited, various circuit blocks are formed on the semiconductor chip CHP by a well-known semiconductor manufacturing technique. The semiconductor device is configured by sealing the semiconductor chip CHP with a package, for example. Terminals (a power supply terminal, a ground terminal, an input / output terminal, and the like) of the circuit blocks formed in the semiconductor chip CHP are connected to an exposed terminal (not illustrated) of the semiconductor device.

[0025] Although various circuit blocks are formed in the semiconductor chip CHP as described above, in Fig. 1 only illustrates circuit blocks necessary for the description to avoid complicating the drawing.

[0026] In Fig. 1 shows two circuit blocks (cells) as typical examples. That is, Fig. Figure 1 illustrates a power supply cell PW_CL and a signal cell IO_CL connected to a common power supply wiring LVCC and a ground wiring LVSS. Here, the power supply cell PW_CL corresponds to an ESD protection circuit, and the signal cell IO_CL corresponds to a protected circuit that is protected by the ESD protection circuit PW_CL when an ESD event occurs. Of course, the protected circuit is not limited to the signal cell IO_CL and can be any circuit block connected to the same power supply wiring LVCC and ground wiring LVSS as the power supply cell PW_CL. In addition, the number of protected circuits is not limited to one, and the power supply cell PW_CL common to a plurality of protected circuits can be provided.

[0027] In Fig. 1, the reference symbols VCCQ and VSSQ are the same as those in Fig. 12A and Fig. 12B and indicate the power supply terminal and the ground terminal, which are connected to the power supply wiring and the ground wiring.

[0028] The power supply cell PW_CL (ESD protection circuit ESDP) includes a trigger circuit TGC, a discharge switch circuit B-NMOS, and a blocking diode REV-D, which are connected in parallel between the power supply wiring LVCC and the ground wiring LVSS. The discharge switch circuit B-NMOS is connected to the trigger circuit TGC via internal wirings LINA and LINB and is controlled by the trigger circuit TGC. Although the discharge switch circuit B-NMOS and the trigger circuit TGC will be described later with reference to the drawings, for example, when a steep high voltage is applied to the power supply terminal VCCQ, the trigger circuit TGC controls the discharge switch circuit B-NMOS to turn on, so that the power supply wiring LVCC and the ground wiring LVSS are short-circuited by the discharge switch circuit B-NMOS to perform discharge.

[0029] The blocking diode REV-D has an anode connected to the ground wiring LVSS and a cathode connected to the power supply wiring LVCC, and performs discharging from the ground wiring LVSS toward the power supply wiring LVCC, for example, when a steep high voltage is applied to the ground terminal VSSQ, thereby providing protection.

[0030] Although not specifically limited, the signal cell IO_CL includes an input / output terminal IO, protection diodes PD and ND, and a signal processing circuit SPC. The signal processing circuit SPC and the series-connected protection diodes PD and ND are connected in parallel between the power supply wiring LVCC and the ground wiring LVSS. The signal processing circuit SPC performs a predetermined operation using a power supply voltage VCC as an operating voltage. For example, when the input / output terminal IO is an input terminal, a signal supplied to the input / output terminal is input to the signal processing circuit SPC, and the signal processing circuit SPC performs a predetermined operation on the input signal and outputs a signal OUT. The output signal OUT is supplied to another circuit block (not illustrated) and processed by the other circuit block.

[0031] The protection diode PD has an anode connected to an input node SPC_I of the signal processing circuit SPC, which is connected to the input / output terminal IO, and a cathode connected to the power supply wiring LVCC. In addition, the protection diode ND has a cathode connected to the input node SPC_I and an anode connected to the ground wiring LVSS. The protection diodes PD and ND work to discharge current between the input / output terminal IO and the power supply wiring LVCC or the ground wiring LVSS when a high voltage or a negative voltage is applied to the input / output terminal IO, and function to prevent the signal processing circuit SPC from being destroyed by the high voltage or the negative voltage. <Konfiguration einer ESD-Schutzschaltung (Auslöserschaltung und Entladungsschalterschaltung)>

[0032] Next, configurations of the trigger circuit TGC and the discharge switch circuit B-NMOS used in Fig. 1 are described with reference to the drawings.

[0033] Fig. Fig. 2 is a block diagram illustrating a configuration of the ESD protection circuit according to the first embodiment. Here, the ESD protection circuit is provided with a configuration similar to that shown in Fig. 12A is described as an example, but the invention is not limited thereto. < <entladungsschalterschaltung>>

[0034] In the ESD protection circuit ESDP (power supply cell PW_CL), the discharge switch circuit B-NMOS includes two NMOS transistors BN1 and BN2, whose source-drain paths are connected in series between the power supply wiring LVCC and the ground wiring LVSS. Incidentally, back-gate electrodes of the NMOS transistors BN1 and BN2 are connected to the ground wiring LVSS. Here, an example in which the discharge switch circuit B-NMOS includes the two NMOS transistors connected in series will be described, but the invention is not limited to this. For example, the discharge switch circuit B-NMOS may include one MOS transistor or may include three or more MOS transistors as described in a second embodiment. <<Auslöserschaltung> >

[0035] In the ESD protection circuit ESDP, the trigger circuit TGC includes resistors R1 to R4, an NMOS switch circuit NMOS-SW1, time constant circuits RC-1 and RC-2, inverter circuits INV-1 and INV-2, and internal wiring LINC. In addition, the trigger circuit TGC and gate electrodes of the NMOS transistors BN1 and BN2, which constitute the discharge switch circuit B-NMOS, are connected by the internal wirings LINA and LINB, and the like. The trigger circuit TGC supplies a first control signal for controlling the NMOS transistors BN1 and BN2 to the gate electrodes (corresponding to a first gate electrode) of the NMOS transistors BN1 and BN2.

[0036] In a case where the discharge switch circuit B-NMOS is considered to be formed of two-stage NMOS transistors, the trigger circuit TGC can also be considered to be formed of two stages. That is, the time constant circuit RC-1 and the inverter circuit INV-1 can be considered to form a stage corresponding to the NMOS transistor BN1, and the time constant circuit RC-2 and the inverter circuit INV-2 can be considered to form a stage corresponding to the NMOS transistor BN2. In this case, the NMOS switch circuit NMOS-SW1 can be considered to form the stage corresponding to the NMOS transistor BN1 or to be provided commonly for the two stages. In this case, the internal wirings LINA and LINB can be considered to be wirings connecting the corresponding stages.

[0037] Resistors R1 and R2 are connected in series between the power supply wiring (LVCC) and the ground wiring (LVSS). The internal wiring (LINC) is connected to a connection node that connects resistors R1 and R2.

[0038] The NMOS switch circuit NMOS-SW1 and the time constant circuit RC-1 are connected in parallel between the power supply wiring LVCC and the internal wiring LINC.

[0039] In addition, the inverter circuit INV-1 is also connected between the power supply wiring LVCC and the internal wiring LINC. The inverter circuit INV-1 operates by using a voltage difference between the power supply wiring LVCC and the internal wiring LINC as an operating voltage. That is, the source-drain paths of a P-channel MOS transistor (hereinafter also referred to as a PMOS transistor) P1 and an NMOS transistor N1, which constitute the inverter circuit INV-1, are connected in series between the power supply wiring LVCC and the internal wiring LINC.

[0040] An output signal OUT_1 of the time constant circuit RC-1 is supplied to the gate electrodes of the PMOS transistor P1 and the NMOS transistor N1, which form the inverter circuit INV-1. Additionally, a connection node connecting a drain of the PMOS transistor P1 and a drain of the NMOS transistor N1 is connected to the internal wiring LINA, and the internal wiring LINA is connected to the gate electrode of the NMOS transistor BN1. Furthermore, a resistor R3 is connected between the internal wiring LINA and the internal wiring LINC.

[0041] The time constant circuit RC-2 is connected between the internal wiring LINC and the ground wiring LVSS. Additionally, the inverter circuit INV-2 is connected between the internal wiring LINC and the ground wiring LVSS. The inverter circuit INV-2 operates using a voltage difference between the internal wiring LINC and the ground wiring LVSS as an operating voltage. That is, the source-drain paths of a PMOS transistor P2 and an NMOS transistor N2, which form the inverter circuit INV-2, are connected in series between the internal wiring LINC and the ground wiring LVSS.

[0042] An output signal OUT_2 of the time constant circuit RC-2 is supplied to the gate electrodes of the PMOS transistor P2 and the NMOS transistor N2, which form the inverter circuit INV-2. Additionally, a connection node connecting a drain of the PMOS transistor P2 and a drain of the NMOS transistor N2 is connected to the internal wiring LINB, and the internal wiring LINB is connected to the gate electrode of the NMOS transistor BN2. Furthermore, a resistor R4 is connected between the internal wiring LINB and the ground wiring LVSS.

[0043] Although not particularly limited, the NMOS switch circuit NMOS-SW1 includes an NMOS transistor N3 with a source-drain path connected between the power supply wiring LVCC and the internal wiring LINC. When a steep high voltage is applied to the power supply terminal VCCQ, the NMOS transistor N3 becomes conductive, and the NMOS switch circuit NMOS-SW1 increases a voltage of the internal wiring LINC toward a voltage on the power supply wiring LVCC.

[0044] The time constant circuit RC-1 includes a capacitive element. Although not particularly limited, the capacitive element includes an NMOS transistor N4 with a source and drain connected to each other. When a steep high voltage is applied to the power supply terminal VCCQ, the capacitive element (NMOS transistor N4) is charged (including discharged) in the time constant circuit RC-1. The time constant circuit RC-1 sets the output signal OUT_1 to a low level (internal wiring voltage LINC) and then sets the output signal OUT_1 to a high level (power supply wiring voltage LVCC) during a period in which the capacitive element is charged.That is, the time constant circuit RC-1 sets the output signal OUT_1 to the low level for a time determined by the capacitive element when a steep high voltage is applied to the power supply terminal VCCQ.

[0045] The time constant circuit RC-2 is configured similarly to the time constant circuit RC-1, and when a steep high voltage is applied to the power supply terminal VCCQ and the voltage of the internal wiring LINC increases, the time constant circuit RC-1 sets the output signal OUT_2 to the low level and then sets the output signal OUT_2 to the high level for a time determined by a capacitive element (not illustrated) included in the time constant circuit RC-2, similarly to the time constant circuit RC-2.

[0046] In response to the output signal OUT_1 of the time constant circuit RC-1, the inverter circuit INV-1 supplies the voltage (high level) of the power supply wiring LVCC or the voltage (low level) of the internal wiring LINC to the internal wiring LINA. This voltage propagates through the internal wiring LINA and is supplied to the gate electrode of the NMOS transistor BN1. Similarly, in response to the output signal OUT_2 of the time constant circuit RC-2, the inverter circuit INV-2 supplies the voltage (high level) of the internal wiring LINC or the voltage (low level) of the ground wiring to the internal wiring LINB. This voltage propagates through the internal wiring LINB and is supplied to the gate electrode of the NMOS transistor BN2.

[0047] When a steep high voltage is applied to the power supply terminal VCCQ, each of the output signals OUT_1 and OUT_2 is set to the low level for the time determined by the capacitive element, and the inverter circuits INV-1 and INV-2 supply the high level to the internal wiring LINA and LINB, respectively. As a result, when a steep high voltage is applied to the power supply terminal VCCQ, both of the NMOS transistors BN1 and BN2 are in a conductive state, and the high voltage is discharged through the power supply wiring LVCC, the discharge switch circuit B-NMOS, and the ground wiring LVSS, and it can prevent, for example, the Fig. 1 illustrated signal cell IO_CL is destroyed by the high voltage.

[0048] Note that in a state where no steep high voltage is applied to the power supply terminal VCCQ, that is, in a state where the power supply voltage VCC is supplied, the power supply voltage VCC is divided by the resistors R1 and R2, and a voltage (divided voltage) obtained by the division is applied to the internal wiring LINC. In this state, the NMOS transistor N3 in the NMOS switch circuit NMOS-SW1 is in a non-conductive state. In this state, the capacitive elements in the time constant circuits RC-1 and RC-2 are charged, and the output signals OUT_1 and OUT_2 are set to the high level. As a result, the NMOS transistors BN1 and BN2 constituting the discharge switch circuit B-NMOS are turned off, and the discharge by the ESD protection circuit ESDP is not performed.Incidentally, the resistors R3 and R4 are configured to reliably make the NMOS transistors BN1 and BN2 non-conductive in the state where the power supply voltage VCC is supplied to the power supply terminal VCCQ. <Layout der ESD-Schutzschaltung>

[0049] Fig. 3 is a plan view illustrating a schematic layout of the ESD protection circuit according to the first embodiment. As described with reference to Fig. 13, the ESD protection circuit ESDP is formed on the semiconductor chip CHP constituting the semiconductor device. Fig. 3 also illustrates only the schematic layout of the ESD protection circuit ESDP formed on a part of the semiconductor chip CHP to avoid complicating the drawing, although a plurality of circuit blocks (for example, the signal cell IO_CL in Fig. 1 and the like) including the ESD protection circuit ESDP are formed on the semiconductor chip CHP, which is illustrated in a dashed line.

[0050] In the following description regarding the layout, the horizontal direction in the drawings is an X direction (first direction) and a direction that intersects the X direction, i.e., the vertical direction in the drawings is a Y direction (second direction). In the drawings relating to the layout, the Fig. 3, the X direction and the Y direction are represented by arrows, which are designated by the reference symbols X and Y, respectively.

[0051] The layout of the ESD protection circuit ESDP according to the first embodiment is different from the layout of the ESD protection circuit shown in Fig. 13 is a plan view in which the main surface of the semiconductor chip CHP is viewed from above. That is, the layout of the ESD protection circuit according to the first embodiment is provided with dedicated wiring areas (dedicated wiring spaces) in which the internal wirings (for example, LINA to LINC of Fig. 2) The ESD protection circuit (ESDP) is arranged. Wires connecting the circuits forming the ESD protection circuit are bundled together by the internal wiring arranged in the dedicated wiring areas, making it possible to reduce the wiring resistance of the wiring connecting the circuits and suppress the deterioration of the ESD protection function.

[0052] In Fig. 3, the dedicated wiring areas are designated by reference symbols EXLSP-11 and EXLSP-21. The layout of the ESD protection circuit ESDP is described in detail as follows.

[0053] In Fig. 3, the discharge switch circuit B-NMOS, the blocking diode REV-D, the inverter circuits INV-2 and INV-1, the time constant circuits RC-2 and RC-1, and the NMOS switch circuit NMOS-SW1 are arranged in this order in the Y direction from the bottom to the top of the paper surface. In this case, the inverter circuit INV-2 and the inverter circuit INV-1 are arranged in this order in the X direction horizontally from the left side of the paper surface of Fig. 3, and similarly, the time constant circuits RC-2 and RC-1 are arranged horizontally in this order from the left side to the paper surface side.

[0054] As in Fig. As shown in Figure 3, the dedicated wiring area EXLSP-11 is arranged above the time constant circuits RC-2 and RC-1 and is partially arranged between the time constant circuit RC-2 and the NMOS switch circuit NMOS-SW1. Additionally, the dedicated wiring area EXLSP-21 is arranged between the inverter circuits INV-2 and INV-1 and the blocking diode REV-D, as shown in Fig. 3 shown.

[0055] Although described later, a plurality of wirings are arranged in the dedicated wiring area EXLSP-11, and the plurality of wirings are electrically connected to a wiring of the NMOS switch circuit NMOS-SW1, a wiring of the time constant circuit RC-2, a wiring of the time constant circuit RC-1, a wiring of the inverter circuit INV-2, and a wiring of the inverter circuit INV-1. It can be considered that the plurality of wirings arranged in the dedicated wiring area EXLSP-11 constitute the internal wiring LINC, which is Fig. 2 is shown.

[0056] Although described later, two wirings, each containing a plurality of wirings, are arranged in the dedicated wiring area EXLSP-21. Fig. 3, the two wirings are distinguished by a solid line and a dashed line. One wiring (dashed line) is electrically connected to the wiring of the inverter circuit INV-1 and the discharge switch circuit B-NMOS, and the other wiring (solid line) is electrically connected to the wiring of the inverter circuit INV-2 and the discharge switch circuit B-NMOS. It can be considered that dashed wirings and solid wirings arranged in the dedicated wiring area EXLSP-21 represent the internal wiring LINA located in Fig. 2, or form the internal wiring LINB, which is shown in Fig. 2 is shown.

[0057] Furthermore, the resistors R1 to R4, which are Fig. 2 are shown in Fig. 3 omitted. Similarly, resistors corresponding to resistors R1 to R4 are omitted in the following drawings related to the layout. <Halbleiterschicht und Verdrahtungsschicht>

[0058] Elements such as a MOS transistor and internal wiring (including LINA to LINC and the wirings connecting circuits) constituting the ESD protection circuit ESDP, the power supply wiring LVCC, the ground wiring LVSS, and the like are formed from a plurality of layers (including a semiconductor layer such as a diffusion region and a wiring layer) formed on the surface of the semiconductor chip CHP.

[0059] For example, in the case of the MOS transistor, a diffusion region forming a source region, a drain region, and the like, and a gate electrode provided with a gate insulating film therebetween are formed on the surface of the semiconductor chip CHP, thereby constituting the MOS transistor. In the present specification, the description is given assuming that the diffusion region forming the source region and the drain region, and the gate electrode arranged with the gate insulating film therebetween correspond to a layer (hereinafter also referred to as a diffusion layer or a first layer) formed on the surface of the semiconductor chip CHP.

[0060] In the first embodiment, a plurality of wiring layers are formed on the diffusion layer with the surface of the semiconductor chip CHP as a reference. Each of the wiring layers is a conductive metal layer, and, for example, fourteen wiring layers (metal wiring layers, hereinafter also referred to as metal layers) are formed over the diffusion layer. In this case, an insulating layer for electrical insulation is formed between the diffusion layer and a metal layer (hereinafter also referred to as a first metal layer) closest to the diffusion layer, and between metal layers closest to each other in an upper layer of the first metal layer.To form a desired circuit block, a contact hole is formed in the insulating layer between the diffusion layer and the first metal layer, and the diffusion layer and a first-layer wiring formed using the first metal layer are electrically connected via the contact hole. In addition, the insulating layer between the metal layers is also opened as needed, and wirings formed using the metal layers are electrically connected through a through hole.

[0061] The following description is given with reference to the drawings. The ESD protection circuit ESDP used in Fig. 3, will be described separately for an area including the dedicated wiring area EXLSP-21 and an area including the dedicated wiring area EXLSP-11. <<Bereich inklusive dediziertem Verdrahtungsbereich EXLSP-21> >

[0062] Fig. 4A to Fig. 4E are diagrams for describing layers according to the first embodiment. Fig. 4A to Fig. 4E schematically illustrate sections corresponding to the inverter circuits INV-1 and INV-2, the dedicated wiring area EXLSP-21, the blocking diode REV-D and the discharge switch circuit B-NMOS in the layout of the ESD protection circuit EDSP shown in Fig. 3. Here, Fig. 4A shows a diffusion layer formed on the semiconductor chip CHP, Fig. 4B illustrates a first metal layer formed on the diffusion layer, and Fig. 4C illustrates a second metal layer formed on the diffusion layer and closest to the first metal layer. Fig. 4D illustrates an example of a third metal layer to a twelfth metal layer, which are upper layers of the second metal layer, and Fig. 4E illustrates a thirteenth metal layer and a fourteenth metal layer, which are upper layers of the twelfth metal layer. Although not particularly limited, the thirteenth metal layer and the fourteenth metal layer are used to supply the power supply voltage VCC and the ground voltage, and the first metal layer to the twelfth metal layer are used to connect elements and circuits or the like. In the present specification, with respect to the diffusion layer (first layer), the first metal layer to the twelfth metal layer, which are upper layers of the diffusion layer, are hereinafter also referred to as a second layer.

[0063] In Fig. 4A, solid lines D-AR indicate diffusion regions formed on the surface of the semiconductor chip CHP, and solid lines G-AR indicate gate electrodes formed on the surface of the semiconductor chip CHP with the gate insulating film interposed therebetween. The MOS transistors constituting the inverter circuits INV-1 and INV-2 and the discharge switch circuit B-NMOS include the diffusion region D-AR and the gate electrode G-AR. In addition, the blocking diode REV-D also includes the diffusion region D-AR. Incidentally, in Fig. 4A Diffusion regions of different conductivity types are also shown as identical for the sake of schematic representation.

[0064] In Fig. 4A, an area surrounded by a dashed line indicates the dedicated wiring area EXLSP-21, which is located in Fig. 3. In the first embodiment, the elements constituting the ESD protection circuit ESDP are not formed in the dedicated wiring area EXLSP-21. That is, in Fig. 4A, a portion of the dedicated wiring area EXLSP-21 corresponds to the surface of the semiconductor chip CHP.

[0065] In Fig. 4B shows M1 first-layer wirings formed using the first metal layer formed on the diffusion layer formed on the semiconductor chip CHP with the insulating layer (not shown) interposed therebetween. In addition, Fig. 4B M1-E shows first-layer wirings formed using the first metal layer formed on the dedicated wiring region EXLSP-21 in the semiconductor chip CHP, with the insulating layer (not shown) interposed therebetween. Since the diffusion region D-AR and the gate electrode G-AR are not formed in the dedicated wiring region EXLSP-21, as shown in Fig. 4A, the wirings of the first layer M1-E are formed on the surface of the semiconductor chip CHP with the insulating layer (not shown) interposed therebetween.

[0066] In Fig. 4C shows M2 second-layer wirings formed using the second metal layer made of metal and formed on the first metal layer formed on the semiconductor chip CHP with the insulating layer (not shown) interposed therebetween. Furthermore, FIG. Fig. 4C M2-E shows second layer wirings formed using the second metal layer made of metal and formed on the first metal layer with the insulating layer (not shown) interposed therebetween in the dedicated wiring region EXLSP-21.

[0067] As in Fig. 4B, the wirings of the first layer M1 are basically formed so that they extend in the Y direction and are arranged side by side in the X direction. On the other hand, as shown in Fig. 4C, the wirings of the second layer M2 are formed so that they extend in principle in the X direction and are arranged side by side in the Y direction. As a result, elements such as the MOS transistors can be connected to form the inverter circuits INV-1 and INV-2 and the discharge switch circuit B-NMOS using the wirings of the first layer M1 and the wirings of the second layer M2. For example, the inverter circuit INV-1 can be formed by connecting the diffusion regions, the source regions, and the drain regions of the MOS transistors ( Fig. 2, for example N1 and P1) are to be achieved by the wiring of the first layer M1 and the wiring of the second layer M2 via openings in the insulating layer.

[0068] As in Fig. 4B, in the dedicated wiring area EXLSP-21, the wirings of the first layer M1-E are formed to extend in the X direction and to be arranged side by side in the Y direction. In addition, as shown in Fig. 4C, the wirings of the second layer M2-E are also formed to extend in the X direction and to be juxtaposed in the Y direction. As described later with reference to the drawings, openings are provided in the insulating layer between the wirings of the first layer M1-E and the wirings of the second layer M2-E, and the wirings of the first layer M1-E and the wirings of the second layer M2-E are electrically connected by through holes.

[0069] A plurality of metal layers (in the first embodiment, the third metal layer to the twelfth metal layer) are formed over the second layer wirings formed using the second metal layer shown in Fig. 4C is shown. Fig. 4D illustrates, as an example, third-layer wirings formed using the third metal layer below these metal layers. Fig. 4D, M3 indicates the third-layer wirings, and the third-layer wirings M3 are formed to extend in the Y direction and are arranged side by side in the X direction.

[0070] In the first embodiment, a plurality of circuits formed using the diffusion layer, the first metal layer, and the second metal layer are connected through the third-layer wirings to the twelfth-layer wirings formed using the third metal layer to the twelfth-layer metal layer.For example, as described above, the inverter circuit INV-1 is achieved by connecting elements through the first-layer wirings M1 formed using the first metal layer and the second-layer wirings M2 formed using the second metal layer, and the electrical connection between the inverter circuit INV-1 and the discharge switch circuit B-NMOS is achieved through the third-layer to twelfth-layer wirings formed using the third-layer to twelfth-layer wirings and wirings arranged in the dedicated wiring region EXLSP-21. Here, the connection between the inverter circuit INV-1 and the discharge switch circuit B-NMOS was described as an example, but the same applies to the connection between the inverter circuit INV-2 and the discharge switch circuit B-NMOS.

[0071] The thirteenth metal layer and the fourteenth metal layer are formed over the twelfth metal layer. Fig. 4E illustrates the thirteenth metal layer and the fourteenth metal layer formed over the twelfth metal layer on the surface of the semiconductor chip CHP. In Fig. 4E, dashed lines M13 indicate thirteenth-layer wirings formed using the thirteenth metal layer, and solid lines M14 indicate fourteenth-layer wirings formed using the fourteenth metal layer. Although not particularly limited, the thirteenth-layer wirings M13 are formed to extend in the X direction and are arranged side by side in the Y direction, and the fourteenth-layer wirings M14 are arranged to extend in the Y direction and are arranged side by side in the X direction.

[0072] In the first embodiment, some thirteenth-layer wirings M13 among the plurality of thirteenth-layer wirings M13 formed using the thirteenth metal layer and some fourteenth-layer wirings M14 among the plurality of fourteenth-layer wirings M14 formed using the fourteenth metal layer are electrically connected to form the power supply wiring LVCC. In addition, the other thirteenth-layer wirings M13 among the plurality of thirteenth-layer wirings M13 and the other fourteenth-layer wirings M14 among the plurality of fourteenth-layer wirings M14 are electrically connected to form the ground wiring LVSS.

[0073] The connection between a circuit (for example, the inverter circuit INV-1) constituting the ESD protection circuit ESDP and the power supply wiring LVCC is achieved by connecting the inverter circuit INV-1 and the thirteenth-layer wirings M13 and the fourteenth-layer wirings M14 constituting the power supply wiring LVCC using the third-layer wirings M3 to the twelfth-layer wirings M12. Similarly, the connection between the inverter circuit INV-1 and the ground wiring LVSS is also achieved by connecting the inverter circuit INV-1 and the thirteenth-layer wirings M13 and the fourteenth-layer wirings M14 constituting the ground wiring LVSS using the third-layer wirings M3 to the twelfth-layer wirings M12. <<Verdrahtungslayout in dediziertem Verdrahtungsbereich> >

[0074] Next, a detailed layout of the EXLSP-21 dedicated wiring area is described with reference to the drawings. Fig. 5 is a plan view illustrating a wiring layout in the dedicated wiring area according to the first embodiment. As shown in Fig. As shown in Figure 3, the internal wirings LINA and LINB are arranged in the dedicated wiring area EXLSP-21, and the inverter circuits INV-1 and INV-2 and the gate electrodes of the NMOS transistors BN1 and BN2 of the discharge switch circuit B-NMOS are connected using the internal wirings LINA and LINB. Fig. 5, the first-layer wirings M1 and M1-E formed using the first metal layer are shown in dashed lines, and the second-layer wirings M2 and M2-E formed using the second metal layer and the third-layer wirings M3 formed using the third metal layer are shown in solid lines. Fig. 5 indicates bra through holes.

[0075] Although not particularly limited, in the first embodiment, the internal wiring LINA is formed by six wirings LINA_1 to LINA_6, and the internal wiring LINB is also formed by six wirings LINB_1 to LINB_6.

[0076] Each of the wirings LINA_1 to LINA_6 and LINB_1 to LINB_6 is formed by the first layer wiring M1-E formed of the first metal layer and the second layer wiring M2-E formed of the second metal layer. That is, as shown in Fig. 5, when viewed in a plan view, the wiring of the first layer M1-E and the wiring of the second layer M2-E are formed to overlap each other, and the wiring of the first layer M1-E and the wiring of the second layer M2-E are electrically connected through the through hole BH shown in a dashed line. Although the wiring of the first layer M1-E is drawn larger than the wiring of the second layer M2-E, so that the wirings in Fig. 5 can be easily distinguished, the invention is not limited thereto.

[0077] In Fig. 5, the first-layer wirings M1 arranged along the Y direction outside the dedicated wiring area EXLSP-21 indicate the first-layer wirings of the inverter circuits INV-1 and INV-2. Fig. 5, the three wirings of the first layer M1, represented by the reference symbol INV-1 in parentheses, are connected to the drain region of the PMOS transistor P1 and the drain region of the NMOS transistor N1, as described with reference to Fig. 2. Similarly, the three wirings of the first layer M1, represented by the reference symbol INV-2 in parentheses, are connected to a drain region of the PMOS transistor P2 and a drain region of the NMOS transistor N2, as described with reference to Fig. 2 described.

[0078] Although not particularly limited, the first-layer wirings M1 of the inverter circuit INV-1 are connected to the third-layer wirings M3-A formed of the third metal layer through the circled through holes BH, and the third-layer wirings M3-A are connected to the first-layer wiring M1-E and the second-layer wiring M2_E constituting each of the internal wirings LINA_1 to LINA_6 through the through holes BH. In addition, the third-layer wirings M3-A are connected to the gate electrode of the NMOS transistor BN1 constituting the discharge switch circuit B-NMOS.

[0079] Similarly, the first-layer wirings M1 of the inverter circuit INV-2 are connected to the third-layer wirings M3-B formed of the third metal layer through the through holes BH, and the third-layer wirings M3-B are connected to the first-layer wiring M1-E and the second-layer wiring M2_E, which form each of the internal wirings LINB_1 to LINB_6, through the through holes BH. The third-layer wirings M3-B are connected to the gate electrode of the NMOS transistor BN2, which forms the discharge switch circuit B-NMOS.

[0080] Wirings (hereinafter also referred to as a first wiring and a third wiring) connecting the inverter circuits INV-1 and INV-2 and the discharge switch circuit B-NMOS, that is, the first wiring and the third wiring connecting the trigger circuit TGC and the discharge switch circuit B-NMOS shown in Fig. 1, the internal wirings (a first portion) include LINA and LINB extending in the X direction, and the third layer wirings (a second portion) include M3-A and M3-B extending in the Y direction intersecting the X direction. In this case, the plurality of (three in Fig. 5) Third-layer wirings M3-A (M3-B) are electrically connected to be bundled by the plurality of internal wirings LINA_1 to LINA_6 (LINB_1 to LINB_6). Therefore, a combined resistance value of the third-layer wirings M3-A (M3-B) is equal to or lower than a resistance value of the internal wiring LINA (LINB). In addition, the first-layer wiring M1-E and the second-layer wiring M2-E are also electrically connected in parallel in the internal wiring LINA (LINB) used to bundle the third-layer wirings M3-A (M3-B). A combined resistance value of the internal wiring LINA (LINB) can be reduced, and the third-layer wirings M3-A (M3-B) can be bundled by a wiring with a low resistance value.

[0081] Fig. 5 illustrates an example in which the third-layer wiring formed using the third metal layer is used as the wiring connecting the inverter circuits INV-1 and INV-2, the internal wiring (LINA, LINB), and the discharge switch circuit B-NMOS, but the invention is not limited to this, and any of the fourth-layer wiring to the twelfth-layer wiring may be used. In addition, the number of wirings constituting each of the internal wirings LINA and LINB is not limited to six, and may be, for example, one. Further, for example, the inverter circuit and the internal wiring, and the internal wiring and the discharge switch circuit may be connected by mutually different third-layer wirings M3-A (M3-B).

[0082] Fig. 5 illustrates an example in which the internal wirings LINA and LINB are laid in parallel in the X direction, but the invention is not limited to this, and for example, a part of the internal wirings LINA and LINB may be laid in parallel. <<Bereich inklusive dediziertem Verdrahtungsbereich EXLSP-11> >

[0083] Fig. 6A to Fig. 6E are diagrams for describing layers according to the first embodiment. Fig. 6A to Fig. 6E schematically illustrate sections corresponding to the NMOS switch circuit NMOS-SW1, the dedicated wiring area EXLSP-11, the time constant circuits RC-1 and RC-2, and the inverter circuits INV-1 and INV-2 in the layout of the ESD protection circuit EDSP shown in Fig. 3. Here are Fig. 6A to Fig. 6E similar to Fig. 4A to Fig. 4E. That is, Fig. 6A illustrates a diffusion layer formed on the semiconductor chip CHP, Fig. 6B illustrates a first metal layer formed on the diffusion layer, and Fig. 6C illustrates a second metal layer formed on the diffusion layer with an insulating layer disposed therebetween. In addition, Fig. 6D shows a third metal layer from the third metal layer to a twelfth metal layer formed on the second metal layer with an insulating layer interposed therebetween, and Fig. 6E illustrates a thirteenth metal layer and a fourteenth metal layer formed on the twelfth metal layer with an insulating layer disposed therebetween.

[0084] There Fig. 6A to Fig. 6E similar to Fig. 4A to Fig. 4E, a detailed description thereof is omitted, except for the dedicated wiring area EXLSP-11. In the dedicated wiring area EXLSP-11, as shown in Fig. As shown in Figure 6B, the first layer wirings M1-E formed from the first metal layer are formed on the surface of the semiconductor chip CHP with the insulating layer interposed therebetween. Thereafter, as shown in Fig. As shown in Figure 6C, the second-layer wirings M2-E formed of the second metal layer are formed on the first-layer wirings M1-E with the insulating layer interposed therebetween in the dedicated wiring region EXLSP-11. When viewed from a plan view, the first-layer wiring M1-E and the second-layer wiring M2-E, which are arranged to overlap each other, are connected through a through-hole and used as the internal wiring LINC. The internal wiring LINC is connected to the NMOS switch circuit NMOS-SW1, the time constant circuits RC-1 and RC-2, and the inverter circuits INV-1 and INV-2 through the third-layer wiring M3 and the like shown in Figure 6C. Fig. 6D is shown. <<Verdrahtungslayout in dediziertem Verdrahtungsbereich> >

[0085] Next, a detailed layout of the EXLSP-11 dedicated wiring area is described with reference to the drawings. Fig. 7 is a plan view illustrating a wiring layout in the dedicated wiring area according to the first embodiment. As shown in Fig. As shown in Figure 3, the internal wiring LINC is arranged in the dedicated wiring area EXLSP-11, and the NMOS switch circuit NMOS-SW1, the inverter circuits INV-1 and INV-2, and the time constant circuits RC-1 and RC-2 are connected using the internal wiring LINC. Also in Fig. 7, the first layer wirings M1 and M1-E formed using the first metal layer are shown in dashed lines, and the second layer wirings M2 and M2-E formed using the second metal layer and the third layer wirings M3 formed using the third metal layer are shown in solid lines.

[0086] Although not particularly limited, the internal wiring LINC in the first embodiment is constituted by eight wirings LINC_1 to LINC_8.

[0087] Similarly to the internal wirings LINA_1 to LINA_6 described above, each of the wirings LINC_1 to LINC_8 is formed by the first layer wiring M1-E formed of the first metal layer and the second layer wiring M2-E formed of the second metal layer. That is, as shown in Fig. 7, when viewed in a plan view, the wiring of the first layer M1-E and the wiring of the second layer M2-E are formed to overlap each other, and the wiring of the first layer M1-E and the wiring of the second layer M2-E are electrically connected through the through hole BH. Also in Fig. 7, the wiring of the first layer M1-E is drawn larger than the wiring of the second layer M2-E so that the wirings can be easily distinguished.

[0088] In Fig. 7, the first-layer wirings M1 arranged along the Y direction outside the dedicated wiring area EXLSP-11 indicate the first-layer wirings of the NMOS switch circuit NMOS-SW1. Fig. 7, the three wirings of the first layer M1, represented by the reference symbol NMOS-SW1 in parentheses, are connected, for example, to a source region of the NMOS transistor N3, as described with reference to Fig. 2 described.

[0089] Although not particularly limited, the first-layer wirings M1 of the NMOS switch circuit NMOS-SW1 are connected to the third-layer wirings M3-2 formed of the third metal layer through the circled through holes BH, and the third-layer wirings M3-2 are connected to the first-layer wiring M1-E and the second-layer wiring M2_E, which constitute each of the internal wirings LINC_1 to LINC_8, through the through holes BH. In addition, these third-layer wirings M3-2 are connected to the time constant circuit RC-2 and the inverter circuit INV-2.

[0090] Similarly, the third-layer wiring M3-1 is connected to the first-layer wiring M1-E and the second-layer wiring M2_E, which form each of the internal wirings LINC_1 to LINC_8, through the through holes BH. These third-layer wirings M3-1 are connected to the time constant circuit RC-2 and the inverter circuit INV-2.

[0091] A wiring (hereinafter also referred to as a second wiring) connecting the NMOS switch circuit NMOS-SW1, the time constant circuits RC-1 and RC-2, and the inverter circuits INV-1 and INV-2 includes the internal wiring (a first portion) LINC extending in the X direction and the third-layer wirings (a second portion) M3-1 and M3-2 extending in the Y direction intersecting the X direction. In this case, since the respective third-layer wirings M3-1 and M3-2 are electrically connected to be bundled by the plurality of internal wirings LINC_1 to LINC_8, a resistance value of the third-layer wirings M3-1 and M3-1 is equal to or lower than a resistance value of the internal wiring LINC.

[0092] Fig. 7 illustrates an example in which the third-layer wiring formed of the third metal layer is used as the wiring connecting the NMOS switch circuit NMOS-SW1, the internal wiring (LINC), the time constant circuits RC-1 and RC-2, and the inverter circuits INV-1 and INV-2. However, the invention is not limited to this, and any of the fourth-layer wiring to the twelfth-layer wiring may be used. In addition, the number of wirings constituting the internal wiring LINC is eight as an example, but is not limited to this, and may be one, for example. <<Layout der Stromversorgungsverdrahtung und der Masseverdrahtung> >

[0093] Fig. 8 is a plan view illustrating a layout of the power supply wiring and the ground wiring according to the first embodiment. Fig. Figure 8 shows a layout of sections related to the signal cell IO_CL and the power supply cell PW_CL shown in Fig. 1 are illustrated.

[0094] In Fig. 8, reference symbols PD and ND denote the protection diodes provided in the signal cell IO_CL. Dashed lines drawn to surround the symbols PD and ND indicate diffusion regions forming the protection diodes PD and ND.

[0095] In Fig. 8, the power supply wiring LVCC is configured by electrically connecting some thirteenth-layer wirings M13 among the plurality of thirteenth-layer wirings M13 and some fourteenth-layer wirings M14 among the plurality of fourteenth-layer wirings M14 as described above. In addition, the other thirteenth-layer wirings M13 among the plurality of thirteenth-layer wirings M13 and the other fourteenth-layer wirings M14 among the plurality of fourteenth-layer wirings M14 are electrically connected to form the ground wiring LVSS.

[0096] As in Fig. 8, the power supply wiring LVCC extends to overlap the discharge switch circuit B-NMOS and the protection diode PD, and is electrically connected to a drain region of the NMOS transistor BN1 ( Fig. 2) and the protection diode PD. In addition, the ground wiring LVSS extends to overlap the discharge switch circuit B-NMOS and the protection diode ND, and is electrically connected to a source region of the NMOS transistor BN2 ( Fig. 2) and the protection diode ND.

[0097] The power supply wiring LVCC is connected through the through holes BH to the VCCL wirings formed by the third-layer wiring M3 to the twelfth-layer wiring M12 and extending in the Y direction. The ground wiring LVSS is connected through the through holes BH to the VSSL wirings formed by the third-layer wiring M3 to the twelfth-layer wiring M12 and extending in the Y direction. The VCCL and VSSL wirings are connected through the through holes BH to the inside of the trigger circuit TGC and the blocking diode REV-D to supply the power supply voltage VCC and the ground voltage VSS.

[0098] That is, the power supply wiring LVCC and the ground wiring LVSS, which correspond to the main discharge wiring, are connected to the discharge switch circuit B-NMOS and the protection diodes PD and ND. On the other hand, for example, the inside of the trigger circuit TGC is connected to the main discharge wiring via the wirings VCCL and VSSL.

[0099] It is believed that the discharge performance deteriorates when the NMOS transistors BN1 and BN2 are distributed, and thus the NMOS transistors BN1 and BN2 constituting the discharge switch circuit B-NMOS are arranged adjacent to each other.

[0100] Since the blocking diode REV-D forms a discharge path when a high voltage is applied to the ground terminal, the blocking diode REV-D is also desirably arranged near the power supply wiring LVCC and the ground wiring LVSS. However, in the first embodiment, the blocking diode REV-D is arranged between the discharge switch circuit B-NMOS and the trigger circuit TGC to give priority to arranging the NMOS transistors BN1 and BN2 adjacent to each other and to prevent a dead space from occurring in the adjacent signal cell IO_CL. Although it is Fig. 8, the internal wirings LINA to LINC in the trigger circuit TGC extend in the X direction. Therefore, the blocking diode REV-D is arranged along the X direction between the internal wirings LINA to LINC in the trigger circuit TGC and the NMOS transistors BN1 and BN2. <<Layout der Entladungsschalterschaltung> >

[0101] Fig. 9A to Fig. 9C are diagrams for describing the discharge switch circuit according to the first embodiment. Here, Fig. 9A shows a circuit configuration of the discharge switch circuit B-NMOS and Fig. 9B and Fig. 9C are diagrams illustrating layouts of the discharge switch circuit.

[0102] The configuration of the B-NMOS discharge switch circuit used in Fig. 9A is similar to that shown in Fig. 1. A difference in Fig. 9A is that the gate electrode of the NMOS transistor BN1 is denoted by reference symbol A, the gate electrode of the NMOS transistor BN2 is denoted by reference symbol B, an electrode of the drain region of the NMOS transistor BN1 is denoted by reference symbol DD, and an electrode of the source region of the NMOS transistor BN2 is denoted by reference symbol SS.

[0103] In the layout shown in Fig. 9B, the gate electrode A of the NMOS transistor BN1 and the gate electrode B of the NMOS transistor BN2 are arranged in series between the drain electrode DD and the source electrode SS. On the other hand, in the layout shown in Fig. 9C, the gate electrodes A and B of the NMOS transistors BN1 and BN2 are arranged separately between the drain electrodes DD and between the source electrodes SS, respectively.

[0104] If that in Fig. 9B, it is possible to reduce the occupied area of ​​the B-NMOS discharge switch circuit and improve heat dissipation. Therefore, the Fig. 9B is used in the B-NMOS discharge switch circuit according to the first embodiment.

[0105] In the first embodiment, the source regions, the drain regions and the like of the MOS transistors and the gate electrodes are formed in the first layer (diffusion layer) as described with reference to Fig. 4A to Fig. 4E and Fig. 6A to Fig. 6E. Therefore, it can be considered that the MOS transistor and the trigger circuit TGC including the MOS transistor and the like are formed in the first layer. In this regard, it can be considered that the internal wirings and the wirings (for example, the third-layer wiring) electrically connected to the internal wirings are formed in the second layer, which is an upper layer of the first layer. Further, it can be considered that the power supply wiring LVCC and the ground wiring LVSS are formed in an upper layer of the second layer.

[0106] In the ESD protection circuit ESDP according to the first embodiment, the internal wirings formed by wirings in the same layer as the first-layer wiring and the second-layer wiring used in the circuits constituting the ESD protection circuit are arranged in the dedicated wiring areas, and the wirings (for example, the third-layer wirings) connecting the circuits are bundled by the internal wirings. This makes it possible to reduce the wiring resistance connecting the circuits constituting the ESD protection circuit ESDP and suppress deterioration of the ESD protection function. (Second embodiment)

[0107] Fig. 10 is a block diagram illustrating a configuration of an ESD protection circuit according to the second embodiment. In the ESD protection circuit according to the second embodiment, the B-NMOS discharge switch circuit connected to a main discharge wiring includes three-stage MOS transistors whose source-drain paths are connected in series. As a result, a MOS transistor with a lower withstand voltage can be used as the B-NMOS discharge switch circuit.

[0108] Fig. 10 is similar to Fig. 2. The ESD protection circuit ESDP, which is Fig. 10 is different from the ESD protection circuit of Fig. 2 in that it further comprises resistors R5 and R6, an NMOS switch circuit NMOS-SW2, a time constant circuit RC-3, an inverter circuit INV-3, and an NMOS transistor BN3. Furthermore, the ESD protection circuit ESDP differs from Fig. 10 also in that it further includes internal wiring LIND and LINE.

[0109] As in Fig. As shown in Figure 10, resistor R1, NMOS switch circuit NMOS-SW1, time constant circuit RC-1, and inverter circuit INV-1 are connected to the internal wiring LIND instead of the power supply wiring LVCC. Resistor R5, NMOS switch circuit NMOS-SW2, time constant circuit RC-3, and inverter circuit INV-3 are connected in parallel between the power supply wiring LVCC and the internal wiring LIND. In addition, an output node (the node to which a drain region of PMOS transistor P3 and a drain region of NMOS transistor N5 are connected) of inverter circuit INV-3 is connected to a gate electrode of NMOS transistor BN3 via the internal wiring LINE. In addition, resistor R6 is connected between the internal wiring LIND and the internal wiring LINE. As shown in Fig. As shown in Figure 10, the NMOS transistors BN1 to BN3 are connected between the power supply wiring LVCC and the ground wiring LVSS, so that source-drain paths are connected in series between the power supply wiring and the ground wiring.

[0110] The NMOS switch circuit NMOS-SW2, the time constant circuit RC-3, the inverter circuit INV-3 and the resistors R5 and R6 function similarly to the NMOS switch circuit NMOS-SW1, the time constant circuit RC-1, the inverter circuit INV-1 and the resistors R1 and R3 shown in Fig. 2, and therefore, a detailed description will be omitted. When a steep high voltage is applied to the power supply terminal VCCQ, each of the internal wirings LINA to LINE changes toward a voltage of the power supply wiring LVCC, and the NMOS transistors BN1 to BN3 are turned on. As a result, current flows between the power supply wiring LVCC and the ground wiring LVSS via the B-NMOS discharge switch circuit, and a protected circuit can be prevented from being destroyed. <Layout der ESD-Schutzschaltung>

[0111] Fig. 11 is a plan view illustrating a layout of the ESD protection circuit according to the second embodiment. That is, Fig. 11 illustrates an example of the layout of the Fig. 10 illustrated ESD protection circuit. This Fig. 11 is similar to Fig. 3. A difference in Fig. 11 is that the NMOS switch circuit NMOS-SW2 is arranged next to the NMOS switch circuit NMOS-SW1 (X direction), and the time constant circuit RC-3 and the inverter circuit INV-3 are arranged between the NMOS switch circuit NMOS-SW2 and the blocking diode REV-D (Y direction).

[0112] In addition, the dedicated wiring areas EXLSP-11 and EXLSP-21, which are located in Fig. 3 are enlarged in area to be arranged as dedicated wiring areas EXLSP-12 and EXLSP-22. The internal wirings LINC and LIND are arranged in the dedicated wiring area EXLSP-12, and the internal wirings LINA, LINB, and LINE are arranged in the dedicated wiring area EXLSP-22. Each of these internal wirings LINA to LINE is formed by the first-layer wiring M1-E and the second-layer wiring M2-E as described in the first embodiment. In addition, the internal wirings and circuit blocks (for example, the NMOS switch circuits, the inverter circuits, the time constant circuits, and the like) in the ESD protection circuit are connected by the third-layer wiring M3 to the twelfth-layer wiring M12.

[0113] Also in the second embodiment, the internal wirings formed by wirings in the same layer as the first-layer wiring and the second-layer wiring used in the circuits constituting the ESD protection circuit are arranged in the dedicated wiring areas, and the wirings (for example, the third-layer wirings) connecting the circuits are bundled by the internal wirings. This makes it possible to reduce the wiring resistance connecting the circuits constituting the ESD protection circuit ESDP and suppress deterioration of the ESD protection function.

[0114] In addition, the MOS transistor having the lower withstand voltage can be used as the NMOS transistor (BN1 to BN3) constituting the discharge switch circuit B-NMOS in the second embodiment. The withstand voltage of the NMOS transistor is determined, for example, by a film thickness of a gate insulating film. When a newer-generation process is used, the film thickness of the gate insulating film becomes thinner, and the withstand voltage of the NMOS transistor (BN1 to BN3) decreases. By increasing the number of stages of the NMOS transistors constituting the discharge switch circuit as in the second embodiment, it is possible to prevent a decrease in the voltage at which the protection function operates.

[0115] The MOS transistor may be a fin-type MOS transistor, which is limited to a planar-type MOS transistor.

[0116] The invention made by the present inventors has been described in detail based on the embodiments as above, but the present invention is not limited to the above-described embodiments, and it is understood that various kinds of modifications can be made within the range of not departing from a gist thereof. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2023-187662

[0001] US 7,397,642

[0004] < / entladungsschalterschaltung>

Claims

[1] Semiconductor device comprising: a semiconductor chip having a plurality of layers formed on a surface, where in the multitude of layers, a first power supply wiring to which a power supply voltage is supplied, a second power supply wiring to which a ground voltage is supplied, a MOS transistor connected to the first power supply wiring and the second power supply wiring and configured to electrically short-circuit the first power supply wiring and the second power supply wiring, and a trigger circuit electrically connected to a first gate electrode of the MOS transistor via a first wiring and configured to output a first control signal for controlling the first gate electrode, wherein the MOS transistor and the trigger circuit are formed in a first layer of the plurality of layers, wherein the first wiring is formed in a second layer which is an upper layer of the first layer, and where the first wiring contains the following: a first section extending in a first direction; and a second portion extending in a second direction intersecting the first direction and electrically connected to the first portion. [2] The semiconductor device according to claim 1, wherein a resistance value of the second portion of the first wiring is equal to or lower than a resistance value of the first portion of the first wiring. [3] The semiconductor device according to claim 2, wherein the first wiring includes a plurality of wirings. [4] The semiconductor device according to claim 3, wherein, in a plan view from the surface of the semiconductor chip, the second portion of the first wiring is arranged between the trigger circuit and the MOS transistor, and the second portion of the first wiring, the trigger circuit and the MOS transistor are arranged to face the first direction. [5] A semiconductor device according to claim 4, wherein the trigger circuit includes: a switch circuit electrically connected to the first power supply wiring; a first RC circuit electrically connected to the first power supply wiring; and a first inverter circuit electrically connected to the switch circuit and the first RC circuit via a second wiring and electrically connected to the first gate electrode of the MOS transistor via the first wiring, and wherein the second wiring is formed in the second layer and includes a first portion extending in the first direction and a second portion extending in the second direction. [6] The semiconductor device according to claim 5, wherein a resistance value of the second portion of the second wiring is equal to or lower than a resistance value of the first portion of the second wiring. [7] The semiconductor device according to claim 6, wherein the second wiring includes a plurality of wirings. [8] A semiconductor device according to claim 7, wherein, in plan view, the first RC circuit is arranged between the switch circuit and the first inverter circuit, and the first RC circuit, the switch circuit and the first inverter circuit are arranged to face the first direction, and wherein the second portion of the second wiring is arranged between the switch circuit and the first RC circuit. [9] The semiconductor device according to claim 8, wherein the trigger circuit further includes: a second RC circuit electrically connected to the switch circuit via the second wiring; and a second inverter circuit electrically connected to the switch circuit and the second RC circuit via the second wiring, electrically connected to a second gate electrode of the MOS transistor in a subsequent stage of the first gate electrode via a third wiring, and configured to output a second control signal to the second gate electrode of the MOS transistor, and wherein the third wiring is formed in the second layer and includes a first portion extending in the first direction and a second portion extending in the second direction. [10] The semiconductor device according to claim 9, wherein a resistance value of the second portion of the third wiring is equal to or lower than a resistance value of the first portion of the third wiring. [11] The semiconductor device according to claim 10, wherein the third wiring includes a plurality of wirings. [12] A semiconductor device according to claim 11, wherein, in plan view, the second portion of the third wiring is arranged between the trigger circuit and the MOS transistor, and the second portion of the third wiring, the trigger circuit and the MOS transistor are arranged to face the first direction, and wherein the second section of the third wiring is partially laid parallel to the second section of the first wiring. [13] The semiconductor device according to claim 4, further comprising a diode connected to the first power supply wiring and the second power supply wiring and configured to electrically short-circuit the first power supply wiring and the second power supply wiring, the diode being arranged between the second portion of the first wiring and the MOS transistor in plan view along the first direction.

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