SIGNAL PROCESSING CIRCUIT, SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM

Abstract

A signal processing circuit includes a plurality of first contact pads, a second contact pad, and signal processing logic circuitry. The plurality of first contact pads are associated with input and output data, commands, and addresses. The signal processing logic circuitry detects a received request based on a combination of a first set of signals transmitted across the plurality of first contact pads and a second signal transmitted across the second contact pad during operating modes other than a data input mode and a data output mode.

Description

BACKGROUND 1. TECHNICAL FIELD

[0001] Various embodiments generally relate to a semiconductor circuit including, but not limited to, a signal processing circuit, a semiconductor device, and a data processing system including the signal processing circuit. 2. STATE OF THE ART

[0002] Electronic devices including semiconductor devices are subject to simultaneous switching noise (SSN) and inter-symbol interference (ISI) when the number of data bits that are out of phase with respect to a previous time increases during transmission from a controller or host. Therefore, semiconductor devices reduce the occurrence of SSN and ISI by using a data bus inversion (DBI) operation, which inverts and transmits data when many of the transmitted data bits contain bits that are out of phase with respect to the previous time. DBI is included in the operating standard of the semiconductor device, and the semiconductor device includes a DBI pad for input / output of the DBI flag, in addition to a plurality of data input / output pads for data input / output. SUMMARY

[0003] In one embodiment, a signal processing circuit may include a plurality of first contact pads, a second contact pad, and signal processing logic circuitry. The plurality of first contact pads may be associated with input and output data, commands, and addresses. The signal processing logic circuitry may be configured to identify or recognize a received request based on a combination of a first set of signals transmitted across the plurality of first contact pads and a second signal transmitted across the second contact pad during operating modes other than a data input mode and a data output mode.

[0004] In one embodiment, a semiconductor device may include a plurality of first contact pads, a second contact pad, a data bus inverting circuit, and a signal processing logic circuit. The plurality of first contact pads may be associated with input and output data, commands, and addresses. The data bus inverting circuit may be configured to invert signals transmitted over the plurality of first contact pads during a data input mode and a data output mode according to a signal input over the second contact pad. The signal processing logic circuit may be configured to detect a received request based on a combination of signals input over the plurality of first contact pads and a signal input over the second contact pad during operating modes other than the data input mode and the data output mode.

[0005] In one embodiment, a data processing system may include a semiconductor device and a controller. The semiconductor device may be configured to invert signals transmitted via a plurality of first contact pads corresponding to input and output of data, commands, and addresses during a data input mode and a data output mode according to a signal input via a second contact pad associated with input and output of a data bus inversion signal, and may be configured to recognize a combination of signals input via the plurality of first contact pads and a signal input via the second contact pad as a command set during operating modes other than the data input mode and the data output mode.The controller may be configured to output the data bus reversal signal via the second contact pad during the data input mode and to encode signals transmitted via the plurality of first contact pads in response to the data bus reversal signal, and may be configured to provide signals output via the plurality of first contact pads and the second contact pad to the semiconductor device as a command set during the operating modes.

[0006] In one embodiment, a method may include, in response to a data bus reversal signal input via a second pad in a semiconductor device, inverting signals transmitted via a plurality of first pads corresponding to input and output of data during a data input mode and a data output mode; and recognizing a combination of signals input via the plurality of first pads and a signal input via the second pad during operation modes other than the data input mode and the data output mode as a command set. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a table including the use of a data bus inversion signal pad for each operating mode of a semiconductor device. Fig. 2 is a diagram illustrating an arrangement of an input and output signal processing circuit according to an embodiment of the present disclosure. Fig. 3 shows a table including data during operation of a data bus inverter circuit. Fig. 4 is a diagram illustrating a configuration of a semiconductor device according to an embodiment of the present disclosure. Fig. 5 is a diagram illustrating an arrangement of a data processing system according to an embodiment of the present disclosure. Fig. 6 shows a table including the use of a data bus inversion signal pad for various operating modes of a semiconductor device according to an embodiment of the present disclosure. Fig. Figure 7A is a diagram illustrating an example of an instruction set configuration. Fig. 7B is a diagram illustrating an example of an instruction set configuration according to an embodiment of the present disclosure. Fig. Figure 8A shows a table comprising an address mapping scheme. Fig. 8B shows a table including an address mapping scheme according to an embodiment of the present disclosure. Fig. 9A shows a diagram illustrating an example of parameter setting. Fig. 9B is a diagram illustrating an example of parameter setting according to an embodiment of the present disclosure. Fig. 10A is a diagram showing an example of an operation of a status information output mode. Fig. 10B is a diagram illustrating an example of an operation of a status information output mode according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0007] Embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0008] With reference to Fig. 1, a semiconductor device according to the prior art inputs DBI-encoded (w / o DBI CODING, where w is a width) data through an input / output pad (DQ PAD) in a data input mode (DATA INPUT) and a data output mode (DATA OUTPUT), and transmits DBI flags used for DBI encoding through a DBI PAD. In operation modes other than a data input mode and a data output mode, such as a command input mode (COMMAND INPUT), an address input mode (ADDRESS INPUT), a parameter setting mode (PARAMETER SET), and a status read mode (STATUS READ), DBI-uncoded (w / o DBI CODING, where w / o stands for "without") commands and addresses are transmitted through the data input / output pad (DQ PAD), and the DBI PAD is not used.

[0009] Fig. 2 is a diagram illustrating an arrangement of an input and output signal processing circuit 10 according to an embodiment of the present disclosure.

[0010] With reference to Fig. 2, the input and output signal processing circuit 10 comprises a plurality of first contact surfaces 11 (several contact surfaces indicated by three diagonal points in Fig. 2), a second contact surface 12, a receiver circuit (RX) 13, a transmitter circuit (TX) 14, a data bus inversion (DBI) circuit 15, a data transmission circuit 16, and a signal processing logic circuit 17. The input and output signal processing circuit 10 further includes a voltage detection circuit 18.

[0011] The plurality of first contact pads 11 are associated with the input and output of data, commands, and addresses. The second contact pad 12 is associated with the input and output of DBI flags and additional signals, which may be generally referred to as data bus reversal signals or DBI signals.

[0012] During a data input mode, data is input via the plurality of first contact pads 11, and DBI flags are input via the second contact pad 12. During a data output mode, data is output via the plurality of first contact pads 11, and DBI flags are output via the second contact pad 12.

[0013] During operating modes other than the data input mode and the data output mode, a first signal set including at least one of a command and an address is input via the plurality of first contact pads 11, and a second signal set including one or more additional signals is input or output via the second contact pad 12. The other operating modes include a command input mode, an address input mode, a parameter setting mode, and a status information output mode.

[0014] The receiver circuit 13 is coupled to the plurality of first contact pads 11 and the second contact pad 12. The receiver circuit 13 receives signals transmitted across the plurality of first contact pads 11 and the second contact pad 12 and provides the signals to the DBI circuit 15, which may be received by one or more devices external to the input and output signal processing circuit 10.

[0015] The transmitting circuit 14 is coupled to the plurality of first contact pads 11 and the second contact pad 12. The transmitting circuit 14 transmits internal signals outwardly to the input and output signal processing circuit 10 via the plurality of first contact pads 11 and the second contact pad 12.

[0016] The DBI circuit 15 outputs data during the data input mode and the data output mode by inverting the data according to the DBI flag. The DBI circuit 15 outputs write data DIN <n:0>generated by performing a DBI decoding operation on the data provided by the receiver circuit 13. The DBI circuit 15 provides the result of performing a DBI encoding operation on the read data DOUT <n:0>to the transmitting circuit 14.

[0017] The data input via the plurality of first contact pads 11 is DBI-encoded externally, for example, outside the input and output signal processing circuit 10. DBI encoding is an operation that involves inverting / non-inverting the data to be transmitted when the number of 1s (or 0s) in the data to be transmitted is greater than / less than a predetermined number, and transmitting the DBI flag as 1 / 0 along with the data to the receiver to detect whether the data is inverted or not. DBI decoding is an operation that returns the DBI-encoded data to its original state by inverting / non-inverting the data according to the DBI flag.

[0018] The data transmission circuit 16 transmits the write data DIN provided by the DBI circuit 15 <n:0>into a memory area. The data transmission circuit 16 transmits the read data DOUT output from the memory area <n:0>to the DBI circuit 15.

[0019] The signal processing logic circuit 17 detects or interprets a received request based on, for example, a combination of a first set of signals transmitted via the plurality of first contact pads 11 and the receiver circuit 13, and one or more additional signals transmitted via the second contact pad 12 and the receiver circuit 13 during operating modes other than the data input mode and the data output mode. The first set of signals may, for example, include at least one of a setup command, at least one address, data, and an acknowledge command.

[0020] During the command input mode, the signal processing logic circuit 17 receives a first set of signals transmitted via the plurality of first contact pads 11 and the receiver circuit 13, and one or more additional signals transmitted via the second contact pad 12 and the receiver circuit 13, as a command set. The signal processing logic circuit 17 decodes the command set.

[0021] During the address input mode, the signal processing logic circuit 17 recognizes as addresses a first set of signals transmitted via the plurality of first contact pads 11 and the receiver circuit 13, and one or more additional signals transmitted via the second contact pad 12 and the receiver circuit 13.

[0022] During the status information output mode, the signal processing logic circuit 17 outputs status information, for example, a status information signal set, via the transmitting circuit 14 and the plurality of first contact pads 11 and outputs one or more additional signals related to the status information via the transmitting circuit 14 and the second contact pad.

[0023] The signal processing logic circuit 17 includes a command decoder 17-1, an address memory 17-2, and a status information encoder 17-3. The command decoder 17-1 receives and decodes a first set of signals and one or more additional signals as a command set during the command input mode. The address memory 17-2 receives and stores a first set of signals and one or more additional signals as addresses during the address input mode. The status information encoder 17-3 encodes data corresponding to the requested status information during the status information output mode. The status information encoder 17-3 encodes data corresponding to the status information in response to a low-voltage detection signal LVDET during the status information output mode.

[0024] The voltage detection circuit 18 generates the low voltage detection signal LVDET by detecting when a voltage level, for example, a level of a power supply voltage, is lower than a predetermined level.

[0025] The additional signals used during the command input mode are called additional commands, the additional signals used during the address input mode are called additional addresses, and the additional signals used during the status information output mode are called additional flag signals.

[0026] Fig. 3 shows a table showing data during operation of the data bus inverter circuit 15 of Fig. 2 includes.

[0027] With reference to Fig. 3, when the DBI coding is not applied, '10101110' / '00000001' / '11111111' is transmitted via the plurality of first contact surfaces 11 when the write data DIN<7:0> or the read data DOUT<7:0> are 'AEh' / '01h' / 'FFh', respectively, where 'h' indicates hexadecimal numbers. When the previous data is 'AEh' and the current data is '01h', the receiver circuit RX 13 or the transmitter circuit TX 14 drives six (6) data bits to the opposite level, and when the previous data is '01h' and the current data is 'FFh', the receiver circuit RX 13 or the transmitter circuit TX 14 drives seven (7) data bits to the opposite level.

[0028] When DBI coding is applied, as shown in the lower part of Fig. 3, when the write data DIN<7:0> or the read data DOUT<7:0> is 'AEh' / 'Olh' / 'FFh' in hexadecimal code, '01010001' / '00000001' / '00000000' is transmitted via the plurality of first contact pads 11, and '1' / '0' / '1' is transmitted via the second contact pad 12. The receiver circuit RX 13 or the transmitter circuit TX 14 transmits a smaller amount of data at the opposite level than when DBI coding is not applied, for example, three (3) bits when the previous data is 'AEh' and the current data is '01h', or two (2) bits when the previous data is '01h' and the current data is 'FFh'.

[0029] Therefore, by applying DBI coding, the efficiency of data transmission can be increased, and DBI is mainly used in semiconductor devices in which data transmission is performed.

[0030] Fig. 4 is a diagram illustrating a configuration of a semiconductor device 100 according to an embodiment of the present disclosure.

[0031] With reference to Fig. 4, the semiconductor device 100 includes a memory area having a plurality of levels (level 1 to level k), a peripheral circuit 120, a control circuit 130, and an input / output pad circuit 140.

[0032] Each of the plurality of levels level 1 to level k includes memory cell arrays, is coupled to an address decoder 121 via word lines WL, and is coupled to a read and write circuit 123 via bit lines BL1 to BLm, where m is a positive integer. Each of the plurality of levels level 1 to level k includes a plurality of memory areas, for example, a plurality of memory blocks BLK1 to BLKz, where k and z are positive integers. The plurality of memory blocks BLK1 to BLKz are coupled to the address decoder 121 via the word lines WL. The plurality of memory blocks BLK1 to BLKz are coupled to the read and write circuit 123 via the bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. The plurality of memory cells may be non-volatile memory cells. The plurality of memory blocks BLK1 to BLKz may include a plurality of pages.Among the plurality of memory cells, memory cells associated with the same word line may be referred to as a page. The plurality of memory blocks BLK1 to BLKz store normal data, such as data transmitted and received through a normal read operation and a normal write operation. Each memory cell may be a single-level cell (SLC) for storing one bit of data, a multi-level cell (MLC) for storing two bits of data, a triple-level cell (TLC) for storing three bits of data, or a quad-level cell (QLC) for storing four bits of data.

[0033] The peripheral circuit 120 includes an address decoder 121, a voltage generation circuit 122, a read / write circuit 123, and a data input / output circuit 124. The read / write circuit 123 includes a plurality of page buffers PB1 to PBm.

[0034] The address decoder 121 is configured to operate in response to control from the control circuit 130. The address decoder 121 receives addresses from the control circuit 130. The address decoder 121 selects at least one memory block from the memory blocks BLK1 to BLKz based on a decoded address. The address decoder 121 is configured to decode a row address from the received address. The address decoder 121 selects at least one word line of the selected memory block by applying a voltage provided by the voltage generation circuit 122 to the at least one word line WL according to the decoded row address. The address decoder 121 performs a programming operation by applying a programming voltage to the selected word line and applying a pass voltage at a lower level relative to the programming voltage to unselected word lines.The address decoder 121 performs a read operation by applying a read voltage to the selected word line and applying a pass voltage having a higher level than the read voltage to unselected word lines.

[0035] A voltage generation circuit 122, under the control of the control circuit 130, generates various voltages used during operation of the semiconductor device 100, such as a read voltage, a pass voltage, a program voltage, and an erase voltage, and provides them to the address decoder 121.

[0036] The plurality of page buffers PB1 to PBm are coupled to a first level 1 via a first bit line BL1 and an m-th bit line BLm, respectively. The plurality of page buffers PB1 to PBm operate in response to control signals received from the control circuit 130. The plurality of page buffers PB1 to PBm are in data communication with the data input / output circuit 124. The plurality of page buffers PB1 to PBm perform programming operations by receiving data to be stored via the data input / output circuit 124 and the data lines DL and forwarding the data to level 1. The read / write circuit 123 performs a read operation by reading data from memory cells of a selected page via the bit lines BL1 to BLm and outputting the read data to the data input / output circuit 124. The read / write circuit 123 performs an erase operation by floating the bit lines BL1 to BLm.

[0037] The data input / output circuit 124 is coupled between the plurality of page buffers PB1 to PBm and the input / output pad circuit 140. The data input / output circuit 124 performs data input and output operations in response to control signals received from the control circuit 130. The data input / output circuit 124 outputs data transferred from the plurality of memory blocks BLK1 to BLKz through the plurality of page buffers PB1 to PBm during a read operation to the input / output pad circuit 140. The data input / output circuit 124 transfers data input via the input / output pad circuit 140 to the plurality of page buffers PB1 to PBm during a write operation.The data input / output circuit 124 outputs status information transmitted by the control circuit 130 to a device external to the semiconductor device 100 via the input / output pad circuit 140 during a status information read operation.

[0038] The input / output pad circuit 140 receives commands, addresses, and clock signals and includes a plurality of pads through which data DQ is input and output, such as a plurality of DQ pads 141-1 to 141-n, a DBI pad 142, a CLE pad 143, and an ALE pad 144. The CLE pad 143 is used to input a Command Latch Enable (CLE) signal, and the ALE pad 144 is used to input an Address Latch Enable (ALE) signal.

[0039] The control circuit 130 is coupled to the address decoder 121, the voltage generation circuit 122, the read / write circuit 123, the data input / output circuit 124, and the input / output pad circuit 140. The control circuit 130 receives commands, addresses, and clock signals via the input / output pad circuit 140. The control circuit 130 generates various control signals in response to the commands.The control circuit 130 determines that the signal input through the plurality of DQ pads 141-1 to 141-n is a command when the CLE signal is at a predetermined logic level, for example, when the CLE signal is at a high level, the signal input through the plurality of DQ pads 141-1 to 141-n is an address when the ALE signal is at a high level, and the signal input through the plurality of DQ pads 141-1 to 141-n is data when both the CLE signal and the ALE signal are at a low level.

[0040] The semiconductor device 100 includes the input and output signal processing circuit 10 according to an embodiment of the present disclosure, which is described with reference to Fig. 2. The receiver circuit 13, the transmitter circuit 14, the DBI circuit 15 and the data transmission circuit 16 of Fig. 2 are in the data input / output circuit 124 of Fig. 4. The signal processing logic circuit 17 of Fig. 2 is in the control circuit 130 of Fig. 4. The plurality of first contact surfaces 11 in Fig. 2 corresponds to the plurality of DQ contact surfaces 141-1 to 141-n in Fig. 4, and the second contact surface 12 in Fig. 2 corresponds to the DBI contact area 142 in Fig. 4.

[0041] The semiconductor device 100 inverts the signals transmitted through a plurality of first pads, for example, the plurality of DQ pads 141-1 to 141-n, during the data input mode and the data output mode according to the signal input through the DBI pad 142, for example, the DBI flag, and recognizes as a command set a combination of the signals input through the plurality of DQ pads 141-1 to 141-n and the signal input through the DBI pad 142 during the operation modes other than the data input mode and the data output mode.

[0042] During the command input mode, the semiconductor device 100 recognizes the signal transmitted through the plurality of DQ pads 141-1 to 141-n as a first command when a logic level of the signal input through the DBI pad 142 is at a first value (logic low or logic high), and recognizes the signal transmitted through the plurality of DQ pads 141-1 to 141-n as a second command different from the first command when a logic level of the signal input through the DBI pad 142 is at a second level (logic high or logic low).

[0043] During the address input mode, the semiconductor device 100 recognizes the signals transmitted through the plurality of DQ pads 141-1 to 141-n and the signal transmitted through the DBI pad 142 as addresses.

[0044] During the parameter setting mode, the semiconductor device 100 selects a memory block for storing parameters among the unit memory areas, for example, the plurality of memory blocks BLK1 to BLKz, based on a result of combining the signals transmitted through the plurality of DQ pads 141-1 to 141-n and the signal transmitted through the DBI pad 142.

[0045] During the status information output mode, the semiconductor device 100 outputs status information via the plurality of DQ pads 141-1 to 141-n and outputs additional signals detecting one type of status information via the DBI pad 142.

[0046] The semiconductor device 100 sets a logic level of a signal input to the second pad to a first level to indicate that the status information is a status abnormality signal due to detection of a low voltage.

[0047] Fig. 5 is a diagram illustrating an arrangement of a data processing system 1000 according to an embodiment of the present disclosure.

[0048] With reference to Fig. 5, the data processing system 1000 may include a semiconductor device 2000 and a controller 3000.

[0049] The semiconductor device 2000 includes a plurality of logic units LU0 to LUn. Each of the plurality of logic units LU0 to LUn includes at least one memory die. The semiconductor device 100 according to an embodiment of the present disclosure, which is described with reference to Fig. 4 may be any of the plurality of logic units LU0 to LUn.

[0050] The controller 3000 generates a variety of control signals and commands and provides them to the semiconductor device 2000. The controller 3000 transmits / receives data, commands, addresses, and status information to / from the semiconductor device 2000 according to the data input mode, the data output mode, the command input mode, the address input mode, the parameter setting mode, and the status information output mode.

[0051] The controller 3000 outputs a DBI flag via the DBI pad 142 during the data input mode, encodes the data transmitted via the plurality of DQ pads 141-1 to 141-n to match the DBI flag, and provides the signals output via the plurality of DQ pads 141-1 to 141-n and the DBI pad 142 as a command set to the semiconductor device 2000 during the operating modes including the data input mode, the address input mode, the parameter setting mode, and the status information output mode.

[0052] Fig. 6 shows a table including the use of the data bus inversion signal pad for various operating modes of the semiconductor device 2000 according to an embodiment of the present disclosure.

[0053] With reference to Fig. 6, during the DATA INPUT and DATA OUTPUT modes, the semiconductor device 2000 transmits DBI-encoded data with DBI ENCODING over the plurality of DQ pads 141-1 to 141-n and transmits a DBI flag used for DBI encoding over the DBI pad 142. During the COMMAND INPUT mode, the plurality of DQ pads 141-1 to 141-n receive commands without DBI encoding, and additional commands are received over the DBI pad 142. During the ADDRESS INPUT mode, the plurality of DQ pads 141-1 to 141-n receive addresses without DBI encoding, and additional addresses are received over the DBI pad 142.During the parameter setting mode (SET PARAMETER), the plurality of DQ pads 141-1 to 141-n receive commands without DBI coding, and an additional flag signal is received via the DBI pad 142. The additional flag signal may be associated with signals transmitted via the plurality of first pads. During the status information output mode (STATUS READ), the plurality of DQ pads 141-1 to 141-n receive status information read commands or transmit status information without DBI coding, and an additional flag signal associated with the status information is transmitted via the DBI pad 142.

[0054] A communication method of the data processing system 1000 according to an embodiment of the present disclosure will be described with reference to the Fig. 7A to Fig. 10B. In this example, the data processing system 1000 is configured with a data width of ×8. Since the data width is ×8, the plurality of DQ pads 141-1 through 141-n are referred to as DQ<7:0>.

[0055] Fig. 7A is a diagram illustrating an example of an instruction set configuration according to the prior art. Fig. 7B is a diagram illustrating an example of an instruction set configuration according to an embodiment of the present disclosure.

[0056] The controller 3000 provides the semiconductor device 2000 with a command set corresponding to a selected operation, and the semiconductor device 2000 performs an operation corresponding to the command set received from the controller 3000. The command set is divided into a general command set that requests a general operation, such as a read operation, a write operation, and the like, and an additional command set that requests an additional operation related to the general operation.

[0057] With reference to Fig. 7A, a conventional general command set, for example, a conventional read command set, includes a setup command 00h-address ADD-ADD-ADD-ADD-ADD-confirmation command 30h. The semiconductor device 2000 outputs read data after a predetermined latency period tR1 in response to the read command set. An extended command set associated with the conventional read command set, for example, a fast read command set, further includes a preliminary command B5h before the read command set. The semiconductor device 2000 outputs read data after a read latency period tR2, which is shortened compared to the read latency period tR1, in response to the fast read command set because the data is output at a faster rate compared to the read command set.The extended instruction set, such as the fast read instruction, increases instruction overhead because the preliminary instruction is added compared to the general instruction set, and additional circuitry is required to process the preliminary instruction.

[0058] With reference to Fig. 7B, a read command set according to an embodiment of the present disclosure includes, for example, the one described with respect to Fig. 7A, which differs from the conventional read command set in that a signal input via the DBI pad is at a low level. The semiconductor device 2000 recognizes a command set as a read command set when the signal input via the DBI pad is at a low level during the period in which the confirmation command 30h is input and outputs read data after the predetermined read latency period tR1. A fast read command set according to an embodiment of the present disclosure differs from the read command set in that the signal input via the DBI pad is at a high level.The semiconductor device 2000 recognizes the command set as the fast read command set when the signal inputted via the DBI pad is at a high level during the period in which the confirmation command 30h is inputted, and outputs read data after the read latency period tR2 which is shortened compared to the read latency period tR1, and initiates, for example, data output during fast read at a faster rate than the data output rate during a read command for a read command set.

[0059] The additional instruction set of the present disclosure reduces an instruction cycle by eliminating the need for a pre-instruction, thereby reducing instruction overhead, and reduces circuit area by eliminating the circuitry that processes the pre-instruction.

[0060] Fig. Figure 8A shows a table with an address mapping scheme according to the prior art. Fig. 8B shows a table with an address mapping scheme according to an embodiment of the present disclosure.

[0061] With reference to Fig. 8A, of all address bits, A<14:0> is conventionally used as a main / spare address among column addresses, A<27:16> is used as a word line (WL) / string address among row addresses, A<29:28> is used as a level address among row addresses, A<38:30> is used as a block address among row addresses, and A<40:39> is used as a logical unit number (LUN) address among row addresses. Therefore, to receive addresses comprising a total of 40 bits, six cycles of address transfers are required via input / output lines IO<7:0> coupled to the plurality of DQ pads DQ<7:0>. As shown in Fig. As shown in Figure 7A, the instruction set consists of a combination of instructions and addresses, which results in increased instruction overhead due to the additional address cycles.

[0062] With reference to Fig. 8B, according to one embodiment of the present disclosure, an additional address AD<0:4> is used and is received via the DBI pad. AD<3:2>, which is part of the additional address AD<0:4>, is received via the DBI pad, in contrast to the Fig. 8A is used as the address of a logical unit number (LUN). As a result, the address cycle according to this embodiment is reduced to 5 cycles, which can reduce the instruction overhead compared to the prior art.

[0063] Fig. 9A is a diagram showing an example of parameter setting according to the prior art. Fig. 9B is a diagram illustrating an example of parameter setting according to an embodiment of the present disclosure.

[0064] The parameter setting mode is a mode in which various parameters related to operations of a semiconductor device are stored in a unit memory area such as a memory bank corresponding to a predetermined address.

[0065] With reference to Fig. 9A, conventionally, addresses 00h-7Fh storing parameters are set in a first memory bank BANK0, and other addresses 80h-FFh can be changed to one of a second memory bank BANK1, a third memory bank BANK2, and a fourth memory bank BANK3 according to bank selection information. For example, an operation of sequentially selecting the memory banks BANK0 to BANK3 for storing the parameters according to the prior art is Fig. 9A.

[0066] The controller provides a parameter setting command, including a setup command 36h - address 00h - parameter data DATA - confirmation command 16h, to the semiconductor device. The semiconductor device selects the first memory bank BANK0 with address 00h and stores the parameter data DATA in the area corresponding to address 00h of the first memory bank BANK0.

[0067] The controller then provides a parameter setting command comprising 36h-80h-DATA-16h to the semiconductor device. The semiconductor device selects the second memory bank BANK1 with address 80h and stores the parameter data DATA in the area corresponding to address 80h of the second memory bank BANK1.

[0068] The controller then provides the semiconductor device with a parameter setting range change command including bank selection data DATA-16h (36h-40h). The semiconductor device changes the memory bank for storing the parameter data in the third memory bank BANK2 according to the bank selection data DATA.

[0069] The controller then provides a parameter setting command comprising 36h-80h-DATA-16h to the semiconductor device. The semiconductor device stores the parameter data DATA in the area corresponding to address 80h of the third memory bank BANK2, since the third memory bank BANK2 was selected by the previous parameter setting range change command.

[0070] Then, the controller sequentially provides the parameter setting range change command and the parameter setting command to the semiconductor device as described above, and the semiconductor device stores the parameter data DATA in the area corresponding to the address 80h of the fourth memory bank BANK3.

[0071] As described above, in the prior art, six instruction set inputs are required to sequentially select the four memory banks BANK0 to BANK3 to perform a parameter setting operation, which can be regarded as a high instruction overhead.

[0072] With reference to Fig. 9B, according to one embodiment of the present disclosure, a memory bank is selected to store parameter data based on a combination of a logic level and an address of the DBI pad without a conventional parameter setting range change command. When the signal input via the DBI pad is at a low level and the address is 00h, the first memory bank BANK0 is selected. When the signal input via the DBI pad is at a low level and the address is 80h, the second memory bank BANK1 is selected. When the signal input via the DBI pad is at a high level and the address is 00h, the third memory bank BANK2 is selected. When the signal input via the DBI pad is at a high level and the address is 80h, the fourth memory bank BANK3 is selected.

[0073] An exemplary operation comprising sequentially selecting the four memory banks BANK0 to BANK3 for storing parameters according to an embodiment of the present disclosure is described with reference to Fig. 9B.

[0074] The controller sets the signal input via the DBI pad to a low level and provides a parameter setting command comprising 36h-00h-DATA-16h to the semiconductor device. The semiconductor device selects the first memory bank BANK0 because the signal input via the DBI pad is low and the address is 00h, and stores the parameter data DATA in the area corresponding to the address 00h of the first memory bank BANK0.

[0075] The controller sets the signal input via the DBI pad to a low level and provides a parameter setting command to the semiconductor device comprising 36h-80h-DATA-16h. The semiconductor device selects the second memory bank BANK1 because the signal input via the DBI pad is low and the address is 80h, and stores the parameter data DATA in the area corresponding to the address 80h of the second memory bank BANK1.

[0076] The controller sets the signal input via the DBI pad to a high level and provides the parameter setting command, which has the address 36h-00h-DATA-16h, to the semiconductor device. The semiconductor device selects the third memory bank BANK2 because the signal input via the DBI pad is high and the address is 00h, and stores the parameter data DATA in the area corresponding to the address 00h of the third memory bank BANK2.

[0077] The controller sets the signal input via the DBI pad to a high level and provides a parameter setting command to the semiconductor device comprising 36h-80h-DATA-16h. The semiconductor device selects the fourth memory bank BANK3 because the signal input via the DBI pad is high and the address is 80h, and stores the parameter data DATA in the area corresponding to the address 80h of the fourth memory bank BANK3.

[0078] As in Fig. 9B, an embodiment of the present disclosure uses only four instruction set inputs to perform the parameter setting operation by sequentially selecting the four memory banks BANK0 to BANK3, which reduces the instruction overhead compared to the prior art, as shown in Fig. 9A shown.

[0079] Fig. 10A is a diagram showing an example of an operation of a status information output mode according to the related art. Fig. 10B is a diagram illustrating an example of an operation of a status information output mode according to an embodiment of the present disclosure.

[0080] A status information output mode represents an operation in which a semiconductor device outputs its status information in response to a received request, for example, a request received from a device external to the semiconductor device 100, and status information output mode according to the related art will be described with reference to Fig. 10A described.

[0081] With reference to Fig. 10A, the controller provides a multi-level program command MP PGM to the semiconductor device. The multi-level program command MP PGM is a command that requests a programming operation for a plurality of levels LEVEL 1 to LEVEL k, as described with reference to Fig. 4. During a process of executing the program operation for the plurality of levels LEVEL 1 to LEVEL k, a drop in the operating voltage occurs, and consequently, an error occurs in the program operation. Therefore, the controller issues a status information output command including 7Ah-ADD-ADD-ADD to the semiconductor device to confirm whether the program operation was performed properly. The semiconductor device outputs the status information E3h in response to the status information output command. The status information E3h is used as a status abnormality signal for a program error. Since the status information E3h only includes whether or not the program error occurs, the controller cannot determine the cause of the program error based solely on the status information E3h. Therefore, the controller also provides a read ID command including 90h-ADD to the semiconductor device.In response to the ID read command, the semiconductor device outputs an initialization request signal comprising 00h-00h-00h-00h-00h-00h, indicating to the controller that the semiconductor device needs to be initialized. In response to the initialization request signal, the controller provides an initialization command of 38h to the semiconductor device. The semiconductor device performs an initialization operation in response to the initialization command.

[0082] As with regard to Fig. 10A, in the prior art, six communication sequences between the semiconductor device and the controller are required to inform the semiconductor device of an internal abnormality of the semiconductor device, such as a failure caused by a voltage drop, thereby increasing the command overhead.

[0083] A status information output mode according to an embodiment of the present disclosure will be described with reference to Fig. 10B described.

[0084] With reference to Fig. 10B, the controller provides a multi-level program command MP PGM to the semiconductor device. The controller provides a status information output command to the semiconductor device to confirm whether a programming operation has been performed properly. In response to the status information output command, the semiconductor device outputs status information E3h as a status abnormality signal and sets the signal input via the DBI pad to a high level. The signal input via the DBI pad detects, for example, one type of status abnormality signal. When a drop in the operating voltage occurs during the process of performing the programming operation for the plurality of levels LEVEL 1 to LEVEL k, the semiconductor device initiates the process described with reference to Fig. The voltage detection circuit 18 described in Figure 2 detects the drop in the operating voltage and generates the low-voltage detection signal LVDET. The status information encoder 17-3 performs operations including, for example, generating the status information E3h and setting the signal input via the DBI pad to a high level, for example, to detect that the status abnormality signal is caused by low-voltage detection.

[0085] The controller detects the abnormality of the semiconductor device based on the status information. Since the signal input via the DBI pad is at a high level, the controller detects that the abnormality of the semiconductor device is caused by a voltage drop. Therefore, an initialization command can be immediately provided to the semiconductor device without a conventional read ID command and an initialization request signal, and the semiconductor device can perform an initialization operation in response to the initialization command.

[0086] As described above, an embodiment of the present disclosure can reduce a command overhead because only four sequences are required between the semiconductor device and the controller to inform the occurrence of a fault due to an internal abnormality of the semiconductor device, such as a voltage drop.

[0087] One skilled in the art to which the present disclosure belongs will understand that the present disclosure may be embodied in other forms without altering its scope or technical spirit. The described embodiments are, in all forms, illustrative and not restrictive. Therefore, the scope of the present disclosure should not be limited to the foregoing embodiments. All changes within the meaning and range of equivalence of the claims are intended to be embraced within their scope.

Claims

[1] Signal processing circuit, comprising: a plurality of first contact surfaces associated with the input and output data, commands and addresses; a second contact surface; and a signal processing logic circuit configured to detect a received request based on a combination of a first set of signals transmitted over the plurality of first contact pads and a second signal transmitted over the second contact pad during operating modes other than a data input mode and a data output mode. [2] The signal processing circuit of claim 1, wherein the signal processing logic circuit comprises an instruction decoder configured to receive and decode the first instruction set and the second signal as an instruction set during an instruction input mode among the operating modes. [3] A signal processing circuit according to claim 2, wherein the instruction set comprises: a first signal set comprising at least one of a setup command, at least one address, data, and an acknowledge command; and the second signal transmitted via the second contact surface during a period in which one of the at least one address and the confirmation command is input. [4] The signal processing circuit of claim 2, wherein the signal processing logic circuit further comprises an address memory configured to receive and store the first signal set and the second signal as the addresses during an address input mode among the operating modes. [5] The signal processing circuit of claim 1, further comprising a data bus inversion circuit configured to invert and output a signal transmitted via the plurality of first contact pads in response to a data bus inversion signal transmitted via the second contact pad during the data input mode. [6] The signal processing circuit according to claim 1, wherein the signal processing logic circuit is configured to output status information corresponding to a status information output mode by outputting a third signal set via the plurality of first contact pads and a fourth signal via the second contact pad during the status information output mode among the operating modes. [7] A semiconductor device comprising: a plurality of first contact surfaces associated with the input and output data, commands and addresses; a second contact surface; a data bus inversion circuit configured to invert signals transmitted via the plurality of first contact pads during at least one of a data input mode and a data output mode according to a signal input via the second contact pad; and a signal processing logic circuit configured to detect a received request based on a combination of signals input via the plurality of first contact pads and a signal input via the second contact pad during operating modes other than the data input mode and the data output mode. [8] The semiconductor device according to claim 7, wherein the signal processing logic circuit is configured to, during a command input mode among the operating modes, recognize signals transmitted via the plurality of first contact pads as a first command when a logic level of a signal input via the second contact pad has a first value, and recognize signals transmitted via the plurality of first contact pads as a second command when a logic level of a signal input via the second contact pad has a second value. [9] The semiconductor device of claim 8, wherein the signal processing logic circuit is configured to, upon detecting the first command as a read command, detect the second command as a fast read command set to initiate faster data output relative to the read command. [10] The semiconductor device according to claim 7, wherein the signal processing logic circuit is configured to recognize, during an address input mode among the operating modes, signals transmitted through the plurality of first contact pads and a signal transmitted through the second contact pad as addresses. [11] The semiconductor device according to claim 7, wherein the semiconductor device comprises a plurality of memory dies; and wherein the signal processing logic circuit is configured to recognize, during an address input mode among the operating modes, a signal transmitted via the second pad as an address to select one of the plurality of memory dies. [12] The semiconductor device according to claim 7, wherein the signal processing logic circuit is configured to recognize, during a parameter setting mode among the operating modes, a signal transmitted via the second contact pad as an additional flag signal associated with signals transmitted via the plurality of first contact pads. [13] A semiconductor device according to claim 7, wherein the semiconductor device comprises a plurality of memory dies: wherein each of the plurality of memory dies comprises a plurality of unit memory areas; and wherein the signal processing logic circuit is configured to recognize a signal transmitted via the second contact surface as an additional flag signal to select a unit storage area for storing a parameter among the plurality of unit storage areas. [14] The semiconductor device according to claim 7, wherein the signal processing logic circuit is configured to output status information via the plurality of first contact pads and output an additional flag signal associated with the status information via the second contact pad during a status information output mode among the operating modes. [15] The semiconductor device according to claim 7, wherein the signal processing logic circuit is configured to output a status abnormality signal through the plurality of first pads during a status information output mode among the operation modes and output an additional flag signal detecting a type of the status abnormality signal. [16] The semiconductor device according to claim 15, wherein the signal processing logic circuit is configured to set a logic level of a signal inputted via the second pad to a first level to detect that the status abnormality signal is caused by low voltage detection. [17] Data processing system comprising: a semiconductor device configured to invert signals transmitted via a plurality of first contact pads associated with input and output data, commands, and addresses during a data input mode and a data output mode according to a signal input via a second contact pad associated with input and output of a data bus inversion signal, and configured to recognize a combination of signals input via the plurality of first contact pads and a signal input via the second contact pad as a command set during operating modes other than the data input mode and the data output mode; and a controller configured to output the data bus inversion signal via the second contact pad during the data input mode and to invert signals transmitted via the plurality of first contact pads in response to the data bus inversion signal, and configured to provide signals output via the plurality of first contact pads and the second contact pad to the semiconductor device as the command set during the operating modes. [18] The data processing system of claim 17, wherein the semiconductor device is configured to, during a data input mode among the operating modes, recognize signals transmitted via the plurality of first contact pads as a first command when a logic level of a signal input via the second contact pad is at a first value, and recognize signals transmitted via the plurality of first contact pads as a second command different from the first command when a logic level of a signal input via the second contact pad is at a second value. [19] The data processing system of claim 18, wherein the semiconductor device is configured to, upon detecting the first command as a read command, detect the second command as a fast read command set to initiate faster data output relative to the read command. [20] The data processing system according to claim 17, wherein the semiconductor device is configured to recognize, during an address input mode among the operating modes, signals transmitted via the plurality of first contact pads and a signal transmitted via the second contact pad as addresses. [21] The data processing system of claim 20, wherein the semiconductor device comprises a plurality of memory chips and is further configured to recognize, during an address input mode among the operating modes, a signal transmitted via the second contact pad as an address to select one of the plurality of memory chips. [22] The data processing system according to claim 17, wherein the semiconductor device comprises a plurality of memory chips, each memory chip having a plurality of unit memory areas and further configured to detect a signal transmitted via the second contact area as an additional flag signal to select a unit memory area for storing a parameter among the plurality of unit memory areas. [23] The data processing system according to claim 17, wherein the semiconductor device is configured to output status information via the plurality of first contact pads and output a signal detecting a type of the status information via the second contact pad during a status information output mode among the operating modes. [24] The data processing system according to claim 23, wherein the semiconductor device is configured to set a logic level of a signal inputted via the second pad to a first level to detect that the status information is a status abnormality signal caused by low voltage detection. [25] The data processing system of claim 17, wherein the command set comprises at least one of a setup command, at least one address, data, and an acknowledge command transmitted over the plurality of first contact pads, and a signal transmitted over the second contact pad during a period of time when one of the at least one address and the acknowledge command is input. [26] A method comprising: in response to a data bus inversion signal input via a second contact pad in a semiconductor device, inverting signals transmitted via a plurality of first contact pads associated with the input and output data during a data input mode and a data output mode; and Recognizing a combination of signals input via the plurality of first contact pads and a signal input via the second contact pad during operating modes other than the data input mode and the data output mode as a command set.

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