RESISTIVE STORAGE DEVICE WITH FREE ACCESS AND MANUFACTURING METHOD THE SAME

Abstract

The random-access resistive storage device comprises a first ILD layer on a substrate; a first interconnect structure within the first ILD layer; a capping layer on the first interconnect structure and the first ILD layer; a dielectric intermediate layer on the capping layer; a conductive via in the capping layer and the dielectric intermediate layer; and a resistive switching element on the conductive via. The resistive switching element comprises a bottom electrode layer, a top electrode layer, and a resistive switching material layer located between the top electrode layer and the bottom electrode layer. A hard mask layer is placed on the resistive switching element. A second interconnect structure is placed on the hard mask layer and the resistive switching element.The second interconnect structure comprises a flange section that is in direct contact with an upper side wall of the top electrode layer of the resistive switching element.

Description

Background of the invention 1. Field of the invention

[0001] The present invention relates to the field of semiconductor technology, in particular an improved random-access resistive memory device and a manufacturing method thereof. 2. Description of the state of the art

[0002] RRAM, for example, is a memory structure with an array of RRAM cells, each of which stores one data bit using resistance values ​​instead of electronic charge. Specifically, each RRAM cell has a resistive material layer whose resistance can be set to represent a logical "0" or a logical "1".

[0003] In advanced technology nodes, the size of functions is reduced, and the size of memory devices is correspondingly decreased. However, the miniaturization of RRAM devices is limited due to the "forming" operation. During "forming," a high voltage is applied to the RRAM device to create a conductive path in the resistive switching layer.

[0004] During the RRAM manufacturing process, the etching process can damage the upper electrode of the resistive switching element, resulting in uneven surface contours. These irregularities impair the uniform deposition of the barrier layer in the subsequent upper interconnect structure, reducing the reliability of the components.

[0005] Corresponding resistive switching elements are known from the publications US 11 456 415 B2, US 2014 / 0 097 396 A1, US 2017 / 0 054 070 A1, US 2022 / 0 399 495 A1, DE 11 2018 004 641 B4, US 2021 / 0 013 403 A1 and US 11 227 993 B2. Summary of the invention

[0006] The present invention is based on the objective of providing an improved resistive storage device with random access and a manufacturing method thereof in order to eliminate the deficiencies or disadvantages of the prior art.

[0007] The problem is solved by the resistive random access memory device according to claim 1 and the method for manufacturing a resistive random access memory device according to claim 11.

[0008] Further details are set out in the dependent patent claims.

[0009] One aspect of the invention provides a random-access resistive storage device comprising a substrate, a first interlayer dielectric layer (ILD layer) arranged on the substrate, a first interconnect structure arranged in the first ILD layer, a capping layer arranged on the first interconnect structure and the first ILD layer, an interlayer dielectric layer arranged on the capping layer, and a conductive via arranged in the capping layer and the interlayer dielectric layer. The conductive via is electrically coupled to the first interconnect structure. A resistive switching element is arranged at the conductive via.The resistive switching element comprises a bottom electrode layer, a top electrode layer, and a resistive switching material layer located between the top and bottom electrode layers. A hard mask layer is placed on the resistive switching element. A second interconnect structure is arranged on the hard mask layer and the resistive switching element. This second interconnect structure includes a flange section that is in direct contact with an upper sidewall of the top electrode layer of the resistive switching element.

[0010] According to some embodiments, the random access resistive storage device further comprises a side wall spacer element that surrounds the resistive switching element.

[0011] According to some embodiments, the random access resistive storage device further comprises a second interlayer dielectric layer (ILD layer) arranged around the sidewall spacer element and the second interconnect structure.

[0012] According to some embodiments, the side wall spacer element is in direct contact with the resistive switching element and the dielectric intermediate layer.

[0013] According to some embodiments, the side wall spacer element comprises a silicon nitride layer or a silicon oxide layer.

[0014] According to some embodiments, the hard mask layer comprises a silicon oxide layer or a silicon nitride layer.

[0015] According to some embodiments, the conductive via comprises a barrier layer and a tungsten layer on the barrier layer.

[0016] According to some embodiments, the barrier layer comprises titanium nitride.

[0017] According to some embodiments, the capping layer comprises a nitrogen-doped silicon carbide layer (NDC layer).

[0018] According to some embodiments, the dielectric intermediate layer comprises a TEOS-based silicon oxide layer.

[0019] Another aspect of the invention provides a method for forming a resistive random access memory (RRAM) device. A substrate is provided. A first interlayer dielectric layer (ILD layer) is formed on the substrate. A first interconnect structure is built up in the first ILD layer. A capping layer is arranged on the first interconnect structure and the first ILD layer. A dielectric intermediate layer is formed on the capping layer. A conductive via is formed in the capping layer and the dielectric intermediate layer. The conductive via is electrically coupled to the first interconnect structure. A resistive switching element is formed on the conductive via.The resistive switching element comprises a bottom electrode layer, a top electrode layer, and a resistive switching material layer located between the top and bottom electrode layers. A hard mask layer is placed on the resistive switching element. A second interconnect structure is arranged on the hard mask layer and the resistive switching element. This second interconnect structure includes a flange section that is in direct contact with an upper sidewall of the top electrode layer of the resistive switching element.

[0020] According to some embodiments, the method further includes the step of forming a side wall spacer element that surrounds the resistive switching element.

[0021] According to some embodiments, the method further includes the step of forming a second interlayer dielectric layer (ILD layer) around the sidewall spacer element and the second interconnect structure.

[0022] According to some embodiments, the side wall spacer element is in direct contact with the resistive switching element and the dielectric intermediate layer.

[0023] According to some embodiments, the side wall spacer element comprises a silicon nitride layer or a silicon oxide layer.

[0024] According to some embodiments, the hard mask layer comprises a silicon oxide layer or a silicon nitride layer.

[0025] According to some embodiments, the conductive via comprises a barrier layer and a tungsten layer on the barrier layer.

[0026] According to some embodiments, the barrier layer comprises titanium nitride.

[0027] According to some embodiments, the capping layer comprises a nitrogen-doped silicon carbide layer (NDC layer).

[0028] According to some embodiments, the dielectric intermediate layer comprises a TEOS-based silicon oxide layer.

[0029] Preferred embodiments are shown in the various figures and drawings. Brief description of the characters The Fig. 1 to Fig. Figure 6 are schematic views illustrating a method for manufacturing a random access resistive storage device according to an embodiment of the present invention. Detailed description

[0030] In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form part of this description and in which specific embodiments in which the invention can be carried out are shown by way of illustration.

[0031] It will be directed to the Fig. 1 to Fig. Reference is made to Figure 6, which are schematic views illustrating a method for manufacturing a random-access resistive storage device according to an embodiment of the present invention. As in Fig. As illustrated in Figure 1, a substrate 100 is first provided. According to one embodiment of the present invention, the substrate 100 can be a semiconductor substrate, for example a silicon substrate, but is not limited to this. A first interlayer dielectric layer (ILD layer) 110 is formed on the substrate 100. According to one embodiment of the present invention, the first ILD layer 110 can, for example, comprise a material layer with a low dielectric constant (low-k) or a material layer with an ultra-low dielectric constant (ULK). According to one embodiment of the present invention, the thickness of the first ILD layer 110 can, for example, be about 80.0–90.0 nm.

[0032] According to one embodiment of the present invention, a first interconnect structure M1 is formed in the first ILD layer 110. According to one embodiment of the present invention, the first interconnect structure M1 can, for example, be a copper damascus structure built up using a copper damascus process. According to one embodiment of the present invention, a capping layer 120 is formed on the first interconnect structure M1 and the first ILD layer 110. According to one embodiment of the present invention, the capping layer 120 can, for example, comprise a nitrogen-doped silicon carbide layer (NDC layer), but is not limited to this. According to one embodiment of the present invention, the thickness of the capping layer 120 is, for example, about 10.0 nm.

[0033] According to one embodiment of the present invention, a dielectric intermediate layer 130 is formed on the capping layer 120. According to one embodiment of the present invention, the dielectric intermediate layer 130 can, for example, comprise a TEOS-based silicon oxide layer, but is not limited to this. According to one embodiment of the present invention, the thickness of the dielectric intermediate layer 130 can, for example, be about 10.0–50.0 nm.

[0034] As in Fig. As illustrated in Figure 2, a chemical vapor deposition (CVD) process is then carried out to deposit a dielectric intermediate layer 130 on the capping layer 120. According to one embodiment of the present invention, the dielectric intermediate layer 130 comprises, for example, a TEOS-based silicon oxide layer.

[0035] As in Fig. Figure 3 illustrates how a photolithography process, an etching process, and a metallization process are carried out to form a conductive via 200 in the dielectric intermediate layer 130 and the capping layer 120, such that the conductive via 200 is electrically connected to the underlying first interconnect structure M1. According to one embodiment of the present invention, the height of the conductive via 200 is approximately between 20.0 and 60.0 nm, for example, between 40.0 and 50.0 nm. According to one embodiment of the present invention, the conductive via 200 can, for example, comprise a barrier layer 202 and a tungsten layer 203 arranged on the barrier layer 202. According to one embodiment of the present invention, the barrier layer 202 can, for example, comprise titanium nitride, but is not limited to this.To remove the excess tungsten layer 203 on the dielectric intermediate layer 130, a chemical-mechanical tungsten polishing process (WCMP) can be carried out.

[0036] As in Fig. Figure 4 illustrates how a deposition process is then carried out to form a film stack structure 300 on the conductive via 200 and the dielectric intermediate layer 130. According to one embodiment of the present invention, the film stack structure 300 can, for example, comprise a bottom electrode layer 310, a top electrode layer 320, a top electrode layer 330, and a hard mask layer 340. According to one embodiment of the present invention, the bottom electrode layer 310 can, for example, comprise TaN, TiN, Pt, Ir, Ru, or W, but is not limited to this. The resistive switching layer 320 can, but is not limited to, comprise hafnium oxide, tantalum oxide, titanium, titanium oxide, or combinations thereof. The top electrode layer 330 can, but is not limited to, comprise TiN, TaN, Pt, Ir, or W.The hard mask layer 340 may include a silicon oxide layer or a silicon nitride layer, but is not limited to either.

[0037] As in Fig. Figure 5 illustrates how a photolithography and an etching process are then carried out to structure the film stack structure 300 into a resistive switching element 300a. At this point, the hard mask layer 340 can remain on the top electrode layer 330 with a predetermined thickness. According to one embodiment of the present invention, the aforementioned predetermined thickness can, for example, be in the range of 0–50.0 nm, but is not limited thereto.

[0038] As in Fig. Figure 6 illustrates a deposition process to form a sidewall spacer SP surrounding the resistive switching element 300a. According to one embodiment of the present invention, the sidewall spacer SP may, for example, comprise a silicon nitride layer or a silicon oxide layer. In one embodiment of the present invention, the sidewall spacer SP is in direct contact with the resistive switching element 300a and the dielectric intermediate layer 130. Subsequently, a deposition process is carried out to form a second dielectric intermediate layer (ILD) 160 on the sidewall spacer SP and the resistive switching element 300a, such that the second ILD layer 160 covers the remaining hard mask layer 340.According to one embodiment of the present invention, the second ILD layer 160 may, for example, comprise a material layer with a low dielectric constant or a material layer with an ultra-low dielectric constant.

[0039] Subsequently, a photolithography, etching, and metallization process are used to form a second interconnect structure M2 on the second ILD layer 160, which is arranged on the hard mask layer 340 and the resistive switching element 300a. The second interconnect structure M2 comprises a flange section LP that is in direct contact with the upper side wall S1 of the top electrode layer 330 of the resistive switching element 300a. According to one embodiment of the present invention, for example, the flange section LP extends downwards by no more than half the thickness of the top electrode layer 330.

[0040] Since the entire (or at least the largest part, for example at least 80% of the area) of the upper surface of the upper electrode layer 330 of the resistive switching element 300a is covered by the remaining hard mask layer 340, the second interconnect structure M2 is only in direct contact with the upper side wall S1 (or the upper side wall S1 and the upper corner) of the upper electrode layer 330. During operation, current flows through the flange section LP and the upper side wall S1 of the top electrode layer 330 to complete the resistive circuit of the resistive switching element 300a.

[0041] Structurally, as in Fig.As illustrated in Figure 6, the random-access resistive storage device 1 comprises: a substrate 100; a first ILD layer 110 arranged on the substrate 100; a first via structure M1 arranged on the first ILD layer 110; a capping layer 120 arranged on the first interconnect structure M1 and the first ILD layer 110; a dielectric intermediate layer 130 arranged on the capping layer 120; and a conductive via 200 arranged in the capping layer 120 and the dielectric intermediate layer 130. The conductive via 200 is electrically connected to the first interconnect structure M1.

[0042] According to one embodiment of the present invention, the resistive storage device 1 further comprises: a resistive switching element 300a, which is arranged on the conductive via 200. The resistive switching element 300a comprises a bottom electrode layer 310, a top electrode layer 330 and a resistive switching layer 320 between the top electrode layer 330 and the bottom electrode layer 310.

[0043] According to one embodiment of the present invention, the resistive storage device 1 further comprises a hard mask layer 340, which is arranged on the resistive switching element 300a.

[0044] According to one embodiment of the present invention, the resistive storage device 1 further comprises: a second interconnect structure M2, which is arranged on the hard mask layer 340 and the resistive switching element 300a. The second interconnect structure M2 comprises a flange section LP, which is in direct contact with the upper side wall S1 of the top electrode layer 330 of the resistive switching element 300a.

[0045] According to one embodiment of the present invention, the resistive storage device 1 further comprises: a side wall spacer element SP surrounding the resistive switching element 300a.

[0046] According to one embodiment of the present invention, the resistive storage device 1 further comprises: a second ILD layer 160 arranged around the side wall spacer element SP and the second interconnect structure M2.

[0047] According to one embodiment of the present invention, the side wall spacer element SP is in direct contact with the resistive switching element 300a and the dielectric intermediate layer 130.

[0048] According to one embodiment of the present invention, the side wall spacer SP comprises a silicon nitride layer or a silicon oxide layer.

[0049] According to one embodiment of the present invention, the hard mask layer 340 comprises a silicon oxide mask layer or a silicon nitride mask layer.

[0050] According to one embodiment of the present invention, the conductive via 200 comprises a barrier layer 202 and a tungsten layer 203 arranged on the barrier layer 202.

[0051] According to one embodiment of the invention, the barrier layer comprises 202 titanium nitride.

[0052] According to one embodiment of the present invention, the capping layer 120 comprises a nitrogen-doped silicon carbide layer.

[0053] According to one embodiment of the present invention, the dielectric intermediate layer 130 comprises a silicon oxide layer based on TEOS.

Claims

[1] Resistive random access memory device, RRAM device (RRAM: Resistive Random Access Memory), comprising: a substrate; a first interlayer dielectric layer, ILD layer, which is arranged on the substrate; a first interconnect structure built in the first ILD layer; a capping layer that is placed on top of the first interconnect structure and the first ILD layer; a dielectric intermediate layer that is arranged on the capping layer; a conductive via located in the capping layer and the dielectric intermediate layer, wherein the conductive via is electrically coupled to the first interconnect structure; a resistive switching element arranged on the conductive via, wherein the resistive switching element comprises a bottom electrode layer, a top electrode layer and a resistive switching material layer arranged between the top electrode layer and the bottom electrode layer; a hard mask layer that is arranged on the resistive switching element; a second interconnect structure arranged on the hard mask layer and the resistive switching element, wherein the second interconnect structure comprises a flange section in direct contact with an upper side wall of the top electrode layer of the resistive switching element; wherein the flange section is not in direct contact with a side wall of the resistive switching material layer and the flange section does not extend downwards further than half the thickness of the top electrode layer. [2] Resistive storage device with random access according to claim 1, further comprising: a side wall spacer element that surrounds the resistive switching element. [3] Resistive storage device with random access according to claim 2, further comprising: a second interlayer dielectric layer, ILD layer, which is arranged around the sidewall spacer element and the second interconnect structure. [4] Resistive storage device with random access according to claim 2, wherein the side wall spacer element is in direct contact with the resistive switching element and the dielectric intermediate layer. [5] Resistive storage device with random access according to claim 2, wherein the side wall spacer element is in direct contact with the top electrode layer and the second interconnect structure. [6] Resistive storage device with random access according to claim 1, wherein the top electrode layer comprises a top surface which is connected to the upper side wall of the top electrode layer, and wherein at least 80% of the area of ​​the top surface is covered by the hard mask layer. [7] Resistive random access storage device according to claim 1, wherein the conductive via comprises a barrier layer and a tungsten layer on the barrier layer. [8] Resistive storage device with random access according to claim 7, wherein the barrier layer comprises titanium nitride. [9] Resistive storage device with random access according to claim 2, wherein the flange section is in direct contact with the side wall spacer element. [10] Resistive random access storage device according to claim 1, wherein the hard mask layer comprises a top surface and the second interconnect structure is in direct contact with the top surface of the hard mask layer. [11] Method for manufacturing a resistive random access memory device, RRAM device (RRAM: Resistive Random Access Memory), comprising: Providing a substrate; Formation of a first interlayer dielectric layer, ILD layer, on the substrate; Forming a first interconnect structure in the first ILD layer; Forming a capping layer on the first interconnect structure and the first ILD layer; Formation of a dielectric intermediate layer on the capping layer; Forming a conductive via in the capping layer and the dielectric intermediate layer, wherein the conductive via is electrically coupled to the first interconnect structure; Forming a resistive switching element on the conductive via, wherein the resistive switching element comprises a bottom electrode layer, a top electrode layer and a resistive switching material layer arranged between the top electrode layer and the bottom electrode layer; Forming a hard mask layer on the resistive switching element; Forming a second interconnect structure on the hard mask layer and the resistive switching element, wherein the second interconnect structure comprises a flange section that is in direct contact with an upper side wall of the top electrode layer of the resistive switching element; wherein the flange section is not in direct contact with a side wall of the resistive switching material layer and the flange section does not extend downwards further than half the thickness of the top electrode layer. [12] The method of claim 11, further comprising: Forming a side wall spacer element that surrounds the resistive switching element. [13] The method of claim 12, further comprising: Forming a second interlayer dielectric layer, ILD layer, around the sidewall spacer element and the second interconnect structure. [14] Method according to claim 12, wherein the side wall spacer element is in direct contact with the resistive switching element and the dielectric intermediate layer. [15] Method according to claim 12, wherein the side wall spacer element is in direct contact with the top electrode layer and the second interconnect structure. [16] Method according to claim 11, wherein the top electrode layer comprises a top surface which is connected to the upper side wall of the top electrode layer, and wherein at least 80% of the area of ​​the top surface is covered by the hard mask layer. [17] Method according to claim 11, wherein the conductive via comprises a barrier layer and a tungsten layer on the barrier layer. [18] Method according to claim 17, wherein the barrier layer comprises titanium nitride. [19] Method according to claim 11, wherein the flange section is in direct contact with the side wall spacer element. [20] Method according to claim 11, wherein the hard mask layer comprises a top surface and the second interconnect structure is in direct contact with the top surface of the hard mask layer.

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