DISPLAY DEVICE WITH A PIXEL DRIVER CIRCUIT

Abstract

A display device is disclosed for improving the display of low gray-level images and increasing the drive current. A light-emitting device (500) and a pixel drive circuit electrically connected to the light-emitting device (500) can be arranged in each pixel region (PA). The drive circuit for the pixels can comprise a drive thin-film transistor. A semiconductor structure (221) of the drive thin-film transistor can comprise a first active region (A1) and a second active region (A2) parallel to the first active region (A1). A first sub-gate (223a) of the drive thin-film transistor can be arranged on a first active channel (221c1) of the first active region (A1) and a second active channel (221c2) of the second active region (A2). The driver thin-film transistor may have a second sub-gate (223b) between the semiconductor structure (221) and the first sub-gate (223a).The second active region (A2) may have a portion disposed outside the second sub-gate (223b).

Description

CROSS REFERENCE TO RELATED APPLICATIONSThis application claims the benefit of Korean Patent Application No. 10-2023-0179958 filed on Dec. 12, 2023.Technical FieldThe present disclosure relates to a display apparatus in which a pixel driving circuit electrically connected to a light emitting device is disposed in each pixel region.Prior ArtGenerally, a display device provides an image to a user. For example, the display device may include a plurality of pixel regions. Each of the pixel regions can realize a specific color. For example, a light emitting device may be disposed in each pixel region. The light emitting device may emit light indicating a certain color. The light emitting device may include a light emitting layer between a first electrode and a second electrode.A pixel driving circuit is electrically connected to the light emitting device and may be disposed in each pixel region. An operation of the light emitting device in each pixel region may be controlled by the pixel driving circuit in the corresponding pixel region. The pixel driving circuit of each pixel region may supply a driving current corresponding to a data signal to the light emitting device of the corresponding pixel region according to a gate signal for one frame. The pixel driving circuit of each pixel region may include a driving thin film transistor and at least one switching thin film transistor.The driving thin film transistor of each pixel region may generate the driving current corresponding to the data signal. For example, gray levels of the colors realized by each pixel region may be determined by the driving current generated by the driving thin film transistor of the corresponding pixel region. Therefore, in the display device, the driving thin film transistor of each pixel region may have different electrical characteristics from the switching thin film transistor of the corresponding pixel region. Therefore, in the display device, a method of forming the pixel driving circuit in each pixel region may be complicated. In addition, in the display device, the quality of the image may deteriorate due to the difference in characteristics of the driving thin film transistors in each pixel region.The description provided in the section "Prior Art" should not be considered as prior art alone because it is mentioned in or associated with the section "Prior Art". The section "prior art" may include information describing one or more aspects of the subject technology.BRIEF DESCRIPTIONAccordingly, the present disclosure is directed to a display device that substantially eliminates one or more problems due to limitations and disadvantages of the related art.An object of the present disclosure is to provide a display device capable of simplifying a method of manufacturing the pixel driving circuit in each pixel region.Another object of the present disclosure is to provide a display device that can increase both the S factor of the thin film transistor in each pixel region and the driving current generated by the thin film transistor.Additional advantages, objects, and features of the disclosure will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following, or may be learned from practice of the disclosure. The objects and other advantages of the disclosure may be realized and attained by the structures particularly pointed out in the written description and claims, and the appended drawings.To achieve these objects and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, display devices according to the independent claims are provided. Further embodiments are described in the dependent claims. In one aspect, a display device is provided that includes a semiconductor structure. The semiconductor structure has a first active region and a second active region. The second active region is arranged parallel to the first active region. A first sub-gate is disposed on the semiconductor structure. The first sub-gate overlaps a first active channel of the first active region and a second active channel of the second active region. A second sub-gate is disposed between the semiconductor structure and the first sub-gate. The second sub-gate is insulated from the semiconductor structure. A first active drain of the first active region and a second active drain of the second active region are electrically connected to a drain electrode. A first active source of the first active region and a second active source of the second active region are electrically connected to a source electrode. The width of the second sub-gate on the second active channel is smaller than the width of the second sub-gate on the first active channel.The width of the second sub-gate on the first active channel may be greater than the width of the first sub-gate on the first active channel.The second sub-gate may be electrically connected to the first sub-gate. The first sub-gate may be disposed on a different layer than the second sub-gate.The first sub-gate may be disposed on a layer other than the drain electrode and the source electrode.The second active channel may include a first sub-channel and a second sub-channel. The first sub-channel may overlap the second sub-gate. The second sub-channel may be disposed outside the second sub-gate. A distance between the first sub-channel and the second sub-gate may be smaller than a distance between the second sub-channel and the first sub-gate.A resistance of the second sub-channel may be equal to a resistance of the first sub-channel.The second active channel may include a third sub-channel disposed outside the second sub-gate. A distance between the third sub-channel and the first sub-gate may be greater than a distance between the first sub-channel and the second sub-gate. The first sub-channel may be disposed between the second sub-channel and the third sub-channel.The semiconductor structure may be constructed from an oxide semiconductor. The amount of oxygen contained in the second active channel may be the same as the amount of oxygen contained in the first active channel.In another aspect, a display device is provided that includes a device substrate. A first thin film transistor, a second thin film transistor, and a light emitting device are disposed on a pixel region of the device substrate. The first thin film transistor includes a first semiconductor structure and a first gate electrode. The second thin film transistor has a second semiconductor structure and a second gate electrode. The light emitting device is electrically connected to the second thin film transistor. The second gate electrode includes a first sub-gate and a second sub-gate. The first sub-gate overlaps a channel region of the second semiconductor structure. The second sub-gate is disposed between the second semiconductor structure and the first sub-gate. The channel region of the second semiconductor structure includes a first active channel and a second active channel. The first active channel has a portion overlapping with the second sub-gate. The second active channel is disposed outside the second sub-gate. A resistance of the second active channel is less than a resistance of the first active channel. The first active channel includes a first sub-channel and a second sub-channel. The first sub-channel overlaps the second sub-gate. The second sub-channel is disposed outside the second sub-gate.A resistance of the second sub-channel may be the same as a resistance of the second active channel.The second sub-gate may include a different material than the first sub-gate.The first gate electrode may include a same material as the second sub-gate.A first gate insulating layer may be disposed between the second semiconductor structure and the second sub-gate. A second gate insulating layer may be disposed between the second sub-gate and the first sub-gate. The first gate electrode may be disposed between the first gate insulating film and the second gate insulating film.An upper interlayer insulating layer may be disposed on the second gate insulating layer. The upper interlayer insulating film may cover the first sub-gate. A storage capacitor may be disposed on the pixel region of the device substrate. The storage capacitor may include a first capacitor electrode, a second capacitor electrode, and a third capacitor electrode. The first capacitor electrode may be disposed between the first gate insulating film and the second gate insulating film. The second capacitor electrode may be disposed between the second gate insulating film and the upper interlayer insulating film. The third capacitor electrode may be disposed on the upper interlayer insulating layer.A channel region of the first semiconductor structure may have a greater resistance than a drain region and a source region of the first semiconductor structure. The first sub-channel may have a same resistance as the channel region of the first semiconductor structure.Other systems, methods, features, and advantages will become apparent to those skilled in the art upon consideration of the following figures and detailed description. It is intended that all such additional systems, methods, features, and advantages be included in this specification, be within the scope of the present disclosure, and be protected by the following claims. Nothing in this section should be understood as limiting these claims. Other aspects and advantages are discussed further below in connection with embodiments of the disclosure.Both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed inventive concepts.BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings, which are provided to further understand the present disclosure and form a part of this application, illustrate one or more aspects of the present disclosure and together with the description serve to explain the principle of the present disclosure. In the drawings: FIG. 1 is a schematic view of a display device according to an aspect of the present disclosure; FIG. 2 is a view showing a circuit of a pixel region in the display device according to the aspect of the present disclosure; FIG. 3 is a view showing a cross section along I-I' of FIG. 1 and a cross section of the pixel region in the display device according to the aspect of the present disclosure; FIG. 4 is a plan view showing a second thin film transistor of the pixel region in the display device according to the aspect of the present disclosure; FIG. 5 is a view with cross sections taken along II-II' and III-III' of FIG. 4; FIG. 6 is a view with cross sections taken along IV-IV' of FIG. 4; FIG. 7 is an enlarged view of the K1 region in FIG. 5 ; FIG. 8 is an enlarged view of the K2 region in FIG. 5 ; FIG. 9 is a diagram showing a driving current depending on a voltage applied to a gate electrode according to a structure of a thin film transistor; and FIGS. 10 to 22 are views of the display device according to another aspect of the present disclosure.In the drawings and the detailed description, unless otherwise specified, the same reference numerals refer to the same elements, features, and structures. The relative size and representation of these elements may be exaggerated for clarity, illustration and convenience.DETAILED DESCRIPTIONReference will now be made in detail to embodiments of the present disclosure, which are illustrated by way of example in the accompanying drawings. In the following description, if a detailed description of known functions or configurations related to this document unnecessarily obscures the gist of the inventive concept, the detailed description will be omitted. The described sequence of method steps and / or acts are exemplary; the sequence of steps and / or acts is not limited to the sequence set forth herein and may be modified as known in the art, except for steps and / or acts that necessarily proceed in a particular order. Like reference numerals designate like elements throughout. Names of the respective elements used in the following explanations have been selected only for the sake of simplicity in the description practice, and therefore may be different from those used in the actual products.Hereinafter, details of the above-mentioned objects, technical configurations, and operational effects of the embodiments of the present disclosure will be clearly understood from the following detailed description with reference to the drawings illustrating some embodiments of the present disclosure. The embodiments of the present disclosure are provided herein in order that the technical concept of the present disclosure can be satisfactorily understood by those skilled in the art. Therefore, the present disclosure can be realized in other embodiments, and is not limited to the embodiments described below. Any embodiment described herein as "example" is not necessarily to be understood as preferred or advantageous over other embodiments.The shapes, sizes, ratios, angles, numbers, and the like illustrated in the drawings to describe various exemplary embodiments of the present disclosure are given by way of example only. Therefore, the present disclosure is not limited to the drawings. The same or similar elements are denoted by the same reference numerals throughout the specification unless otherwise indicated. In cases where the detailed description of the corresponding known function or configuration might unnecessarily obscure an important point of the present disclosure, a detailed description of this known function or configuration may be omitted in the following description.In the design of an element, it is assumed that the element includes an error or tolerance range, even if this is not expressly described.Moreover, the same or very similar elements may be denoted by the same reference numerals throughout the specification, and in the drawings, the lengths and thicknesses of layers and regions may be exaggerated for convenience. When a first element is referred to as being "on" a second element, a third element may be disposed between the first and second elements, although the first element may be disposed on the second element to contact the second element.When describing positional relationships, for example, when describing the positional relationships between two parts with "on", "over", "under", "above", "below", "near", "near" or "adjacent", "next" or the like, one or more other parts may be arranged between the two parts unless a further limiting term such as "immediate(e)", "immediate(e)" or "near(e)" is used. For example, when a structure is described as being "on", "over", "under", "above", "below", "near", "adjacent", or "adjacent" to another structure, this description should be construed to include both a case where the structures contact each other and a case where a third structure is interposed or interposed therebetween. Moreover, the terms "left", "right", "top", "bottom", "down", "up", "top", "bottom" and the like refer to an arbitrary reference frame.Here, terms such as "first" and "second" may be used to distinguish any element from another. However, the first element and the second element can be arbitrarily designated by those skilled in the art without departing from the technical spirit of the present disclosure.The terms used in the description of the present disclosure are merely for describing particular embodiments and are not intended to limit the scope of the present disclosure. For example, an element described in the singular is intended to include a plurality of elements unless the context clearly indicates otherwise. Moreover, in the description of the present disclosure, the terms "comprises", "includes", and "includes" are intended to indicate the presence of certain features, integers, steps, acts, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, acts, elements, components, and / or combinations thereof.Unless used "directly" or "directly", the terms "connected" and "coupled" may also include two components being "connected" or "coupled" by one or more other components located between the two components.As will be sufficiently understood by those skilled in the art, features of various embodiments of the present disclosure may be partially or wholly coupled or combined with each other and may cooperate and operate in various ways. Embodiments of the present disclosure may be carried out independently of each other or together in a mutually dependent relationship.Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. It will be further understood that terms as defined in commonly used dictionaries should be construed as having a meaning that is consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein. Thus, those skilled in the art will understand that the term "part," "portion," or "unit" may refer to, for example, a separate circuit or structure, an integrated circuit, a computing portion of a switching device, or any structure configured to perform a described function.Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Further, all components of each display device are operatively coupled and configured according to all embodiments of the present disclosure.FIG. 1 is a view schematically showing a display device according to an aspect of the present disclosure. FIG. 2 is a view showing a circuit of a pixel region in the display device according to the aspect of the present disclosure.Referring to FIGS. 1 and 2, the display apparatus according to the aspect of the present disclosure may include a display panel DP. The display panel DP may generate an image provided to a user. For example, the display panel DP may include a plurality of pixel regions PA. In each pixel area PA, various signals may be provided via the signal lines GL, DL, and PL. The signal lines GL, DL, and PL may include, for example, gate lines GL that sequentially apply a gate signal to each pixel area PA, data lines DL that apply a data signal to each pixel area PA, and power supply lines PL that supply a power supply voltage to each pixel area PA. The gate lines GL may be electrically connected to a gate driver GD. The data lines DL may be electrically connected to a data driver DD. The supply voltage supply lines PL may be electrically connected to a power supply unit PU.The gate driver GD and the data driver DD may be controlled by a timing controller TC. For example, the gate driver GD may receive clock signals, reset signals, and a start signal of the timing controller TC, and the data driver DD may receive digital video data and a source clock signal from the timing controller TC.The display panel DP may include a display area AA including the pixel areas PA and a bezel area BZ outside the display area AA. The enclosure area BZ may be disposed outside the pixel areas PA. For example, the enclosure area BZ may surround the display area AA. Each of the signal lines GL, DL, and PL may be electrically connected to each pixel area PA via at least a part of the enclosure area BZ.At least one of the gate driver GD, the data driver DD, the power supply unit PU, and the timing controller TC may be disposed on the surrounding area BZ of the display panel DP. For example, the display device according to the aspect of the present disclosure may be a gate-in-panel (GIP) type display device in which the gate driver GD is formed on the surrounding area BZ of the display panel DP.Each of the pixel areas PA can realize a specific color. For example, a light emitting device 500 and a pixel driving circuit DC electrically connected to the light emitting device 500 may be disposed in each pixel area PA. The pixel driving circuit DC of each pixel region PA may be electrically connected to the signal lines GL, DL, and PL. For example, the pixel driving circuit DC of each pixel region PA may be electrically connected to one of the gate lines GL, one of the data lines DL, and one of the power supply voltage supply lines PL. The pixel driving circuit DC of each pixel region PA may supply a driving current corresponding to the data signal corresponding to the gate signal for one frame to the light emitting device 500 of the corresponding pixel region PA. For example, the pixel driving circuit DC of each pixel region PA may include, but is not limited to, a first thin film transistor TR 1, a second thin film transistor TR 2, and a storage capacitor Cst, and may include more or fewer elements than illustrated. For example, 3T1C, 4T1C, 5T1C, 3T2C, 4T2C, 5T2C, 6T2C, 7T1C, 7T2C, 8T2C structures, etc. are also possible. In addition, more or fewer transistors and capacitors may be included in the pixel driving circuit DC for the pixels.FIG. 3 is a view showing a cross section along I-I' of FIG. 1 and a cross section of the pixel region in the display device according to the aspect of the present disclosure.Referring to FIGS. 2 and 3, the first thin film transistor TR 1 of each pixel region PA may transmit the data signal corresponding to the gate signal to the second thin film transistor TR 2 of the corresponding pixel region PA. For example, the first thin film transistor TR 1 of each pixel region PA may be a switching thin film transistor. The first thin film transistor TR 1 of each pixel region PA may include a first semiconductor structure 211, a first gate electrode 213, a first drain electrode 215, and a first source electrode 217. The first gate electrode 213 of each pixel region PA may be electrically connected to the corresponding gate line GL, and the first drain electrode 215 of each pixel region PA may be electrically connected to the corresponding gate line DL.The first semiconductor structure 211 may include a semiconductor material. For example, the first semiconductor structure 211 may include an oxide semiconductor such as IGZO. In another example, the oxide semiconductors may include a metal oxide such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or a combination of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti), and its oxide. In particular, the oxide semiconductor may include, but is not limited to, zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO). The first semiconductor structure 211 may include a first drain region, a first channel region, and a first source region. The first channel region may be disposed between the first drain region and the first source region. The first drain region and the first source region may have a lower resistance than the first channel region. For example, the first drain region and the first source region may comprise a conductive region made of an oxide semiconductor. The first channel region may be a region of an oxide semiconductor that is non-conductive.The first gate electrode 213 may be disposed on a portion of the first semiconductor structure 211. For example, the first gate electrode 213 may overlap the first channel region of the first semiconductor structure 211. The first drain region and the first source region of the first semiconductor structure 211 may be arranged outside the first gate electrode 213. The first gate electrode 213 may include a conductive material. For example, the first gate electrode 213 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first gate electrode 213 may be separated from the first semiconductor structure 211. The first gate electrode 213 may be insulated from the first semiconductor structure 211. For example, the first drain region of the first semiconductor structure 211 may be electrically connected to the first source region of the first semiconductor structure 211 according to a voltage applied to the first gate electrode 213.The first drain electrode 215 may include a conductive material. For example, the first drain electrode 215 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first drain electrode 215 may include a different material than the first gate electrode 213. For example, the first drain electrode 215 may be disposed on a different layer from the first gate electrode 213. The first drain electrode 215 may be insulated from the first gate electrode 213. The first drain electrode 215 may be electrically connected to the first drain region of the first semiconductor structure 211.The first source electrode 217 may include a conductive material. For example, the first source electrode 217 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first source electrode 217 may include a different material than the first gate electrode 213. For example, the first source electrode 217 may be disposed on a different layer from the first gate electrode 213. The first source electrode 217 may be insulated from the first gate electrode 213. The first source electrode 217 may be disposed on the same layer as the first drain electrode 215. The first source electrode 217 may include a same material as the first drain electrode 215. The first source electrode 217 may be formed by the same method as the first drain electrode 215. For example, the first source electrode 217 may be formed simultaneously with the first drain electrode 215. The first source electrode 217 may be separated from the first drain electrode 215. The first source electrode 217 may be electrically connected to the first source region of the first semiconductor structure 211.FIG. 4 is a plan view showing a second thin film transistor of the pixel region in the display apparatus according to the aspect of the present disclosure. FIG. 5 is a view showing cross sections along II-II' and III-III' of FIG. 4. FIG. 6 is a view showing cross sections taken along IV-IV' of FIG. 4. FIG. 7 is an enlarged view of the K1 region in FIG. 5, FIG. 8 is an enlarged view of the K2 region in FIG. 5.As illustrated in FIGS. 2 to 8, the second thin film transistor TR 2 of each pixel region PA may generate the driving current corresponding to the data signal. For example, the second thin film transistor TR 2 of each pixel region PA may be a driving thin film transistor. The second thin film transistor TR 2 of each pixel region PA may include a second semiconductor structure 221, a second gate electrode 223, a second drain electrode 225, and a second source electrode 227. For example, the second gate electrode 223 of each pixel region PA may be electrically connected to the first source electrode 217 of the corresponding pixel region PA, and the second drain electrode 225 of each pixel region PA may be electrically connected to the corresponding supply voltage supply line PL.The second semiconductor structure 221 may include a first active region A 1 and a second active region A 2, as illustrated in FIGS. 4, 7, and 8. The second active region A 2 may be disposed side by side with the first active region A 1. The second active region A 2 may extend parallel to the first active region A 1. For example, the length of the second active region A 2 may be the same as the length of the first active region A 1. The second active region A 2 may have the same width as the first active region A 1. For example, a side surface of the second active region A 2 may be in direct contact with a side surface of the first active region A 1.The first active region A 1 may include a semiconductor material. For example, the first active region A 1 may include an oxide semiconductor such as IGZO. The first active region A 1 may include a same material as the first semiconductor structure 211. The first active region A 1 may be disposed on the same layer as the first semiconductor structure 211. The first active region A 1 may be formed by a same method as the first semiconductor structure 211. For example, the first active region A 1 may be formed simultaneously with the first semiconductor structure 211.The first active region A 1 may include a first active channel 221 c 1 between a first active drain 221 d 1 and a first active source 221 s 1. The first active drain 221 d 1 and the first active source 221 s 1 may have a smaller resistance than the first active channel 221 c 1. For example, the first active drain 221 d 1 and the first active source 221 s 1 may include a conductive region made of an oxide semiconductor. The first active channel 221 c 1 may be a region of an oxide semiconductor that is non-conductive. For example, the first active channel 221 c 1 may have a same resistance as the first channel region.The second active region A 2 may include a semiconductor material. For example, the second active region A 2 may include an oxide semiconductor such as IGZO. The second active region A 2 may comprise a same material as the first active region A 1. The second active region A 2 may be disposed on a same layer as the first active region A 1. The second active region A 2 may be formed by a same method as the first active region A 1. For example, the second active region A 2 may be formed simultaneously with the first active region A 1. A boundary layer between the first active region A 1 and the second active region A 2 may not be recognizable.The second active region A 2 may include a second active channel 221 c 2 between a second active drain 221 d 2 and a second active source 221 s 2. The second active drain 221 d 2 and the second active source 221 s 2 may have a smaller resistance than the second active channel 221 c 2. For example, the second active drain 221 d 2 and the second active source 221 s 2 may include a conductive region made of an oxide semiconductor. The second active channel 221 c 2 may be a region of an oxide semiconductor that is non-conductive.The second active drain 221 d 2 may be in direct contact with the first active drain 221 d 1. The first active drain 221 d 1 and the second active drain 221 d 2 may form a second drain region of the second semiconductor structure 221. For example, a length of the second active drain 221 d 2 may be the same as a length of the first active drain 221 d 1. A resistance of the second active drain 221 d 2 may be the same as a resistance of the first active drain 221 d 1. For example, the second active drain 221 d 2 may be formed simultaneously with the first active drain 221 d 1.The second active source 221 s 2 may be in direct contact with the first active source 221 s 1. The first active source 221 s 1 and the second active source 221 s 2 may form a second source region of the second semiconductor structure 221. For example, a length of the second active source 221 s 2 may be the same as a length of the first active source 221 s 1. The second active source 221 s 2 may have a same resistance as the first active source 221 s 1. For example, the second active source 221 s 2 may be formed simultaneously with the first active source 221 s 1.The second active channel 221 c 2 may be in direct contact with the first active channel 221 c 1. The first active channel 221 c 1 and the second active channel 221 c 2 may form a second channel region 221 cof the second semiconductor structure 221. For example, a length of the second active channel 221 c 2 may be the same as a length of the first active channel 221 c 1. The second active channel 221 c 2 may have a same resistance as the first active channel 221 c 1. For example, the amount of oxygen that the second active channel 221 c 2 has may be the same as the amount of oxygen that the first active channel 221 c 1 has.The second gate electrode 223 may be disposed on a portion of the second semiconductor structure 221. For example, the second gate electrode 223 may be disposed on the second channel region 221 cof the second semiconductor structure 221. The second drain region and the second source region of the second semiconductor structure 221 may be arranged outside the second gate electrode 223. The second gate electrode 223 may include a first sub-gate 223 aand a second sub-gate 223 b.The first sub-gate 223 amay be disposed on the second channel region 221 cof the second semiconductor structure 221. For example, the first active channel 221 c 1 and the second active channel 221 c 2 of the second semiconductor structure 221 may overlap the first sub-gate 223 a. The second drain region and the second source region of the second semiconductor structure 221 may be arranged outside the first sub-gate 223 a. The first sub-gate 223 amay include a conductive material. For example, the first sub-gate 223 amay include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first sub-gate 223 amay be insulated from the second semiconductor structure 221.The second sub-gate 223 bmay extend parallel to the first sub-gate 223 a. The second sub-gate 223 bmay be disposed on a different layer from the first sub-gate 223 a. For example, the second sub-gate 223 bmay be arranged between the second semiconductor structure 221 and the first sub-gate 223 a. The second sub-gate 223 bmay include a conductive material. The second sub-gate 223 bmay include, for example, a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second sub-gate 223 bmay include a different material than the first sub-gate 223 a. The second sub-gate 223 bmay be insulated from the second semiconductor structure 221.The second sub-gate 223 bmay overlap the first active channel 221 c 1 of the second semiconductor structure 221. For example, the second sub-gate 223 bmay include a region arranged between the first active channel 221 c 1 of the second semiconductor structure 221 and the first sub-gate 223 a. A width of the second sub-gate 223 bon the first active channel 221 c 1 may be larger than a width of the first sub-gate 223 aon the first active channel 221 c 1. For example, the first active channel 221 c 1 of the second semiconductor structure 221 may have an electrical conductivity corresponding to a voltage applied to the second sub-gate 223 b. The first active drain 221 d 1 may be electrically connected to the first active source 221 s 1 when a voltage is applied to the second sub-gate 223 b.The second sub-gate 223 bmay include a region on the second active channel 221 c 2 of the second semiconductor structure 221. A width of the second sub-gate 223 bon the second active channel 221 c 2 may be smaller than a width of the second sub-gate 223 bon the first active channel 221 c 1. A portion of the second active channel 221 c 2 may be disposed outside the second sub-gate 223 b. For example, the second active channel 221 c 2 may include a first sub-channel SC 1, a second sub-channel SC 2, and a third sub-channel SC 3 that are arranged side by side between the second active drain 221 d 2 and the second active source 221 s 2, the second sub-gate 223 bmay overlap the first sub-channel SC 1 of the second active channel 221 c 2, and the second sub-channel SC 2 and the third sub-channel SC 3 of the second active channel 221 c 2 may be arranged outside the second sub-gate 223 b. The first sub-channel SC 1 of the second active channel 221 c 2 may have an electrical conductivity corresponding to a voltage applied to the second sub-gate 223 b. The second sub-channel SC 2 and the third sub-channel SC 3 of the second active channel 221 c 2 may have an electrical conductivity based on a voltage applied to the first sub-gate 223 a.The first sub-channel SC 1 may be disposed between the second sub-channel SC 2 and the third sub-channel SC 3. For example, the second sub-channel SC 2 may be disposed between the second active drain 221 d 2 and the first sub-channel SC 1, and the third sub-channel SC 3 may be disposed between the first sub-channel SC 1 and the second active source 221 s 2. A resistance of the second sub-channel SC 2 and a resistance of the third sub-channel SC 3 may be the same as a resistance of the first sub-channel SC 1. A distance between the first sub-channel SC 1 and the second sub-gate 223 bmay be smaller than a distance between the second sub-channel SC 2 and the first sub-gate 223 aand a distance between the third sub-channel SC 3 and the first sub-gate 223 a.In a usual thin film transistor, the voltage applied to the gate electrode to form a conductive channel in the channel region of the semiconductor structure is defined as a threshold voltage. The threshold voltage of the thin film transistor is proportional to the distance between the semiconductor structure and the gate electrode of the corresponding thin film transistor. That is, in the display apparatus according to the aspect of the present disclosure, a first threshold voltage applied to the second sub-gate 223 bwhen a channel is formed in the first sub-channel SC 1 may be lower than a second threshold voltage applied to the first sub-gate 223 awhen a channel is formed in the second sub-channel SC 2 and the third sub-channel SC 3. Thus, in the display apparatus according to the aspect of the present disclosure, a channel of the first sub-channel SC 1 may be formed before a channel of the second sub-channel SC 2 and a channel of the third sub-channel SC 3. Further, in the display apparatus according to the aspect of the present disclosure, when a channel of the second sub-channel SC 2 and a channel of the third sub-channel SC 3 are not formed, the second active drain 221 d 2 may not be electrically connected to the second active source 221 s 2. For example, when a voltage between the first threshold voltage and the second threshold voltage is applied to the first sub-gate 223 aand the second sub-gate 223 b, a channel of the first active channel 221 c 1 and a channel of the first sub-channel SC 1 may be formed, but a channel of the second sub-channel SC 2 and a channel of the third sub-channel SC 3 may not be formed. Therefore, in the display device according to the aspect of the present disclosure, when a voltage between the first threshold voltage and the second threshold voltage is applied to the first sub-gate 223 aand the second sub-gate 223 b, the first active drain 221 d 1 may be electrically connected to the first active source 221 s 1, and the second active drain 221 d 2 may not be electrically connected to the second active source 221 s 2.In the display apparatus according to the aspect of the present disclosure, a voltage between the first threshold voltage and the second threshold voltage may be applied to the first sub-gate 223 aand the second sub-gate 223 bof each pixel region PA when a low gray level image is realized. Thus, in the display device according to the aspect of the present disclosure, when an image having a low gray level is to be output, only the first active region A 1 of the second semiconductor structure 221 in each pixel may be activated. That is, in the display apparatus according to the aspect of the present disclosure, when an image of low gray level is to be output, the driving current applied to the light emitting device 500 of each pixel region PA can be reduced. Moreover, when an image of low gray level is to be output, the variation of the driving current generated by the second thin film transistor TR 2 of each pixel region PA can be reduced. Therefore, in the display apparatus according to the aspect of the present disclosure, the quality of a low-gray-level image can be improved.In the display apparatus according to the aspect of the present disclosure, when a voltage higher than the second threshold voltage is applied to the first sub-gate 223 aand the second sub-gate 223 bof each pixel region PA, a channel of the second sub-channel SC 2 and a channel of the third sub-channel SC 3 may be formed, and the second active drain 221 d 2 may be electrically connected to the second active source 221 s 2. For example, in the display apparatus according to the aspect of the present disclosure, when a voltage higher than the second threshold voltage is applied to the first sub-gate 223 aand the second sub-gate 223 bof each pixel region PA, both the first active channel 221 c 1 and the second active channel 221 c 2 in each pixel region PA may be activated to output a high gray level image. That is, in the display apparatus according to the aspect of the present disclosure, when an image having a high gray level is to be output, the driving current generated by the second thin film transistor TR 2 of each pixel region PA can be increased. Therefore, in the display apparatus according to the aspect of the present disclosure, both the quality of a low-gray-level image and the quality of a high-gray-level image can be improved.And in the display apparatus according to the aspect of the present disclosure, a channel of the second sub-channel SC 2 and a channel of the third sub-channel SC 3 in each pixel area PA may function as an effective channel of the second active channel 221 c 2. In general, a driving current generated by a thin film transistor may be inversely proportional to a channel length of the corresponding thin film transistor. Thus, in the display apparatus according to the aspect of the present disclosure, the driving current generated in the second active channel 221 c 2 of each pixel region PA may be larger than the driving current generated in the first active channel 221 c 1 of the corresponding pixel region PA. Therefore, in the display apparatus according to the aspect of the present disclosure, the efficiency of the second thin film transistor TR 2 in each pixel region PA can be improved.FIG. 9 is a diagram showing a driving current depending on an applied voltage, the voltage being applied to a gate electrode of a first comparative example thin film transistor 1 having only a channel region in which a channel is formed by a first threshold voltage, a gate electrode of a second comparative example thin film transistor 2 having only a channel region in which a channel is formed by a second threshold voltage, and a gate electrode of a second thin film transistor TR 2 according to the aspect of the present disclosure. Here, the channel region of the first comparative example thin film transistor 1, the channel region of the second comparative example thin film transistor 2, and the second channel region 221 cof the second thin film transistor TR 2 according to the aspect of the present disclosure may be formed to have the same length and the same width.Referring to FIG. 9, a threshold voltage of the second thin film transistor TR 2 according to the aspect of the present disclosure may be lower than a threshold voltage of the first comparative example thin film transistor 1 and a threshold voltage of the second comparative example thin film transistor 2. Moreover, the driving current generated at a high voltage by the second thin film transistor TR 2 according to the aspect of the present disclosure may be larger than the driving current generated at a high voltage by the first comparative example thin film transistor 1 and the second comparative example thin film transistor 2. Further, the second thin film transistor TR 2 according to the aspect of the present disclosure can increase the driving current corresponding to the voltage increase, which is smaller than that of the first comparative example thin film transistor 1 and the second comparative example thin film transistor 2, in a portion to which a relatively low voltage is applied. In the display apparatus according to the aspect of the present disclosure, the driving current applied to the light emitting device 500 of each pixel region PA can be effectively controlled according to a gray level of an realized image without degrading the characteristics of the second thin film transistor TR 2 in the corresponding pixel region PA. Therefore, in the display apparatus according to the aspect of the present disclosure, power consumption can be reduced based on improved driving of the low-power display.As shown in FIGS. 2 to 8, the second sub-gate 223 bmay include a same material as the first gate electrode 213. The second sub-gate 223 bmay be disposed on a same layer as the first gate electrode 213. The second sub-gate 223 bmay be formed by a same method as the first gate electrode 213. For example, the second sub-gate 223 bmay be formed simultaneously with the first gate electrode 213. According to some examples, the first sub-gate 223 amay include a different material than the first gate electrode 213. The first sub-gate 223 amay be disposed on a different layer than the first gate electrode 213.The second sub-gate 223 bmay be electrically connected to the first sub-gate 223 a. For example, the second gate electrode 223 may include a connection gate 223 cthat electrically connects the first sub-gate 223 ato the second sub-gate 223 b. The electrical connection between the first sub-gate 223 aand the second sub-gate 223 bmay be formed outside the second semiconductor structure 221. For example, the connection gate 223 cmay be disposed outside the second semiconductor structure 221. The second semiconductor structure 221 may not overlap the connection gate 223 c. Therefore, in the display apparatus according to the aspect of the present disclosure, a channel of the second channel region 221 cmay not be formed by the connection gate 223 c. Therefore, in the display apparatus according to the aspect of the present disclosure, based on the connection gate 223 cof the corresponding pixel region PA, this configuration can prevent or reduce a variation in characteristics of the second thin film transistor TR 2 in each pixel region PA.The connection gate 223 cmay be disposed on a different layer from the first sub-gate 223 aand the second sub-gate 223 b. The connection gate 223 cmay include a different material than the first sub-gate 223 aand the second sub-gate 223 b. For example, the connection gate 223 cmay be disposed on a same layer as the first drain electrode 215 and the first source electrode 217. The connection gate 223 cmay include a same material as the first drain electrode 215 and the first source electrode 217. The connection gate 223 cmay be formed by a same method as the first drain electrode 215 and the first source electrode 217. For example, the connection gate 223 cmay be formed simultaneously with the first drain electrode 215 and the first source electrode 217. Thus, in the display apparatus according to the aspect of the present disclosure, a variation in process efficiency caused by a method of manufacturing the second gate electrode 223 is minimized or reduced.The second drain electrode 225 may include a conductive material. For example, the second drain electrode 225 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second drain electrode 225 may include a different material than the first sub-gate 223 aand the second sub-gate 223 b. The second drain electrode 225 may be disposed on a different layer from the first sub-gate 223 aand the second sub-gate 223 b. For example, the second drain electrode 225 may be disposed on a same layer as the connection gate 223 c. The second drain electrode 225 may include a same material as the connection gate 223 c. The second drain electrode 225 may be formed by a same method as the connection gate 223 c. For example, the second drain electrode 225 may be formed simultaneously with the connection gate 223 c. The second drain electrode 225 may be separated from the connection gate 223 c. The second drain electrode 225 may be insulated from the second gate electrode 223. The second drain electrode 225 may be electrically connected to the first active drain 221 d 1 and the second active drain 221 d 2 of the second semiconductor structure 221.The second source electrode 227 may include a conductive material. For example, the second source electrode 227 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second source electrode 227 may include a different material than the first sub-gate 223 aand the second sub-gate 223 b. The second source electrode 227 may be disposed on a different layer from the first sub-gate 223 aand the second sub-gate 223 b. For example, the second source electrode 227 may be disposed on a same layer as the second drain electrode 225. The second source electrode 227 may comprise a same material as the second drain electrode 225. The second source electrode 227 may be formed by a same method as the second drain electrode 225. For example, the second source electrode 227 may be formed simultaneously with the second drain electrode 225. The second source electrode 227 may be separated from the connection gate 223 cand the second drain electrode 225. The second source electrode 227 may be insulated from the second gate electrode 223. The second source electrode 227 may be electrically connected to the first active source 221 s 1 and the second active source 221 s 2 of the second semiconductor structure 221.The storage capacitor Cst of each pixel region PA may maintain a signal applied to the second gate electrode 223 of the corresponding pixel region PA for one frame. For example, the storage capacitor Cst of each pixel region PA may be electrically connected between the second gate electrode 223 and the second source electrode 227 of the corresponding pixel region PA. The storage capacitor Cst of each pixel region PA may have a stacked structure of capacitor electrodes 251, 252, and 253. The storage capacitor Cst of each pixel region PA may be formed using a method of forming the first thin film transistor TR 1 and the second thin film transistor TR 2 of the corresponding pixel region PA. For example, the storage capacitor Cst of each pixel region PA may include a first capacitor electrode 251 disposed on the same layer as the second sub-gate 223 b, a capacitor electrode 252 disposed on a same layer as the first sub-gate 223 a, and a third capacitor electrode 253 disposed on a same layer as the second source electrode 227. Thus, in the display apparatus according to the aspect of the present disclosure, a size occupied by the storage capacitor Cst in each pixel region PA can be minimized or reduced without reducing the efficiency of the method.The gate driver GD formed in the bezel area BZ may include at least one circuit thin film transistor 290. The switching thin film transistor 290 may be a switching thin film transistor. For example, the circuit thin film transistor 290 may include a circuit semiconductor structure 291, a circuit gate electrode 293, a circuit drain electrode 295, and a circuit source electrode 297.The circuit semiconductor structure 291 may include a semiconductor material. The circuit semiconductor structure 291 may include a different material from the first semiconductor structure 211, the first active region A 1, and the second active region A 2 of each pixel region PA. For example, the circuit semiconductor structure 291 may include low temperature poly-Si (LTPS). The circuit semiconductor structure 291 may be disposed on a different layer from the first semiconductor structure 211, the first active region A 1, and the second active region A 2 of each pixel region PA. However, the present disclosure is not limited thereto, and the circuit semiconductor structure 291 may include a same material as the first semiconductor structure 211 or the second semiconductor structure 221 and / or may be disposed on a same layer as the first semiconductor structure 211 or the second semiconductor structure 221.The circuit semiconductor structure 291 may include a circuit drain region, a circuit channel region, and a circuit source region. The circuit channel region may be disposed between the circuit drain region and the circuit source region. The circuit drain region and the circuit source region may have a lower resistance than the circuit channel region. For example, the circuit drain region and the circuit source region may include conductive impurities. The circuit channel region may be a region that is not doped with conductive impurities.The circuit gate electrode 293 may be disposed on a portion of the circuit semiconductor structure 291. For example, the gate electrode 293 may overlap the circuit channel region of the circuit semiconductor structure 291. The circuit drain region and the circuit source region of the circuit semiconductor structure 291 may be arranged outside the circuit gate electrode 293. The circuit gate electrode 293 may include a conductive material. For example, the circuit gate electrode 293 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The circuit gate electrode 293 may be insulated from the circuit semiconductor structure 291. The circuit drain region of the circuit semiconductor structure 291 may be electrically connected to the circuit source region of the circuit semiconductor structure 291 according to a voltage applied to the circuit gate electrode 293.The circuit gate electrode 293 may include a different material from the first gate electrode 213, the first sub-gate 223 a, and the second sub-gate 223 bof each pixel region PA. The circuit gate electrode 293 may be disposed on a different layer from the first gate electrode 213, the first sub-gate 223 a, and the second sub-gate 223 bof each pixel region PA.The circuit drain electrode 295 may include a conductive material. For example, the circuit drain electrode 295 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The circuit drain electrode 295 may include a different material than the circuit gate electrode 293. For example, the circuit drain electrode 295 may be disposed on a different layer than the circuit gate electrode 293. The circuit drain electrode 295 may be isolated from the circuit gate electrode 293. For example, the circuit drain electrode 295 may be disposed on a same layer as the first drain electrode 215 of each pixel region PA. The circuit drain electrode 295 may include a same material as the first drain electrode 215 of each pixel region PA. The circuit drain electrode 295 may be formed by a same method as the first drain electrode 215 of each pixel region PA. For example, the circuit drain electrode 295 may be formed simultaneously with the first drain electrode 215 of each pixel region PA. The circuit drain electrode 295 may be electrically connected to the circuit drain region of the circuit semiconductor structure 291.The circuit source electrode 297 may include a conductive material. For example, the circuit source electrode 297 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The circuit source 297 may include a different material than the circuit gate. For example, the circuit source electrode 297 may be disposed on a different layer than the circuit gate electrode 293. The circuit source 297 may be insulated from the circuit gate 293. For example, the circuit source 297 may be disposed on a same layer as the circuit drain 295. The circuit source 297 may comprise a same material as the circuit drain 295. The circuit source 297 may be formed by a same method as the circuit drain 295. For example, the circuit source 297 may be formed simultaneously with the circuit drain 295. The circuit source 297 may be separated from the circuit drain 295. The circuit source electrode 297 may be electrically connected to the circuit source region of the circuit semiconductor structure 291.The pixel driving circuit DC of each pixel region PA and the circuit thin film transistor 290 may be supported by a device substrate 100. For example, the first thin film transistor TR 1, the second thin film transistor TR 2, and the storage capacitor Cst of the pixel driving circuit DC may be disposed in each pixel region PA on the corresponding pixel region PA of the device substrate 100. The circuit thin film transistor 290 may be disposed on the surrounding region BZ of the device substrate 100. The device substrate 100 may include an insulating material. For example, the device substrate 100 may include glass or plastic. In another example, the device substrate 100 may include a flexible polymer film. The flexible polymer film may be constructed of, for example, any of the following materials: polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyethersulfone (PES), cyclic olefin copolymer (COC), triacetylcellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film, and polystyrene (PS), but is only exemplary and not necessarily limited thereto.A plurality of insulating layers prevent unnecessary electrical connection and may be disposed on the device substrate 100. For example, a lower buffer layer 110, a lower gate insulating layer 121, a first upper gate insulating layer 122, a second upper gate insulating layer 123, a lower interlayer insulating layer 130, a separation insulating layer 140, an upper buffer layer 150, an upper interlayer insulating layer 160, a lower planarization layer 170, an upper planarization layer 180, and a bank insulating layer 190 may be disposed on the device substrate 100. Note that, although FIGS. 2 to 8 show an example of the layer structure of the display device according to the present disclosure, the embodiments of the present disclosure are not limited thereto. For example, one or more of the plurality of insulating layers 110, 121, 122, 123, 130, 140, 150, 160, 170, 180, and 190 may be omitted, changed, or replaced with other layers. The structure shown in FIGS. 2 to 8 is therefore provided only by way of example, the present disclosure is not limited thereto.The lower buffer layer 110 may be disposed in the vicinity of the device substrate 100. The lower buffer layer 110 may prevent or reduce contamination due to the device substrate 100 in a method of manufacturing the pixel driving circuit DC of each pixel region PA and the circuit thin film transistor 290. For example, an upper surface of the device substrate 100 toward the pixel driving circuit DC of each pixel region PA and the circuit thin film transistor 290 may be completely covered by the lower buffer layer 110. The lower buffer layer 110 may be in direct contact with the upper surface of the device substrate 100. The pixel driving circuit DC of each pixel region PA and the circuit thin film transistor 290 may be disposed on the lower buffer layer 110. The lower buffer layer 110 may include an insulating material. For example, the lower buffer layer 110 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The lower buffer layer 110 may have a multilayer structure. For example, the lower buffer layer 110 may have a stacked structure of an inorganic insulating layer of silicon oxide (SiOx) and an inorganic insulating layer of silicon nitride (SiNx).The lower gate insulating layer 121 may be disposed on the lower buffer layer 110. The circuit gate electrode 293 may be insulated from the circuit semiconductor structure 291 by the lower gate insulating layer 121. The circuit semiconductor structure 291 may be disposed between the lower buffer layer 110 and the lower gate insulating layer 121, for example. The lower gate insulating layer 121 may cover the circuit semiconductor structure 291. The circuit gate electrode 293 may be disposed on the lower gate insulating film 121. The lower gate insulating layer 121 may include an insulating material. For example, the gate lower insulating layer 121 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx).The lower interlayer insulating film 130 may be disposed on the lower gate insulating film 121. The circuit drain electrode 295 and the circuit source electrode 297 may be insulated from the circuit gate electrode by the lower interlayer insulating film 130. For example, the circuit gate structure 293 may be disposed between the lower gate insulating layer 121 and the lower interlayer insulating layer 130. The lower interlayer insulating film 130 may cover the circuit gate electrode 293. The circuit drain electrode 295 and the circuit source electrode 297 may be disposed on the lower interlayer insulating film 130. The lower interlayer insulating layer 130 may include an insulating material. For example, the lower interlayer insulating film 130 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx).A first light blocking structure 310 may be disposed between the lower gate insulating layer 121 and the lower interlayer insulating layer 130 of each pixel region PA. The first light blocking structure 310 of each pixel region PA may include a material that absorbs or reflects light. For example, the first light blocking structure 310 of each pixel region PA may include a metal. The first light blocking structure 310 of each pixel region PA may include a same material as the circuit gate electrode. The first light blocking structure 310 of each pixel region PA may be disposed on a same layer as the circuit gate electrode. The first light blocking structure 310 of each pixel region PA may be formed by a same method as the circuit gate electrode 293. For example, the first light blocking structure 310 of each pixel region PA may be formed simultaneously with the circuit gate electrode 293.The first light blocking structure 310 of each pixel region PA may overlap the first semiconductor structure 211 of the corresponding pixel region PA. For example, light moving toward the first semiconductor pattern 211 of each pixel region PA by passing through the device substrate 100 may be blocked by the first light blocking pattern 310 of the corresponding pixel region PA. Thus, in the display apparatus according to the aspect of the present disclosure, a change in characteristics of the first thin film transistor TR 1 in each pixel region PA due to external light introduced through the device substrate 100 can be prevented or reduced.A certain voltage may be applied to the first light blocking structure 310 of each pixel region PA. For example, the first light blocking structure 310 of each pixel region PA may be electrically connected to the first gate electrode 213 of the corresponding pixel region PA. Thus, in the display apparatus according to the aspect of the present disclosure, the first light blocking structure 310 of each pixel region PA may function as a gate electrode of the first thin film transistor TR 1 in the corresponding pixel region PA. The first semiconductor structure 211 of each pixel region PA may be disposed between the first light blocking structure 310 and the first gate electrode 213 of the corresponding pixel region PA. That is, in the display apparatus according to the aspect of the present disclosure, a channel of the first semiconductor pattern 211 may be formed by a voltage applied to the first gate electrode 213 of the corresponding pixel region PA and a voltage applied to the first light blocking pattern 310 of the corresponding pixel region PA. Therefore, in the display apparatus according to the aspect of the present disclosure, the response speed of the first thin film transistor TR 1 in each pixel region PA can be increased.The isolation insulating layer 140 may be disposed on the lower interlayer insulating layer 130. The isolation insulating layer 140 may prevent or reduce the deterioration and damage of the circuit semiconductor structure 291 due to a method of manufacturing the pixel driving circuit DC in each pixel region PA. For example, the first thin film transistor TR 1, the second thin film transistor TR 2, and the storage capacitor Cst of each pixel region PA may be disposed on the isolation insulating film 140. The isolation insulating layer 140 may include an insulating material. For example, the isolation insulating layer 140 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The isolation insulating layer 140 may have a multilayer structure. For example, the isolation insulating layer 140 may have a stacked structure of an inorganic insulating layer of silicon oxide (SiOx) and an inorganic insulating layer of silicon nitride (SiNx). The thickness of the isolation insulating layer 140 may be greater than the thickness of the lower interlayer insulating layer 130. Thus, in the display apparatus according to the aspect of the present disclosure, damage to the circuit semiconductor structure 291 due to a method of manufacturing the pixel driving circuit DC of each pixel region PA can be effectively prevented or reduced.The upper buffer layer 150 may be disposed on the isolation insulating layer 140. The upper buffer layer 150 may include an insulating material. For example, the upper buffer layer 150 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). A second light blocking structure 320 may be disposed between the separation insulating layer 140 and the upper buffer layer 150 of each pixel region PA. For example, the upper buffer layer 150 may prevent or reduce contamination by the second light blocking structure 320 of each pixel region PA in a method of manufacturing the first semiconductor structure 211 and the second semiconductor structure 221 of each pixel region PA. For example, the pixel driving circuit DC of each pixel region PA may be disposed on the upper buffer layer 150.The second light blocking structure 320 of each pixel region PA may include a material that absorbs or reflects light. For example, the second light blocking structure 320 of each pixel region PA may include a metal. The second light blocking structure 320 of each pixel region PA may overlap the second semiconductor structure 221 of the corresponding pixel region PA. For example, light moving toward the second semiconductor pattern 221 of each pixel region PA by passing through the device substrate 100 may be blocked by the second light blocking pattern 320 of the corresponding pixel region PA. Thus, in the display apparatus according to the aspect of the present disclosure, the second light blocking structure 320 may prevent or reduce a change in characteristics of the second thin film transistor TR 2 in each pixel region PA due to the external light introduced through the device substrate 100. In other words, in the display apparatus according to the aspect of the present disclosure, a deviation of the characteristics of the second thin film transistor TR 2 due to the external light can be prevented or reduced. Therefore, in the display apparatus according to the aspect of the present disclosure, deterioration of image quality due to external light can be prevented or reduced.A certain voltage may be applied to the second light blocking structure 320 of each pixel region PA. For example, the second light blocking structure 320 of each pixel region PA may be electrically connected to the second drain electrode 225 of the corresponding pixel region PA. Therefore, in the display apparatus according to the aspect of the present disclosure, a change in characteristics of the second thin film transistor TR 2 in each pixel region PA due to the external light can be effectively prevented or reduced.A distance between the second light blocking structure 320 and the second semiconductor structure 221 in each pixel region PA may be smaller than a distance between the first light blocking structure 310 and the first semiconductor structure 211 in the corresponding pixel region PA. In general, the amount of change in the effective gate voltage of a thin film transistor disposed on a conductive pattern can be determined by the following equation. Here, ΔV eff represents the amount of change in the effective gate voltage, ΔV GAT represents the amount of change in a voltage applied to the gate electrode, C1 represents the capacitance of the parasitic capacitor formed between the conductive structure and a semiconductor structure of the corresponding thin film transistor, C2 represents the capacitance of the parasitic capacitor formed between the semiconductor structure and the gate electrode of the corresponding thin film transistor, and C ACT represents the capacitance of the parasitic capacitor formed by a voltage applied to a drain region and a source region of the corresponding thin film transistor.The capacitance of a capacitor is inversely proportional to a distance between the conductors forming the corresponding capacitor. In the display apparatus according to the aspect of the present disclosure, the capacitance of the parasitic capacitor formed between the second light blocking structure 320 and the second semiconductor structure 221 of each pixel region PA may be larger than the capacitance of the parasitic capacitor formed between the first light blocking structure 310 and the first semiconductor structure 211 of the corresponding pixel region PA. Thus, in the display apparatus according to the aspect of the present disclosure, the amount of change in the effective gate voltage of the second thin film transistor TR 2 in each pixel region PA may be smaller than the amount of change in the effective gate voltage of the first thin film transistor TR 1 in the corresponding pixel region PA. In a general thin film transistor, the current may decrease according to the change in the voltage applied to the gate electrode of the corresponding thin film transistor as the amount of change in the effective gate voltage is decreased, and the S factor of the corresponding thin film transistor may be increased. Here, the S factor of the thin film transistor is an inverse ratio between the amount of change in the current generated by the corresponding thin film transistor and the amount of change in the voltage applied to the gate electrode of the corresponding thin film transistor. That is, in the display apparatus according to the aspect of the present disclosure, the S factor of the second thin film transistor TR 2 in each pixel region PA and the amount of change in the driving current generated by the second thin film transistor TR 2 of each pixel region PA can be decreased according to the change in the voltage applied to the second gate electrode 223 of the corresponding pixel region PA. Therefore, in the display apparatus according to the aspect of the present disclosure, the display apparatus can prevent or reduce the occurrence of spots due to luminance variations and improve the quality of the image.The first upper gate insulating layer 122 may be disposed on the upper buffer layer 150. The first gate electrode 213 of each pixel region PA may be insulated from the first semiconductor structure 211 of the corresponding pixel region PA by the first upper gate insulating layer 122. The second sub-gate 223 bof each pixel region PA may be insulated from the first active region A 1 and the second active region A 2 of the corresponding pixel region PA by the first upper gate insulating layer 122. For example, the first upper gate insulating film 122 may cover the first semiconductor pattern 211 and the second semiconductor pattern 221 of each pixel region PA. The first gate electrode 213 and the second sub-gate 223 bof each pixel region PA may be disposed on the first upper gate insulating film 122. The first upper gate insulating layer 122 may include an insulating material. For example, the first upper gate insulating film 122 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx).The second upper gate insulating film 123 may be disposed on the first upper gate insulating film 122. The first sub-gate 223 aof each pixel region PA may be separated from the second sub-gate 223 bof the corresponding pixel region PA by the second upper gate insulating layer 123. For example, the second upper gate insulating film 123 may cover the first gate electrode 213 and the second sub-gate 223 bof each pixel region PA. The first sub-gate 223 aof each pixel region PA may be disposed on the second upper gate insulating film 123. The second upper gate insulating layer 123 may include an insulating material. The second upper gate insulating film 123 may include an inorganic insulating material, for example, silicon oxide (SiOx) and / or silicon nitride (SiNx). The second upper gate insulating layer 123 may include a same material as the first upper gate insulating layer 122. For example, an interface between the first upper gate insulating layer 122 and the second upper gate insulating layer 123 may not be detectable.In each pixel region PA, only the first upper gate insulating film 122 may be disposed between the first active channel 221 c 1 and the second sub-gate 223 band between the first sub-channel SC 1 and the second sub-gate 223 bof the second active channel 221 c 2. In each pixel region PA, the first upper gate insulating film 122 and the second upper gate insulating film 123 may be disposed between the second sub-channel SC 2 of the second active channel 221 c 2 and the first sub-gate 223 aand between the third sub-channel SC 3 of the second active channel 221 c 2 and the first sub-gate 223 a. For example, a distance between the first sub-channel SC 1 and the second sub-gate 223 bin each pixel region PA may be the same as a distance between the first active channel 221 c 1 and the second sub-gate 223 bin the corresponding pixel region PA, and a distance between the second sub-channel SC 2 and the first sub-gate 223 aand a distance between the third sub-channel SC 3 and the first sub-gate 223 ain each pixel region PA may be larger than a distance between the first sub-channel SC 1 and the second sub-gate 223 bin the corresponding pixel region PA. That is, in the display apparatus according to the aspect of the present disclosure, a capacitance of the parasitic capacitor formed between the second sub-channel SC 2 and the first sub-gate 223 aand a capacitance of the parasitic capacitor formed between the third sub-channel SC 3 and the first sub-gate 223 ain each pixel region PA may be smaller than a capacitance of the parasitic capacitor formed between the first active channel 221 c 1 and the second sub-gate 223 bin the corresponding pixel region PA. Thus, in the display apparatus according to the aspect of the present disclosure, the S factor of the second thin film transistor TR 2 in each pixel region PA can be increased based on the distance between the second sub-channel SC 2 and the first sub-gate 223 aand the distance between the third sub-channel SC 3 and the first sub-gate 223 ain the corresponding pixel region PA. Therefore, in the display apparatus according to the aspect of the present disclosure, the change in current flow flowing through the second active region A 2 of each pixel region PA based on a change in voltage applied to the first sub-gate 223 aof the corresponding pixel region PA may not be large. Therefore, in the display apparatus according to the aspect of the present disclosure, a variation in characteristics of the second thin film transistors TR 2 can be effectively prevented or reduced.The upper interlayer insulating film 160 may be disposed on the second upper gate insulating film 123. The upper interlayer insulating film 160 may cover the first sub-gate 223 aof each pixel region PA. The upper interlayer insulating layer 160 may include an insulating material. The upper interlayer insulating film 160 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx).The first drain electrode 215, the first source electrode 217, the second drain electrode 225, the second source electrode 227, and the connection gate 223 cof each pixel region PA may be disposed on the upper interlayer insulating film 160. For example, the first drain electrode 215 and the first source electrode 217 of each pixel region PA may be insulated from the first gate electrode 213 of the corresponding pixel region PA by the first upper gate insulating film 122, the second upper gate insulating film 123, and the upper interlayer insulating film 160. The connection gate 223 cof each pixel region PA may be separated from the first sub-gate 223 aof the corresponding pixel region PA by the upper interlayer insulating film 160. For example, the first sub-gate 223 aof each pixel region PA may be insulated from the second drain electrode 225 and the second source electrode 227 of the corresponding pixel region PA by the upper interlayer insulating film 160.The first drain electrode 215 of each pixel region PA may be electrically connected to the first drain region of the first semiconductor structure 211 in the corresponding pixel region PA and pass through the first upper gate insulating film 122, the second upper gate insulating film 123, and the upper interlayer insulating film 160. The first source electrode 217 of each pixel region PA may be electrically connected to the first source region of the first semiconductor structure 211 in the corresponding pixel region PA and pass through the first upper gate insulating layer 122, the second upper gate insulating layer 123, and the upper interlayer insulating layer 160. The second drain electrode 225 of each pixel region PA may be electrically connected to the first active drain 221 d 1 and the second active drain 221 d 2 of the second semiconductor structure 221 in the corresponding pixel region PA and pass through the first upper gate insulating layer 122, the second upper gate insulating layer 123, and the upper interlayer insulating layer 160. The second source electrode 227 of each pixel region PA may be electrically connected to the first active source 221 s 1 and the second active source 221 s 2 of the second semiconductor structure 221 of the corresponding pixel region PA and pass through the first upper gate insulating layer 122, the second upper gate insulating layer 123, and the upper interlayer insulating layer 160.The second upper gate insulating film 123 and the upper interlayer insulating film 160 may include first contact holes partially exposing the second sub-gate 223 bof each pixel region PA. The upper interlayer insulating film 160 may include second contact holes partially exposing the first sub-gate 223 aof each pixel region PA. The connection gate 223 cof each pixel region may be connected to the second sub-gate 223 bof the corresponding pixel region PA via one of the first contact holes. The connection gate 223 cof each pixel region may be connected to the first sub-gate 223 aof the corresponding pixel region PA through one of the second contact holes. The first contact holes and the second contact holes may be formed simultaneously with a contact hole connecting the second drain electrode 225 of each pixel region PA to the first active drain 221 d 1 and the second active drain 221 d 2 of the corresponding pixel region PA and a contact hole connecting the second source electrode 227 of each pixel region PA to the first active source 221 s 1 and the second active source 221 s 2 of the corresponding pixel region PA. Thus, in the display device according to the aspect of the present disclosure, a decrease in efficiency in a method due to a method of manufacturing the second gate electrode 223 of each pixel region PA can be minimized or reduced.The first capacitor electrode 251 of each pixel region PA may be separated from the second capacitor electrode 252 of the corresponding pixel region PA by the second upper gate insulating layer 123. For example, the first capacitor electrode 251 of each pixel region PA may be disposed between the first upper gate insulating film 122 and the second upper gate insulating film 123. The second capacitor electrode 252 of each pixel region PA may be separated from the third capacitor electrode 253 of the corresponding pixel region PA by the upper interlayer insulating layer 160. For example, the second capacitor electrode of each pixel region PA may be disposed between the second upper gate insulating film 123 and the upper interlayer insulating film 160. The third capacitor electrode of each pixel region PA may be disposed on the upper interlayer insulating film 160.The circuit drain electrode 295 and the circuit source electrode 297 may be disposed on the upper interlayer insulating film 160. For example, the circuit drain electrode 295 may be connected to the circuit drain region of the circuit semiconductor structure 291 by passing through the lower gate insulating film 121, the lower interlayer insulating film 130, the isolation insulating film 140, the upper buffer film 150, the first upper gate insulating film 122, the second upper gate insulating film 123, and the upper interlayer insulating film 160. The circuit source electrode 297 may be connected to the circuit source region of the circuit semiconductor structure 291 by passing through the lower gate insulating film 121, the lower interlayer insulating film 130, the isolation insulating film 140, the upper buffer film 150, the first upper gate insulating film 122, the second upper gate insulating film 123, and the upper interlayer insulating film 160. Therefore, in the display apparatus according to the aspect of the present disclosure, a decrease in efficiency in a method due to a method of manufacturing the circuit thin film transistor 290 can be minimized or reduced.The lower planarization layer 170 may be disposed on the upper interlayer insulating layer 160. The upper planarization layer 180 may be disposed on the lower planarization layer 170. The lower planarization layer 170 and the upper planarization layer 180 may cancel a thickness difference due to the pixel driving circuit DC of each pixel region PA. For example, an upper surface of the upper planarization layer 180 opposite to the device substrate 100 may be a planar surface. The first drain electrode 215, the first source electrode 217, the second drain electrode 225, the second source electrode 227, the connection gate 223 c, and the third capacitor electrode 253 of each pixel region PA may be covered by the lower planarization layer 170. The lower planarization layer 170 and the upper planarization layer 180 may extend onto the bezel area BZ of the device substrate 100. For example, the lower planarization layer 170 and the upper planarization layer 180 may be stacked on the drain electrode 295 and the circuit source electrode 297. A difference in thickness due to the circuit thin film transistor 290 may be cancelled by the lower planarization layer 170 and the upper planarization layer 180.The lower planarization layer 170 and the upper planarization layer 180 may include an insulating material. The lower planarization layer 170 and the upper planarization layer 180 may include a different material than the upper interlayer insulating layer 160. The lower planarization layer 170 and the upper planarization layer 180 may be formed of a material having a relatively high flowability. For example, the lower planarization layer 170 and the upper planarization layer 180 may include an organic insulating material. The upper planarization layer 180 may include a same material as the lower planarization layer 170. For example, an interface between the lower planarization layer 170 and the upper planarization layer 180 may not be detectable. For example, the lower planarization layer 170 and the upper planarization layer 180, respectively, may be formed of one or more materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, and benzocyclobutene, but embodiments are not limited thereto.The light emitting device 500 of each pixel region PA may be disposed on the upper planarization layer 180 of the corresponding pixel region PA. For example, the light emitting device 500 of each pixel region PA may be supported by the corresponding pixel region PA of the device substrate 100. The light emitting device 500 of each pixel region PA may emit light in a certain color. For example, the light emitting device 500 of each pixel region PA may include a first electrode 510, a light emitting layer 520, and a second electrode 530, which are sequentially stacked on the upper planarization layer 180 of the corresponding pixel region PA.The first electrode 510 may include a conductive material. The first electrode 510 may include a material having a high reflectance. For example, the first electrode 510 may include a metal such as aluminum (Al) or silver (Ag). The first electrode 510 may have a multilayer structure. For example, the first electrode 510 may have a structure in which a reflective electrode made of a metal is disposed between transparent electrodes made of a transparent conductive material such as ITO and IZO.The light emitting layer 520 may generate light having a luminance corresponding to a voltage difference between the first electrode 510 and the second electrode 530. For example, the light emitting layer 520 may include at least one emission material layer (EML). The emission material layer may include an emission material. The emission material may include an organic material, an inorganic material, or a hybrid material. For example, the display apparatus according to the aspect of the present disclosure may be an organic light emitting display apparatus including an organic emitting material, but the present disclosure is not limited thereto.The light emitting layer 520 may include at least one functional layer that supplies holes or electrons. For example, the light emitting layer 520 may include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). In this way, in the display apparatus according to the aspect of the present disclosure, the efficiency of the light emitting layer 520 can be improved.The second electrode 530 may include a conductive material. The second electrode 530 may include a different material than the first electrode 510. The transmittance of the second electrode 530 may be greater than the transmittance of the first electrode 510. For example, the second electrode 530 may be a transparent electrode formed of a transparent conductive material such as ITO and IZO. Thus, in the display apparatus according to the aspect of the present disclosure, the light generated from the light emitting layer 520 may be emitted to the outside through the second electrode 530.The light emitting device 500 of each pixel region PA may be electrically connected to the second thin film transistor TR 2 of the corresponding pixel region PA. For example, the first electrode 510 of each pixel region PA may be electrically connected to the second source electrode 227 of the corresponding pixel region PA. The first electrode 510 of each pixel region PA may include a portion that is in direct contact with the upper surface of the upper planarization layer 180 on the corresponding pixel region PA. The light emitting layer 520 and the second electrode 530 of each pixel region PA may be stacked on a portion of the corresponding first electrode 510 that is in direct contact with the upper surface of the upper planarization layer 180. Thus, in the display apparatus according to the aspect of the present disclosure, a deviation in luminance depending on the generation location of the light emitted from the light emitting device 500 of each pixel region PA can be prevented or reduced.Intermediate electrodes 400 electrically connect the first electrode 510 of each pixel region PA to the second source electrode 227 of the corresponding pixel region PA, and may be disposed between the lower planarization layer 170 and the upper planarization layer 180. The intermediate electrodes 400 may include a conductive material. For example, the intermediate electrodes 400 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). Each of the intermediate electrodes 400 may be in direct contact with the second source electrode 227 and the first electrode 510 in one of the pixel regions PA. For example, the first electrode 510 of each pixel region PA may be in contact with one of the intermediate electrodes 400 by penetrating the upper planarization layer 180, and each of the intermediate electrodes 400 may be in contact with the second source electrode 227 in one of the pixel regions PA by penetrating the lower planarization layer 170. Thus, in the display apparatus according to the aspect of the present disclosure, the first electrode 510 of each pixel region PA may be stably connected to the second source electrode 227 of the corresponding pixel region PA. Therefore, in the display apparatus according to the aspect of the present disclosure, the reliability of the electrical connections between the pixel driving circuit DC and the light emitting device 500 in each pixel area PA can be improved. However, the present disclosure is not limited thereto. For example, the intermediate electrodes 400 may be omitted, and the first electrode 510 of each pixel region PA may be directly connected to the second source electrode 227 of the corresponding pixel region PA.The bank insulating layer 190 may be disposed on the upper planarization layer 180. The bank insulating layer 190 may define an emission region in each pixel region PA. For example, the first electrode 510 of each pixel region PA may be partially exposed through the bank insulating layer 190. A portion of each first electrode 510 exposed by the bank insulating layer 190 may be in direct contact with the upper surface of the upper planarization layer 180. For example, the light emitting layer 520 and the second electrode 530 of each pixel region PA may be stacked on a portion of the corresponding first electrode 510 exposed by the bank insulating layer 190. An edge of the first electrode 510 in each pixel region PA may be covered by the bank insulating layer 190. For example, the first electrode 510 of each pixel region PA may be insulated from the first electrode 510 of the adjacent pixel region PA by the bank insulating layer 190. The bank insulating layer 190 may include an insulating material, for example, acrylic resin, epoxy resin, phenol resin, polyamide resin and / or polyimide resin, etc. Alternatively, the bank insulating layer 190 may include an inorganic insulating material such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide, etc. For example, the bank insulating layer 190 may include an organic insulating material. The bank insulating layer 190 may include a different material than the upper planarization layer 180. Moreover, the bank insulating layer 190 may be formed of an insulating material including a black material. The bank insulating layer 190 may be made of, for example, a transparent carbon-based mixture. In particular, the bank insulating layer 190 may include, but is not limited to, carbon black. The bank insulating layer 190 may also be formed of a transparent insulating material.The light emitted from the light emitting device 500 of each pixel region PA may have a different color from the light emitted from the light emitting device 500 of an adjacent pixel region PA. For example, the light emitting layer 520 of each pixel region PA may be separated from the light emitting layer 520 of the adjacent pixel region PA. The light emitting layer 520 of each pixel region PA may have one end on the bank insulating layer 190. For example, the light emitting layer 520 of each pixel region PA may include a different material than the light emitting layer 520 of an adjacent pixel region PA.The voltage applied to the second electrode 530 of each pixel region PA may be substantially equal to a voltage applied to the second electrode 530 of the adjacent pixel region PA. Substantially equal values are values that deviate based on normal process deviations and are identical for all practical purposes. For example, the second electrode 530 of each pixel region PA may be electrically connected to the second electrode 530 of the adjacent pixel region PA. The second electrode 530 of each pixel region PA may include a same material as the second electrode 530 of the adjacent pixel region PA. The second electrode 530 of each pixel region PA may be formed by a same method as the second electrode 530 of the adjacent pixel region PA. For example, the second electrode 530 of each pixel region PA may be formed simultaneously with the second electrode 530 of the adjacent pixel region PA. The second electrode 530 of each pixel region PA may be in direct contact with the second electrode 530 of the adjacent pixel region PA. For example, the bank insulating layer 190 may be covered by the second electrode 530. In this way, in the display apparatus according to the aspect of the present disclosure, a method of manufacturing the second electrode 530 in each pixel region PA can be simplified. And in the display apparatus according to the aspect of the present disclosure, the luminance of the light generated by the light emitting layer 520 in each pixel region PA may be adjusted by the data signal applied to the pixel driving circuit DC in the corresponding pixel region PA.An encapsulating unit 600 may be disposed on the light emitting device 500 of each pixel region PA. The encapsulating unit 600 may prevent or reduce damage to the light emitting devices 500 due to moisture and external impacts. The encapsulation unit 600 may have a multilayer structure. For example, the encapsulation unit 600 may include a first encapsulation layer 610, a second encapsulation layer 620, and a third encapsulation layer 630 stacked one after another, but the present disclosure is not limited thereto. The first encapsulation layer 610, the second encapsulation layer 620, and the third encapsulation layer 630 may include an insulating material. The second encapsulation layer 620 may comprise a different material than the first encapsulation layer 610 and the third encapsulation layer 630. For example, the first encapsulation layer 610 and the third encapsulation layer 630 may include an inorganic insulating material that can be deposited at low temperatures, such as silicon oxide (SiOx) and silicon nitride (SiNx), and the second encapsulation layer 620 may include an organic insulating material. A difference in thickness between the individual pixel regions PA caused by the light-emitting device 500 can be cancelled out by the second encapsulation layer 620. For example, an upper surface of the encapsulating unit 600 opposite to the device substrate 100 may be a planar surface. Thus, in the display apparatus according to the aspect of the present disclosure, damage to the light emitting device 500 in each pixel area PA due to external humidity and shocks can be effectively prevented or reduced.Accordingly, the display apparatus according to the aspect of the present disclosure may include the pixel driving circuits DC respectively connected to the light emitting devices 500, wherein the second thin film transistor TR 2 of each pixel driving circuit DC on a portion of the second semiconductor structure 221 may include the second gate electrode 223, and the second gate electrode 223 may include the first sub-gate 223 athat overlaps with the second channel region 221 cof the second semiconductor structure 221 and the second sub-gate 223 bthat is disposed between the second semiconductor structure 221 and the first sub-gate 223 a. The second channel region 221 cmay include the first active channel 221 c 1 fully overlapping with the second sub-gate 223 band the second active channel 221 c 2 partially overlapping with the second sub-gate 223 b. Thus, in the display apparatus according to the aspect of the present disclosure, the driving current generated by the second thin film transistor TR 2 in each pixel driving circuit DC can be reduced to generate a low gray level image without degrading the characteristics of the second thin film transistor TR 2 in each pixel region PA. Moreover, in the display apparatus according to the aspect of the present disclosure, the S factor of the second thin film transistor TR 2 in each pixel driving circuit DC can be increased. Therefore, in the display apparatus according to the aspect of the present disclosure, the efficiency of the second thin film transistor TR 2 in each pixel driving circuit DC can be improved. Further, in the display apparatus according to the aspect of the present disclosure, the reliability of each pixel driving circuit DC and the quality of the image can be improved.The display apparatus according to the aspect of the present disclosure is described such that the pixel driving circuit DC of each pixel region PA may be composed of the first thin film transistor TR 1, the second thin film transistor TR 2, and the storage capacitor Cst. However, in the display apparatus according to another aspect of the present disclosure, the pixel driving circuit DC of each pixel region PA may include a driving thin film transistor and at least one switching thin film transistor. For example, in the display apparatus according to another aspect of the present disclosure, the pixel driving circuit DC of each pixel region PA may further include a third thin film transistor for initializing the storage capacitor Cst according to the gate signal. The third thin film transistor of each pixel region PA may include a third semiconductor structure, a third gate electrode, a third drain electrode, and a third source electrode. For example, the third gate electrode of each pixel region PA may be electrically connected to the corresponding gate line GL, the third drain electrode of each pixel region PA may be electrically connected to an initiation line applying an initiation signal, and the third source electrode of each pixel region PA may be electrically connected to the storage capacitor Cst of the corresponding pixel region PA. Thus, in the display apparatus according to another aspect of the present disclosure, the degree of freedom in the configuration of each pixel driving circuit DC can be improved.In the display apparatus according to the aspect of the present disclosure, the position and electrical connection of the first drain electrode 215, the first source electrode 217, the second drain electrodes 225, and the second source electrode 227 in each pixel driving circuit DC may vary depending on the configuration of the respective pixel driving circuit DC and / or the type of the respective thin film transistors TR 1 and TR 2. For example, in the display apparatus according to another aspect of the present disclosure, the second gate electrode 223 of each pixel driving circuit DC may be electrically connected to the first drain electrode 215 of the corresponding pixel driving circuit DC. Thus, in the display apparatus according to another aspect of the present disclosure, the degree of freedom in the configuration of each pixel driving circuit DC and the type of each thin film transistor TR 1 and TR 2 can be improved.The display apparatus according to the aspect of the present disclosure is described such that the first semiconductor structure 211 and the second semiconductor structure 221 of each pixel region PA may be configured of an oxide semiconductor. However, in the display apparatus according to another aspect of the present disclosure, the second semiconductor structure 221 of each pixel region PA may include a different material than the first semiconductor structure 211 of the corresponding pixel region PA. For example, in the display apparatus according to another aspect of the present disclosure, the first semiconductor structure 211 of each pixel region PA may include amorphous silicon (a-Si) or polycrystalline silicon (poly-Si). The first thin film transistor TR 1 of each pixel region PA may be formed to have the same structure as the circuit thin film transistor 290. For example, the first semiconductor structure 211 of each pixel region PA may be disposed between the lower buffer layer 110 and the lower gate insulating layer 121, and the first gate electrode 213 of each pixel region PA may be disposed between the lower gate insulating layer 121 and the lower interlayer insulating layer 130. The first semiconductor structure 211 of each pixel region PA may include a same material as the circuit semiconductor structure 291. For example, the first semiconductor structure of each pixel region PA may include low-temperature poly-Si (LTPS). In the display apparatus according to another aspect of the present disclosure, the first light blocking structure 310 of each pixel region PA may not be formed. Thus, in the display apparatus according to another aspect of the present disclosure, the degree of freedom in the configuration of each pixel driving circuit DC and the type of each thin film transistor TR 1 and TR 2 can be improved.The display apparatus according to the aspect of the present disclosure is described such that the first active area A 1 of each pixel area PA may be disposed between the second active area A 2 of the corresponding pixel area PA and the connection gate 223 c. However, in the display apparatus according to another aspect of the present disclosure, the second active area A 2 of each pixel area PA may be disposed between the first active area A 1 of the corresponding pixel area PA and the connection gate 223 c, as shown in FIG. 10. Thus, in the display apparatus according to another aspect of the present disclosure, the degree of freedom in arrangement of the first active area A 1 and the second active area A 2 in each pixel area PA can be improved.The display apparatus according to the aspect of the present disclosure is described such that the first sub-gate 223 aof each pixel region PA may be disposed on a different layer from the first drain electrode 215, the first source electrode 217, the second drain electrode 225, and the second source electrode 227 of the corresponding pixel region PA. However, in the display apparatus according to another aspect of the present disclosure, the first sub-gate 223 aof each pixel region PA may be disposed on the same layer as the second drain electrode 225 and the second source electrode 227 of the corresponding pixel region PA, as shown in FIGS. 11 and 12. The first sub-gate 223 aof each pixel region PA may include a same material as the second drain electrode 225 and the second source electrode 227 of the corresponding pixel region PA. The first sub-gate 223 aof each pixel region PA may be formed by a same method as the second drain electrode 225 and the second source electrode 227 of the corresponding pixel region PA. For example, the first sub-gate 223 aof each pixel region PA may be formed simultaneously with the second drain electrode 225 and the second source electrode 227 of the corresponding pixel region PA. The first sub-gate 223 aof each pixel region PA may be separated from the second drain electrode 225 and the second source electrode 227 of the corresponding pixel region PA. For example, the first sub-gate 223 aof each pixel region PA may be in direct contact with the second sub-gate 223 bof the corresponding pixel region PA by penetrating the second upper gate insulating film 123. Therefore, in the display apparatus according to another aspect of the present disclosure, a decrease in efficiency in a method due to a method of manufacturing the second gate electrode 223 in each pixel region PA can be minimized or reduced, and the efficiency of the second thin film transistor TR 2 in each pixel region PA can be improved.In the display apparatus according to another aspect of the present disclosure, the first capacitor electrode 251 of each pixel region PA may be disposed on the same layer as the second light blocking structure 320 of the corresponding pixel region PA, the second capacitor electrode 252 of each pixel region PA may be disposed on the same layer as the second sub-gate 223 bof the corresponding pixel region PA, and the third capacitor electrode of each pixel region PA may be disposed on the same layer as the first sub-gate 223 aof the corresponding pixel region PA. For example, in the display device according to another aspect of the present disclosure, the storage capacitor Cst may include each pixel region PA: the first capacitor electrode 251 between the isolation insulating layer 140 and the upper buffer layer 150, the second capacitor electrode 252 between the first upper gate insulating layer 122 and the second upper gate insulating layer 123, and the third capacitor electrode 253 between the second upper gate insulating layer 123 and the lower planarization layer 170. Therefore, in the display apparatus according to another aspect of the present disclosure, an increase in size of the storage capacitor in each pixel region PA according to the location of the first sub-gate 223 ain the corresponding pixel region PA can be minimized or reduced. Therefore, in the display apparatus according to another aspect of the present disclosure, the degree of freedom in the configuration of the pixel driving circuit DC in each pixel area PA can be improved.The display apparatus according to the aspect of the present disclosure is described such that a channel of the first active area A 1 in each pixel area PA may be formed by the second sub-gate 223 bof the corresponding pixel area PA. However, in the display apparatus according to another aspect of the present disclosure, the first active area A 1 in each pixel area PA may be activated by the first sub-gate 223 aof the corresponding pixel area PA. For example, in the display apparatus according to another aspect of the present disclosure, the first active region A 1 in each pixel region PA may be disposed outside the second sub-gate 223 bof the corresponding pixel region PA, as shown in FIGS. 13 to 16.Only the first upper gate insulating film 122 and the second upper gate insulating film 123 may be disposed between the first active channel 221 c 1 of the first active channel 221 c 1 and the first sub-gate 223 ain each pixel region PA. The second active channel 221 c 2 of each pixel region PA may include the first sub-channel SC 1, the second sub-channel SC 2, and the third sub-channel SC 3. The first sub-channel SC 1 of each pixel region PA may overlap the second sub-gate 223 bof the corresponding pixel region PA. The second sub-channel SC 2 and the third sub-channel SC 3 of each pixel region PA may be disposed outside the second sub-gate 223 bof the corresponding pixel region PA. For example, only the first upper gate insulating layer 122 and the second upper gate insulating layer 123 may be disposed between the second sub-channel SC 2 and the first sub-gate 223 ain each pixel region PA and between the third sub-channel SC 3 and the first sub-gate 223 ain each pixel region PA. Thus, in the display apparatus according to another aspect of the present disclosure, a channel of the first active channel 221 c 1, a channel of the second sub-channel SC 2, and a channel of the third sub-channel SC 3 may be formed by a voltage applied to the first sub-gate 223 a, and a channel of the first sub-channel SC 1 may be formed by a voltage applied to the second sub-gate 223 b.A channel of the first active channel 221 c 1, a channel of the second sub-channel SC 2, and a channel of the third sub-channel SC 3 in each pixel region PA may be formed at a lower voltage than a channel of the first sub-channel SC 1 in the corresponding pixel region PA. For example, the first active channel 221 c 1, the second sub-channel SC 2, and the third sub-channel SC 3 may be doped with conductive impurities in each pixel region PA. The first active channel 221 c 1, the second sub-channel SC 2, and the third sub-channel SC 3 of each pixel region PA may have a smaller resistance than the first sub-channel SC 1 of the corresponding pixel region PA. A resistance of the first active channel 221 c 1, a resistance of the second sub-channel SC 2, and a resistance of the third sub-channel SC 3 in each pixel region PA may be larger than a resistance of the first active drain 221 d 1, a resistance of the second active drain 221 d 2, a resistance of the first active source 221 s 1, and a resistance of the second active source 221 s 2 in the corresponding pixel region PA. For example, the first active drain 221 d 1, the second active drain 221 d 2, the first active source 221 s 1, and the second active source 221 s 2 of each pixel region PA may be doped with a higher concentration of conductive impurities than the first active channel 221 c 1, the second sub-channel SC 2, and the third sub-channel SC 3 of the corresponding pixel region PA. The second sub-channel SC 2 disposed between the second active drain 221 d 2 and the first sub-channel SC 1 in each pixel region PA and the third sub-channel SC 3 disposed between the first sub-channel SC 1 and the second active source 221 s 2 in each pixel region PA may function as a lightly doped drain (LDD) region of the second active region A 2 in the corresponding pixel region PA. Thus, in the display apparatus according to another aspect of the present disclosure, a channel of the first sub-channel SC 1 in each pixel area PA may function as an effective channel of the second active channel 221 c 2 in the corresponding pixel area PA.In the display apparatus according to another aspect of the present disclosure, only the first active region A 1 of each pixel region PA may be activated when a relatively low voltage is applied to the first sub-gate 223 aand the second sub-gate 223 bof each pixel region PA. Thus, in the display apparatus according to another aspect of the present disclosure, occurrence of stains can be prevented or reduced, and quality of a low gray level image can be improved without degrading characteristics of the second thin film transistor TR 2 in each pixel region PA.A distance between the first active channel 221 c 1 and the first sub-gate 223 ain each pixel region PA may be larger than a distance between the first sub-channel SC 1 and the second sub-gate 223 bin the corresponding pixel region PA. Thus, in the display apparatus according to another aspect of the present disclosure, the first active region A 1 of the second thin film transistor TR 2 in each pixel may have a relatively large S factor. That is, in the display apparatus according to another aspect of the present disclosure, the variation of the driving current generated by the second thin film transistor TR 2 in each pixel region PA can be effectively reduced. Therefore, in the display apparatus according to another aspect of the present disclosure, the efficiency of the second thin film transistor TR 2 in each pixel region PA and the quality of the image can be improved.The display apparatus according to the aspect of the present disclosure is described such that the second active area A 2 of each pixel area PA may include the first sub-channel SC 1 disposed between the second sub-channel SC 2 and the third sub-channel SC 3 of the corresponding pixel area PA. However, in the display apparatus according to another aspect of the present disclosure, the second active area A 2 of each pixel area PA may have different structures. For example, in the display apparatus according to another aspect of the present disclosure, the second semiconductor structure 221 may include the first active region A 1 disposed outside the second sub-gate 223 band the second active region A 2 disposed in parallel with the first active region A 1, wherein the second active region A 2 may be configured of the first sub-channel SC 1 overlapping with the second sub-gate 223 band the second sub-channel SC 2 disposed outside the second sub-gate 223 bas shown in FIGS. 17 and 18.The first sub-channel SC 1 may be disposed between the second active drain 221 d 2 and the second sub-channel SC 2. The second sub-channel SC 2 may be disposed between the first sub-channel SC 1 and the second active source 221 s 2. The amount of oxygen contained in the first sub-channel SC 1 may be different from the amount of oxygen contained in the second sub-channel SC 2. For example, the second sub-channel SC 2 may include a resistance between the second active source 221 s 2 and the first sub-channel SC 1. A channel of the second sub-channel SC 2 may be formed with a lower voltage than a channel of the first sub-channel SC 1. Thus, in the display apparatus according to another aspect of the present disclosure, the first sub-channel SC 1 may function as an effective channel of the second active area A 2. Therefore, in the display apparatus according to another aspect of the present disclosure, the degree of freedom in configuration of the second active area A 2 in each pixel area PA can be improved.In the display apparatus according to another aspect of the present disclosure, the length of the second sub-channel SC 2 may be different from the length of the first sub-channel SC 1. For example, in the display apparatus according to another aspect of the present disclosure, a length of the first sub-channel SC 1 may be smaller than a length of the second sub-channel SC 2, as shown in FIGS. 17 and 18. Thus, in the display apparatus according to another aspect of the present disclosure, an effective channel region of the second active region A 2 may be set by a length of the first sub-channel SC 1. Therefore, in the display apparatus according to another aspect of the present disclosure, the driving current generated by the second thin film transistor TR 2 of each pixel region PA can be effectively adjusted when both the first active region A 1 and the second active region A 2 of the corresponding pixel region PA are activated.The display apparatus according to the aspect of the present disclosure is described such that the second active area A 2 of each pixel area PA may have the same size as the first active area A 1 of the corresponding pixel area PA. However, in the display apparatus according to another aspect of the present disclosure, the second active area A 2 of each pixel area PA may have a different width and / or length than the first active area A 1 of the corresponding pixel area PA. Thus, in the display apparatus according to another aspect of the present disclosure, when only the first active region A 1 of each pixel region PA is activated, the driving current generated by the second thin film transistor TR 2 of each pixel region PA can be effectively adjusted without degrading the characteristics of the second thin film transistor TR 2 in the corresponding pixel region PA.The display apparatus according to the aspect of the present disclosure is described such that the second active area A 2 of each pixel area PA may be formed simultaneously with the first active area A 1 of the corresponding pixel area PA. However, in the display apparatus according to another aspect of the present disclosure, the second active region A 2 of each pixel region PA may include a different material from the first active region A 1 of the corresponding pixel region PA. Thus, in the display apparatus according to another aspect of the present disclosure, when only the first active region A 1 of each pixel region PA is activated, the driving current of the second thin film transistor TR 2 of each pixel region PA can be effectively adjusted. Therefore, in the display apparatus according to another aspect of the present disclosure, the efficiency of the second thin film transistor TR 2 in each pixel region PA can be improved.In the display apparatus according to another aspect of the present disclosure, the first sub-channel SC 1 and the third sub-channel SC 3 of the second active area A 2 may be activated before the second sub-channel SC 2 of the second active area A 2. For example, in the display apparatus according to another aspect of the present disclosure, the second active area A 2 may include the second sub-channel SC 2 disposed between the first sub-channel SC 1 and the third sub-channel SC 3, and a resistance of the second sub-channel SC 2 may be smaller than a resistance of the first sub-channel SC 1 and a resistance of the third sub-channel SC 3, as shown in FIGS. 19 and 20. The second gate electrode 223 may include a second sub-gate 223 belapping the first sub-channel SC 1 and a third sub-gate 223 dlapping the third sub-channel SC 3. The second sub-gate 223 band the third sub-gate 223 dmay be electrically connected to the first sub-gate 223 avia the connection gate 223 c. The second sub-channel SC 2 may be disposed outside the second sub-gate 223 band the third sub-gate 223 d. The second sub-channel SC 2 may overlap the first sub-gate 223 a. Thus, in the display apparatus according to another aspect of the present disclosure, a channel of the first sub-channel SC 1 and a channel of the third sub-channel SC 3 may function as an effective channel of the second active area A 2. Therefore, in the display apparatus according to another aspect of the present disclosure, an effective channel of the second active area A 2 can be effectively set.The display apparatus according to the aspect of the present disclosure is described such that the second semiconductor structure 221 of each pixel region PA may include the first active region A 1 and the second active region A 2, and the second active region A 2 may be activated at a voltage lower than the first active region A 1. However, in the display apparatus according to another aspect of the present disclosure, the second semiconductor structure 221 of each pixel region PA may include a plurality of active regions A 1 and A 2. For example, in the display apparatus according to another aspect of the present disclosure, the second semiconductor structure 221 may include a first active area A 1 disposed between a second active area A 2 and a third active area A 3, as shown in FIG. 21. Each of the first active region A 1, the second active region A 2, and the third active region A 3 may include an active channel disposed between an active drain and an active source. The second drain electrode 225 may be electrically connected to an active drain of the first active region A 1, an active drain of the second active region A 2, and an active drain of the third active region A 3. The second source electrode 227 may be electrically connected to an active source of the first active region A 1, an active source of the second active region A 2, and an active source of the third active region A 3.The second gate electrode on the second semiconductor structure 221 may include a first sub-gate 223 a, a second sub-gate 223 b, a first connection gate 223 c, a third sub-gate 223 f, and a second connection gate 223 e. The first active region A 1 may be activated before the second active region A 2 and the third active region A 3. For example, the second sub-gate 223 belectrically connected to the first sub-gate 223 athrough the first connection gate 223 cmay partially overlap an active channel of the second active region A 2, the third sub-gate 223 felectrically connected to the first sub-gate 223 athrough the second connection gate 223 emay partially overlap an active channel of the third active region A 3, and an active channel of the first active region A 1 may be disposed outside the second sub-gate 223 band the third sub-gate 223 f. An active channel of the first active region A 1 may have an electrical conductivity corresponding to a voltage applied to the first sub-gate 223 a. Thus, in the display device according to another aspect of the present disclosure, when a low voltage is applied to the second gate electrode, only the first active region A 1 may be activated. And in the display device according to another aspect of the present disclosure, when a high voltage is applied to the second gate electrode, all of the first active region A 1, the second active region A 2, and the third active region A 3 may be activated. Therefore, in the display apparatus according to another aspect of the present disclosure, the driving current generated by the second thin film transistor TR 2 of each pixel region PA can be effectively adjusted according to the grayscale of the realized image. In addition, in the display apparatus according to another aspect of the present disclosure, the power consumption required to realize a low gray level image can be reduced without degrading the characteristics of the second thin film transistor TR 2 in each pixel region PA.In the display apparatus according to another aspect of the present disclosure, a channel of an active channel of the third active area A 3 may be formed at a voltage different from a channel of an active channel of the second active area A 2. For example, in the display apparatus according to another aspect of the present disclosure, a channel of an active channel of the first active region A 1 may be formed at a first threshold voltage, a channel of an active channel of the second active region A 2 may be formed at a second threshold voltage higher than the first threshold voltage, and a channel of an active channel of the third active region A 3 may be formed at a third threshold voltage higher than the second threshold voltage. Thus, in the display apparatus according to another aspect of the present disclosure, a width of an activation region of the second semiconductor structure 221 in each pixel region PA may be controlled according to the grayscale of the image. Therefore, in the display apparatus according to another aspect of the present disclosure, the efficiency of the second thin film transistor TR 2 in each pixel region can be effectively improved. That is, in the display apparatus according to another aspect of the present disclosure, the efficiency of the pixel driving circuit in each pixel region can be improved without degrading the characteristics of the second thin film transistor TR 2 in the corresponding pixel region. And in the display apparatus according to another aspect of the present disclosure, power consumption can be effectively reduced.In the display device according to another aspect of the present disclosure, the second sub-gate 223 band the third sub-gate 223 fmay be disposed at different locations. For example, in the display device according to another aspect of the present disclosure, the second sub-gate 223 bmay be disposed near the second drain electrode 225, and the third sub-gate 223 fmay be disposed near the second source electrode 227, as shown in FIG. 22. Thus, in the display device according to another aspect of the present disclosure, the degree of freedom in the configuration of the second gate electrode in each pixel region can be improved.As a result, the display apparatus according to the embodiments of the present disclosure may include the pixel driving circuit electrically connected to the light emitting device, wherein a thin film transistor of the pixel driving circuit may include a semiconductor structure, a first sub-gate, and a second sub-gate, wherein the second sub-gate may be disposed between the semiconductor structure and the first sub-gate, and wherein at least a portion of a channel region of the semiconductor structure may not overlap the second sub-gate. Thus, in the display apparatus according to the embodiments of the present disclosure, only a portion of the semiconductor structure may be activated when a low-gray-level image is realized. That is, in the display device according to the embodiments of the present disclosure, when a low gray level image is realized, occurrence of stains can be prevented or reduced without degrading the characteristics of the driving thin film transistor. Thereby, in the display apparatus according to the embodiments of the present disclosure, the quality of the image provided to the user can be improved. In addition, in the display device according to the embodiments of the present disclosure, driving with lower power may be possible, and power consumption may be reduced.References included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedKR 10-2023-0179958

[0001]

Claims

A display device comprising: a semiconductor structure (221) comprising a first active region (A1) and a second active region (A2) arranged in parallel with the first active region (A1); a first sub-gate (223a) on the semiconductor structure (221), wherein the first sub-gate (223a) overlaps a first active channel (221c1) of the first active region (A1) and a second active channel (221c2) of the second active region (A2); a second sub-gate (223b) between the semiconductor structure (221) and the first sub-gate (223a), wherein the second sub-gate (223b) is insulated from the semiconductor structure (221); a drain electrode (225) electrically connected to a drain region of the semiconductor structure (221); and a source electrode (227) electrically connected to a source region of the semiconductor structure (221), wherein a width of the second sub-gate (223b) on the second active channel (221c2) is smaller than a width of the second sub-gate (223b) on the first active channel (221c1).The display device of claim 1, wherein the width of the second sub-gate (223b) on the first active channel (221c1) is greater than a width of the first sub-gate (223a) on the first active channel (221c1).The display device according to claim 1 or 2, wherein the second sub-gate (223b) is electrically connected to the first sub-gate (223a), and wherein the first sub-gate (223a) is disposed on a different layer from the second sub-gate (223b).The display device according to claim 3, wherein the first sub-gate (223a) is disposed on a different layer from the drain electrode (225) and the source electrode (227).The display device of claim 4, wherein the second sub-gate (223b) is electrically connected to the first sub-gate (223a) via a connection gate (223c) disposed outside the semiconductor structure (221).The display device according to claim 3, wherein the first sub-gate (223a) is disposed on the same layer as the drain electrode (225) and the source electrode (227) and spaced apart from the drain electrode (225) and the source electrode (227).The display device according to any one of claims 3 to 6, wherein the second active channel (221c2) includes a first sub-channel (SC1) overlapping with the second sub-gate (223b) and a second sub-channel (SC2) disposed outside the second sub-gate (223b), and wherein a distance between the first sub-channel (SC1) and the second sub-gate (223b) is smaller than a distance between the second sub-channel (SC2) and the first sub-gate (223a).The display apparatus of claim 7, wherein a resistance of the second sub-channel (SC2) is substantially equal to a resistance of the first sub-channel (SC1).The display device according to claim 7 or 8, wherein the second active channel (221c2) includes a third sub-channel (SC3) disposed outside the second sub-gate (223b), wherein a distance between the third sub-channel (SC3) and the first sub-gate (223a) is greater than a distance between the first sub-channel (SC1) and the second sub-gate (223b), and wherein the first sub-channel (SC1) is disposed between the second sub-channel (SC2) and the third sub-channel (SC3).The display device of any one of claims 1 to 9, wherein the semiconductor structure (221) comprises an oxide semiconductor, and wherein an amount of oxygen in the second active channel (221c2) is substantially equal to an amount of oxygen in the first active channel (221c1).The display device of any one of claims 1 to 10, wherein the width of the second sub-gate (223b) on the second active channel (221c2) is smaller than a width of the first sub-gate (223a) on the second active channel (221c2).The display device of any one of claims 1 to 10, wherein the semiconductor structure (221) including the first active region (A1) and the second active region (A2) includes a single doped region, and the first active region (A1) and the second active region (A2) are doped with different impurities.A display apparatus comprising: a first thin film transistor (TR1) on a pixel region (PA) of a device substrate (100), the first thin film transistor (TR1) comprising a first semiconductor structure (211) and a first gate electrode (213); a second thin film transistor (TR2) on the pixel region (PA) of the device substrate (100), the second thin film transistor (TR2) comprising a second semiconductor structure (221) and a second gate electrode (223); and a light emitting device (500) on the pixel region (PA) of the device substrate (100), the light emitting device (500) being electrically connected to the second thin film transistor (TR2), wherein the second gate electrode (223) includes a first sub-gate (223a) overlapped with a channel region (221c) of the second semiconductor structure (221) and a second sub-gate (223b) disposed between the second semiconductor structure (221) and the first sub-gate (223a), wherein the channel region (221c) of the second semiconductor structure (221) includes a first active channel having a portion overlapped with the second sub-gate (223b) and a second active channel disposed outside the second sub-gate (223b), and wherein the first active channel having a resistance larger than the second active channel includes a first sub-channel, which overlaps with the second sub-gate (223b) and has a second sub-channel which is arranged outside the second sub-gate (223b).The display device of claim 13, wherein a resistance of the second sub-channel is equal to a resistance of the second active channel.The display device according to claim 13 or 14, wherein the second sub-gate (223b) includes a different material from the first sub-gate (223a).The display device of claim 15, wherein the first gate electrode (213) comprises a same material as the second sub-gate (223b).The display device of claim 15 or 16, further comprising: a first gate insulating layer (122) between the second semiconductor structure (221) and the second sub-gate (223b); and a second gate insulating layer (123) between the second sub-gate (223b) and the first sub-gate (223a), wherein the first gate electrode (213) is disposed between the first gate insulating layer (122) and the second gate insulating layer (123).The display apparatus of claim 17, further comprising: an upper interlayer insulating film (160) on the second gate insulating film (123), the upper interlayer insulating film (160) covering the first sub-gate (223a); and a storage capacitor (Cst) on the pixel region (PA) of the device substrate (100), the storage capacitor (Cst) comprising: a first capacitor electrode (251) disposed between the first gate insulating film (122) and the second gate insulating film (123), a second capacitor electrode (252) disposed between the second gate insulating film (123) and the upper interlayer insulating film (160), and a third capacitor electrode (253) disposed on the upper interlayer insulating film (160).The display device of any one of claims 13 to 18, wherein a channel region of the first semiconductor structure (211) has a resistance larger than a drain region and a source region of the first semiconductor structure (211), and wherein the first sub-channel has a resistance equal to the channel region of the first semiconductor structure (211).The display device according to any one of claims 13 to 19, wherein the second gate electrode (223) further includes a third sub-gate (223d) disposed on a same layer as the second sub-gate (223b), wherein the channel region (221c) of the second semiconductor structure (221) further includes a third active channel having a portion overlapping with the third sub-gate (223d), and wherein the second active channel is disposed between the first active channel and the third active channel.

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