Semiconductor-on-insulator device with a base substrate and field control area

Abstract

The invention relates to a semiconductor-on-insulator device comprising a base substrate (110) with a background doping of a first conductivity type, wherein a field control region (250) of a complementary second conductivity type extends from a front surface (111) into the base substrate (110), and wherein a net dopant concentration in the field control region (250) decreases along a lateral direction parallel to the front surface (111) at a lower rate than along a vertical direction orthogonal to the front surface (111); an insulator layer (120) formed on the front surface (111);and a semiconductor layer (130) formed on the insulating layer (120), wherein a semiconductor element (300) formed in the semiconductor layer (130) comprises a first contact area (310) formed above the field control area (250) and a second contact area (320) in the lateral direction with decreasing net dopant concentration in the field control area (250).

Description

TECHNICAL FIELDThe present disclosure relates to a semiconductor-on-insulator device including a base substrate in which a field control region is formed. Examples of the present disclosure relate to gate driver circuits having a high voltage part, a low voltage part and high voltage semiconductor elements forming signal and / or power interfaces between the low voltage part and the high voltage part.BACKGROUNDHigh voltage semiconductor devices in CMOS technology (complementary metal oxide semiconductors) interface between standard CMOS devices with input voltages up to 5 V on the one hand and industrial or consumer circuits operating at signal voltage levels above 30 V on the other hand. Applications for such semiconductor devices exist in all types of power conversion and electric drives up to the kV range, e.g., in power converters, robotics, and the automotive industry. High voltage semiconductor devices typically include a low voltage portion operating in a low voltage region and a high voltage portion operating in a high voltage region. In the low voltage part, most of the signal processing is performed at low operating voltage. The high voltage portion operates at a higher voltage level. The low voltage portion and the high voltage portion provide signal interfaces for power semiconductors that use higher voltage levels and / or have higher current driving and sinking capability. The electrical potentials of the different voltage ranges may differ by several 100 V up to several 1000 V. An example of such a high voltage semiconductor device is a gate drive circuit. Gate driver circuits allow a microcontroller or DSP (Digital Signal Processor) to efficiently turn power semiconductor switches on and off. Such semiconductor devices are typically silicon-on-insulator devices with high voltage semiconductor elements for exchanging electrical signals between the CMOS circuits in the various voltage ranges.Generic lateral semiconductor components in semiconductor-on-insulator technology are known, for example, from the following publications: DE 101 06 359 C1, U.S. Pat. No. 2024 / 0 186998 A1, DE 10 2023 116 441 A1, DE 10 2008 034 158 A1, U.S. Pat. No. 10 340 290 B2 and DE 44 41 724 A1.There is a constant need to improve signal transmission in semiconductor-on-insulator devices with high voltage semiconductor elements.SUMMARYThe present disclosure relates to a semiconductor-on-insulator device comprising a base substrate with a background doping of a first conductivity type. A field control region of a complementary second conductivity type extends into the base substrate from a front surface of the base substrate, wherein a net dopant concentration in the field control region decreases along a lateral direction parallel to the front surface at a lesser rate than along a vertical direction orthogonal to the front surface. An insulator layer is formed on the front surface of the base substrate, and a semiconductor layer is formed on the insulator layer. A semiconductor element formed in the semiconductor layer includes a first contact region formed over the field control region and a second contact region spaced from the first contact region in the lateral direction with decreasing net dopant concentration in the field control region.High voltage semiconductor-on-insulator devices typically include a high voltage device having a large potential transition region formed between first doping regions associated with a low voltage portion and second doping regions associated with a high voltage portion. The high voltage device comprises the semiconductor elements for exchanging electrical signals and / or electrical power between the low voltage part and the high voltage part, wherein the semiconductor elements comprise low-doped extension regions (drift regions) in the potential transition region. The field control region is formed in a portion of the base substrate directly below a first of the contact regions of the semiconductor element at a first side of the potential transition region. The field control region comprises a region of variation of the lateral doping (VLD) which extends in the direction of the second contact region. The charges in the VLD region affect the charge carrier contribution in the drift portion and may be used to increase the doping of the drift region, for example to decrease the on-state resistance of a semiconductor element having a switching function. In the case of a high voltage device comprising two or more different semiconductor elements, the device characteristics of the semiconductor elements may be tuned independently of each other.BRIEF DESCRIPTION OF THE DRAWINGSThe present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals refer to similar or identical elements. The elements of the drawings are not necessarily to scale relative to each other. The features of the various illustrated examples may be combined unless they are mutually exclusive. FIGS. 1A and 1B include a schematic horizontal cross-sectional view and a schematic vertical cross-sectional view of a portion of a semiconductor-on-insulator (SOI) device having a field control region with a net dopant concentration decreasing along a lateral direction at a lower rate than along a vertical direction (VLD) region, according to an embodiment. FIGS. 2A and 2B include a schematic horizontal cross-sectional view and a schematic vertical cross-sectional view of a portion of a SOl device according to an embodiment, which relates to a high voltage device having two semiconductor elements sharing a portion of a central field control region in a back-to-back configuration. FIGS. 3A, 3B, and 3C include a schematic horizontal cross-sectional view and two schematic vertical cross-sectional views of a portion of a SOl device according to an embodiment relating to a high voltage, stadione-shaped device having two semiconductor elements formed side by side and VLD regions extending outward into the potential transition region. FIGS. 4A, 4B, and 4C include a schematic horizontal cross-sectional view and two schematic vertical cross-sectional views of a portion of a SOl device according to an embodiment relating to a high voltage, stadione-shaped device having two semiconductor elements formed side by side and VLD regions extending inward into the potential transition region. FIGS. 5A and 5B include a schematic vertical cross-sectional view and a schematic horizontal cross-sectional view of a portion of a SOl device according to an embodiment related to a high voltage device including a high voltage semiconductor diode. FIGS. 6A and 6B include a schematic vertical cross-sectional view and a schematic horizontal cross-sectional view of a portion of a SOl device according to an embodiment related to a high voltage device with a junction field effect transistor (JFET). FIGS. 7A and 7B include a schematic vertical cross-sectional view and a schematic horizontal cross-sectional view of a portion of a SOl device according to an embodiment related to a high voltage device with a high voltage bipolar junction transistor (BJT). FIGS. 8A and 8B include a schematic vertical cross-sectional view and a schematic horizontal cross-sectional view of a portion of a SOl device according to an embodiment related to a high voltage device with an insulated gate high voltage field effect transistor (IGFET). FIG. 9 is a schematic block diagram of a gate driver circuit including BJTs and MOSFETs for conducting differential data signals from a high side portion to a low side portion and from the low side portion to the high side portion, according to an embodiment.DETAILED DESCRIPTIONThe terms "have," "contain," "comprise," "comprise," and the like are open ended terms, and the terms indicate the presence of certain structures, elements, or features, but do not exclude the presence of additional elements or features. The articles "a", "an", and "the / s" include both the plural and the singular, unless the context clearly indicates otherwise.The terms "signal connected" and "electrically coupled" comprise a permanent low-ohmic connection between electrically connected elements, for example a direct contact between the relevant elements or a low-ohmic connection via a metal and / or highly doped semiconductor material, but do not exclude the presence of further passive and / or active elements in the signal path between the "signal connected" or "electrically coupled" elements. For example, the further elements may include resistors, ohmic conductive traces, capacitors and / or inductors, transistors, semiconductor diodes, Schottky diodes, transformers, optocouplers, and others.The term "power semiconductor device" refers to semiconductor devices having a high voltage blocking capability of at least 30 V, for example 48 V, 100 V, 600 V, 1.6 kV, 3.3 kV or more, and having a nominal forward current or forward current of at least 200 mA, for example 1 A, 10 A or more.An ohmic contact describes a non-rectifying electrical transition between two conductors, e.g. between a semiconductor material and a metal. The ohmic contact has a linear or approximately linear current-voltage (I-V) curve in the first and third quadrants of the I-V diagram as in Ohmic Law.Ranges indicated for physical dimensions include the limits. For example, a range for a parameter y reads from a to b as a≤y≤b. The same applies to ranges having a limit value such as "at most" and "at least.".The term "on" should not be construed to mean only "directly on". Rather, when an element is positioned "on" another element (e.g., a layer "on" another layer or "on" a substrate), another component (e.g., another layer) may be positioned between the two elements (e.g., another layer may be positioned between a layer and a substrate when the layer is "on" the substrate).Two adjacent doping regions in a semiconductor layer form a semiconductor junction. Two adjacent doping regions of the same conductivity type and having different dopant concentrations form a unipolar junction, e.g. an n / n+ or p / p+ junction along an interface between the two doping regions. At the unipolar junction, a dopant concentration profile orthogonal to the unipolar junction may show a step or inflection point at which the dopant concentration profile changes from concave to convex, or vice versa. Two adjacent doping regions with complementary conductivities form a pn junction.The figures illustrate relative doping concentrations by indicating "-" or "+" adjacent to the doping type "n" or "p". For example, "n-" means a doping concentration lower than the doping concentration of an "n" doping region, while an "n+" doping region has a higher doping concentration than an "n" doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions may have the same or different absolute doping concentrations.The examples described herein provide a semiconductor-on-insulator device. The semiconductor-on-insulator device includes a base substrate and an insulator layer and a semiconductor layer. The base substrate has a background doping of a first conductivity type, wherein a field control region of a complementary second conductivity type extends from a front surface into the base substrate, and wherein a net dopant concentration in the field control region decreases along a lateral direction parallel to the front surface at a lower rate than along a vertical direction orthogonal to the front surface. The insulator layer is formed on the front surface of the base substrate. The semiconductor layer is formed on the insulator layer, wherein a semiconductor element formed in the semiconductor layer includes a first contact region formed over the field control region and a second contact region formed at a lateral distance from the field control region.The base substrate may include a single crystal silicon layer having a weak background doping of the first conductivity type. The field control region includes the background doping and a complementary doping resulting from implanting dopants of the complementary doping type and annealing the implanted dopants. A net doping is given by the difference between the doping resulting from the implanted dopants and the background doping. In at least a portion of the field control region, the net dopant concentration in the lateral direction decreases from a maximum net dopant concentration on one side to a minimum net dopant concentration on the opposite side of the field control region. In addition to one or more portions of decreasing dopant concentration, the field control region may also include one or more portions of constant net dopant concentration. The net dopant concentration may be in the lateral direction from a maximum net dopant concentration to a minimum net dopant concentration of less than 15% of the maximum net dopant concentration, e.g., zero net doping (equilibrium doping).The lateral decrease in net dopant concentration may be monotone, e.g., stepwise or strictly monotone. For example, the net dopant concentration may decrease linearly, according to a square root function, or according to a logarithmic function. The average rate at which the net dopant concentration decreases in the lateral direction may be at most 50%, e.g. at most 20%, or at most 10%, of the rate at which the net dopant concentration decreases in the vertical direction. The lateral diffusion profile may be obtained by locally modifying the implanted dose of dopants of the second conductivity type using an implantation mask having laterally changing ion permeability per unit area. For example, the area occupancy of the front surface of the base substrate by the implantation mask and / or the vertical extension of the implantation mask in the lateral direction increases.The first conductivity type may be n-type conductivity and the second conductivity type may be p-type conductivity. Alternatively, the first conductivity type is p-type conductivity and the second conductivity type is n-type conductivity.The insulator layer is formed directly on the front surface and separates the base substrate and the semiconductor layer from each other. The insulator layer may be a homogeneous layer or may be a layer stack comprising two or more sub-layers which differ from one another in material composition and / or density.The semiconductor layer may have a uniform background doping of the first or second conductivity type. A vertical extension of the first contact region and the second contact region may be equal to the vertical extension of the semiconductor layer. The first contact region and the second contact region may have the same conductivity type or may have different conductivity types. The dopant concentrations in the first contact region and the second contact region are sufficiently high to form low ohmic contacts with suitable metals, e.g., aluminum, tantalum, titanium, tungsten, copper, silver, or heavily doped polycrystalline silicon. The semiconductor layer, the insulator layer, and the base substrate form an SOI (silicon-on-insulator) die.The semiconductor element may be a high voltage semiconductor device or a semiconductor switching device, for example a bipolar junction transistor (BJT), a junction field effect transistor (JFET), or an insulated gate field effect transistor (IGFET), for example a MOSFET (metal oxide semiconductor field effect transistor (MOSFET) in the broad sense, including FETs with polysilicon gate electrodes.The semiconductor element forms part of a high voltage device having a central region, a peripheral region and a potential transition region separating the peripheral region from the central region. The first contact region is formed in the central region and the second contact region may be formed in the peripheral region. The semiconductor element comprises an extension region or drift region in the potential transition region.Vertical projections of the first contact region and the field control region into the plane of the front surface overlap one another. Vertical projections of the second contact region and a portion of the field control region with laterally decreasing net dopant concentration into the plane of the front surface may overlap one another or may be laterally separated from one another. The smooth lateral transition of the field control region may improve some of the device characteristics of the semiconductor element formed in the semiconductor layer without adverse effects on the voltage blocking capability.According to an embodiment, the field control region may comprise a doping transition region. In the doping transition region, the net dopant concentration decreases at an average first rate in the lateral direction and at an average second rate in the vertical direction, the average second rate being at least twice the average first rate.The shallower decrease in the lateral direction may be achieved by implanting the dopants through an implantation mask having openings and tuning the local implantation dose by varying the local ratio between the cross-sectional area of the openings and the cross-sectional area of the mask material in an area unit from a higher value to a lower value.A lateral length d0of the doping transition region along a lateral direction with maximum doping gradient may be twice, e.g. at least five times or at least 10 times a maximum vertical extension v0of the doping transition region. For example, the net dopant concentration decreases from 85% of the net maximum dopant concentration to 15% of the net maximum dopant concentration over a distance of 65 μm in the lateral direction and over a distance of about 3 μm in the vertical direction.Vertical projections of the second contact region and the doping transition region into the plane of the front surface may overlap each other or may be laterally separated from each other.According to an embodiment, the field control region may further comprise a constant doping region having a constant net dopant concentration in direct lateral contact with the doping transition region.The side of the maximum dopant concentration in the doping transition region is aligned with the constant doping region. The dopant concentration in the constant doping region and the maximum dopant concentration in the doping transition region may be the same.The constant doping region may be a lateral continuous region with the maximum dopant concentration of the doping transition region and without gaps. Alternatively, the constant doping region can laterally embed gaps with a different conductivity type and / or different dopant concentrations. Lateral transitions of the net dopant concentration between the constant doping region and the embedded gaps are significantly steeper than the lateral variation of the doping in the doping transition region.According to an embodiment, the second contact region may be formed at a lateral distance from the constant doping region.The second contact region may be formed over the doping transition region, wherein vertical projections of the second contact region and the doping transition region overlap each other in the plane of the front surface. Alternatively, the second contact region may be formed at a lateral distance from the field control region, wherein vertical projections of the second contact region and the field control region in the plane of the front surface do not overlap each other.According to an embodiment, the doping transition region may comprise portions on opposite sides of the constant doping region, wherein the net dopant concentration in the portions of the doping transition region decreases in a direction away from the constant doping region.The constant doping region may be rectangular, rectangular with rounded corners, circular or stadion-shaped with a rectangular portion and two tapered portions at opposite sides of the rectangular portion. The tapered portions may be semicircular portions, wherein the diameter of each semicircular portion may be equal to the corresponding side length of the rectangular portion.According to an embodiment, the doping transition region may laterally surround the constant doping region, wherein the net dopant concentration in the doping transition region decreases in a radial direction outwards.The constant doping region may be circular, rectangular with rounded corners or stannically with a rectangular portion and two tapered portions on opposite sides of the rectangular portion. The tapered portions may be semicircular portions, wherein the diameter of each semicircular portion may be equal to the corresponding side length of the rectangular portion.The outer edge of the constant doping region may be the outer edge of a first voltage region, which may include the low side portion of a gate driver circuit.For a doping transition region forming a circular ring, the radial direction is directed from the center of the circular ring. For the semicircular sections of a dione-shaped doping transition region, the radial direction is directed from the center point of the respective semicircle. For the rectangular portion of a dione-shaped doping transition region, the radial direction is orthogonal to a line of symmetry connecting the two midpoints of the semicircular portions.According to an embodiment, the doping transition region may laterally surround a second voltage region and the net dopant concentration in the doping transition region decreases in a radially inward direction.In a semiconductor-on-insulator device with constant doping region, the constant doping region forms a ring at the outer edge of the ring-shaped doping transition region. The second voltage range may include the high side portion of a gate driver circuit.The doping transition region may be constant and without steps in a tangential direction orthogonal to the radial direction.According to an embodiment, the doping transition region comprises at least a first sector and a second sector, wherein the first sector and the second sector have different net dopant gradients in the radial direction.Each sector extends in the radial direction as defined above. When the doping transition region forms a ring comprising straight portions, each sector may be formed in a straight portion. The net dopant gradients may differ logarithmically with respect to the maximum dopant concentration, the rate of lateral decrease of the net dopant concentration and / or the type of gradient, linearly, square root, wherein different semiconductor elements are formed in laterally separated parts of the semiconductor layer, wherein the net dopant gradient in each sector may be adapted to the type of semiconductor element formed over the same sector in the semiconductor layer.According to an embodiment, a channel stopper region of the first conductivity type may be formed in the base substrate in direct lateral contact with the field control region.The channel stopper region may extend laterally from the field control region to an adjacent doped region of the second conductivity type, e.g., a field region in the second voltage region. A maximum vertical extension v 2 of the channel stopper portion may be smaller than the maximum vertical extension v 0 of the field control portion, e.g. at most 50%, 20% or 10% of the maximum vertical extension v 0 of the field control portion 250. A net dopant concentration in the channel stopper region is lower than in the field control region 250. A net dopant concentration in the channel stopper region may be lower than the maximum net dopant concentration in the field control region. The channel stopper region may suppress the formation of a parasitic transistor channel along the front surface between the field control region and the next second conductivity type doped region. The presence of the channel stopper region may also increase the process window for the background doping of the base substrate.Forming the channel stopper region may include shallow ion implantation through the front surface of the base substrate and annealing the base substrate. The ion implantation may be an un-masked (blanket) implant that reduces the net dopant concentration in a vertical portion of the field control region directly adjacent the front surface.According to an embodiment, a voltage reduction structure may be formed in the semiconductor layer between the first contact region and the second contact region.The voltage reduction structure may be configured to withstand a blocking voltage applied between the first contact region and the second contact region, wherein the blocking voltage may be at least 60 V, e.g. at least 100 V or at least 600 V. The voltage reduction structure may comprise a lightly doped lateral drift zone of a conductivity type of the second contact region, wherein the drift zone may be uniformly doped or may have a lateral doping gradient, and wherein the drift zone may be combined with a more heavily doped buffer region between the drift zone and the second contact region.According to an embodiment, the voltage reduction structure may include first compensation regions of the first conductivity type and second compensation regions of the second conductivity type, wherein the first and second compensation regions alternate along a tangential direction orthogonal to shortest connection lines between the first contact region and the second contact region.The first compensation regions and the second compensation regions form a compensation structure (superjunction structure), wherein the doping concentrations and the expansions along a lateral tangential direction orthogonal to the radial direction, the number of charges of dopants in the first compensation regions and the number of dopants in the second compensation regions are selected such that in the blocking state the compensation structure is completely depleted of mobile charge carriers. Charges in the first compensation regions and the second compensation regions are largely absorbed in the presence of an electric field to which the field control region contributes.Compared to field rings, the process of forming the doping transition region may be more stable with the variation of the lateral doping and / or the charge compensation effect is less sensitive to process variations for the doping transition region than for field rings. For n-channel IGFETs, the dopant concentration in n conductive compensation regions may be increased to reduce the on-state resistance RDSon. For p-channel JFETs, the dopant concentration in p-type compensation regions may be increased to reduce the on-state resistance RDSon. Additionally, different semiconductor elements may be provided in the same high voltage device with doping transition regions having different lateral lengths d 0.According to an embodiment, the first contact region and the second contact region have a different conductivity type.The stress reduction structure may extend from the first contact region to the second contact region. The voltage reduction structure may include a lightly doped drift zone extending from the first contact region to the second contact region. Alternatively, the voltage reduction structure may comprise a buffer region between the lightly doped drift zone and the second contact region. Alternatively, the voltage reduction structure may comprise a compensation structure, wherein the first compensation regions and the second contact region form unipolar junctions. The second compensation regions and the first contact region may form unipolar junctions or may be separated by a lightly doped region of the conductivity type of the first contact region.For example, the first contact region is p-conductive and the second contact region is n-conductive. The semiconductor element is a semiconductor diode, wherein the first contact region forms the anode and the second contact region forms the cathode.According to an embodiment, the first contact region and the second contact region have the same conductivity type.The voltage reduction structure may be in direct contact with a first one of the first contact region and the second contact region and may be separated from the second one of the first contact region and the second contact region. The voltage reduction structure may comprise a lightly doped drift zone of the conductivity type of the first and second contact regions and form a unipolar junction with one of the first contact region and the second contact region. Alternatively, the voltage reduction structure may comprise a buffer region of the conductivity type of the drift zone between the lightly doped drift zone and a first of the first contact region and the second contact region. Alternatively, the voltage reduction structure may comprise a compensation structure, wherein the first compensation regions and a first of the first contact region and the second contact region form unipolar junctions.For example, the first and the second contact region are p-conductive. The semiconductor element may be a pnp BJT bipolar junction transistor, a p-channel JFET junction field effect transistor, or an insulated gate p-channel IGFET field effect transistor, e.g., a MOSFET.According to an embodiment, a voltage reduction structure may be formed in the semiconductor layer between the first contact region and the second contact region, wherein gate regions of a conductivity type complementary to the conductivity type of the first and second contact regions are formed in the semiconductor layer between the voltage reduction structure and a first of the first and second contact regions. The gate regions are laterally separated along a tangential direction orthogonal to shortest connection lines between the first and second contact regions.The gate regions are laterally separated by channel regions of the complementary conductivity type. If the voltage reduction structure includes first compensation regions and second compensation regions, the first compensation regions may have the same lateral center-to-center distance as the gate regions. Each gate region may form a unipolar junction with a compensation region of the same conductivity type. Each channel region may form a unipolar junction with a compensation region of the same conductivity type.For example, the semiconductor element may be a p-channel JFET, wherein the first and second contact regions are p-conductive and the gate regions are n-conductive. The gate regions may be formed as lateral expansions of the first compensation regions and the channel regions may be formed as lateral expansions of the second compensation regions.According to another embodiment having a voltage reduction structure formed in the semiconductor layer between the first contact region and the second contact region, a base / body region of a conductivity type complementary to the conductivity type of the first and second contact regions may be formed in the semiconductor layer between the voltage reduction structure and a first of the first and second contact regions.The base / body portion may laterally separate the voltage reduction structure from the first of the first and second contact regions. Alternatively, a further doped region of the conductivity type of the adjacent contact region may be formed between the voltage reduction structure and the first of the first and second contact regions, wherein a net dopant dose of the further doped region is less than in the first of the first and second contact regions.According to an embodiment, the semiconductor-on-insulator device may comprise a third contact structure, wherein the third contact structure and the base / body region form an ohmic contact.The base / body region forms the base region of a BJT. For example, the semiconductor element may be a pnp BJT, wherein the first and second contact regions are p-conductive and the base region is n-conductive, wherein the base region may be formed between the voltage reduction structure and the second contact region.According to another embodiment, the semiconductor-on-insulator device may include a gate electrode and a gate dielectric separating the base / body region and the gate electrode from each other.The base / body region forms the body region of an IGFET, e.g. a MOSFET. For example, the semiconductor element may be an n-channel MOSFET, wherein the first and second contact regions are n-conductive and the base / body region is p-conductive, wherein the base / body region is formed between the first contact region and the voltage reduction structure.According to an embodiment, the semiconductor-on-insulator device may include a passivation layer, wherein the passivation layer may be formed on the semiconductor layer and wherein the passivation layer may include a silicon nitride.The silicon nitride may be a silicon nitride having a higher silicon content than a stoichiometric silicon nitride Si 3 N 4( SiSiN). The SiSiN passivation layer is sufficiently resistive to avoid charge accumulation in the layers over the semiconductor element. The SiSiN layer is robust against degradation resulting from the absorption of moisture and may replace a metal structure, e.g. a field plate structure, that shields the semiconductor layer from charges accumulated in the passivation layer.According to an embodiment, the semiconductor-on-insulator device may include a low-side circuit and a high-side circuit. The low-side circuit may be configured to generate a low-side data signal and output a first gate drive signal between a first gate output and a first reference potential VSS. The semiconductor element may be configured to transmit a voltage and / or to conduct the low-side data signal from the low-side circuit to the high-side circuit and / or to conduct the high-side data signal from the high-side circuit to the low-side circuit. The semiconductor-on-insulator device may be a gate driver integrated device.FIGS. 1A and 1B show a portion of a semiconductor-on-insulator device 500 including a high voltage semiconductor diode 383. Semiconductor regions of the high voltage semiconductor diode 383 are formed in a semiconductor layer 130. The semiconductor layer 130 has a first surface 131 on a front side and a second surface 132 opposite to the front side. The first surface 131 and the second surface 132 are formed in two parallel horizontal planes. A normal to the horizontal planes defines a vertical direction. The semiconductor layer 130 includes a single crystal silicon layer having a uniform vertical extension (thickness) between the first surface 131 and the second surface 132. A vertical extension v 3 of the semiconductor layer 130 may be in a range from 50 nm to 1 μm, e.g. in a range from 100 nm to 150 nm.The semiconductor layer 130 has a homogeneous background doping. In the illustrated example, the semiconductor layer 130 has a weak p-type (p-type) background doping. Doped regions 310, 320, 325 in the semiconductor layer 130 contain the background doping and dopants which are implanted by ion beam implantation through the first surface 131 and activated in a heat treatment.An insulator layer 120 separates the second surface 132 of the semiconductor layer 130 from a front surface 111 of a base substrate 110. The semiconductor layer 130 and the insulator layer 120 are in direct contact with each other and form a horizontal interface. A vertical extension of the insulator layer 120 may be in a range from 200 nm to 3 μm, e.g. in a range from 400 nm to 600 nm. The insulator layer 120 may be a homogeneous layer or may be a layer stack comprising at least two layers of different composition and / or structure. For example, the insulator layer 120 may comprise or be a semiconductor oxide layer, e.g. a silicon oxide layer.The base substrate 110 includes a single crystal silicon layer having a weak background doping with n-type conductivity. The semiconductor layer 130, the insulator layer 120, and the base substrate 110 form an SOI (silicon-on-insulator) die 100.A p-type field control region 250 extends from the front surface 111 into the base substrate 110. The field control region 250 includes a constant dopant region 254 having a net constant dopant concentration and a dopant transition region 255. The doping transition region 255 shows a variation in lateral doping, wherein the net dopant concentration decreases at a significantly lower rate in the lateral direction than in the vertical direction. In the embodiment shown, the net dopant concentration decreases linearly with increasing lateral distance from the constant doping region 254 over a lateral length d 0. A vertical extension of the doping transition region 255 decreases linearly with increasing lateral distance from the constant doping region 254. A background doping region 115 with the background doping separates the field control region 250 from a back surface 112 of the base substrate 110.The constant doping region 254 and the doping transition region 255 are in direct contact with each other and the maximum net dopant concentration in the doping transition region 255 is the same as in the constant doping region 254.The semiconductor layer 130 comprises a first contact region 310 and a second contact region 320 at a lateral distance from the first contact region 310. The first contact region 310 is formed over the constant doping region 254, wherein vertical projections of the first contact region 310 and the constant doping region 254 into the plane of the front surface 111 of the base substrate 110 overlap one another. The second contact region 320 is formed at a first lateral distance d 1 from an outer lateral edge of the field control region 250. A vertical extension of the first contact region 310 and the second contact region 320 may be equal to the vertical extension v 3 of the semiconductor layer 130.The first contact region 310 is p-conductive and forms an anode contact region electrically connected to an anode terminal A. The second contact region 320 is n-conductive and forms a cathode contact region which is electrically connected to a cathode terminal K. A voltage reduction region 350 between the first contact region 310 and the second contact region 320 is configured for a high voltage blocking capability of at least 60 V.In the illustrated example, the voltage reduction region 350 comprises a lightly p-doped drift zone in direct contact with the first contact region 310. An n-type buffer region 325 laterally separates the drift zone and the second contact region 320.The first contact region 310 and the constant doping region 254 are formed in a first voltage region 170 of the semiconductor-on-insulator device 500. The second contact region 320 is formed in a second voltage region 190 of the semiconductor-on-insulator device 500. A transition region 180 laterally separating the first voltage region 170 and the second voltage region 190 may extend from an edge of the constant doping region 254 aligned with the second voltage region 190 to an edge of the second contact region 320 aligned with the first voltage region 170.In FIGS. 2A and 2B, the first stress region 170 includes a rectangular portion. Two portions of the transition region 180 on opposite sides of the first stress region 170 separate the first stress region 170 from two portions of the second stress region 190 formed on opposite sides of the first stress region 170. In the base substrate 110, the field control region 250 includes a rectangular portion of a constant doping region 254 in the first voltage region 170 and two portions of a doping transition region 255 on opposite sides of the first voltage region 170 in the transition region 180. In the semiconductor layer 130, a first contact region 310 is formed in the first stress region 170, and two separate second contact regions 320 are formed on opposite sides of the first contact region 310 in the second stress region 190.In a case where the two second contact regions 320 are electrically separated, two different semiconductor elements are formed on opposite sides of the first voltage region 170. In a case where the two second contact regions 320 are directly electrically connected by a low impedance path, two parts of the same semiconductor element are formed on opposite sides of the first voltage region 170.FIGS. 3A, 3B, and 3C show a portion of a semiconductor-on-insulator device 500 with a high voltage device 510 comprising two semiconductor elements 300 formed side-by-side.The high voltage device includes a stadion-shaped first voltage region 170 having a rectangular portion and two tapered portions on opposite sides of the rectangular portion. Each tapered portion comprises two quarter cycle portions and another rectangular portion connecting the two quarter cycle portions. The transition region 180 laterally surrounds the first stress region 170 with a uniform width. The first stress region 170 and the transition region 180 are formed symmetrically with respect to two orthogonal lateral axes of symmetry. A second stress region 190 is connected to the outer edge of the transition region 180 and surrounds the transition region 180.A field control region 250 is formed in the base substrate 110, comprising a constant doping region 254 in the first voltage region 170 and a doping transition region 255 in the transition region 180. The doping transition region 255 laterally surrounds the constant doping region 254, wherein in the doping transition region 255 the net dopant concentration decreases with increasing distance from the constant doping region 254 in a radial direction. The constant doping region 254 laterally surrounds a gap 259 with the background doping of the base substrate 110. A p-type field region 290 is formed in the base substrate 110 in the second voltage region 190.A lateral transition of the net dopant concentration between the constant dopant region 254 and the embedded gap 259 and a lateral transition of the net dopant concentration along the lateral edge of the field region 290 are significantly steeper than the lateral variation of the doping in the doping transition region 255.The doping transition region 255 comprises a first sector 251 and a second sector 252, wherein the first sector 251 and the second sector 252 have different net dopant gradients in a radial direction orthogonal to one of the lateral axes of symmetry. The first sector 251 and the second sector 252 are formed in a straight portion of the transition region 180. The net dopant gradient in the first sector 251 is flatter than the net dopant gradient in the second sector 252. A first lateral length da of the first sector 251 is greater than a second lateral length db of the second sector 252. The first sector 251 is part of a first semiconductor element 300 and the second sector 252 is part of a second semiconductor element 300, wherein the net dopant gradient of the dopant transition region 255 in the first and second sectors 251, 252 are independent of each other and can be individually adapted to the type of semiconductor element 300 formed above the respective sector 251, 252.In the illustrated example, the doping transition region 255 is also formed along the tapering sections of the constant doping region 254. In another example (not shown), the doping transition region 255 is absent along the tapered portions of the constant doping region 254.The semiconductor-on-insulator device 500 may be a gate driver circuit, wherein a high voltage part is formed in the first voltage region and the low voltage part is formed in the second voltage region. The low voltage portion includes logic and analog circuits using a first supply voltage reference potential and the high voltage portion includes logic and analog circuits using a second supply voltage reference potential, wherein the first supply voltage reference potential and the second supply voltage reference potential differ from each other by more than 50 V. A first one of the semiconductor elements may be an n-channel MOSFET for transmitting electrical signals from the low voltage part to the high voltage part and a p-channel JFET for transmitting electrical signals from the high voltage part to the low voltage part.FIGS. 4A, 4B, and 4C show a semiconductor-on-insulator device having a stadion-shaped second voltage region 190 that includes a rectangular portion and two semicircular portions on opposite sides of the rectangular portion. An annular transition region 180 having a uniform width laterally surrounds the second tension region 190. The second stress region 190 and the transition region 180 are formed symmetrically with respect to two orthogonal lateral axes of symmetry. A first stress region 170 is connected to the outer edge of the transition region 180 and surrounds the transition region 180.A field control region 250 is formed in the base substrate 110, comprising a constant doping region 254 in the first voltage region 170 and a doping transition region 255 in the transition region 180. The doping transition region 255 extends from the constant doping region 254 inward into the transition region 180, wherein in the doping transition region 255 the net dopant concentration decreases with increasing distance from the constant doping region 254 in a radial direction. A p-type field region 290 is formed in the base substrate 110 in the second voltage region 190.The doping transition region 255 comprises a first sector 251 and a second sector 252. In the first sector 251, the doping transition region 255 has a flatter gradient than in the second sector 252. The first sector 251 and the second sector 252 are formed in a straight portion of the transition region 180. In the illustrated example, the doping transition region 255 is also formed along the curved portions of the constant doping region 254. In another example (not shown), the doping transition region 255 is absent along the curved portions of the constant doping region 254.In FIGS. 5A and 5B, a p-type field control region 250 having a constant doping region 254 formed in a first voltage region 170 extends from a front surface 111 into a base substrate 110 having a weak n-type background doping. In a second stress region 190 surrounding the first stress region 170, a p-type field region 290 extends from the front surface 111 into the base substrate 110. In a transition region 180 separating the first stress region 170 and the second stress region 190, an n-type channel stopper region 260 extends from the front surface 111 into the base substrate 110. In the radial direction, the channel stopper region 260 extends from a doping transition region 255 of the field control region 250 to the p-type field region 290 in the second voltage region 190. A maximum vertical extension v2 of the channel stopper portion 260 is smaller than the maximum vertical extension v0 of the field control portion 250.An insulator layer 120 is formed on the front surface 111 of the base substrate 110. Substrate contact structures 379 extend through openings in insulator layer 120 to base substrate 110 and form ohmic contacts with constant doping region 254 and field region 290.A portion of a semiconductor layer 130 is formed on the insulator layer 120. A first contact region 310 is formed in the semiconductor layer 130, in the first voltage region 170, and above the constant doping region 254. A second contact region 320 is formed in the semiconductor layer 130 in an outer portion of the junction region 180 aligned with the second voltage region 190 and over the channel stopper region 260.A passivation layer 140 is formed on a first surface 131 of the semiconductor layer 130. The first contact region 310 and a first contact structure 371 extending through an opening in the passivation layer 140 form an ohmic contact. The second contact region 320 and a second contact structure 372, which extend through an opening in the passivation layer 140, form an ohmic contact. Between the first contact region 310 and the second contact region 320, a compensation structure is formed in the semiconductor layer 130.The compensation structure comprises strip-shaped first compensation regions 351 and strip-shaped second compensation regions 352. The first compensation regions 351 and second compensation regions 352 have complementary types of conductivity type and alternate in a tangential direction orthogonal to the radial direction. In the example shown, the first compensation regions 351 are n-conducting and the second compensation regions 352 are p-conducting. Lateral longitudinal axes of the first compensation regions 351 and the second compensation regions 352 are parallel to one another and to the radial direction. The first compensation regions 351 and the second contact regions 320 form semiconductor junctions.The semiconductor element 300 formed in the semiconductor layer 130 is a high voltage semiconductor diode having a p-type first contact region 310 and an n-type second contact region 320. The first contact structure 371 is electrically connected to an anode terminal A and the second contact structure 372 is electrically connected to a cathode terminal K.In FIGS. 6A and 6B, the semiconductor element 300 is a p-channel JFET having a p-type first contact region 310, a p-type second contact region 320, and heavily doped gate regions 313 in direct contact with the n-type first compensation regions 351. P-type lateral extensions of the second compensation regions 352 form channel regions 312 that laterally separate the gate regions 313 from each other. The gate regions 313 and third contact structures 373 extending through openings in the passivation layer 140 form ohmic contacts. The first contact structure 371 is electrically connected to a drain terminal D, the second contact structure 372 is electrically connected to a source terminal S, and the third contact structure 373 is electrically connected to a gate terminal G.In FIGS. 7A and 7B, the semiconductor element 300 is a pnp BJT having a p-type first contact region 310, a p-type second contact region 320, and heavily doped base contact regions 314 in direct contact with the n-type first compensation regions 351. N-type base portions 315 connect the base contact portions 314 along the tangential direction orthogonal to the radial direction. The base contact regions 314 and third contact structures 373 extending through openings in the passivation layer 140 form ohmic contacts. The first contact structure 371 is electrically connected to a collector terminal C, the second contact structure 372 is electrically connected to an emitter terminal E, and the third contact structure 373 is electrically connected to a base terminal B.In FIGS. 8A and 8B, the semiconductor element 300 is an n-channel MOSFET having n-type first contact regions 310, a p-type second contact region 320, heavily doped body contact regions 317 alternating with the first contact regions 317 along the tangential direction, and a p-type body region 316 laterally separating the first contact regions 310 and the body contact regions 317 on a first side from the compensation structure on the opposite side. A gate dielectric 361 is formed directly on the semiconductor layer 130 over the body region 316. A gate electrode 365 is formed directly on the gate dielectric 361.The first contact regions 310 and the body contact regions 317 form ohmic contacts with first contact structures 371 extending to the semiconductor layer 130 through openings in the passivation layer 140. The first contact structures 371 are electrically connected to a source terminal S, the second contact structure 372 is electrically connected to a drain terminal D. The gate electrode 365 is electrically connected to a gate terminal G.FIG. 9 illustrates a semiconductor-on-insulator device 500 configured as a gate driver circuit. The gate driver circuit includes a high-side portion 620 configured to drive a gate of a high-side switch 922 of a half bridge and a low-side portion 610 configured to drive a gate of a low-side switch 921 of the half bridge. The semiconductor-on-insulator device 500 includes a high-side power supply circuit 621 to obtain a positive power supply voltage VB for the high-side part 620 (high-side supply potential VB), and a bootstrap diode 360 charges a bootstrap capacitor from an external supply voltage VCC. The positive power supply voltage VB for the high side portion 620 is related to a high side reference potential VS corresponding to the potential of the switching node of a half bridge 920.A high side desaturation detection circuit 622 is connected to the supply potential VA of the half bridge 920, detects desaturation of the high side switch 922 of the half bridge 920, and outputs a high side desaturation signal indicating whether a desaturation condition is present. A high-side receiver circuit 623 receives a differential gate control signal from two field effect transistors, e.g., n-channel MOSFETs 381 as described above, and outputs an asymmetric high-side gate control signal. A logic circuit 624 in the high side portion 620 receives the high side desaturation signal and the high side gate control signal. The logic circuit 624 in the high side portion 620 outputs a second gate drive signal GOut 2 in response to the high side gate control signal, provided that the high side desaturation signal does not indicate a desaturation condition. A high side driver stage 625 may drive the second gate driver signal GOut 2.The logic circuit 624 in the high side part further outputs a high side differential data signal. Two pnp BJTs 382 as described above transmit the high-side differential data signal from the high-side portion 620 to a low-side receiver circuit 613 in the low-side portion 610.The low side portion 610 of the gate driver circuit includes a low side power supply circuit 611 to obtain a positive power supply voltage VDD for the low side portion 610. The positive power supply voltage VDD for the low side portion 610 is referred to the first reference potential VSS.A low side desaturation detection circuit 612 is connected to the output node of the half bridge 920, detects desaturation of the low side switch 921, and outputs a low side desaturation signal indicating whether a desaturation condition is present. A low-side receiver circuit 613 receives a low-side differential data signal from the pnp BJTs 382 and outputs a low-side asymmetric data signal. Logic circuitry 614 in low side portion 610 receives the low side data signal, the low side desaturation signal, and a low side gate control signal from an external source such as a processor 990. The logic circuit 614 in the low side portion 610 outputs a first gate drive signal GOut 1 in response to the low side gate control signal, provided that none of the low side desaturation signal and the low side data signal indicates a desaturation condition. A low side driver 615 drives the first gate driver signal GOut1.The logic circuit 614 in the low side portion 610 further outputs a differential gate control signal. The two n-channel MOSFETs 381 transmit the differential gate control signal from the low-side part 610 to the high-side part 620. An inductive load 930 is electrically connected between the switching nodes of two half bridges 920.The n-channel MOSFETs 381 and pnp BJTs 382 having any of the configurations of the present embodiments improve signal transmission between the low-side portion 610 and the high-side portion 620, reduce the leakage current between the high-side portion 620 and the low-side portion 610, can be made more compact, and can reduce switching time, and therefore improve performance of the half bridge 920 by allowing higher switching frequencies.

Claims

A semiconductor-on-insulator device, comprising: a base substrate (110) having a background doping of a first conductivity type, wherein a field control region (250) of a complementary second conductivity type extends from a front surface (111) into the base substrate (110), and wherein a net dopant concentration in the field control region (250) decreases along a lateral direction parallel to the front surface (111) at a lower rate than along a vertical direction orthogonal to the front surface (111); an insulator layer (120) formed on the front surface (111); and a semiconductor layer (130) formed on the insulator layer (120), wherein a semiconductor element (300) formed in the semiconductor layer (130) comprises a first contact region (310) formed over the field control region (250) and a second contact region (320) in the lateral direction with decreasing net dopant concentration in the field control region (250).The semiconductor-on-insulator device of claim 1, wherein the field control region (250) comprises a doping transition region (255), wherein in the doping transition region (255), the net dopant concentration decreases at an average first rate in the lateral direction and at an average second rate in the vertical direction, and wherein the average second rate is at least twice the average first rate.The semiconductor-on-insulator device of claim 2, wherein the field control region (250) further comprises a constant doping region (254) having a constant net dopant concentration in direct lateral contact with the doping transition region (255).The semiconductor-on-insulator device of claim 3, wherein the second contact region (320) is formed at a lateral distance from the constant doping region (254).The semiconductor-on-insulator device of claim 4, wherein the doping transition region (255) comprises portions on opposite sides of the constant doping region (254), and the net dopant concentration in the portions of the doping transition region (255) decreases in a direction away from the constant doping region (254).The semiconductor-on-insulator device of any of claims 2 to 4, wherein the doping transition region (255) laterally surrounds a first voltage region (170), and the net dopant concentration in the doping transition region (255) decreases in a radially outward direction.The semiconductor-on-insulator device of any of claims 2 to 4, wherein the doping transition region (255) laterally surrounds a second voltage region (190), and the net dopant concentration in the doping transition region (255) decreases in a radially inward direction.The semiconductor-on-insulator device according to any of claims 6 and 7, wherein the doping transition region (255) comprises at least a first sector (251) and a second sector (252), and wherein the first sector (251) and the second sector (252) have different net dopant gradients in the radial direction.The semiconductor-on-insulator device of any preceding claim, further comprising: a channel stopper region (260) of the first conductivity type formed in the base substrate (110) in direct lateral contact with the field control region (250).The semiconductor-on-insulator device according to any one of the preceding claims, further comprising: a voltage reduction structure (350) formed in the semiconductor layer (130) between the first contact region (310) and the second contact region (320).The semiconductor-on-insulator device according to the preceding claim, wherein the voltage reduction structure (350) comprises first compensation regions (351) of the first conductivity type and second compensation regions (352) of the second conductivity type, wherein the first and second compensation regions (351, 352) alternate along a tangential direction orthogonal to shortest connection lines between the first contact region (310) and the second contact region (320).The semiconductor-on-insulator device according to any one of the preceding claims, wherein the first contact region (310) and the second contact region (320) have a different conductivity type.The semiconductor-on-insulator device according to any one of claims 1 to 11, wherein the first contact region (310) and the second contact region (320) have a same conductivity type.The semiconductor-on-insulator device according to claim 13, wherein a voltage reduction structure (350) is formed in the semiconductor layer (130) between the first contact region (310) and the second contact region (320), and wherein gate regions (313) of a conductivity type complementary to the conductivity type of the first and second contact regions are formed in the semiconductor layer (130) between the voltage reduction structure (350) and a first one of the first and second contact regions (310, 320), wherein the gate regions (313) are laterally separated along a tangential direction orthogonal to shortest connection lines between the first and second contact regions (310, 320).The semiconductor-on-insulator device of claim 12, wherein a voltage reduction structure (350) is formed in the semiconductor layer (130) between the first contact region (310) and the second contact region (320), and wherein a base / body region (314, 315, 316) of a conductivity type complementary to the conductivity type of the first and second contact regions (310, 320) is formed in the semiconductor layer (130) between the voltage reduction structure (350) and a first of the first and second contact regions (310, 320).The semiconductor-on-insulator device of claim 14, further comprising: a third contact structure (373), wherein the third contact structure (373) and the base / body region (314, 315) form an ohmic contact.The semiconductor-on-insulator device of claim 14, further comprising: a gate electrode (365) and a gate dielectric (361) separating the base / body region (316) and the gate electrode (365) from each other.The semiconductor-on-insulator device of any preceding claim, further comprising: a passivation layer (140) formed on the semiconductor layer (130), wherein the passivation layer (140) comprises silicon and silicon nitride.The semiconductor-on-insulator device of any preceding claim, further comprising: a low-side circuit (700) configured to generate a low-side data signal and output a first gate drive signal between a first gate output and a first reference potential (VSS); and a high-side circuit (800) configured to generate a high-side data signal and output a second gate drive signal between a second gate output and a second reference potential (VS), wherein the semiconductor element (300) is configured to transmit a voltage and / or to conduct the low-side data signal from the low-side circuit (700) to the high-side circuit (800) and / or to conduct the high-side data signal from the high-side circuit (800) to the low-side circuit (700).

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