Operational amplifier with main and secondary signal paths

Abstract

The proposed operational amplifier comprises at least one first amplifier circuit in a main signal path between input terminals and one or two output terminals of the operational amplifier. A secondary signal path branches off from the main signal path between the input terminals and the first amplifier circuit, containing a second amplifier circuit. This secondary path is then rejoined to the main signal path in the first amplifier circuit. The first and second amplifier circuits are dimensioned such that the signal bandwidth of the main signal path is at least 10 times greater than the signal bandwidth of the secondary signal path, and the second amplifier circuit has a lower input offset than the first amplifier circuit.This makes it possible to implement an operational amplifier with a small input-related offset error voltage while simultaneously having a fast and broadband main signal path and low power consumption.

Description

Technical application area

[0001] The present invention relates to an operational amplifier comprising at least one amplifier circuit in a main signal path from input terminals to one or two output terminals of the operational amplifier and which can be used in fast control loops.

[0002] The requirements for operational amplifiers (op-amps) in fast control loops for energy-efficient applications include a fast (i.e., broadband) signal path, low power consumption, and a small input-related offset error voltage. A small input-related offset error voltage, resulting from the mismatch between the parameters of the input transistors (e.g., MOS field-effect transistors (MOSFETs) or bipolar transistors (BJTs)), necessitates input transistors with very large channel, gate, or emitter areas. However, large input transistors combined with a fast signal path require a high current at the operating point, which means the low power dissipation requirement can no longer be met. State of the art

[0003] To solve this problem, a technique called "offset sampling" is used. In an initial calibration phase, the output of the operational amplifier is short-circuited to one of its inputs. Due to the high voltage gain of the operational amplifier, an input offset voltage is established at the input. This voltage is stored on a capacitor and, during subsequent operation, connected in series with the input signal. This compensates for the input-related offset. However, due to the capacitor's leakage current, the offset sampling must be repeated periodically.

[0004] Offset sampling therefore requires clocked operation of the operational amplifier, as used, for example, in switched-capacitor (SC) circuits. This necessitates a complex clock control with non-overlapping clock signals. However, many applications require continuous-time operation of the control circuits and thus also of the operational amplifiers. Offset sampling cannot be used for such applications.

[0005] In the publication by KAMPUS, V.; TROJER, M.; TESCHNER, R.: Unleashing the full power of feed-forward opamps: a 200MHz, fully differential, conditionally stable, 36dB gain PGA, using a four-stage multi-path 2.5V amplifier with double feed-forward compensation. In: 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC), 2018, pp. 1–5, a differential, feedforward-compensated, and programmable 200 MHz amplifier is described that employs a four-stage multi-path amplifier with double feedforward compensation.

[0006] DE 38 29 135 A1 describes an operational amplifier according to the preamble of claim 1.

[0007] The object of the present invention is to provide an operational amplifier circuit with which a fast operational amplifier for use in fast control loops can be realized, which has a low input-related offset error voltage and low power consumption. Description of the invention

[0008] The problem is solved with the operational amplifier according to claim 1. Advantageous embodiments of the operational amplifier are the subject of the dependent claims or can be found in the following description and the exemplary embodiments.

[0009] The proposed operational amplifier comprises at least one first amplifier circuit in a main signal path from input terminals to one or two output terminals of the operational amplifier. A secondary signal path branches off from the main signal path at or between the input terminals and the first amplifier circuit, containing a second amplifier circuit. The secondary signal path is then rejoined to the main signal path in the first amplifier circuit. The first and second amplifier circuits are dimensioned such that the signal bandwidth of the main signal path is at least 10 times greater than the signal bandwidth of the secondary signal path, and the second amplifier circuit has a lower input offset than the first amplifier circuit.The terms main signal path and secondary signal path are used solely to distinguish between the two signal paths, without defining any further properties of these signal paths.

[0010] With the proposed operational amplifier, a low input offset can be achieved by appropriately dimensioning the second amplifier circuit, since the second amplifier circuit does not need to be designed for a high signal bandwidth. The transistors in the second amplifier circuit can therefore be dimensioned very large. Because the secondary signal path operates very slowly relative to the main signal path, it can be designed with very low current consumption (a few µA) despite the large transistors. The low input offset of the second amplifier circuit is inherited by the overall amplifier, so that the operational amplifier also exhibits a small input-related offset error voltage.In contrast, the transistors of the first amplifier circuit in the main signal path can be chosen to be geometrically small in order to ensure the high signal bandwidth and thus speed compared to the secondary signal path, while also maintaining low power consumption.

[0011] Preferably, the first and second amplifier circuits are dimensioned such that the second amplifier circuit has an input offset that is at least five times lower than that of the first amplifier circuit. This is achieved in a known manner by appropriately selecting the size of the channel, gate, or emitter area of ​​the transistors in the second amplifier circuit.

[0012] The proposed operational amplifier can thus be implemented as a fast amplifier with low power consumption and a simultaneously small input-related offset voltage, which does not require clock input for offset sampling but operates purely in continuous time. This makes this operational amplifier suitable for fast control loops with only small static control deviations.

[0013] In a preferred embodiment, the operational amplifier has a further amplifier circuit in the main signal path between the first amplifier circuit and the output terminal(s), referred to in the present patent application as the third amplifier circuit. The second amplifier circuit is preferably designed as a two-stage amplifier.

[0014] The proposed operational amplifier is characterized by the fact that the first amplifier circuit is formed by FDSOI MOSFETs (as amplifying transistors). In this configuration, the shunt path is reconnected to the main signal path at the drain terminals of the FDSOI MOSFETs. This results in a very clear and simple circuit design. Brief description of the drawings

[0015] The proposed operational amplifier is briefly explained below using exemplary embodiments in conjunction with the drawings. These show: Fig. 1 a block diagram of the proposed operational amplifier according to one design variant; Fig. 2 a circuit diagram for an embodiment of an operational amplifier that is not part of the invention; Fig. 3 a circuit diagram for a further embodiment of an operational amplifier, which is not part of the invention; Fig. 4 a circuit diagram for a further embodiment of an operational amplifier, which is not part of the invention; Fig. 5 an exemplary circuit diagram for one embodiment of the proposed operational amplifier; and Fig. 6 an exemplary circuit diagram for the second amplifier circuit. Ways to implement the invention

[0016] The present invention enables the realization of a fast operational amplifier with low power consumption and simultaneously low input-related offset voltage. The operational amplifier is characterized by a second signal path (auxiliary signal path) alongside the main signal path. This secondary signal path branches off from the main signal path at or between the input terminals of the operational amplifier and the first amplifier circuit, and is rejoined to the main signal path in the first amplifier circuit. A second amplifier circuit in the secondary signal path, referred to here as the auxiliary signal path, is implemented with a small input offset and a significantly lower signal bandwidth than in the main signal path. The main signal path, on the other hand, can be designed for high speed (large signal bandwidth).A small input offset is preferably understood to be an input offset that is at least 5 times smaller than the input offset at the first amplifier circuit, for example 1 mV with an input offset of 5-10 mV at the input of the main signal path.

[0017] Fig. Figure 1 shows a block diagram of such an operational amplifier in one possible configuration, where the operational amplifier has two cascaded amplifier stages with voltage gains. A voltage U1 applied to the input terminals is amplified to voltage U2 via the first amplifier circuit 1.1 - 1.4 and finally to the output voltage U3 by the second amplifier stage 2 (also referred to here as the third amplifier circuit). The voltage gains in this main signal path (via 1.1, 1.3, 1.4 and optionally 2) are A 11 = G 12*R and A2, where A represents the voltage gain, G the transmission conductance (transconductance), and R the resistance of the load circuit. The amplifier circuits in this main signal path are broadband and therefore designed as fast amplifiers. G 11 Due to its design for high speed and low power consumption, the operational amplifier has small transistors and therefore a relatively large input-related offset error voltage. A secondary signal path (via 3, 1.2, 1.3, 1.4 and optionally 2) branches off between the input terminals of the operational amplifier and the first amplifier circuit 1.1 - 1.4, leading to a second amplifier circuit 3, which is designed for a relatively small input-related offset error voltage. This secondary signal path is rejoined with the main signal path in the first amplifier circuit 1.1 - 1.4, as shown at node 1.3 in the block diagram. Fig. Figure 1 shows that the second amplifier circuit 3 is designed for a narrow bandwidth, meaning it uses transistors with a large area. The auxiliary signal path is therefore a narrowband, slow path compared to the main signal path, resulting in a voltage gain of A. 12 = A3*G 12 *R is present.

[0018] This implementation of the operational amplifier allows it to be fast and broadband in the main signal path, while still oscillating to the small offset error voltage of the slower secondary signal path. Reference symbols 1.1 and 1.2 represent transconductances and transmission conductances, respectively; reference symbol 1.3 represents a node where Kirchhoff's current law applies; and reference symbol 1.4 represents a load circuit. Voltages are denoted by U, and currents by I.

[0019] The proposed operational amplifier, as it is described in Fig. The block diagram shown in section 1 as an example can be implemented in different variations. The following examples are described below. Fig. Figures 2 to 4 initially show circuit diagrams for configurations of operational amplifiers that are not part of the invention. Fig. Figure 2 shows an exemplary circuit diagram of a configuration with a bulk n-channel MOSFET transconductance (TK), p-channel MOSFET load circuit (R), and CMOS inverter. The transconductance (TK) G 11 The first amplifier circuit is thereby replaced by the difference pair N 11+ / - and the footpoint current source N 110 realized. The transconductance G 12 is determined by the difference pair N 12+ / - and the footpoint current source N 120 The load circuit R is implemented by the field-effect transistors P. 14+ / - The second amplifier stage, 2 or A2, is implemented using a differential-to-unipolar function. The second amplifier stage is implemented by the CMOS inverter P2+N2.

[0020] Fig. Figure 3 shows an exemplary circuit diagram of a configuration with an npn-BJT transconductance, a p-channel MOSFET load circuit, and a CMOS inverter. In contrast to the configuration of the Fig. Therefore, bipolar transistors, not MOSFETs, are used in the first amplifier circuit. The transconductance G 11 The first amplifier circuit is again replaced by the difference pair N 11+ / - and the footpoint current source N 110 realized. The transconductance G 12 is determined by the difference pair Q 12+ / - and the footpoint current source N 120 The load circuit R is implemented by the field-effect transistors P. 14+ / - The second amplifier stage, 2 or A2, is implemented using a differential-to-unipolar function. The second amplifier stage is implemented by the CMOS inverter P2+N2.

[0021] Fig. Figure 4 shows an exemplary circuit diagram of a configuration with a bulk CMOS transconductance and load circuit and a CMOS inverter. The transconductance G 11 and the load (partial) circuit R 11 In this configuration, the difference pairs N / P are used. 11+ / - , the transconductance G 12 and the load (partial) circuit R 12 through the difference pairs N / P 12+ / - realized. N 10 and P 10 These represent the common feedpoint current sources. The differential-to-unipolar function is implicitly present in this circuit. The second amplifier stage 2 or A2 is again formed by the CMOS inverter P2+N2.

[0022] Fig. Figure 5 shows an exemplary circuit diagram of an embodiment according to the invention with an FDSOI-CMOS transconductance and load circuit and a CMOS inverter. In this particularly advantageous embodiment, the transconductance G 11 , the transconductance G12 and the load switching R through the differential pairs N / P 1+ / - realized, whereby G 11 via the control at the gate and G 12 This is implemented via the control at the backgate. Here too, common N / P feedpoint current sources are used. 10 The differential-to-unipolar function is again implicitly present. The second amplifier stage 2 or A2 is also formed by the CMOS inverter P2+N2. In this configuration, the parallel, low-offset slow signal path (auxiliary signal path) at the backgates of the FDSOI input MOSFETs is thus recombined with the main signal path of the first amplifier circuit. In all the above configurations, U represents eD the input voltage and U 3+ represents the output voltage.

[0023] Fig.Figure 6 shows an exemplary circuit diagram for implementing the second amplifier circuit 3 or A3 in the shunt path. This is a two-stage operational amplifier. The first stage consists of the feedpoint current source P. 10 , the difference pair P 1+ / - , the load MOSFETs N 1+ / - and the common-mode control via R ∞ together. The second stage is represented by the pseudo-difference pair N. 2+ / - , the load MOSFETs / current sources P 20+ / - and the load matching is achieved via R2. Compensation or bandwidth limiting is done via R C C C .

Claims

[1] Operational amplifier comprising at least one first amplifier circuit (1.1, 1.2, 1.3, 1.4) in a main signal path from input terminals to one or two output terminals of the operational amplifier, wherein a secondary signal path branches off from the main signal path at or between the input terminals and the first amplifier circuit (1.1, 1.2, 1.3, 1.4), in which a second amplifier circuit (3) is formed and which is merged back with the main signal path in the first amplifier circuit (1.1, 1.2, 1.3, 1.4), wherein the first and second amplifier circuits (1.1, 1.2, 1.3, 1.4, 3) are dimensioned such that the signal bandwidth of the main signal path is at least 10 times greater than the signal bandwidth of the secondary signal path and the second amplifier circuit (3) has a lower input offset than the first amplifier circuit (1.1, 1.2, 1.3, 1.4), characterized by , that the first amplifier circuit (1.1, 1.2, 1.3, 1.4) is formed by FDSOI MOSFETs, with the secondary signal path being reconnected to the main signal path via backgate terminals of the FDSOI MOSFETs. [2] Operational amplifier according to claim 1, characterized by , that the first and second amplifier circuits (1.1, 1.2, 1.3, 1.4, 3) are dimensioned such that the second amplifier circuit (3) has an input offset that is at least 5 times lower than that of the first amplifier circuit (1.1, 1.2, 1.3, 1.4). [3] Operational amplifier according to claim 1 or 2, characterized by , that a third amplifier circuit (2) is arranged in the main signal path between the first amplifier circuit (1.1, 1.2, 1.3, 1.4) and the output terminal(s). [4] Operational amplifier according to any one of claims 1 to 3, characterized by , that the second amplifier circuit (3) is designed as a two-stage amplifier.

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