METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Abstract

A silicon film in an amorphous state is formed on a semiconductor substrate located in a first to a fourth region. The silicon film located in the first region and the fourth region is removed, leaving the silicon film located in the second region and the third region. A polycrystalline silicon film is formed by crystallizing the silicon film through a heat treatment.

Description

CROSS REFERENCE TO RELATED APPLICATIONSThe disclosure of Japanese Patent Application No. 2023-206254 filed on Dec. 6, 2023, including the specification, the drawings and the abstract, is incorporated herein by reference in its entirety.BACKGROUNDThe present invention relates to a method of manufacturing a semiconductor device, and more particularly relates to a method of manufacturing a semiconductor device including a ferroelectric memory cell.In recent years, ferroelectric memory cells using a ferroelectric film have been developed as semiconductor memory elements operating at low voltages. Ferroelectric memory cells are nonvolatile memory cells capable of changing the write state and the erase state by controlling the polarization direction of the ferroelectric.Techniques listed below are disclosed.[Patent Document 1] Japanese Patent Application Laid-Open No. 2018-96243Patent Document 1 discloses a semiconductor device in which a ferroelectric memory cell and a MISFET (Metal Insulator Field Effect Transistor) constituting a logic circuit are mounted together.In a manufacturing method disclosed in Patent Document 1, first, a gate insulating film is formed on a semiconductor substrate in each of a memory cell region and a peripheral region located at a periphery of the memory cell region. Then, a ferroelectric film is formed on each of the gate insulating films. Next, a titanium nitride film is formed on the ferroelectric film. Next, the titanium nitride film and the ferroelectric film located in the peripheral region are selectively removed. Next, a polycrystalline silicon film is formed on the titanium nitride film in the memory cell region, and a polycrystalline silicon film is formed on the gate insulating film in the peripheral region. These polycrystalline silicon films are formed for use as gate electrodes of the ferroelectric memory cell and the MISFET.SUMMARYConventionally, in the case of forming a silicon film on a titanium nitride film in a ferroelectric memory cell, a polycrystalline silicon film is formed at a film forming temperature of about 600 degrees Celsius by a film forming process using the CVD method (Chemical Vapor Deposition]). However, the studies of the inventors of this application have shown that in this case, abnormal growth of the polycrystalline silicon film is likely to occur on the titanium nitride film. Therefore, the present inventors have considered the formation of a silicon film in an amorphous state at a temperature lower than the film-forming temperature of the polycrystalline silicon film instead of the polycrystalline silicon film.Meanwhile, in the peripheral region, a resistance element and the like are also formed as semiconductor elements other than the MISFET. The silicon film constituting the resistance element is formed by the same manufacturing step as the silicon film of the ferroelectric memory cell and the silicon film of the MISFET. Here, it has been found that when a resistance element is formed of a silicon film in an amorphous state in consideration of the abnormal growth of the polycrystalline silicon film, the characteristics of the resistance element vary. Specifically, it was found that the sheet resistance of the resistance element is lower than the sheet resistance of the case. forming the resistance element from a polycrystalline silicon film in advance. Therefore, there is a need for a technique capable of improving the reliability of a semiconductor device by suppressing characteristic variation of a resistance element and suppressing abnormal growth in a ferroelectric memory cell.For example, it is conceivable to form a silicon film in an amorphous state in the memory cell region and the peripheral region and adjust the sheet resistance by selectively implanting ions. In particular, the decrease in sheet resistance of the resistance element can be suppressed by performing a first ion implantation into the silicon film located in the memory cell region and performing a second ion implantation into the silicon film located in the peripheral region at a dose lower than that of the first ion implantation.However, the number of manufacturing steps and masks required for performing ion implantation increases, leading to the increase in manufacturing cost. In addition, when two kinds of resistance elements, p-type and n-type, are to be formed, the number of manufacturing steps and masks further increases.When the selective ion implantation is not performed, it is also conceivable to separately form an amorphous state silicon film for the ferroelectric memory cell and a polycrystalline silicon film for the resistance element. In this case, it is necessary to selectively leave the silicon film in the amorphous state only in the memory cell region and selectively leave the polycrystalline silicon film only in the peripheral region. Accordingly, since the formation and patterning of the silicon film are repeated, the number of manufacturing steps and masks increases, resulting in the increase in manufacturing cost.Therefore, a technique capable of improving the reliability of semiconductor devices while suppressing the increases in manufacturing cost is required. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.An outline of a typical embodiment disclosed in this application will be described simply as follows.A method for manufacturing a semiconductor device according to an embodiment includes a step of forming a first silicon film in an amorphous state on a semiconductor substrate located in a first region and a second region, a step of removing the first silicon film located in the first region, a step of forming a first polycrystalline silicon film by crystallizing the first silicon film by a first heat treatment, a step of forming a ferroelectric film on the semiconductor substrate located in the first region and on the first polycrystalline silicon film located in the second region, a step of forming a metal film on the ferroelectric film, a step of removing the metal film and the ferroelectric film located in the second region, and a step of forming a second silicon film on the metal film located in the first region and on the first polycrystalline silicon film located in the second region.According to an embodiment, it is possible to improve the reliability of the semiconductor device while suppressing the increase in the manufacturing cost.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 1. FIG. 4 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 2. FIG. 5 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 3. FIG. 6 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 4. FIG. 7 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 5. FIG. 8 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 6. FIG. 9 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 7. FIG. 10 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 8. FIG. 11 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 9. FIG. 12 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 10. FIG. 13 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 11. FIG. 14 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 12. FIG. 15 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 13. FIG. 16 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 14. FIG. 17 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 15. FIG. 18 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 16. FIG. 19 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 17. FIG. 20 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 18. FIG. 21 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 19. FIG. 22 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 20. FIG. 23 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 21. FIG. 24 is a cross-sectional view illustrating the manufacturing process of the semiconductor device of FIG. 22. Figure 25 illustrates data obtained from experiments of the inventors of this application.DETAILED DESCRIPTIONHereinafter, an embodiment will be described in detail with reference to drawings. In all the drawings for describing the embodiment, the elements having the same function are denoted by the same reference numerals, and the repetitive descriptions thereof are omitted. Moreover, in the following embodiment, the description of the same or similar part is not repeated in principle unless particularly required.(First Embodiment)< For Manufacturing Semiconductor Device>A semiconductor device includes a region 1A and regions 2A, 3A, and 4A located at a periphery of the region 1A. First, semiconductor elements formed in each region will be described with reference to FIGS. 23 and 24.As illustrated in FIG. 23, a ferroelectric memory cell MC is formed as a semiconductor element in the region 1A. The ferroelectric memory cell MC is an electrically rewritable nonvolatile memory cell, and includes a memory transistor MQ and a selection transistor 1Q. The memory transistor MQ has a ferroelectric film FE and can change the write state and the erase state by controlling the polarization direction of the ferroelectric film FE. The selection transistor 1Q controls supply of a write voltage, an erase voltage and a read voltage to a drain region of the memory transistor MQ during selection and non-selection of the ferroelectric memory cell MC.In the region 2A, a plurality of MISFETs are formed as semiconductor elements. The plurality of MISFETs include a plurality of high withstand voltage n-type and p-type MISFETs and a plurality of low withstand voltage n-type and p-type MISFETs. The plurality of high withstand voltage MISFETs form part of an I / O circuit, for example. The low withstand voltage MISFET is driven at a voltage lower than that of the high withstand voltage MISFET, and includes a gate insulating film thinner than that of the high withstand voltage MISFET. The plurality of low withstand voltage MISFETs constitute, for example, a logic circuit including a CPU and an SRAM. In FIG. 23, an n-type MISFET having high withstand voltage is illustrated as an example of the MISFET formed in the region 2A.As illustrated in FIG. 24, a plurality of resistance elements RS 1 are formed as semiconductor elements in the region 3A. A polycrystalline silicon film PL 1 and a polycrystalline silicon film PL 2 formed in the region 3A function as the resistor element RS 1, and n-type or p-type impurities are introduced into the polycrystalline silicon film PL 1 and the polycrystalline silicon film PL 2. In FIG. 24, the resistor element RS 1 including the n-type polycrystalline silicon film PL 1 and the n-type polycrystalline silicon film PL 2 is illustrated as an example of the resistor element formed in the region 3A.In the region 4A, a plurality of resistance elements RS 2 are formed as semiconductor elements. A polycrystalline silicon film PL 3 formed in the region 4A functions as the resistor element RS 2, and n-type or p-type impurities are introduced into the polycrystalline silicon film PL 3. In FIG. 24, the resistance element RS 2 including the n-type polycrystalline silicon film PL 3 is illustrated as an example of the resistance element formed in the region 4A.Each manufacturing step included in the method for manufacturing the semiconductor device according to the first embodiment will be described below with reference to FIGS. 1 to 24.As illustrated in FIGS. 1 and 2, first, a semiconductor substrate SUB made of single crystal silicon into which, for example, p-type impurities are introduced is prepared. Next, an n-type well region DNW is formed in the semiconductor substrate SUB located in the regions 1A to 4A by photolithography and ion implantation.Next, a plurality of trenches are formed in the semiconductor substrate SUB located in the regions 1A to 4A by photolithography and anisotropic etching. Next, an insulating film IF 1 is formed to fill the inner sides of the plurality of trenches by a film forming process using, for example, the CVD method. Next, the insulating film IF 1 located outside the plurality of trenches is removed by a polishing process using the CMP (Chemical Mechanical Polishing) method. The insulating film IF 1 functions as an element isolation portion that isolates the semiconductor elements formed in each region. A depth of the trench is, for example, 300 nm or more and 400 nm or less.Next, by photolithography and ion implantation, a p-type well region PW 1 is formed in the semiconductor substrate SUB located in the region 1A, a p-type well region PW 2 is formed in the semiconductor substrate SUB located in the region 2A, and a p-type well region PW 3 is formed in the semiconductor substrate SUB located in the region 3A and the region 4A.Further, although not illustrated, by photolithography and ion implantation, n-type impurities such as arsenic or phosphorus are introduced into the semiconductor substrate SUB in the region 2A where the p-type MISFET is formed, thereby forming an n-type well region.As illustrated in FIGS. 3 and 4, a gate insulating film GI 3 is formed on the semiconductor substrate SUB located in the regions 1A to 4A by thermal oxidation, for example. The gate insulating film GI 3 is, for example, a silicon oxide film and has a thickness of, for example, 8 nm or more and 10 nm or less.Next, an amorphous state silicon film AM 1 is formed on the semiconductor substrate SUB located in the regions 1A to 4A via the gate insulating film GI 3 or the insulating film TF 1. The silicon film AM 1 is formed by a film forming process using, for example, the CVD method, and is formed within a temperature range of 400 degrees Celsius or more and 550 degrees Celsius or less. A thickness of the silicon film AM 1 is, for example, 15 nm or more and 30 nm or less.Note that when the thickness of the silicon film AM 1 is relatively small, such as 30 nm or less, the silicon film AM 1 is formed in an amorphous state without being crystallized even when the temperature of the film forming process is 600 degrees Celsius or more, for example.As illustrated in FIGS. 5 and 6, the silicon film AM 1 located in the region 1A and the region 4A is removed, so that the silicon film AM 1 located in the region 2A and the region 3A remains.First, a resist pattern RP1 is formed on the silicon film AM1. The resist pattern RP 1 has a pattern that selectively covers the silicon film AM 1 located in the region 2A and the region 3A. Next, anisotropic etching is performed using the resist pattern RP1 as a mask to remove the silicon film AM1 exposed from the resist pattern RP1. Next, isotropic etching is performed using the resist pattern RP 1 as a mask to remove the gate insulating film GI 3 exposed from the resist pattern RP 1. Thereafter, the resist pattern RP1 is removed by an ashing process.First, as illustrated in FIGS. 7 and 8, a gate insulating film GI 2 is formed on the semiconductor substrate SUB located in the region 1A, on the silicon film AM 1 located in the region 2A, and on the silicon film AM 1 located in the region 3A, for example, by thermal oxidation. The gate insulating film GI 2 is, for example, a silicon oxide film and has a thickness of, for example, 5 nm or more and 7 nm or less. Next, a resist pattern RP 2 is formed on a part of the gate insulating film GI 2 located in the region 1A. Next, isotropic etching is performed using the resist pattern RP 2 as a mask to remove the gate insulating film GI 2 exposed from the resist pattern RP 2. Thereafter, the resist pattern RP2 is removed by an ashing process.The portion of the region 1A where the gate insulating film GI 2 remains is used for the selection transistor 1Q. The portion of the region 1A where the gate insulating film GI 2 is removed and the semiconductor substrate SUB is exposed is used for the memory transistor MQ. In the region 2A and the region 3A, the silicon film AM 1 is exposed, but the thickness of the silicon film AM 1 is reduced due to the presence of the gate insulating film GI 2.As illustrated in FIGS. 9 and 10, the silicon film AM 1 is crystallized by a heat treatment to form the polycrystalline silicon film PL 1. This heat treatment is performed in a nitrogen atmosphere within a temperature range of 800 degrees Celsius or more and 1000 degrees Celsius or less and for a time range of 10 seconds or more and 100 seconds or less. In this state, a thickness of the polycrystalline silicon film PL 1 is preferably 20 nm or less.First, as illustrated in FIGS. 11 and 12, a gate insulating film GI 1 is formed on the semiconductor substrate SUB located in the region 1A, on the polycrystalline silicon film PL 1 located in the region 2A, and on the polycrystalline silicon film PL 1 located in the region 3A by thermal oxidation using the ISSG (In Situ Steam Generation) oxidation method. The gate insulating film GI 1 is, for example, a silicon oxide film and has a thickness of, for example, 1 nm or more and 5 nm or less.Next, by a film forming process using, for example, the ALD (atomic layer deposition) / atomic layer deposition method, the ferroelectric film FE is formed on the semiconductor substrate SUB located in the region 1A via the gate insulating film GI 1 or the gate insulating film GI 2, the ferroelectric film FE is formed on the polycrystalline silicon film PL 1 located in the region 2A and the region 3A via the gate insulating film GI 1, and the ferroelectric film FE is formed on the semiconductor substrate SUB located in the region 4A via the insulating film IF 1. In this state, the ferroelectric film FE is in an amorphous state.The ferroelectric film FE is an HfO 2- film or an HfO 2- film to which at least one of zirconium (Zr), silicon (Si), nitrogen (N), carbon (C) and aluminum (Al) is added. A thickness of the ferroelectric film FE is, for example, 4 nm or more and 20 nm or less.Next, a metal film MF is formed on the ferroelectric film FE located in the regions 1A to 4A by a film forming process using, for example, the CVD method or the sputtering method. The metal film MF is, for example, a titanium nitride film. A thickness of the metal film MF is, for example, 10 nm or more and 20 nm or less.Next, the ferroelectric film FE is crystallized by a heat treatment to form the orthorhombic ferroelectric film FE. This heat treatment is performed within a temperature range of 400 degrees Celsius or more and 600 degrees Celsius or less. Here, the metal film MF applies stress to the ferroelectric film FE during the heat treatment and controls the crystal orientation of the ferroelectric film FE. In other words, the metal film MF has a function of orienting the crystal phase of the ferroelectric film FE into an orthorhombic crystal.As illustrated in FIGS. 13 and 14, the metal film MF and the ferroelectric film FE located in the regions 2A to 4A are removed, so that the metal film MF and the ferroelectric film FE located in the region 1A remain.First, a resist pattern RP3 is formed on the metal film MF. The resist pattern RP 3 has a pattern that selectively covers the metal film MF located in the region 1A. Next, anisotropic etching is performed using the resist pattern RP3 as a mask to remove the metal film MF and the ferroelectric film FE exposed from the resist pattern RP3. Thereafter, the resist pattern RP3 is removed by an ashing process.In the above anisotropic etching, overetch is performed so that the metal film MF and the ferroelectric film FE located in the regions 2A to 4A are surely removed. This overetch also removes the gate insulating film GI1 formed on the polycrystalline silicon film PL1 in the region 2A and the region 3A. Further, the thickness of the polycrystalline silicon film PL 1 is reduced due to the presence of the gate insulating film GI 1.The polycrystalline silicon film PL 1 functions as a protective film for protecting the gate insulating film GI 2 located in the region 2A from the above over-etching.Here, the reason why the thickness of the polycrystalline silicon film PL 1 in the state of FIGS. 9 and 10 is preferably 20 nm or less will be described. The metal film MF and the ferroelectric film FE are formed not only on the upper surface of the polycrystalline silicon film PL1 but also on the side surfaces of the polycrystalline silicon film PL1. Therefore, as the thickness of the polycrystalline silicon film PL1 becomes larger, the step difference becomes larger, and the height of the metal film MF and the ferroelectric film FE formed on the side surfaces of the polycrystalline silicon film PL1 becomes larger.Consequently, even after the removal of the metal film MF and the ferroelectric film FE formed on the upper surface of the polycrystalline silicon film PL1, it becomes difficult to completely remove the metal film MF and the ferroelectric film FE formed on the side surfaces of the polycrystalline silicon film PL1. Therefore, in order to reduce such a step difference and make it easier to completely remove the metal film MF and the ferroelectric film FE, the thickness of the polycrystalline silicon film PL 1 is preferably as small as possible, and is preferably 20 nm or less.In addition, in view of the purpose of having the polycrystalline silicon film PL 1 function as a protective film for the gate insulating film GI 2, it is not always necessary to form the polycrystalline silicon film PL 1 in the region 3A. Further, after the removal of the metal film MF and the ferroelectric film FE, the polycrystalline silicon film PL 1 located in the region 2A and the region 3A may be removed.In the first embodiment, the polycrystalline silicon film PL1 is intentionally formed in the region 3A, and the polycrystalline silicon film PL1 is left in the region 2A and the region 3A. The reason for this will be described in detail later.First, as illustrated in FIGS. 15 and 16, a silicon film is formed on the metal film MF located in the region 1A, the silicon film is formed on the polycrystalline silicon film PL 1 located in the region 2A, the silicon film is formed on the polycrystalline silicon film PL 1 located in the region 3A, and the silicon film is formed on the semiconductor substrate SUB located in the region 4A via the insulating film IF 1.The silicon film is formed by a film forming process using, for example, the CVD method, and is formed within a temperature range of 400 degrees Celsius or more and 550 degrees Celsius or less. A thickness of the silicon film is larger than the thickness of the polycrystalline silicon film PL 1, for example, 40 nm or more and 100 nm or less.In the film forming process, a silicon film is usually formed in an amorphous state. Therefore, in the region 1A and the region 4A, the silicon film is formed as an amorphous state silicon film AM2. On the other hand, in the region 2A and the region 3A, since the polycrystalline silicon film PL 1 functions as a seed film, the silicon film is formed as the polycrystalline silicon film PL 2.When the thickness of the polycrystalline silicon film PL 1 is too small, the polycrystalline silicon film PL 1 cannot function as a seed film. In order to make the polycrystalline silicon film PL 1 function as a seed film, it is preferable that the thickness of the polycrystalline silicon film PL 1 be 5 nm or more. In addition, in view of the purpose of making it easier to completely remove the metal film MF and the ferroelectric film FE formed on the side surfaces of the polycrystalline silicon film PL 1 as described above, it is preferable that the thickness of the polycrystalline silicon film PL 1 be 5 nm or more and 20 nm or less.Next, by photolithography and ion implantation, n-type impurities such as arsenic or phosphorus are introduced into the silicon film AM 2 located in the region 1A, the polycrystalline silicon film PL 2 and the polycrystalline silicon film PL 1 located in the region 2A, the polycrystalline silicon film PL 2 and the polycrystalline silicon film PL 1 located in the region 3A, and the silicon film AM 2 located in the region 4A.Further, although not illustrated, by photolithography and ion implantation, p-type impurities such as boron or boron difluoride are introduced into the polycrystalline silicon film to be a gate electrode of the p-type MISFET in the region 2A, the polycrystalline silicon film to be a p-type resistance element in the region 3A, and the silicon film in an amorphous state to be a p-type resistance element in the region 4A.Thereafter, an insulating film IF 2 is formed on the silicon film AM 2 and the polycrystalline silicon film PL 2 by a film forming process using, for example, the CVD method. The insulating film IF 2 is, for example, a silicon nitride film and has a thickness of, for example, 20 nm or more and 40 nm or less.In the manufacturing process illustrated in FIGS. 17 to 20, the silicon film AM 2, the metal film MF, and the ferroelectric film FE located in the region 1A are patterned, the polycrystalline silicon film PL 2 and the polycrystalline silicon film PL 1 located in the region 2A are patterned, the polycrystalline silicon film PL 2 and the polycrystalline silicon film PL 1 located in the region 3A are patterned, and the silicon film AM 2 located in the region 4A is patterned.As illustrated in FIGS. 17 and 18, first, a resist pattern RP 4 is formed on the insulating film IF 2. The resist pattern RP4 has a pattern selectively covering a part of the insulating film IF2 located in the regions 1A to 4A. Next, anisotropic etching is performed using the resist pattern RP4 as a mask to remove the insulating film IF2, the silicon film AM2, the polycrystalline silicon film PL2, and the polycrystalline silicon film PL1 exposed from the resist pattern RP4. Thereafter, the resist pattern RP4 is removed by an ashing process.First, as illustrated in FIGS. 19 and 20, anisotropic etching is performed using the insulating film IF 2 as a mask to remove the metal film MF and the ferroelectric film FE exposed from the insulating film IF 2 in the region 1A.Next, by photolithography and ion implantation, n-type impurities such as arsenic or phosphorus are introduced into the semiconductor substrate SUB located in the regions 1A to 4A, thereby forming n-type extension regions (impurity regions) EX.Further, although not illustrated, by photolithography and ion implantation, p-type impurities such as boron or boron difluoride are introduced into the semiconductor substrate SUB located in the region 2A, thereby forming p-type extension regions to be a source region or drain region of the p-type MISFET.First, as illustrated in FIGS. 21 and 22, in the regions 1A to 4A, a silicon oxide film and a silicon nitride film are sequentially formed on the semiconductor substrate SUB to cover the insulating film IF 2 by a film forming process using, for example, the CVD method. Next, the silicon oxide film and the silicon nitride film are processed by anisotropic etching, thereby forming sidewall spacers SW. Note that the insulating film IF 2 is removed by this anisotropic etching.In the region 1A, the sidewall spacer SW is formed on each of the side surfaces of the ferroelectric film FE, the metal film MF, and the silicon film AM2. In the region 2A and the region 3A, the sidewall spacer SW is formed on each of the side surfaces of the polycrystalline silicon film PL 2 and the polycrystalline silicon film PL 1. In the region 4A, the sidewall spacer SW is formed on the side surfaces of the silicon film AM 2.Next, by photolithography and ion implantation, n-type impurities such as arsenic or phosphorus are introduced into the semiconductor substrate SUB located in the regions 1A to 4A, thereby forming n-type diffusion regions (impurity regions) ND. The diffusion regions ND and the extension regions EX form a part of the source region or a part of the drain region of the memory transistor MQ and the selection transistor 1Q in the region 1A, and form a part of the source region or a part of the drain region of the MISFET 2Q in the region 2A.In forming the diffusion regions ND, the n-type impurities are also introduced into the silicon film AM 2 located in the region 1A, the polycrystalline silicon film PL 2 and the polycrystalline silicon film PL 1 located in the region 2A, the polycrystalline silicon film PL 2 and the polycrystalline silicon film PL 1 located in the region 3A, and the silicon film AM 2 located in the region 4A.Further, although not illustrated, by photolithography and ion implantation, p-type impurities such as boron or boron difluoride are introduced into the semiconductor substrate SUB located in the region 2A, thereby forming p-type diffusion regions to be the source region or the drain region of the p-type MISFET.In forming the p-type diffusion regions, the p-type impurities are also introduced into the polycrystalline silicon film to be the gate electrode of the p-type MISFET in the region 2A, the polycrystalline silicon film to be the p-type resistance element in the region 3A, and the amorphous state silicon film to be the p-type resistance element in the region 4A.As illustrated in FIGS. 23 and 24, by heat treatment, the diffusion regions ND and the extension regions EX are activated, and the silicon films AM 2 located in the region 1A and the region 4A are crystallized, thereby forming the polycrystalline silicon films PL 3. This heat treatment is performed by the RTA (Rapid Thermal Annealing / Rapid Thermal Annealing) method in a nitrogen atmosphere within a temperature range of 1000 degrees Celsius or more and 1100 degrees Celsius or less and for a time range of 0.1 seconds or more and 1.0 seconds or less.The polycrystalline silicon film PL 3 and the metal film MF located in the region 1A function as a gate electrode GE 1 of the memory transistor MQ and a gate electrode GE 2 of the selection transistor 1Q. The polycrystalline silicon film PL 2 and the polycrystalline silicon film PL 1 located in the region 2A function as a gate electrode GE 3 of the MISFET 2Q. The polycrystalline silicon film PL 2 and the polycrystalline silicon film PL 1 located in the region 3A function as the resistance element RS 1. The polycrystalline silicon film PL 3 located in the region 4A functions as the resistance element RS 2.As described above, the ferroelectric memory cell MC including the memory transistor MQ and the selection transistor 1Q is formed in the region 1A, the MISFET 2Q is formed in the region 2A, the resistance element RS1 is formed in the region 3A, and the resistance element RS2 is formed in the region 4A.<Haupt of First Embodiment>As illustrated in FIGS. 15 and 16, when a silicon film for the gate electrode of the ferroelectric memory cell MC is formed on the metal film MF in the region 1A, the temperature of the film forming process is set to 400 degrees Celsius or more and 550 degrees Celsius or less. Therefore, the amorphous state silicon film AM2 is formed on the metal film MF. As a result, it is possible to solve the problem that the abnormal growth of the polycrystalline silicon film is likely to occur when the polycrystalline silicon film is formed on the metal film MF.On the other hand, in the region 3A, the silicon film formed by the same manufacturing step as the silicon film of the ferroelectric memory cell MC is deposited on the resistance element RS1. Therefore, since it is not necessary to form the silicon film for the resistor element RS 1 separately, the manufacturing process can be simplified and the increase in manufacturing cost can be suppressed. When the amorphous state silicon film AM 2 is deposited on the resistor element RS 1, the silicon film AM 2 is crystallized by the heat treatment illustrated in FIGS. 23 and 24. In this case, however, it has been found that the sheet resistance of the resistance element RS 1 becomes lower than the sheet resistance in the case of forming the resistance element from a polycrystalline silicon film in advance.Therefore, in the first embodiment, as described with reference to FIGS. 9 and 10, the polycrystalline silicon film PL 1 is formed by crystallizing the silicon film AM 1 formed in the region 2A and the region 3A. Further, the polycrystalline silicon film PL1 is left in the region 2A and the region 3A without removing it. Since the polycrystalline silicon film PL1 functions as a seed film in the region 2A and the region 3A, when the silicon film is formed in the amorphous state AM2, the silicon film is formed in the region 2A and the region 3A as the polycrystalline silicon film PL2.FIG. 25 illustrates a comparison between the resistance element RS 1 (polycrystalline silicon film PL 1 / polycrystalline silicon film PL 2) of the first embodiment and a resistance element of a comparative example. The resistance element of the comparative example is made of a polycrystalline silicon film obtained by crystallizing a silicon film in an amorphous state.In the case of the resistance element of the comparative example, ions are implanted into the silicon film when the silicon film is in an amorphous state in the manufacturing step illustrated in FIGS. 15 and 16 and the manufacturing step illustrated in FIGS. 21 and 22. One possible reason for the low sheet resistance is that ion implantation into the silicon film in the amorphous state has increased the solid solubility. In addition, the thickness of the amorphous state silicon film is, for example, 40 nm or more and 100 nm or less. Another possible reason for the low sheet resistance is that the grain size in the polycrystalline silicon film crystallized from an amorphous state becomes large.In the first embodiment, since the polycrystalline silicon film PL 1 functions as a seed film, when a silicon film is formed on the seed film, a large number of crystal seeds are present in the silicon film. Therefore, it is considered that the grain size in the polycrystalline silicon film PL 3 of the first embodiment is smaller than that in the polycrystalline silicon film of the comparative example.Note that a polycrystalline silicon film formed at a film forming temperature of about 600 degrees Celsius has conventionally been used as a resistance element, but the sheet resistance of the resistance element RS 1 of the first embodiment is almost the same as that of the conventional resistance element. In this way, in the first embodiment, the decrease in sheet resistance of the resistance element RS 1 can be suppressed, and the variation in characteristics of the resistance element RS 1 can be suppressed, so that the reliability of the semiconductor device can be improved.Further, in the first embodiment, the resistance element RS 2 is formed in the region 4A. Since the polycrystalline silicon film PL1 in the region 4A is removed, the resistance element RS2 is made of the polycrystalline silicon film PL3 obtained by crystallizing the amorphous state silicon film AM2. In other words, the resistance element RS 2 corresponds to the resistance element of the comparative example and has a sheet resistance lower than that of the resistance element RS 1.Depending on the product specifications, a plurality of resistor elements having different sheet resistances may be required. As described in the first embodiment, by simply leaving the polycrystalline silicon film PL1 in the region 3A and removing the polycrystalline silicon film PL1 in the region 4A, the resistor element RS1 and the resistor element RS2 having different sheet resistances can be obtained without adding any manufacturing steps. In the case of the first embodiment, the n-type resistance element RS 1, the p-type resistance element RS 1, the n-type resistance element RS 2, and the p-type resistance element RS 2 having different sheet resistances can be obtained.Although the invention made by the inventors of this application and specifically described above on the basis of the embodiment, the present invention is not limited to the above embodiment and can be modified in various ways within the range that does not depart from the gist of the present invention.References included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedJP 2023-206254

[0001] JP 2018-96243

[0005]

Claims

A method of manufacturing a semiconductor device including a first region in which a ferroelectric memory cell is formed and a second region located at a periphery of the first region, the method comprising: (a) preparing a semiconductor substrate; (b) forming a first amorphous silicon film on the semiconductor substrate located in the first region and the second region; (c) after the (b), removing the first silicon film located in the first region so as to leave the first silicon film located in the second region; (d) after the (c), forming a first polycrystalline silicon film by crystallizing the first silicon film by a first heat treatment; (e) after (d), forming a ferroelectric film on the semiconductor substrate located in the first region and on the first polycrystalline silicon film located in the second region; (f) after (e), forming a metal film on the ferroelectric film located in the first region and the second region; (g) after (f), removing the metal film and the ferroelectric film located in the second region, so that the metal film and the ferroelectric film located in the first region remain; and (h) after (g), forming a second silicon film on the metal film located in the first region and on the first polycrystalline silicon film located in the second region.The method for manufacturing the semiconductor device according to claim 1, wherein in the (h), the second silicon film formed on the metal film is formed in an amorphous state, and the second silicon film formed on the first polycrystalline silicon film is formed as a second polycrystalline silicon film because the first polycrystalline silicon film functions as a seed film.The method for manufacturing the semiconductor device according to claim 2, further comprising: (i) after the (h), patterning the second silicon film, the metal film, and the ferroelectric film located in the first region, and patterning the first polycrystalline silicon film and the second polycrystalline silicon film located in the second region; (j) after the (i), forming an impurity region in the semiconductor substrate located in the first region; and (k) after the (j), activating the impurity region, and forming a third polycrystalline silicon film by crystallizing the second silicon film located in the first region by a second heat treatment.The method for manufacturing the semiconductor device according to claim 3, wherein after the (k), the third polycrystalline silicon film and the metal film located in the first region function as a gate electrode of a transistor included in the ferroelectric memory cell, and the first polycrystalline silicon film and the second polycrystalline silicon film located in the second region function as a gate electrode of a resistance element or an MISFET.The method for manufacturing the semiconductor device according to claim 4, wherein the semiconductor device further includes a third region located at the periphery of the first region and different from the second region, in which (b) the first silicon film is also formed in the third region, in which (c) the first silicon film located in the first region and the third region is removed so that the first silicon film located in the second region remains, in which (e) the ferroelectric film is also formed in the third region, in which (f) the metal film is also formed on the ferroelectric film located in the third region, in which (g) the metal film and the ferroelectric film located in the second region and the third region are removed, such that the metal film and the ferroelectric film located in the first region remain, in which (h) the second silicon film in the amorphous state is also formed on the semiconductor substrate located in the third region, in which (i) the second silicon film located in the third region is also patterned, in which (k) a fourth polycrystalline silicon film is formed by crystallizing the second silicon film located in the third region by the second heat treatment, and after (k), the first polycrystalline silicon film and the second polycrystalline silicon film located in the second region function as a first resistance element, and the fourth polycrystalline silicon film located in the third region function as a second resistance element.The method for manufacturing the semiconductor device according to claim 5, wherein a sheet resistance of the second resistance element is lower than a sheet resistance of the first resistance element.The method for manufacturing the semiconductor device according to claim 2, wherein in (h), a thickness of the first polycrystalline silicon film is 5 nm or more.The method for manufacturing the semiconductor device according to claim 7, wherein in (e), the thickness of the first polycrystalline silicon film is 20 nm or less.The method for manufacturing the semiconductor device according to claim 1, wherein a thickness of the second silicon film is greater than a thickness of the first polycrystalline silicon film.The method for manufacturing the semiconductor device according to claim 9, wherein the thickness of the first polycrystalline silicon film is 5 nm or more and 20 nm or less, and wherein the thickness of the second silicon film is 40 nm or more and 100 nm or less.The method for manufacturing the semiconductor device according to claim 1, wherein in the (d), the first heat treatment is performed in a nitrogen atmosphere within a temperature range of 800 degrees Celsius or more and 1000 degrees Celsius or less and for a time range of 10 seconds or more and 100 seconds or less.The method for manufacturing the semiconductor device according to claim 1, wherein in the (h), the second silicon film is formed within a temperature range of 400 degrees Celsius or more and 550 degrees Celsius or less.The method for manufacturing the semiconductor device according to claim 1, wherein the metal film is a titanium nitride film.

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