semiconductor device

Abstract

A semiconductor device comprising: a plurality of first trench active gates (1) extending in a first direction and facing a source layer (5) and a base layer (14) via a trench gate insulating layer (9); and a second trench active gate (4) extending in a second direction intersecting the first direction and connecting the adjacent first trench active gates (1) to each other. A gate wiring electrode (2) is connected to a wide part in the first trench active gate (1). The second trench active gate (4) is arranged below the gate wiring electrode (2). A connecting part between the first trench active gate (1) and the second trench active gate (4) is T-shaped in a plan view.

Description

Background of the inventionField of the invention

[0001] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device having a trench gate semiconductor element. Description of the state of the art

[0002] A semiconductor device including a trench-gate semiconductor element with a gate electrode embedded in a trench (hereinafter referred to as a "trench gate") is known. For example, in a semiconductor device including a trench-gate insulated-gate bipolar transistor (IGBT), a gate drive signal for driving the IGBT is input to a gate pad provided on the upper surface of the semiconductor device, passes through a gate wiring electrode, and is provided to a plurality of trench gates.

[0003] Typically, the plurality of trench gates extend in a specific direction and are arranged side by side at regular intervals in a direction intersecting the extension direction. The gate wiring electrode is connected to all the trench gates to which gate drive signals are supplied (hereinafter referred to as "active trench gates"). Therefore, when a defect occurs in a connection portion between the gate wiring electrode and a portion of the active trench gate, the active trench gate portion is isolated from the gate wiring electrode, and the IGBT partially stops operating. As a technique for solving this problem, Japanese Patent Application Laid-Open No. 2005-235913 discloses a structure provided with a coupling trench gate connecting adjacent active trench gates.

[0004] In the technique of Japanese Patent Application Laid-Open No. 2005-235913, there is a problem that the trench becomes locally deeper at the intersection between the active trench gate and the coupling trench gate, resulting in deteriorated embeddability of the gate electrode in that part. Summary

[0005] It is an object of the present disclosure to provide a semiconductor device capable of preventing the generation of an active trench gate isolated from a gate wiring electrode while minimizing deterioration in embeddability of a gate electrode.

[0006] A semiconductor device according to the present disclosure includes: a semiconductor substrate; an emitter electrode and a gate wiring electrode provided on an upper surface of the semiconductor substrate; a source layer of a first conductivity type disposed on a surface portion on the upper surface side of the semiconductor substrate and connected to the emitter electrode; a base layer of a second conductivity type disposed below the source layer; a collector electrode provided on a lower surface of the semiconductor substrate; a plurality of first active trench gates extending in a first direction and facing the source layer and the base layer via a trench gate insulating layer;and a second trench active gate extending in a second direction that intersects the first direction and connects the adjacent first trench active gates. Each of the plurality of first trench active gates includes a portion that is wider than other portions. The gate wiring electrode extends in the second direction and is connected to the wider portion in each of the plurality of first trench active gates. The second trench active gate is disposed below the gate wiring electrode. A connecting portion between the first trench active gate and the second trench active gate is T-shaped in a plan view.

[0007] According to the semiconductor device of the present disclosure, it is possible to prevent the generation of an active trench gate isolated from the gate wiring electrode while minimizing deterioration in embeddability of the gate electrode.

[0008] These and other objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when taken in conjunction with the accompanying figures. Short description of the characters Fig. 1 is a plan view illustrating a semiconductor device according to a first preferred embodiment; Fig. 2 is a cross-sectional view taken along a line AA in Fig. 1 is taken; Fig. 3 is a cross-sectional view taken along a line BB in Fig. 1 is taken; Fig. 4 is a cross-sectional view taken along a line CC in Fig. 1 is taken; Fig. 5 is a plan view illustrating a semiconductor device according to a second preferred embodiment; Fig. 6 is a plan view illustrating a semiconductor device according to a third preferred embodiment; Fig. 7 is a plan view illustrating a semiconductor device according to a fourth preferred embodiment; Fig. Fig. 8 is a cross-sectional view taken along a line DD in Fig. 7; Fig. 9 is a cross-sectional view taken along a line EE in Fig. 7; and Fig. 10 is a cross-sectional view taken along a line FF in Fig. 7 is taken. Description of the preferred embodiments

[0009] In the following preferred embodiment, the first conductivity type is described as an n-type and the second conductivity type is described as a p-type, but conversely, the first conductivity type may be a p-type and the second conductivity type may be an n-type. Furthermore, an n-type with a relatively high impurity concentration is referred to as "n + ", an n-type with a relatively low impurity concentration is called "n - ”, a p-type with a relatively high impurity concentration as “p + ”, and a p-type with a relatively low impurity concentration as “p - ". Here, the level of impurity concentration in each region is defined by the peak concentration. That is, a region with a high (or low) impurity concentration denotes a region with a high (or low) peak impurity concentration. <Erste bevorzugte Ausführungsform>

[0010] The Fig. 1 to 4 are diagrams illustrating a configuration of a semiconductor device according to a first preferred embodiment. Fig. 1 is a plan view of the semiconductor device. Fig. 2 is a cross-sectional view taken along a line AA in Fig. 1 is taken. Fig. 3 is a cross-sectional view taken along a line BB in Fig. 1 is taken. Fig. 4 is a cross-sectional view taken along a line CC in Fig. 1. In the present preferred embodiment, a semiconductor element included in the semiconductor device is assumed to be an IGBT. However, the semiconductor element need only be a trench-gate semiconductor element and may be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0011] Fig. 1 illustrates the main part and its periphery of the semiconductor device according to the first preferred embodiment, and specifically illustrates an end of an active region of the semiconductor device and a termination region outside the end part. The active region is a region in which a cell of the semiconductor element is arranged and the main current flows. The termination region is a region provided to surround the active region and in which a withstand voltage holding structure, a gate wiring for controlling the semiconductor element in the active region, and other components are arranged. Fig. 1 illustrates a gate wiring region 100 as the termination region and a cell region 200 as the active region.

[0012] The semiconductor device according to the first preferred embodiment is formed by using a substrate on which an n-type drift layer 11 is formed. The upper main surface of the semiconductor substrate in the respective Fig. 2 to 4 is defined as an "upper surface", and the lower main surface is defined as a "lower surface". That is, Fig. 1 illustrates the configuration of the upper surface of the semiconductor device.

[0013] The material of the semiconductor substrate can be silicon or a wide-bandgap semiconductor such as silicon carbide (SiC). A semiconductor device formed from a wide-bandgap semiconductor is superior to a conventional semiconductor device using silicon in terms of operation at high voltage, higher current, and higher temperature. Examples of wide-bandgap semiconductors include gallium nitride (GaN)-based materials and diamond, in addition to silicon carbide.

[0014] A p-type collector layer 12 is formed in a surface portion on the lower surface side of the semiconductor substrate, that is, on the lower side of the n-type drift layer 11. A collector electrode 13 connected to the p-type collector layer 12 is formed on the lower surface of the semiconductor substrate. The p-type collector layer 12 and the collector electrode 13 are formed over the entire gate wiring region 100 and the cell region 200.

[0015] In the cell region 200, a p-type base layer 14 is formed in a surface part on the side of the upper surface of the semiconductor substrate, that is, on the upper side of the n-type drift layer 11. In the surface part of the p-type base layer 14, an n + -type source layer 5 and a p + -type contact layer 6 is selectively formed. Conversely, the n + -type source layer 5 and the p +-type contact layer 6 is arranged in the surface part of the semiconductor substrate, and the p-type base layer 14 is under the n + -type source layer 5 and the p + -Type contact layer 6 arranged.

[0016] A plurality of trenches extending in the first direction are formed on the upper surface of the semiconductor substrate. The trench is in contact with the n + -type source layer 5 and the p-type base layer 14 and reaches the n-type drift layer 11 under the p-type base layer 14. On the inner surface of the trench, a trench gate insulating layer 9 is formed, and on the trench gate insulating layer 9, a first active trench gate 1 is formed so as to embed the trench.

[0017] The first active trench gate 1 extends in the first direction, and the p-type base layer 14, the n + -type source layer 5, and the p +-type contact layer 6 are arranged between the first active trench gates 1. The first active trench gate 1 is the n + -type source layer 5 and the p-type base layer 14 via the trench gate insulating layer 9. The end of the first active trench gate 1 is arranged in the gate wiring region 100.

[0018] An interlayer insulating layer 10 is formed on the upper surface of the semiconductor substrate. The gate wiring electrode 2 is formed on the interlayer insulating layer 10 of the gate wiring region 100. The gate wiring electrode 2 is connected to a gate pad (not illustrated) to which a gate drive signal is input. The gate wiring electrode 2 is connected to the first trench active gate 1 through a contact hole formed in the interlayer insulating layer 10. A first conductive part 3 is a contact part between the gate wiring electrode 2 and the first trench active gate 1. The first trench active gate 1 has a part that is wider than other parts in the gate wiring region 100, and the first conductive part 3 is arranged on the wider part.

[0019] On the upper surface of the semiconductor substrate in the gate wiring region 100, a trench is formed extending in the second direction intersecting the first direction. A trench gate insulating layer 9 is formed on the inner surface of the trench, and a second trench active gate 4 is formed on the trench gate insulating layer 9 to embed the trench.

[0020] The second active trench gate 4 extends in the second direction and connects the adjacent first active trench gates 1. A connecting part between the first active trench gate 1 and the second active trench gate 4 is T-shaped in a plan view. The second active trench gate 4 is arranged below the gate wiring electrode 2, specifically between the first conductive part 3 and the end of the gate wiring electrode 2.

[0021] An emitter electrode 7 is formed on the interlayer insulating layer 10 in the cell region 200. The emitter electrode 7 is connected to the n + -type source layer 5 and the p + -type contact layer 6 through a contact hole formed in the interlayer insulating layer 10. A contact part 8 is a contact part between the emitter electrode 7 and the n + -type source layer 5 and the p + -Type contact layer 6.

[0022] According to the semiconductor device of the first preferred embodiment, since the adjacent first trench active gates 1 are connected by the second trench active gate 4, for example, even if a defect occurs in the first conductive part 3 and a connection failure occurs between some of the first trench active gates 1 and the gate wiring electrode 2, the first trench active gates 1 are isolated from the gate wiring electrodes 2. Moreover, since the connection part between the first trench active gate 1 and the second trench active gate 4 is T-shaped, there is also an advantage in that the trench is prevented from locally becoming deeper at the connection part between the first trench active gate 1 and the second trench active gate 4, and the embeddability of the gate electrode at the connection is less likely to deteriorate.Moreover, since the second active trench gate 4 is arranged in the gate wiring region 100 (below the gate wiring electrode 2), the effective area of ​​the semiconductor element is prevented from becoming narrower by providing the second active trench gate 4. <Zweite bevorzugte Ausführungsform>

[0023] Fig. 5 is a plan view illustrating a semiconductor device according to a second preferred embodiment. In Fig. 5 are components that are identical or corresponding to those in the Fig. 1 to 4 are identified by identical reference numerals as those in the Fig. 1 to 4, and their descriptions are omitted.

[0024] In the semiconductor device according to the second preferred embodiment, the second active trench gate 4 is arranged at the end of the first active trench gate 1. That is, the second active trench gate 4 connects the ends of the adjacent first active trench gates 1. Also in this case, a connecting part between the first active trench gate 1 and the second active trench gate 4 is T-shaped in a plan view.

[0025] According to the semiconductor device of the second preferred embodiment, the number of T-shaped junctions between the first active trench gates 1 and the second active trench gates 4 is smaller than that in the first preferred embodiment. An electric field concentrates at the corner of the T-shaped junction, and the concentration of electrolysis causes a gate leakage current. Therefore, reducing the number of T-shaped junctions has the effect of suppressing a gate leakage current. <Dritte bevorzugte Ausführungsform>

[0026] Fig. 6 is a plan view of a semiconductor device according to a third preferred embodiment. Also in Fig. 6 are components that are identical or corresponding to those in the Fig. 1 to 4 are identified by identical reference numerals as those in the Fig. 1 to 4, and their descriptions are omitted.

[0027] In the semiconductor device according to the third preferred embodiment, the first active trench gates 1 and the dummy trench gates 15 are arranged alternately in the second direction on the surface of the semiconductor substrate. Similar to the first active trench gate 1, the dummy trench gate 15 is embedded in a trench extending in the first direction and is the n +-type source layer 5 and the p-type base layer 14 via the trench gate insulating layer 9. However, the dummy trench gate 15 is not connected to the gate wiring electrode 2 but to the emitter electrode 7. Therefore, in the third preferred embodiment, as shown in Fig. 6, the second conductive part 8 is formed to partially overlap the dummy trench gate 15. It is possible that the end of the dummy trench gate 15 does not reach the gate wiring region 100.

[0028] The second trench active gate 4, which extends in the second direction, connects the first trench active gates 1, which are adjacent to each other, by interposing the dummy trench gate 15 therebetween. A connecting part between the first trench active gate 1 and the second trench active gate 4 is T-shaped in plan view. The position of the second trench active gate 4 may be on the side closer to the cell region 200 than the first conductive part 3, as in the first preferred embodiment, or it may be at the end of the first trench gate 1, as in the second preferred embodiment.

[0029] According to the semiconductor device of the third preferred embodiment, in addition to the effect similar to that of the first or second embodiment, reducing the number of the first active trench gates 1 has the effect of reducing a gate leakage current generated when the gate drive signal is inputted. <Vierte bevorzugte Ausführungsform>

[0030] The Fig. 7 to 10 are diagrams illustrating a configuration of a semiconductor device according to a fourth preferred embodiment. Fig. 7 is a plan view of the semiconductor device. Fig. Fig. 8 is a cross-sectional view taken along a line DD in Fig. 7 is taken. Fig. 9 is a cross-sectional view taken along a line EE in Fig. 7 is taken. Fig. 10 is a cross-sectional view taken along a line FF in Fig. 7 is taken.

[0031] On the upper surface of the semiconductor substrate, first trenches 21 and second trenches 22 extending in the first direction are arranged alternately in the second direction.

[0032] On the inner surface (bottom surface and side surface) of the first trench 21, the trench gate insulating layer 9 is formed, and a first lower electrode 25 as a first trench active gate is disposed on the trench gate insulating layer 9. Furthermore, in the first trench 21, a first upper electrode 24 is disposed above the first lower electrode 25 via the electrode insulating layer 23. That is, the first lower electrode 25 is disposed in the lower part of the first trench 21, and the first upper electrode 24 is disposed in the upper part of the first trench 21. However, as shown in Fig. As illustrated in Figure 8, the first lower electrode 25 extends further to the outer side of the gate wiring region 100 than the first upper electrode 24, and the first lower electrode 25 is embedded throughout the first trench 21 in the part extending beyond the first electrode 24. The first lower electrode 25 is connected to the gate wiring electrode 2 through a contact hole formed in the interlayer insulating film 10 in the part extending beyond the first upper electrode 24. A third conductive part 17 is a contact part between the gate wiring electrode 2 and the first trench active gate (the first lower electrode 25 and a second lower electrode 27, which will be described later). In the first trench 21, the third conductive part 17 is a contact part between the gate wiring electrode 2 and the first lower electrode 25.The first lower electrode 25 has a part that is wider than the other parts, where the third conductive part 17 is arranged.

[0033] An electrode connection wiring 20 extending in the second direction is formed on the interlayer insulating layer 10 of the gate wiring region 100. The electrode connection wiring 20 is connected to the first upper electrode 24 through a contact hole formed in the interlayer insulating layer 10. The first upper electrode 24 has a portion that is wider than other portions at a contact portion with the electrode connection wiring 20.

[0034] As in Fig. 10, the electrode connection wiring 20 extends in the second direction to cross the first trench 21 and the second trench 22. The emitter electrode 7 is connected to the electrode connection wiring 20 through a contact hole formed in the interlayer insulating film 10, which covers the electrode connection wiring 20. A fourth conductive part 18 is a contact part between the emitter electrode 7 and the electrode connection wiring 20. As described above, the electrode connection wiring 20 connects the first upper electrodes 24 to each other and also connects a plurality of first upper electrodes 24 to the emitter electrode 7.

[0035] On the inner surface (bottom surface and side surface) of the second trench 22, the trench gate insulating layer 9 is formed, and a second lower electrode 27 as a first trench active gate is disposed on the trench gate insulating layer 9. Furthermore, in the second trench 22, a second upper electrode 26 is disposed above the second lower electrode 27 via the electrode insulating layer 23. That is, the second lower electrode 27 is disposed in the lower part of the second trench 22, and the second upper electrode 26 is disposed in the upper part of the second trench 22. However, as shown in Fig. As illustrated in Fig. 9, the second lower electrode 27 extends further to the outer side in the gate wiring region 100 than the second upper electrode 26, and the second lower electrode 27 is embedded throughout the second trench 22 in the part extending beyond the second upper electrode 26. The second lower electrode 27 is connected to the gate wiring electrode 2 through a contact hole formed in the interlayer insulating film 10 in the part extending beyond the second upper electrode 26. In the second trench 22, the third conductive part 17 is a contact part between the gate wiring electrode 2 and the second lower electrode 27. The second lower electrode 27 has a part that is wider than other parts where the third conductive part 17 is arranged.

[0036] As in Fig. As illustrated in FIG. 10, the electrode connection wiring 20 crosses the second lower electrode 27 of the second trenches 22, but the electrode connection wiring 20 and the second lower electrode 27 are insulated from each other by the interlayer insulating film 10. Therefore, the electrode connection wiring 20 can connect the first upper electrodes 24 of the first trenches 21 via the second lower electrodes 27 of the second trenches 22.

[0037] The second upper electrode 26 is connected to the emitter electrode 7 through a contact hole formed in the interlayer insulating film 10 at the end of the cell region 200. Therefore, the end of the second upper electrode 26 may not reach the gate wiring region 100. The fifth conductive part 19 is a contact part between the emitter electrode 7 and the second upper electrode 26. The second upper electrode 26 includes a part that is wider than other parts where the fifth conductive part 19 is located.

[0038] As in Fig.As illustrated in Figure 7, the second trench active gate 4, which extends in the second direction, connects the first lower electrode 25 and the second lower electrode 27, which are adjacent to each other. A connecting part between the first trench active gate 1 and the first lower electrode 25 and a connecting part between the first trench active gate 1 and the second lower electrode 27 are T-shaped in a plan view. The position of the second trench active gate 4 may be on the side closer to the cell region 200 than the third conductive part 17, or it may be at the ends of the first lower electrode 25 and the second lower electrode 27.

[0039] According to the semiconductor device of the fourth preferred embodiment, since the first lower electrode 25 and the second lower electrode 27 are connected by the second trench active gate 4, even if a disconnection occurs in a part of the third conductive part 17, conduction can be maintained between the electrode connection wiring 20 and the first lower electrode 25 and the second lower electrode 27. Moreover, since the first upper electrodes 24 are connected to each other by the electrode connection wiring 20, conduction can be maintained between the electrode connection wiring 20 and the first upper electrode 24 even if a disconnection occurs in a part of the fourth conductive part 18.

[0040] It should be noted that it is possible to freely combine any of the preferred embodiments and to appropriately modify or omit the preferred embodiments. <appendix>

[0041] Below, different aspects of the present disclosure are described collectively as appendices. (Appendix 1)

[0042] Semiconductor device comprising: a semiconductor substrate; an emitter electrode and a gate wiring electrode provided on an upper surface of the semiconductor substrate; a source layer of a first conductivity type disposed on a surface portion on the upper surface side of the semiconductor substrate and connected to the emitter electrode; a base layer of a second conductivity type provided under the source layer; a collector electrode provided on a lower surface of the semiconductor substrate; a plurality of first active trench gates extending in a first direction and facing the source layer and the base layer via a trench gate insulating layer; and a second active trench gate extending in a direction intersecting the first direction and connecting the adjacent active trench gates, wherein each of the plurality of first active trench gates has a part that is wider than other parts, the gate wiring electrode extends in the second direction and is connected to the wider part in each of a plurality of the first active trench gates, the second active trench gate is arranged under the gate wiring electrode, and a connecting part between the first active trench gate and the second active trench gate is T-shaped in a plan view. (Appendix 2)

[0043] The semiconductor device according to Appendix 1, wherein the second active trench gate is connected to one end of the first active trench gate. (Appendix 3)

[0044] The semiconductor device according to Appendix 1 or 2, wherein a dummy trench gate extending in the first direction and connected to the emitter electrode is provided between the first active trench gates. (Appendix 4)

[0045] Semiconductor device according to Appendix 1 or 2 further comprising: a first trench extending in the first direction and in which a first lower electrode serving as the first active trench gate and a first upper electrode are embedded, wherein the first upper electrode is provided above the first lower electrode via an electrode insulation layer; and a second trench extending in the first direction and in which a second lower electrode serving as the first active trench gate and a second upper electrode are embedded, the second upper electrode being provided above the second electrode via the electrode insulation layer, wherein the first trenches and the second trenches are provided alternately in the second direction, the semiconductor device further comprises an electrode connection wiring extending in the second direction and connecting the first upper electrodes adjacent to each other via the second trench, the second trench being interposed between the first upper electrodes, and the electrode connection wiring is connected to the gate wiring electrode.

[0046] While the disclosure has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations may be devised.< / appendix>

Claims

[1] Semiconductor device comprising: • a semiconductor substrate; • an emitter electrode (7) and a gate wiring electrode (2) provided on an upper surface of the semiconductor substrate; • a source layer (5) of a first conductivity type which is arranged on a surface part on the side of the upper surface of the semiconductor substrate and is connected to the emitter electrode (7); • a base layer (14) of a second conductivity type arranged under the source layer (5); • a collector electrode (13) provided on a lower surface of the semiconductor substrate; • a plurality of first active trench gates (1) extending in the first direction and facing the source layer (5) and the base layer (14) via a trench gate insulating layer (9); and • a second active trench gate (4) extending in the second direction, which intersects the first direction and which connects the adjacent first active trench gates (1) to each other, wherein • each of a plurality of first active trench gates (1) has a part that is wider than other parts, • the gate wiring electrode (2) extends in the second direction and is connected to the wider part in each of the plurality of first active trench gates (1), • the second active trench gate (4) is arranged below the gate wiring electrode (2), and • a connecting part between the first active trench gate (1) and the second active trench gate (4) is T-shaped in a plan view. [2] A semiconductor device according to claim 1, wherein the second active trench gate (4) is connected to one end of the first active trench gate (1). [3] A semiconductor device according to claim 1 or 2, wherein a dummy trench gate (15) extending in the first direction and connected to the emitter electrode (7) is provided between the first active trench gates (1). [4] A semiconductor device according to claim 1 or 2, further comprising: • a first trench (21) extending in the first direction and in which a first lower electrode (25) serving as the first active trench gate (1) and a first upper electrode (24) are embedded, wherein the first upper electrode (24) is provided above the first lower electrode (25) via an electrode insulation layer (23); and • a second trench (22) extending in the first direction and in which a second lower electrode (27) serving as the first active trench gate (1) and a second upper electrode (26) are embedded, wherein the second upper electrode (26) is provided above the second lower electrode (27) via the electrode insulation layer (23), wherein • the first trenches (21) and the second trenches (22) are provided alternately in the second direction, • the semiconductor device further comprises an electrode connection wiring (20) extending in the second direction and connecting the first upper electrodes (24) adjacent to each other via the second trench (22), the second trench (22) being interposed between the first upper electrodes (24), and • the electrode connection wiring (20) is connected to the gate wiring electrode (2).

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