SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Abstract

The reliability of a semiconductor device is improved. A resistance element and a trench form a closed path in plan view. The semiconductor device includes: first and second contact elements, each electrically connecting a gate pad and the resistance element; third and fourth contact elements, each electrically connecting a gate wiring and the resistance element; and fifth to eighth contact elements, each electrically connecting a first conductive element and the resistance element. A current path, which runs from the gate pad to the gate wiring through the first conductive element, is made of the plurality of contact elements and the resistance element. The first conductive element cooperates with the fifth to eighth contact elements to form a bypass path for reducing the current flowing through some portions of the closed path made of the resistance element.

Description

CROSS REFERENCE TO RELATED APPLICATIONThe disclosure of Japanese Patent Application No. 2023-208126 filed on Dec. 11, 2023, including the specification, the drawings and the abstract, is incorporated herein by reference in its entirety.BACKGROUNDThe present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including a resistance element used to electrically connect a gate pad and a gate wiring, and a method for manufacturing the semiconductor device.In an IGBT (Insulated Gate Bipolar Transistor) or the like, a resistance element is disposed between a gate wiring connected to a gate electrode and a gate pad in some cases to adjust or limit the switching speed of the IGBT or the like or to prevent vibration that occurs when a plurality of IGBTs are connected in parallel.A technique set forth below is disclosed.[Patent Document 1] Japanese Patent Application Laid-Open No. 2022-82244Patent Document 1 describes an IGBT provided with a built-in resistance element connected in series between a gate pad and a trench gate electrode. The built-in resistance element is formed directly over a P-type semiconductor region through an insulating film and is electrically connected to a gate electrode.For layouts for a resistance element, various types thereof may be used. For example, by using a layout in which a resistance element having a (continuous) trench structure having a loop shape in plan view is disposed between a gate pad and a gate wiring, the switching speed can be adjusted or limited, or the vibration occurring when a plurality of IGBTs are connected in parallel can be prevented. In one example, a resistor element is formed by forming a trench and then embedding polysilicon in the trench. The trench may be formed so that the width of the trench in plan view is made narrow at a boundary which is a folded portion of the loop shape, mainly from the viewpoint of the embedding property of polysilicon.In this case, a portion with the particularly narrow trench width has a relatively high risk of short circuit of the resistance element due to electromigration caused by continuous current flow. In other words, a portion having the narrow trench width has a low electromigration resistance. Accordingly, when a resistor element including a trench structure having a narrow width is used, the influence of electromigration needs to be suppressed by reducing the current flowing in the narrow width portion from the viewpoint of the requirements for downsizing the device structure or the embedding property of polysilicon in the trench.Other problems and novel features will become apparent from the description of the application text and the accompanying drawings.The outline of the typical aspects of the embodiments disclosed in the present application will be briefly described as follows.In a semiconductor device according to an embodiment, a resistor element electrically connecting a gate pad and a gate wiring and a trench accommodating the resistor element form a closed path in plan view. The semiconductor device includes: first and second contact elements that electrically connect the gate pad and the resistor element, respectively; third and fourth contact elements that electrically connect the gate wiring and the resistor element, respectively; and fifth to eighth contact elements that electrically connect a first conductive element and the resistor element, respectively. A current path extending from the gate pad to the gate wiring through the first conductive member is made up of the plurality of contact members and the resistance member. The first conductive member cooperates with the fifth to eighth contact members to form a bypass path for reducing the current flowing through some portions of the closed path made of the resistive element.A method of manufacturing a semiconductor device according to an embodiment includes: a step of forming a well region on a first main surface of a semiconductor substrate; a step of forming a trench in a well region, the trench forming a closed path in plan view; a step of forming an insulating film inside the trench; a step of forming a resistance element inside the trench through the insulating film; a step of forming an interlayer insulating film on the first main surface; a step of forming first to eighth contact elements penetrating the interlayer insulating film and reaching the resistance element; and a step of forming a gate pad, a gate wiring, and a first conductive element on the interlayer insulating film. The first and second contact elements electrically connect the gate pad and the resistance element, respectively, the third and fourth contact elements electrically connect the gate wiring and the resistance element, respectively, and the fifth to eighth contact elements electrically connect the first conductive element and the resistance element, respectively. The first conductive member cooperates with the fifth to eighth contact members to form a bypass path for reducing the current flowing in some portions of the closed path made of the resistive element.According to an embodiment, reliability of a semiconductor device may be improved.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a plan view showing the entire semiconductor device in the first embodiment; FIG. 2 is a conceptual equivalent circuit diagram showing the semiconductor device in the first embodiment; FIG. 3 is a plan view of a main part showing the semiconductor device in the first embodiment; FIG. 4 is a plan view of a main part showing the semiconductor device in the first embodiment; FIG. 5 is a plan view of a main part showing the semiconductor device in the first embodiment; FIG. 6 is a cross-sectional view (A-A cross-sectional view) of the semiconductor device in the first embodiment; FIG. 7 is a cross-sectional view (B-B cross-sectional view) of the semiconductor device in the first embodiment; FIG. 8 is a cross-sectional view (C-C cross-sectional view) of the semiconductor device in the first embodiment; FIG. 9 is a cross-sectional view (D-D cross-sectional view) of the semiconductor device in the first embodiment; FIG. 10 is a plan view of a main part showing a modification example of the semiconductor device in the first embodiment; FIG. 11 is a plan view of a main part showing the semiconductor device in the second embodiment; FIG. 12 is a plan view of a main part showing the semiconductor device in the second embodiment; FIG. 13 is a plan view of a main part showing a first modification example of the semiconductor device in the second embodiment; FIG. 14 is a plan view of a main part showing a second modification example of the semiconductor device in the second embodiment; FIG. 15 is a plan view of a main part showing a third modification example of the semiconductor device in the second embodiment; FIG. 16 is a plan view of a principal part showing the semiconductor device in the third embodiment 3; FIG. 17 is a plan view of a principal part showing the semiconductor device in the third embodiment; FIG. 18 is a plan view of a main part showing a modification example of the semiconductor device in the third embodiment; FIG. 19 is a plan view of a principal part showing the semiconductor device in the fourth embodiment; FIG. 20 is a cross-sectional view (E-E cross-sectional view) showing the semiconductor device in the fourth embodiment; FIG. 21 is a cross-sectional view (A-A cross-sectional view) showing a step of manufacturing the semiconductor device in the first embodiment; FIG. 22 is a cross-sectional view (C-C cross-sectional view) showing a step of manufacturing the semiconductor device in the first embodiment; FIG. 23 is a cross-sectional view (A-A cross-sectional view) showing the manufacturing step continued from the manufacturing step shown in FIGS. 21 and 22 ; FIG. 24 is a cross-sectional view (C-C cross-sectional view) showing the manufacturing step continued from the manufacturing step shown in FIGS. 21 and 22 ; FIG. 25 is a cross-sectional view (A-A cross-sectional view) showing the manufacturing step continued from the manufacturing step shown in FIGS. 23 and 24 ; FIG. 26 is a cross-sectional view (C-C cross-sectional view) showing the manufacturing step continued from the manufacturing step shown in FIGS. 23 and 24 ; FIG. 27 is a cross-sectional view (A-A cross-sectional view) showing the manufacturing step continued from the manufacturing step shown in FIGS. 25 and 26 ; FIG. 28 is a cross-sectional view (C-C cross-sectional view) showing the manufacturing step continued from the manufacturing step shown in FIGS. 25 and 26 ; FIG. 29 is a cross-sectional view (A-A cross-sectional view) showing the manufacturing step continued from the manufacturing step shown in FIGS. 27 and 28 ; FIG. 30 is a cross-sectional view (C-C cross-sectional view) showing the manufacturing step continued from the manufacturing step shown in FIGS. 27 and 28 ; FIG. 31 is a cross-sectional view (A-A cross-sectional view) showing the manufacturing step continued from the manufacturing step shown in FIGS. 29 and 30 ; FIG. 32 is a cross-sectional view (A-A cross-sectional view) showing the manufacturing step continued from the manufacturing step shown in FIG. 31 ; FIG. 33 is a cross-sectional view (C-C cross-sectional view) showing the manufacturing step continued from the manufacturing step shown in FIG. 31 ; FIG. 34 is a cross-sectional view (A-A cross-sectional view) showing the manufacturing step continued from the manufacturing step shown in FIGS. 32 and 33 ; and FIG. 35 is a cross-sectional view (C-C cross-sectional view) showing the manufacturing step continued from the manufacturing step shown in FIGS. 32 and 33.SummaryHereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that components having the same function are denoted by the same reference numerals throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. Moreover, in the following embodiments, explanations of the same or similar parts will not be repeated in principle unless otherwise particularly required. In addition, FIGS. 3 to 5 and FIGS. 10 to 19 may not correctly illustrate the relationship of components in the up and down direction in part to assist in understanding the shapes of the components. FIGS. 6 to 9 and FIGS. 20 to 35, which are cross-sectional views, illustrate the relationship of components in the up-and-down direction.First EmbodimentStructure of Semiconductor DeviceFIG. 1 is a plan view showing a semiconductor device 100 configured as a semiconductor chip. The semiconductor device 100 includes a cell region 1A including a cell configured as an IGBT and a peripheral region 1B located near the cell region 1A and including a gate wiring and the like. The cell region 1A includes a plurality of IGBT cells. In the example of FIG. 1, the cell region 1A is divided into three partial regions along the Y direction (at each of the boundaries between the partial regions, a gate wiring GW extends in the X direction orthogonal to the Y direction). The three portions are covered with an emitter electrode EE.The peripheral region 1B includes a gate pad GP for applying a voltage to a gate electrode GE 1, the gate wiring GW for electrically connecting the gate pad GP and the gate electrode GE 1, and a resistance element region RGA. Although the detailed shapes of the gate pad GP, the gate wiring GW, and the resistor element region RGA are omitted in FIG. 1, the gate pad GP and the gate wiring GW are electrically connected by a resistor element Rg formed in the resistor element region RGA as shown in FIG. 3 described later and the like, and the gate wiring GW is electrically connected to the gate electrode GE 1 of the IGBT by a contact element (a plug) PG formed in a contact hole CH 3 described later (see the B-B cross-sectional view in FIG. 7 ).Note that the emitter electrode EE, the gate pad GP, the gate wiring GW, and the resistor element region RGA are each covered with a protective film such as a polyimide film, and the protective film covering the emitter electrode EE and the protective film covering the gate pad GP have openings OPEN and OPG, respectively. An external connection terminal is connected to each of the portion of the emitter electrode EE exposed from the opening OPEN and the portion of the gate pad GP exposed from the opening OPG, and the semiconductor device 100 is electrically connected to a lead frame, another semiconductor chip, a circuit board, or the like through the external connection terminals. The external connection terminal is, for example, a bonding wire made of gold, copper, or aluminum, or a clip made of a copper plate.In addition, on the first main surface SUBa of the semiconductor substrate SUB, ring-shaped field plates are overlapped to surround the outer shape of the gate wiring GW. The innermost one of the field plates is integrated with the end portion of the emitter electrode EE with the end opposite to the gate pad GP side, and does not overlap and is separated from the gate wiring GW.FIG. 2 is a conceptual equivalent circuit diagram of the semiconductor device 100. The IGBT includes a gate electrode GE 1, a collector region PC, and an emitter region NE. The collector electrode CE is electrically connected to the collector region PC, and the emitter electrode EE is electrically connected to the emitter region NE. As described above, the gate pad GP and the gate electrode GE 1 are electrically connected by the resistance element. More specifically, as shown in FIG. 2, the gate pad GP is electrically connected to a first conductive element CE 1 (such as a flat conductive pad, see FIG. 3 described later) through a resistance element part Rg 1, and the first conductive element CE 1 is electrically connected to the gate electrode GE 1 through a resistance element part Rg 2. In the example of FIG. 3, a portion of a first extended part P 1 between the first contact element CM 1 and the fifth contact element CM 5 and a portion of a second extended part P 2 between the second contact element CM 2 and the eighth contact element CM 8 correspond to the resistor element portion Rg 1, and a portion of a third extended part P 3 between the third contact element CM 3 and the sixth contact element CM 6 and a portion of a fourth extended part P 4 between the fourth contact element CM 4 and the seventh contact element CM 7 correspond to the resistor element portion Rg 2.Structure of IGBTEach of FIGS. 3 to 5 is a plan view of a principal part of the region near the resistance element region RGA in the semiconductor device 100. FIG. 6 is a cross-sectional view taken along line A-A in FIG. 3, FIG. 7 is a cross-sectional view taken along line B-B in FIG. 3.As shown in FIG. 6, the cell region 1A of the semiconductor device 100 includes an active cell AC for performing the main operation of the IGBT and an inactive cell IAC other than the active cell AC. The IGBT shown in FIG. 6 is an IE-type IGBT that enables use of the IE effect (injection amplification) that increases the concentration of the charge stored in a drift region NV by making it difficult to discharge holes from the emitter electrode EE side when the IGBT is in an ON state. The gate electrode GE 1 aof the active cell AC is electrically connected to the gate wiring GW through the contact member PG filled in a contact hole CH 3 (FIGS. 3 and 7 ), and the gate potential is supplied during the IGBT operation. A gate electrode GE 2 of the inactive cell IAC is electrically connected to the emitter electrode EE through the contact element PG filled in a contact hole CH 2 (FIGS. 3 and 6 ), and the emitter potential is supplied during the IGBT operation.As shown in FIG. 3, in the cell region 1A, a trench TR (in the active cell AC) in which the gate electrode GE 1 is formed and a trench TR (in the inactive cell IAC) in which the gate electrode GE 2 is formed are alternately formed along the X direction while extending in the Y direction. The trench TR formed in the active cell AC and the gate electrode GE 1 formed within the trench TR form a gate trench. The trench TR formed in the inactive cell IAC and the gate electrode GE 2 formed within the trench TR form an emitter trench. A contact hole CH1 is formed in the active cell AC, and the contact hole CH1 is filled with the contact element PG. A contact hole CH2 is formed in the inactive cell IAC, and the contact hole CH2 is filled with the contact element PG. Both the contact element PG in the contact hole CH 1 and the contact element PG in the contact hole CH 2 are electrically connected to the emitter electrode EE (FIG. 6 ). The emitter region NE is also formed in the active cell AC.As shown in FIG. 6, the semiconductor device 100 includes an n-type semiconductor substrate SUB having a first main surface (upper surface) SUBa and a second main surface (lower surface) SUBb. The semiconductor substrate SUB is made of n-type silicon and has a low-concentration n-type semiconductor layer (drift region) NV. On the second main surface SUBb side of the semiconductor substrate SUB, an n-type field stop region (impurity region) NS having an impurity concentration higher than the drift region NV, a p-type collector region (impurity region) PC, and a collector electrode CE are formed of a metal film. The field stop region NS is provided to prevent a depletion layer extending from a p-n junction on the upper surface side of the semiconductor substrate SUB from reaching the p-type collector region PC when the IGBT is turned off. During the IGBT operation, a collector potential is supplied to the collector region PC through the collector electrode CE. The collector electrode CE is either a single-layered metal film such as an Au film, Ni film, Ti film or AlSi film, or a stacked metal film, these films being optionally stacked.On the first main surface SUBa side of the semiconductor substrate SUB, the trench TR is formed in the semiconductor substrate SUB. The trench TR penetrates the emitter region NE and / or a base region PB and reaches the inside of the semiconductor substrate SUB. The depth of the trench TR is, for example, 2 μm or more and 5 μm or less. A gate insulating film GI is formed inside the trench TR. The gate electrodes GE 1 and GE 2 are formed on the gate insulator GI to fill the inside of the trench TR. The gate insulating film GI is, for example, a silicon oxide film, and the gate electrodes GE1 and GE2 are, for example, polycrystalline silicon films (polysilicon films) doped with an n-type impurity. The thickness of the gate insulating film GI is, for example, 70 nm or more and 150 nm or less.In the active cell AC, a hole barrier region (impurity region) NHB having a higher impurity concentration than the drift region NV is formed in the semiconductor substrate SUB between a pair of gate electrodes GE 1. In the hole barrier region NHB, a p-type base region (impurity region) PB is formed. In the p-type base region PB, an n-type emitter region (impurity region) NE having a higher impurity concentration than the drift region NV is formed. The base region PB is formed to be shallower than the depth of the trench TR, and the emitter region NE is formed to be shallower than the depth of the base region PB. The base region PB which is located under the emitter region NE is used as a channel region.In the inactive cell IAC, a hole barrier region NHB is formed in the semiconductor substrate SUB between a pair of gate electrodes GE 2. In addition, a p-type floating region (impurity region) PF is formed in the semiconductor substrate SUB between the gate electrodes GE 1 and GE 2. A p-type base region PB having a higher impurity concentration than the floating region PF is formed in the hole barrier region NHB and the floating region PF. The floating region PF is preferably formed to a position deeper than the bottom of the trench TR to improve the high breakdown voltage resistance, and is more preferably formed to cover the bottom of the trench TR. In addition, in the inactive cell IAC, the floating region PF is formed in the semiconductor substrate SUB of the cell region 1A except for the portion between the pair of trenches TR. The floating region PF and the base region PB formed within the floating region PF are not electrically connected to the gate wiring GW and the emitter electrode EE, and are electrically floating.On the first main surface SUBa of the semiconductor substrate SUB, an interlayer insulating film IL is formed to cover each trench TR. The interlayer insulating film IL is, for example, a silicon oxide film. The thickness of the interlayer insulating film IL is, for example, 600 nm or more and 1500 nm or less. In addition, a planarization process for planarizing the upper surface of the interlayer insulating film IL is performed on the interlayer insulating film IL. In the active cell AC, the contact hole CH1 penetrates the interlayer insulating film IL and the emitter region NE and reaches the base region PB. The contact hole CH 1 is formed to be in contact with the emitter region NE and the base region PB. The contact element PG is embedded in the contact hole CH1, and the contact element PG is electrically connected to the emitter region NE and the base region PB. In the inactive cell IAC, the contact hole CH2 penetrates the interlayer insulating film IL and reaches the inside of the base region PB. The contact hole CH 2 is formed to overlap the gate electrode GE 2 in plan view. The contact element PG is embedded within the contact hole CH 2, and the contact element PG is electrically connected to the gate electrode GE 2 and the base region PB. The contact member PG includes a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a stacked film of a titanium film and a titanium nitride film formed on the titanium film. The conductive film is, for example, a tungsten film.A p-type high concentration diffusion region (impurity region) PR having an impurity concentration higher than the base region PB is formed around the bottom of the contact holes CH1 and CH2. The high concentration diffusion region PR is provided to reduce contact resistance with the contact element PG and prevent latch-up.The emitter electrode EE is formed on the interlayer insulating film IL. The emitter electrode EE is electrically connected to the emitter region NE, the base region PB and the high density diffusion region PR through the contact member PG and supplies emitter potential to these regions. Although not shown in FIG. 6, the gate pad GP (including the gate pad wiring GPW) formed by the same process as the emitter electrode EE, the gate wiring GW, and the first conductive member CE 1 are also formed on the interlayer insulating film IL (FIGS. 3 and 7 to 9 ).Such an emitter electrode EE, such a gate pad GP, such a gate wiring GW, and such a first conductive element CE 1 include a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a TiW film. The conductive film is, for example, an aluminum alloy film to which copper or silicon is added. The aluminum alloy film is a main conductive film of the emitter electrode EE and the gate wiring GW, and is sufficiently thicker than the TiW film.As shown in FIG. 3, a pair of the gate electrodes GE 1 are also connected to each other and are electrically connected to the gate wiring GW in the peripheral region 1B through the contact member PG formed in the contact hole CH 3. As shown in FIG. 7, a well region PW, which is a p-type semiconductor region, is provided in the peripheral region 1B. The gate electrode GE1 formed in the trench TR in the well region PW is electrically connected to the gate wiring GW through the contact member PG formed in the contact hole CH3. The well region PW is formed by the same process as that of the floating region PF in the cell region 1A, and therefore has the same depth as that of the floating region PF. However, in plan view, the well region is physically separated from the floating region PF.The resistive element and its surrounding structure FIGS. 4 and 5 are plan views of the resistive element region RGA shown in FIG. 3. FIG. 8 is a cross-sectional view taken along line C-C of FIG. 4, FIG. 9 is a cross-sectional view taken along line D-D of FIG. 4.As shown in FIG. 1, two resistance element regions RGA are formed in the semiconductor device 100 to sandwich the gate pad GP in the Y direction. FIGS. 3 and 4 show the structure of the resistance element region RGA located under the gate pad GP. The structure of the resistor element region RGA located above the gate pad GP has the same structure as in FIGS. 3 and 4, and the two resistor element regions RGA are in a line-symmetric relationship in the Y direction with respect to the X axis passing through the center of the gate pad GP.As shown in FIG. 3, the semiconductor device 100 includes, in the X direction, the cell region 1A and a peripheral region 1B adjacent to the cell region 1A. The peripheral portion 1B is formed in the tray portion PW in plan view.As shown in FIG. 3, the peripheral region 1B includes the gate pad GP and the resistance element region RGA disposed under the gate pad GP (in the negative direction of the Y direction). The gate pad GP has a quadrangle (such as a square or a rectangle) in plan view, and has an opening OPG at the center thereof.A gate pad wiring GPW (assumed to be a part of the gate pad GP) is connected to the gate pad GP, and the gate pad wiring GPW extends to the resistor element region RGA. The gate pad wiring GPW is a wiring extending from the gate pad GP, and the wiring width of the gate pad wiring GPW is smaller than the length of the side of the gate pad GP (for example, the side from which the gate pad wiring GPW protrudes). The gate wiring GW is disposed around the gate pad GP and the resistor element region RGA, and extends to the resistor element region RGA.The resistance element region RGA is formed in the well region PW in plan view. A resistor element Rg exists in the resistor element region RGA, and the gate pad wiring GPW, the gate wiring GW (which is connected to a gate inspection pad GIP), and the first conductive member CE 1 exist in the positive direction of Z as viewed from the resistor element Rg. A part of the emitter electrode EE extends in a gap between the elements of the gate pad GP, the gate wiring GW, and the first conductive element CE 1 in the resistor element region RGA. As described above, the plan views of FIG. 3 and other drawings do not accurately show the positional relationship of the components in the up-and-down direction. See the cross-sectional views of FIGS. 8 and 9 for the positional relationship of the components in the resistance element region RGA in the up and down direction. The resistor element Rg, the gate pad GP (the gate pad wiring GPW), the gate wiring GW, and the first conductive element CE 1 are electrically connected through the contact element PG formed in the contact hole CH 3.The resistor element Rg shown in FIG. 3 is the integral type resistor element formed by the insulating film within the trench forming the closed path (having the endless loop shape) in plan view, but is explained while being divided into the first extended part P 1 to the seventh extended part P 7 and a first connection part CP 1 as shown in FIG. 4 for convenience of explanation. The first and second extended parts P 1 and P 2 extend in the Y direction and are separated from each other in the X direction. The first connection part CP 1 electrically connects an end of the first extended part P 1 to an end of the second extended part P 2. The third and fourth extended parts P 3 and P 4 extend in the Y direction, are separated from each other in the X direction, and are disposed between the first and second extended parts in plan view. The fifth extended part P 5 extends in the X direction and electrically connects an end of the third extended part P 3 to an end of the fourth extended part P 4. The sixth extended part P 6 extends in the X direction and electrically connects the other end of the first extended part P 1 to the other end of the third extended part P 3. The seventh extended part P 7 extends in the X direction and electrically connects the other end of the second extended part P 2 to the other end of the fourth extended part P 4. Since the other end of the first extended part P 1 and the other end of the second extended part P 2 are electrically connected by the third to seventh extended parts P 3 to P 7, the third to seventh extended parts P 3 to P 7 are sometimes collectively referred to as a second connection part CP 2. As described above, the trench may be formed so that the width of the trench in plan view is made narrow at a boundary that is the folded portion of the loop shape, mainly from the viewpoint of the embedding property of polysilicon. In the first embodiment, the widths of the first to fourth extended parts P 1 to P 4 extending in the Y direction (width in the X direction in plan view) are set to 0.8 μm (micrometers), and the widths of the fifth to seventh extended parts P 5 to P 7 extending in the X direction and the width of the first connection part CP 1 (width in the Y direction in plan view) are set to 0.4 μm (micrometers).As shown in FIG. 5, the resistor element Rg formed within the trench is electrically connected to the first to eighth contact elements CM 1 to CM 8. As shown in FIGS. 3 to 5, the first and second contact members CM 1 and CM 2 electrically connect the gate pad GP to the first and second extended parts P 1 and P 2, the third and fourth contact members CM 3 and CM 4 electrically connect the gate wiring GW to the third and fourth extended parts P 3 and P 4, the fifth contact member CM 5 electrically connects the first conductive member CE 1 to the first extended part P 1, the sixth contact member CM 6 electrically connects the first conductive member CE 1 to the third extended part P 3, the seventh contact member CM 7 electrically connects the first conductive member CE 1 to the fourth extended part P 4, and the eighth contact member CM 8 electrically connects the first conductive member CE 1 to the second extended part P 2. As shown in FIGS. 8 and 9, each contact element penetrating the interlayer insulating film IL electrically connects any one of the gate pad GP, the gate wiring GW, and the first conductive member CE 1 formed on the interlayer insulating film IL to the resistance element Rg formed in the p-type well region PW.Features of the First EmbodimentSince the resistance element Rg is provided with the configurations shown in FIGS. 3 to 5, 8, and 9, the resistance of the resistance element Rg against electromigration can be improved. In particular, when the first conductive member CE 1 and the fifth to eighth contact members CM 5 to CM 8 are not provided, when at least a part of the current flowing through the sixth and seventh narrow width extended parts P 6 and P 7 is bypassed to flow through the first conductive member CE 1, the current flowing through the sixth and seventh extended parts P 6 and P 7 may be decreased, thereby reducing the influence of the electromigration in the sixth and seventh extended parts P 6 and P 7. The current path formed when the current flows from the gate pad GP to the gate wiring GW will be described in detail below.First, a current path formed when the first conductive member CE 1 and the fifth to eighth contact members CM 5 to CM 8 are not provided in the resistor element region RGA shown in FIG. 3 and other drawings will be described. The current from the gate pad GP flows through the contact element CM 1 to the first extended part P 1 of the resistor element Rg, and then through the sixth extended part P 6, the third extended part P 3, and the third contact element CM 3 to the gate wiring GW. At the same time, the current flows from the gate pad GP through the contact member CM 2 to the second extended part P 2 of the resistor element Rg, and then through the seventh extended part P 7, the fourth extended part P 4, and the fourth contact member CM 4 to the gate wiring GW. Since both paths extend through the sixth or seventh narrow width extended part and do not include the bypass path for bypassing the current flowing through the sixth and seventh extended parts P 6 and P 7, the resistance element Rg in the sixth and seventh narrow width extended parts P 6 and P 7 may be deteriorated over time particularly by the influence of electromigration.Next, as shown in FIG. 3 and other drawings, a current path formed when the first conductive member CE 1 and the fifth to eighth contact members CM 5 to CM 8 are provided in the resistance element region RGA will be described as a first embodiment. The current from the gate pad GP is branched into current flowing from the first extended part P 1 through the sixth extended part P 6 into the third extended part and current flowing through the first contact element CM 1 to the first extended part P 1 of the resistor element Rg, and then flows from the first extended part P 1 through the fifth contact element CM 5 to the first conductive element CE 1, and then flows through the sixth contact element CM 6 to the third extended part. That is, when the first conductive member CE 1 and the fifth to eighth contact members CM 5 to CM 8 are not provided, at least a part of the current flowing to the sixth extended part P 6 is bypassed to the first conductive member CE 1. At the same time, the current from the gate pad GP is branched into current flowing from the second extended part P 2 through the seventh extended part P 7 to the fourth extended part and current flowing through the contact element CM 2 into the second extended part P 2 of the resistor element Rg, and then flows from the second extended part P 2 through the eighth contact element CM 8 to the first conductive element CE 1, and then flows through the seventh contact element CM 7 to the fourth extended part. That is, when the first conductive member CE 1 and the fifth to eighth contact members CM 5 to CM 8 are not provided, at least a part of the current flowing to the seventh extended part P 7 is bypassed to the first conductive member CE 1. The current flowing to the third extended part P 3 and the current flowing to the fourth extended part P 4 flow to the gate wiring GW through the third contact member CM 3 and the fourth contact member CM 4, respectively. As described above, when the resistance element Rg, the first to eighth contact elements CM 1 to CM 8, and the first conductive element CE 1 of the first embodiment are used, at least a part of the current flowing into the sixth and seventh narrow width extended parts P 6 and P 7 can be bypassed. This can improve the resistance of the resistance element Rg to electromigration. In a preferred aspect, when the distance D 1 (see FIG. 5 ) between the fifth to eighth contact members CM 5 to CM 8 and the sixth and seventh extended parts P 6 and P 7 is set such that a ratio of the electric resistance value between the bypass path and the non-bypass path is 1:1, an amount of current flowing to the sixth and seventh narrow width extended parts P 6 and P 7 may be made half as large as an amount of current flowing to the sixth and seventh extended parts P 6 and P 7 in the case without the bypass path.In the configuration of the first embodiment, the ratio of the amount between the current flowing in the bypass path from the first extended part P 1 to the third extended part P 3 through the fifth contact element CM 5, the first conductive element CE 1, and the sixth contact element CM 6 and the current flowing in the non-bypass path flowing from the first extended part P 1 to the third extended part P 3 through the sixth extended part P 6 corresponds to the ratio of the electric resistance of the two paths. Similarly, the ratio of the amount between the current flowing in the bypass path flowing from the second extended part P 2 to the fourth extended part P 4 through the eighth contact element CM 8, the first conductive element CE 1, and the seventh contact element CM 7 and the amount of the current flowing in the non-bypass path flowing from the second extended part P 2 to the fourth extended part P 4 through the seventh extended part P 7 corresponds to the ratio of the electric resistance of the two paths. That is, when the path length of the non-bypass path is extremely short while the electric resistance of the non-bypass path is extremely smaller than the electric resistance of the bypass path, most of the current flows in the non-bypass path, and therefore the effect of improving the resistance to electromigration cannot be sufficiently obtained. In an aspect for adjusting the path length of the non-bypass path, the current flowing in the bypass path may be adjusted by adjusting the distance D 1 shown above in FIG. 5, that is, the distance D 1 from the fifth to eighth contact members CM 5 to CM 8 to the sixth and seventh extended parts P 6 and P 7 to be a predetermined distance or greater to adjust the electric resistance of the non-bypass path to a predetermined value or greater. In addition, when the first to eighth contact elements CM 1 to CM 8 are extremely short in the Y direction, the current densities in the first to eighth contact elements CM 1 to CM 8 are high, and the influence of electromigration in the first to eighth contact elements CM 1 to CM 8 is large. Meanwhile, the current flowing through the first to eighth contact elements CM 1 to CM 8 concentrates on the central edge of the loop shape of the trench TR including the resistance element Rg. Therefore, when the first to eighth contact members CM 1 to CM 8 are made extremely long in the Y direction, the first to eighth contact members CM 1 to CM 8 include a large area in which no current flows, and therefore the first to eighth contact members CM 1 to CM 8 cannot be used efficiently. In view of the above, the lengths of the first to eighth contact members CM 1 to CM 8 in the Y direction are preferably made within a predetermined range. In an example, the lengths of the first to eighth contact members CM 1 to CM 8 in the Y direction may be set to 20 μm (micrometers).Modification Example of First EmbodimentFIG. 10 is a plan view of a main part showing a modification example of the semiconductor device in the first embodiment. Two sets of resistance elements Rg, first to eighth contact elements CM 1 to CM 8 described with reference to FIG. 3 and other drawings are formed to separate in the X direction. The configuration of each of the two sets is the same as that described above in the first embodiment. The configuration shown in FIG. 10 corresponds to a configuration in which two sets of current paths are provided from the gate pad GP to the gate wiring GW in parallel, as described with reference to FIG. 3 and other drawings. Based on the same principle as that described with reference to FIG. 3 and other drawings, the resistance of the resistance element Rg in each of the two sets against electromigration can be improved by reducing the current flowing in the sixth and seventh narrow width extended parts P 6 and P 7 in each of the two sets of resistance elements RgA and RgB. Note that the number of the sets of the resistance element Rg and the first to eighth contact elements CM 1 to CM 8 to be formed may be any number of three or more. That is, a plurality of sets of the resistance element Rg formed in the trench TR by the insulating film GI and the first to eighth contact elements CM 1 to CM 8 may be formed, the sets may be disposed so as to separate from each other in the X direction in plan view, the gate pad wiring GPW included in the gate pad GP may be formed so as to overlap the first and second contact elements CM 1 and CM 2 in each of the plurality of sets in plan view, the gate wiring GW may be disposed so as to overlap the third and fourth contact elements CM 3 and CM 4 in each of the plurality of sets in plan view, and the first conductive member CE 1 may be disposed to overlap the fifth to eighth contact members CM 5 to CM 8 in each of the plurality of sets in plan view.Second EmbodimentEach of FIGS. 11 and 12 is a plan view of a main part showing a semiconductor device 100 in a second embodiment. In the second embodiment, the shape of the resistance element Rg is different from that of the first embodiment, and the layout and the number of the contact elements CM are also different from those of the first embodiment. Further, in the second embodiment, a second conductive member CE 2 (such as a flat plate type conductive pad) is provided. The second conductive member CE 2 is also the same as the first conductive member CE 1 in that the CE 2 is disposed on the interlayer insulating film IL and includes the barrier metal film and the conductive film formed on the barrier metal film. In the following description, differences from the first embodiment will be mainly explained, and common points with the first embodiment will be omitted as appropriate.As shown in FIG. 11, the first and second extended parts P 1 and P 2 extend in the Y direction and are arranged to separate from each other in the X direction. The third and fourth extended parts P 3 and P 4 extend in the Y direction, are separated from each other in the X direction, and are disposed between the first and second extended parts in plan view. The fifth extended part P 5 extends in the X direction and electrically connects an end of the third extended part P 3 to an end of the fourth extended part P 4. The sixth extended part P 6 extends in the X direction and electrically connects the other end of the first extended part P 1 to the other end of the third extended part P 3. The seventh extended part P 7 extends in the X direction and electrically connects the other end of the second extended part P 2 to the other end of the fourth extended part P 4. The eighth and ninth extended parts P 8 and P 9 extend in the Y direction, are separated from each other in the X direction, and are disposed between the first extended part P 1 and the second extended part P 2 in plan view. The tenth extended part P 10 extends in the X direction and electrically connects an end of the first extended part P 1 and an end of the eighth extended part P 8. The eleventh extended part P 11 extends in the X direction and electrically connects an end of the second extended part P 2 to an end of the ninth extended part P 9. The twelfth extended part P 12 extends in the X direction and electrically connects the other end of the eighth extended part P 8 to the other end of the ninth extended part P 9. Since the eighth to twelfth extended parts P 8 to P 12 electrically connect an end of the first extended part P 1 and an end of the second extended part P 2, the eighth to twelfth extended parts P 8 to P 12 are collectively referred to as the first connection part CP 1. Since the third to seventh extended parts P 3 to P 7 electrically connect the other end of the first extended part P 1 to the other end of the second extended part P 2, the third to seventh extended parts P 3 to P 7 are collectively referred to as the second connection part CP 2. In the second embodiment, the widths of the first to fourth, eighth, and ninth extended parts P 1 to P 4, P 8, and P 9 extending in the Y direction (widths in the X direction in plan view) are set to 0.8 μm (micrometers), and the widths of the fifth to seventh, tenth to twelfth extended parts P 5 to P 7, and P 10 to P 12 extending in the X direction (widths in the Y direction in plan view) are set to 0.4 μm (micrometers).As shown in FIG. 12, the resistor element Rg formed within the trench is electrically connected to the first contact element CM 1 to the twelfth contact element CM 12.The first and second contact members CM 1 and CM 2 electrically connect the gate pad GP and the eighth and ninth extended parts P 8 and P 9, respectively. The third and fourth contact members CM 3 and CM 4 electrically connect the gate wiring GW and the third and fourth extended parts P 3 and P 4, respectively. The fifth contact element CM 5 electrically connects the first conductive element CE 1 and the first extended part P 1. The sixth contact element CM 6 electrically connects the first conductive element CE 1 and the third extended part P 3. The seventh contact element CM 7 electrically connects the first conductive element CE 1 and the fourth extended part P 4. The eighth contact element CM 8 electrically connects the first conductive element CE 1 and the second extended part P 2. The ninth contact member CM 9 electrically connects the second conductive member CE 2 and the first extended part P 1. The tenth contact element CM 10 electrically connects the second conductive element CE 2 and the eighth extended part P 8. The eleventh contact member CM 11 electrically connects the second conductive member CE 2 and the ninth extended part P 9. The twelfth contact element CM 12 electrically connects the second conductive element CE 2 and the second extended part P 2.In the semiconductor device 100 shown in FIGS. 11 and 12, a current path passing through the fifth contact element CM 5, the first conductive element CE 1, and the sixth contact element CM 6 is formed as the bypass path for the current path passing through the sixth extended part P 6. In addition, a current path passing through the seventh contact element CM 7, the first conductive element CE 1, and the eighth contact element CM 8 is formed as the bypass path for the current path passing through the seventh extended part P 7. In addition, a current path passing through the ninth contact element CM 9, the second conductive element CE 2, and the tenth contact element CM 10 is formed as the bypass path for the current path passing through the 10th extended part P 10. In addition, a current path passing through the eleventh contact element CM 11, the second conductive element CE 2, and the twelfth contact element CM 12 is formed as the bypass path for the current path passing through the eleventh extended part P 11. Accordingly, since the current flowing through the sixth, seventh, tenth, and eleventh narrow width extended parts P 6, P 7, P 10, and P 11 is reduced, the influence of electromigration on these extended parts is reduced.Note that the shape of the resistor element Rg in the second embodiment is also distinctive in that the electrical resistance of the current path running from the gate pad GP to the gate wiring GW can be adjusted by the change in the position of the contact element CM together with the securing of the resistance against electromigration. The following is the description for an example in which the electric resistance of the resistance element Rg is changed from the electric resistance of the resistance element Rg of FIGS. 11 and 12 by the change in the position of the contact element CM with reference to FIGS. 13 to 15.First Modification Example of the Second EmbodimentFIG. 13 is a plan view of a main part showing a first modification example of the semiconductor device in the second embodiment. As compared with the configurations of FIGS. 11 and 12, the positions of the first and second contact members CM 1 and CM 2 are different, and the first and second contact members CM 1 and CM 2 electrically connect the gate pad GP and the first and second extended parts P 1 and P 2, respectively.The paths of the current flowing from the gate pad GP to the gate wiring GW (paths including the bypass path) in the configurations of FIGS. 11 and 12 are the following two parallel paths that are:(1) the path leading to the gate wiring GW through the first contact member CM 1, the eighth extended part P 8, the tenth contact member CM 10, the second conductive member CE 2, the ninth contact member CM 9, the first extended part P 1, the fifth contact member CM 5, the first conductive member CE 1, the sixth contact member CM 6, the third extended part P 3, and the third contact member CM 3,(2) the path leading to the gate wiring GW through the second contact member CM 2, the ninth extended part P 9, the eleventh contact member CM 11, the second conductive member CE 2, the twelfth contact member CM 12, the second extended part P 2, the eighth contact member CM 8, the first conductive member CE 1, the seventh contact member CM 7, the fourth extended part P 4, and the fourth contact member CM 4.The paths of the current flowing from the gate pad GP to the gate wiring GW (paths including the bypass path) in the configurations of FIG. 13 are the following two parallel paths, which are:(1) the path leading to the gate wiring GW through the first contact member CM 1, the first extended part P 1, the fifth contact member CM 5, the first conductive member CE 1, the sixth contact member CM 6, the third extended part P 3, and the third contact member CM 3,(2) the path leading to the gate wiring GW through the second contact member CM 2, the second extended part P 2, the eighth contact member CM 8, the first conductive member CE 1, the seventh contact member CM 7, the fourth extended part P 4, and the fourth contact member CM 4.The current paths in the configuration of FIG. 13 are shorter than those in the configurations of FIGS. 11 and 12, in other words, the electric resistance of the current paths extending from the gate pad GP to the gate wiring GW can be reduced by changing the positions of the first and second contact members CM 1 and CM 2 from those in the configurations of FIGS. 11 and 12.Second Modification Example of the Second EmbodimentFIG. 14 is a plan view of a main part showing a second modification example of the semiconductor device in the second embodiment. As compared with the configurations of FIGS. 11 and 12, the positions of the third and fourth contact members CM 3 and CM 4 are different, and the third and fourth contact members CM 3 and CM 4 electrically connect the gate wiring GW and the first and second extended parts P 1 and P 2, respectively.The paths of the current flowing from the gate pad GP to the gate pad. Wiring GW flows (paths including the bypass path) in the configurations of FIG. 14 are the following two parallel paths that are:(1) the path leading to the gate wiring GW through the first contact member CM 1, the eighth extended part P 8, the tenth contact member CM 10, the second conductive member CE 2, the ninth contact member CM 9, the first extended part P 1, and the third contact member CM 3,(2) the path leading to the gate wiring GW through the second contact member CM2, the ninth extended part P9, the eleventh contact member CM11, the second conductive member CE2, the twelfth contact member CM12, the second extended part P2 and the fourth contact member CM4.The current paths in the configuration of FIG. 14 are shorter than those in the configurations of FIGS. 11 and 12.When the distance between the first conductive element CE 1 and the gate wiring GW (distance in the Y direction) is larger than the distance between the second conductive element CE 2 and the gate pad GP (distance in the Y direction), the current paths in the configuration of FIG. 14 are shorter than those in the configuration of FIG. 13. in other words, the electric resistance of the current paths extending from the gate pad GP to the gate wiring GW can be reduced by changing the positions of the third and fourth contact members CM 3 and CM 4 from those in the configurations of FIGS. 11 and 12.Third Modification Example of the Second EmbodimentFIG. 15 is a plan view of a main part showing a third modification example of the semiconductor device in the second embodiment. As compared with the configurations of FIGS. 11 and 12, the positions of the first to fourth contact members CM 1 to CM 4 are different. The first and second contact members CM 1 and CM 2 electrically connect the gate pad GP and the first and second extended parts P 1 and P 2, respectively. The third and fourth contact members CM 3 and CM 4 electrically connect the gate wiring GW and the first and second extended parts P 1 and P 2, respectively.The paths of the current flowing from the gate pad GP to the gate wiring GW (paths including the bypass path) in the configurations of FIG. 15 are the following two parallel paths, which are:(1) the path leading to the gate wiring GW through the first contact member CM 1, the first extended part P 1, and the third contact member CM 3,(2) the path leading to the gate wiring GW through the second contact member CM 2, the second conductive member CE 2, the twelfth contact member CM 12, the second extended part P 2, and the fourth contact member CM 4.The current paths in the configuration of FIG. 15 are shorter than those in the configurations of FIGS. 11, 12, 13, and 14. in other words, the electric resistance of the current paths extending from the gate pad GP to the gate wiring GW can be reduced by changing the positions of the first to fourth contact members CM 1 to CM 4 from those in the configurations of FIGS. 11 and 12.Third EmbodimentEach of FIGS. 16 and 17 is a plan view of a main part showing a semiconductor device 100 in the third embodiment. In the third embodiment, the shape of the resistance element Rg is similar to that of the second embodiment (FIGS. 11 and 12 ), and the extended parts and contact elements through which the current paths from the gate pad GP to the gate wiring GW pass are also the same as those of the second embodiment. However, the widths of the gate pad GP and the gate wiring GW in the Y direction are larger than those in the second embodiment. The assumption of the configuration shown in FIGS. 16 and 17 makes large clearances for changing the positions of the first and second contact members CM 1 and CM 2 in the Y direction together with securing the electrical connection to the gate pad GP and for changing the positions of the third and fourth contact members CM 3 and CM 4 in the Y direction together with securing the electrical connection to the gate wiring GW. By such a position change, the electric resistance of the current path extending from the gate pad GP to the gate wiring GW can be changed.Modification Example of Third EmbodimentFIG. 18 is a plan view of a main part showing a modification example of the semiconductor device in the third embodiment. As compared with the configurations of FIGS. 16 and 17, the positions of the first and second contact members CM 1, CM 2 are moved in the positive direction of the Y direction, and the positions of the third and fourth contact members CM 3, CM 4 are moved in the negative direction of the Y direction. By these movements, the current path running from the gate pad GP to the gate wiring GW is shortened, and the electric resistance of the current path in the configuration of FIG. 18 is decreased than the electric resistance of the current path in the configurations of FIGS. 16 and 17.Fourth EmbodimentFIG. 19 is a plan view of a main part showing a semiconductor device 100 in the fourth embodiment. In the fourth embodiment, the shape of the resistance element Rg is similar to that of the second embodiment (FIGS. 11 and 12 ), and the extended parts and contact elements through which the current paths from the gate pad GP to the gate wiring GW pass are also the same as those of the second embodiment. However, a well contact element (contact element (plug) PG) for electrically connecting the emitter electrode EE and the well region PW is formed in the well contact hole CH 4.FIG. 20 is a cross-sectional view taken along line E-E in the plan view of FIG. 19 ; five well contact elements (contact elements (plugs) PG) electrically connect the emitter electrode EE and the well region PW. By such a configuration, the potential difference of the well region PW between the regions of the trench TR on the positive and negative sides of the X direction can be reduced. Further, the dielectric breakdown of the gate insulating film GI in the trench TR in which the resistance element Rg is embedded can be prevented.Method of Manufacturing a Semiconductor DeviceEach manufacturing step included in the method for manufacturing the semiconductor device 100 in the first embodiment will be described below with reference to FIGS. 21 to 35.First, a semiconductor substrate SUB having an n-type drift region NV is fabricated. The semiconductor substrate SUB is made of n-type silicon. Note that the semiconductor substrate SUB may be a stacked body of an n-type silicon substrate and an n-type silicon layer grown on the silicon substrate while being doped with phosphorus (P) by an epitaxial growth method. Next, as shown in FIG. 21, an n-type hole barrier region NHB is formed in a region 1A of the semiconductor substrate SUB near the upper surface side of the semiconductor substrate SUB by a photolithography technique and an ion implantation method. Next, a p-type floating region PF is formed in the region 1A of the semiconductor substrate SUB near the upper surface side of the semiconductor substrate SUB by a photolithography technique and an ion implantation method (FIG. 21 ), and simultaneously a p-type well region PW is formed in a region 2A of the semiconductor substrate SUB as shown in FIG. 22. The floating region PF is physically separated from the well region PW.Subsequently, as shown in FIG. 23, a pair of trenches TR are formed in the semiconductor substrate SUB of the active cell AC and the inactive cell IAC in the region 1A near the upper surface side of the semiconductor substrate SUB. First, a resist pattern RP1 is formed on the upper surface of the semiconductor substrate SUB in the region 1A to cover the region 2A and a part of the region 1A. Next, an anisotropic etching process is performed on the semiconductor substrate SUB in the region 1A while using the resist pattern RP 1 as a mask. Thereby, a plurality of trenches TR are formed in the semiconductor substrate SUB in the region 1A. Thereafter, the resist pattern RP1 is removed by an ashing process.Simultaneously with the step shown in FIG. 23, a trench TR (see FIG. 3 ) forming a closed path for forming the resistance element Rg in plan view is formed in the semiconductor substrate SUB in the region 1B, specifically, in the well region PW near the upper surface side of the semiconductor substrate SUB, as shown in FIG. 24. The method of forming the trench TR is the same as the method of forming the trench TR in the region 1A.As shown in FIGS. 25 and 26, a sacrificial oxide film SOF is formed within the trench TR and on the upper surface of the semiconductor substrate SUB. Thereby, a damaged layer formed in the semiconductor substrate SUB is removed. Thereafter, the sacrificial oxide film SOF is removed, for example, by an isotropic etching process using a solution containing hydrofluoric acid.Note that the sacrificial oxide film SOF is formed by heating the semiconductor substrate SUB. This heating process is performed, for example, in an atmosphere filled with oxygen gas and under conditions at 1100° C. for 30 minutes or longer and 60 minutes or shorter. By this heating process, the impurities in the hole barrier region NHB, the floating region PF, and the well region PW are diffused.Next, as shown in FIGS. 27 and 28, the gate insulating film GI and the conductive film CF 1 are formed. First, the gate insulating film GI is formed inside the trench TR and on the upper surface of the semiconductor substrate SUB by a thermal oxidation method.Next, the conductive film CF 1 is formed inside the trench TR and on the upper surface of the semiconductor substrate SUB to fill the inside of the trench TR through the gate insulating film GI by, for example, a CVD method. The conductive film CF 1 is, for example, a polycrystalline silicon film doped with an n-type impurity.As shown in FIG. 29, a gate insulating film GI and gate electrodes GE 1 and GE 2 are formed within the trench TR. First, the conductive film CF 1 formed outside the trench TR is removed by an anisotropic etching process. The conductive film CF 1 formed within the trench TR remains as gate electrodes GE 1 and GE 2. Next, the gate insulating film GI formed outside the trench TR is removed by an isotropic etching process, an anisotropic etching process, or an etching process combining these etching processes.Simultaneously with the step shown in FIG. 29, a resistance element Rg is formed within the trench TR as shown in FIG. 30. First, the conductive film CF 1 formed outside the trench TR is removed by an anisotropic etching process. The conductive film CF 1 formed within the trench TR remains as the resistance element Rg. Next, the gate insulating film GI formed outside the trench TR is removed by an isotropic etching process, an anisotropic etching process, or an etching process combining these etching processes.Next, as shown in FIG. 31, a p-type base region PB is formed inside the semiconductor substrate SUB in the region 1A (floating region PF and hole barrier region NHB) near the upper surface side of the semiconductor substrate SUB by a photolithography technique and an ion implantation method. Next, an n-type emitter region NE is formed within the base region PB by a photolithography technique and an ion implantation method. Subsequently, a heating process is performed on the semiconductor substrate SUB to activate the impurity contained in each impurity region.Next, as shown in FIGS. 32 and 33, an interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB in the regions 1A and 2A to cover the trench TR in the region 1A and the resistance element Rg in the region 2A by, for example, a CVD method. Subsequently, a polishing process is performed on the interlayer insulating film IL in the regions 1A and 2A by a CMP method to planarize the upper surface of the interlayer insulating film IL. Further, contact holes CH 1 to CH 3 are formed in the interlayer insulating film IL in the regions 1A and 2A by a photolithography technique and an anisotropic etching process. Next, as shown in FIG. 32, a high-concentration p-type diffusion region PR is formed on the bottoms of the contact holes CH1 and CH2 by an ion implantation method.The contact hole CH1 penetrates the interlayer insulating film IL and the emitter region NE and reaches the inside of the base region PB. The contact hole CH2 penetrates the interlayer insulating film IL and reaches the inside of the base region PB. In addition, the contact hole CH 2 is formed to overlap the gate electrode GE 2 in plan view. The contact hole CH 3 (eight contact holes CH 3 are formed to correspond to the first to eighth contact elements CM 1 to CM 8 shown in FIG. 5 ) penetrates the interlayer insulating film IL and reaches the inside of the resistance element Rg.As shown in FIGS. 34 and 35, a contact member PG is formed inside each of the contact holes CH 1 to CH 3. First, a barrier metal film is formed within each of the contact holes CH 1 to CH 3 and on the interlayer insulating film IL. The barrier metal film described above can be formed, for example, by a sputtering method for forming a titanium film in each of the contact holes CH 1 to CH 3 and on the interlayer insulating film IL, and, for example, by a sputtering method for forming a titanium nitride film on the titanium film.Next, a conductive film made of, for example, a tungsten film is formed on the barrier metal film to fill the inside of each of the contact holes CH1 to CH3 by, for example, a CVD method. Next, the conductive film and the above-described barrier metal film formed outside each of the contact holes CH 1 to CH 3 are removed by an anisotropic etching process. As a result, a contact member PG is formed to fill the inside of each of the contact holes CH 1 to CH 3.Next, a gate pad GP (including a gate pad wiring GPW), a gate wiring GW, a first conductive element CE 1, and an emitter electrode EE are formed on the interlayer insulating film IL. First, a TiW film is formed on the interlayer insulating film IL by, for example, a sputtering method, and then an aluminum alloy film is formed on the TiW film by, for example, a sputtering method. Next, the TiW film and the aluminum alloy film are patterned by a photolithography technique and a dry etching process, thereby forming the gate pad GP, the gate wiring GW, the first conductive member CE 1, and the emitter electrode EE.Thereafter, the structure shown in FIGS. 3 to 9 is obtained by the following manufacturing step. First, an n-type field stop region NS and a p-type collector region PC are formed by ion implantation from the lower surface side of the semiconductor substrate SUB. After the ion implantation, the impurities included in the field stop region NS and the collector region PC are activated by laser annealing. Next, a metal film such as an Au film, Ni film, Ti film or AlSi film is formed under the lower surface of the semiconductor substrate SUB by, for example, a sputtering method. This metal film serves as a collector electrode CE. The collector electrode CE may be a stacked film in which the metal films are optionally stacked.The method of manufacturing the semiconductor device 100 in the second to fourth embodiments is approximately the same as the method described with reference to FIGS. 21 to 35. To form a second conductive element CE 2, the second conductive element CE 2 may be formed on the interlayer insulating film IL similarly to the first conductive element CE 1. In order to form a well contact member (contact member PG) in the well contact hole CH4, as shown in Figs. 33 to 35, after forming the contact holes CH1 to CH3, the well contact hole CH4 may be formed simultaneously with the step of forming the contact member PG within the contact holes CH1 to CH3, and the contact member PG may be formed within the well contact hole CH4.In the foregoing, the present invention has been concretely described based on the embodiments. However, the present invention is not limited to the foregoing embodiments, and various modifications may be made within the scope of the present invention.For example, in the above embodiments, the IGBT is exemplified as the device formed in the cell region 1A. However, the technique disclosed in the above embodiments is not limited to the IGBT, but is also applicable to a power MOSFET having a vertical trench gate structure.In addition, the material used for the semiconductor substrate SUB is not limited to silicon (Si), and silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3) or the like are also applicable. The n-type impurity may be, for example, phosphorus (P), arsenic (As), or the like, and the p-type impurity may be, for example, boron (B), indium (In), or the like.In addition, various configurations described in the embodiments and the modification examples of the embodiments may be combined with each other. This application text describes, for example, the following configurations,StatementsStatement 1A semiconductor device, comprising:a semiconductor substrate having a first main surface and a well region formed on the first main surface;an interlayer insulating film formed on the first main surface;a gate pad, a gate wiring, and a first conductive element formed on the interlayer insulating film;a resistance element formed by an insulating film inside a trench forming a closed path in plan view, the trench being formed in the well region; andfirst to eighth contact elements which penetrate the interlayer insulating film and reach the resistance element,the resistance element comprises:first and second elongated portions extending in a first direction in plan view and separating from each other in a second direction crossing the first direction in plan view;a first connection part electrically connecting an end of the first extended part and an end of the second extended part; anda second connection part electrically connecting the other end of the first extended part and the other end of the second extended part,the first and second contact elements electrically connect the gate pad and the resistor element, respectively,the third and fourth contact elements electrically connect the gate wiring and the resistance element, respectively; andthe fifth to eighth contact members electrically connect the first conductive member and the resistance member, respectively.Statement 2In the semiconductor device according to Claim 1, the second connection part includes:third and fourth elongated parts extending in the first direction separate from each other in the second direction and interposed between the first and second elongated parts in plan view;a fifth extended part extending in the second direction and electrically connecting an end of the third extended part and an end of the fourth extended part;a sixth extended part extending in the second direction and electrically connecting the other end of the first extended part and the other end of the third extended part; anda seventh extended part extending in the second direction and electrically connecting the other end of the second extended part and the other end of the fourth extended part,wherein the fifth contact element electrically connects the first conductive element and the first elongated portion,the sixth contact member electrically connects the first conductive member and the third extended part,the seventh contact member electrically connects the first conductive member and the fourth elongated part; andthe eighth contact member electrically connects the first conductive member and the second extended part.Statement 3In the semiconductor device according to claim 1 or 2, wherein the third contact element electrically connects the gate wiring and the third extended part, and the fourth contact element electrically connects the gate wiring and the fourth extended part.Statement 4In the semiconductor device according to any one of Expressions 1 to 3, wherein each width of the first to fourth extended parts in the second direction in plan view is larger than each width of the fifth to seventh extended parts in the first direction in plan view.Statement 5In the semiconductor device according to any one of claims 1 to 4, wherein the fifth to eighth contact members separate from the sixth and seventh extended parts in the first direction by at least a predetermined distance.Statement 6In the semiconductor device according to any one of Claims 1 to 5, wherein the first to eighth contact elements each have a length within a predetermined range in the first direction.Statement 7wherein the semiconductor device according to any one of Expressions 1 to 6 includes a plurality of sets of the insulating film, the resistance element, and the first to eighth contact elements, the sets separate from each other in the second direction in plan view, the gate pad includes a gate pad wiring, and the gate pad wiring overlaps the first and second contact elements in each of the plurality of sets in plan view, the gate wiring overlaps the third and fourth contact elements in each of the plurality of sets in plan view, and the first conductive element overlaps the fifth to eighth contact elements in each of the plurality of sets in plan view.Statement 8The semiconductor device according to any one of claims 1 to 7, further comprising:a second conductive element formed on the interlayer insulating film; andninth to twelfth contact elements which penetrate the interlayer insulating film and reach the resistance element,wherein the first connection part comprises:eighth and ninth extended parts extending in the first direction separate from each other in the second direction and are disposed between the first and second extended parts in plan view;a tenth extended part extending in the second direction and electrically connecting an end of the first extended part and an end of the eighth extended part;an eleventh extended part extending in the second direction and electrically connecting an end of the second extended part and an end of the ninth extended part; anda twelfth extended part extending in the second direction and electrically connecting the other end of the eighth extended part and the other end of the ninth extended part,wherein the ninth contact element electrically connects the second conductive element and the first extended part, the tenth contact element electrically connects the second conductive element and the eighth extended part, the eleventh contact element electrically connects the second conductive element and the ninth extended part, and the twelfth contact element electrically connects the second conductive element and the second extended part.Statement 9In the semiconductor device according to any one of Claims 1 to 8, wherein the gate pad includes a gate pad wiring, the gate pad wiring has a width of at least a first predetermined length in the first direction in plan view, and the gate wiring has a width of at least a second predetermined length in the first direction in plan view.Statement 10The semiconductor device according to any one of claims 1 to 9, further comprising:an emitter electrode formed on the interlayer insulating film; anda well contact element which penetrates the interlayer insulating film and reaches the well region; andwherein the well contact element electrically connects the emitter electrode and the well region.Statement 11A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a semiconductor substrate having a first main surface; (b) forming a well region on the first main surface of the semiconductor substrate; (c) forming a trench in the well region, the trench forming a closed path in plan view; (d) forming an insulating film within the trench; (e) forming a resistance element within the trench through the insulating film; (f) forming an interlayer insulating film on the first main surface; (g) forming first to eighth contact elements penetrating the interlayer insulating film and reaching the resistance element; and (h) forming a gate pad, a gate wiring, and a first conductive element on the interlayer insulating film, wherein in step (e), the resistance element comprises:first and second elongated portions extending in the first direction in plan view and separating from each other in a second direction crossing the first direction in plan view;a first connection part electrically connecting an end of the first extended part and an end of the second extended part; anda second connection part electrically connecting the other end of the first extended part and the other end of the second extended part,wherein in steps (g) and (h)the first and second contact elements electrically connect the gate pad and the resistor element, respectively,the third and fourth contact elements electrically connect the gate wiring and the resistance element, respectively; andthe first to eighth contact members, the gate pad, the gate wiring, and the first conductive member are formed such that the fifth to eighth contact members electrically connect the first conductive member and the resistor member, respectively.Statement 12The method for manufacturing a semiconductor device according to claim 11, wherein in step (e), the resistor element is formed such that the second connection part includes: third and fourth extended parts extending in the first direction, separating from each other in the second direction, and being disposed between the first and second extended parts in plan view; a fifth extended part extending in the second direction and electrically connecting one end of the third extended part and one end of the fourth extended part; a sixth extended part extending in the second direction and electrically connecting the other end of the first extended part and the other end of the third extended part; and a seventh extended part extending in the second direction and electrically connecting the other end of the second extended part and the other end of the fourth extended part, and wherein in steps (g) and (h), the fifth to eighth contact elements and the first conductive element are formed such that the fifth contact element electrically connects the first conductive element and the first extended part, such that the sixth contact element electrically connects the first conductive element and the third extended part, such that the seventh contact element electrically connects the first conductive element and the fourth extended part, and such that the eighth contact element electrically connects the first conductive element and the second extended part.Statement 13The method for manufacturing a semiconductor device according to claim 11 or 12, wherein in the steps (g) and (h), the third and fourth contact elements and the gate wiring are formed such that the third contact element electrically connects the gate wiring and the third extended part, and such that the fourth contact element electrically connects the gate wiring and the fourth extended part.Statement 14The method for manufacturing a semiconductor device according to any one of claims 11 to 13, wherein in step (e), the resistance element is formed such that each width of the first to fourth extended parts in the second direction in plan view is larger than each width of the fifth to seventh extended parts in the first direction in plan view.Statement 15The method for manufacturing a semiconductor device according to any one of claims 11 to 14, wherein in step (g), the fifth to eighth contact members separate from the sixth and seventh extended parts in the first direction by at least a predetermined distance.Statement 16The method for manufacturing a semiconductor device according to any one of claims 11 to 15, wherein in step (g), the first to eighth contact members are formed to have a length within a predetermined range in the first direction.Statement 17The method for manufacturing a semiconductor device according to any one of claims 11 to 16, wherein in the steps (c) to (e), a plurality of the trenches, a plurality of the insulating films, and a plurality of the resistor elements are formed, wherein in the step (g), the semiconductor device is configured to include a plurality of sets of the insulating film, the resistor element, and the first to eighth contact elements by forming a plurality of the first to eighth contact elements, the sets being separated from each other in the second direction in plan view, wherein in the step (h), the gate pad is formed such that the gate pad includes a gate pad wiring, and such that the gate pad wiring overlaps the first and second contact elements in each of the plurality of the sets in plan view, wherein in step (h), the gate wiring is formed to overlap the third and fourth contact elements in each of the plurality of sets in plan view, and wherein in step (h), the first conductive element is formed to overlap the fifth to eighth contact elements in each of the plurality of sets in plan view.Statement 18The method for manufacturing a semiconductor device according to any one of claims 11 to 17, wherein in step (g), the ninth to twelfth contact elements are further formed that penetrate the interlayer insulating film and reach the resistor element, wherein in step (h), a second conductive element is further formed on the interlayer insulating film, wherein in step (e), the resistor element is formed such that the first connection part comprises:eighth and ninth extended parts extending in the first direction separate from each other in the second direction and are disposed between the first and second extended parts in plan view;a tenth extended part extending in the second direction and electrically connecting an end of the first extended part to an end of the eighth extended part;an eleventh extended part extending in the second direction and electrically connecting an end of the second extended part and an end of the ninth extended part; anda twelfth extended part extending in the second direction and electrically connecting the other end of the eighth extended part and the other end of the ninth extended part; andwherein, in steps (g) and (h), the ninth to twelfth contact members and the second conductive member are formed such that the ninth contact member electrically connects the second conductive member and the first extended part, such that the tenth contact member electrically connects the second conductive member and the eighth extended part, such that the eleventh contact member electrically connects the second conductive member and the ninth extended part, and such that the twelfth contact member electrically connects the second conductive member and the second extended part.Statement 19The method for manufacturing a semiconductor device according to any one of claims 11 to 18, wherein in step (h), the gate pad is formed such that the gate pad includes a gate pad wiring and such that the gate pad wiring has a width of at least a first predetermined length in the first direction in plan view, and the gate wiring is formed such that the gate wiring has a width of at least a second predetermined length in the first direction in plan view.Statement 20The method for manufacturing a semiconductor device according to any one of claims 11 to 19, wherein in step (g), a well contact element penetrating the interlayer insulating film and reaching the well region is further formed, wherein in step (h), an emitter electrode is further formed on the interlayer insulating film, and wherein the well contact element electrically connects the emitter electrode and the well region.References included in the specificationThis list of documents cited by the applicant has been produced in an automated manner and is only included for the better information of the reader. The list is not part of the German patent application or utility model application. The DPMA does not take any adhesion for any faults or omissions.Patent Literature citedJP 2023-208126

[0001] JP 2022-82244

[0005]

Claims

A semiconductor device comprising: a semiconductor substrate having a first main surface and a well region formed on the first main surface; an interlayer insulating film formed on the first main surface; a gate pad, a gate wiring, and a first conductive element formed on the interlayer insulating film; a resistor element formed by an insulating film inside a trench forming a closed path in plan view, the trench being formed in the well region; and first to eighth contact elements penetrating the interlayer insulating film and reaching the resistor element, wherein the resistor element comprises: first and second extended parts extending in a first direction in plan view and separating from each other in a second direction crossing the first direction in plan view; a first connection part electrically connecting one end of the first extended part and one end of the second extended part; and a second connection part electrically connecting the other end of the first extended part and the other end of the second extended part, wherein the first and second contact elements electrically connect the gate pad and the resistor element, respectively, wherein the third and fourth contact elements electrically connect the gate wiring and the resistor element, respectively, and wherein the fifth to eighth contact elements electrically connect the first conductive element and the resistor element, respectively.The semiconductor device according to claim 1, wherein the second connection part comprises: third and fourth extended parts extending in the first direction, separating from each other in the second direction, and being disposed between the first and second extended parts in plan view; a fifth extended part extending in the second direction and electrically connecting one end of the third extended part and one end of the fourth extended part; a sixth extended part extending in the second direction and electrically connecting the other end of the first extended part and the other end of the third extended part; a seventh extended part extending in the second direction and electrically connecting the other end of the second extended part and the other end of the fourth extended part, wherein the fifth contact element electrically connects the first conductive element and the first extended part, wherein the sixth contact element electrically connects the first conductive element and the third extended part, wherein the seventh contact element electrically connects the first conductive element and the fourth extended part, and wherein the eighth contact element electrically connects the first conductive element and the second extended part.The semiconductor device according to claim 2, wherein the third contact element electrically connects the gate wiring and the third extended part, and the fourth contact element electrically connects the gate wiring and the fourth extended part.The semiconductor device according to claim 2, wherein each width of the first to fourth extended parts in the second direction in plan view is greater than each width of the fifth to seventh extended parts in the first direction in plan view.The semiconductor device according to claim 2, wherein the fifth to eighth contact members separate from the sixth and seventh extended parts by at least a predetermined distance in the first direction.The semiconductor device according to claim 1, wherein the first to eighth contact members each have a length within a predetermined range in the first direction.The semiconductor device according to claim 1, further comprising a plurality of sets of the insulating film, the resistance element, and the first to eighth contact elements, the sets being separated from each other in the second direction in plan view, wherein the gate pad includes a gate pad wiring, and the gate pad wiring overlaps the first and second contact elements in each of the plurality of sets in plan view, wherein the gate wiring overlaps the third and fourth contact elements in each of the plurality of sets in plan view, and wherein the first conductive element overlaps the fifth to eighth contact elements in each of the plurality of sets in plan view.The semiconductor device according to claim 1, further comprising: a second conductive element formed on the interlayer insulating film; and ninth to twelfth contact elements that penetrate the interlayer insulating film and reach the resistor element, wherein the first connection part comprises: eighth and ninth extended parts extending in the first direction, separate from each other in the second direction, and are arranged between the first and second extended parts in plan view; a tenth extended part extending in the second direction and electrically connecting an end of the first extended part and an end of the eighth extended part; an eleventh extended part extending in the second direction and electrically connecting an end of the second extended part and an end of the ninth extended part; and a twelfth extended part extending in the second direction and electrically connecting the other end of the eighth extended part and the other end of the ninth extended part, wherein the ninth contact element electrically connects the second conductive element and the first extended part, the tenth contact element electrically connects the second conductive element and the eighth extended part, the eleventh contact element electrically connects the second conductive element and the ninth extended part, and the twelfth contact element electrically connects the second conductive element and the second extended part.The semiconductor device according to claim 1, wherein the gate pad includes a gate pad wiring, the gate pad wiring has a width of at least a first predetermined length in the first direction in plan view, and the gate wiring has a width of at least a second predetermined length in the first direction in plan view.The semiconductor device according to claim 1, further comprising: an emitter electrode formed on the interlayer insulating film; and a well contact element that penetrates the interlayer insulating film and reaches the well region, and wherein the well contact element electrically connects the emitter electrode and the well region.A method of manufacturing a semiconductor device, comprising the steps of: (a) manufacturing a semiconductor substrate having a first main surface; (b) forming a well region on the first main surface of the semiconductor substrate; (c) forming a trench in the well region, the trench forming a closed path in plan view; (d) forming an insulating film within the trench; (e) forming a resistance element within the trench through the insulating film; (f) forming an interlayer insulating film on the first main surface; (g) forming first to eighth contact elements penetrating the interlayer insulating film and reaching the resistance element; (h) forming a gate pad, a gate wiring, and a first conductive member on the interlayer insulating film, wherein in step (e), the resistor element includes: first and second extended parts extending in the first direction in plan view and separating from each other in a second direction crossing the first direction in plan view; a first connection part electrically connecting an end of the first extended part and an end of the second extended part; and a second connection part electrically connecting the other end of the first extended part and the other end of the second extended part, wherein in steps (g) and (h), the first and second contact elements electrically connect the gate pad and the resistor element, respectively, the third and fourth contact elements electrically connect the gate wiring and the resistor element, respectively, and the first to eighth contact elements, the gate pad, the gate wiring, and the first conductive element are formed such that the fifth to eighth contact elements electrically connect the first conductive element and the resistor element, respectively.The method for manufacturing the semiconductor device according to claim 11, wherein in step (e), the resistor element is formed such that the second connection part includes: third and fourth extended parts extending in the first direction, separating from each other in the second direction, and being disposed between the first and second extended parts in plan view; a fifth extended part extending in the second direction and electrically connecting one end of the third extended part and one end of the fourth extended part; a sixth extended part extending in the second direction and electrically connecting the other end of the first extended part and the other end of the third extended part; and a seventh extended part extending in the second direction and electrically connecting the other end of the second extended part and the other end of the fourth extended part, and wherein in steps (g) and (h), the fifth to eighth contact elements and the first conductive element are formed such that the fifth contact element electrically connects the first conductive element and the first extended part, such that the sixth contact element electrically connects the first conductive element and the third extended part, such that the seventh contact element electrically connects the first conductive element and the fourth extended part, and such that the eighth contact element electrically connects the first conductive element and the second extended part.The method for manufacturing the semiconductor device according to claim 12, wherein in the steps (g) and (h), the third and fourth contact elements and the gate wiring are formed such that the third contact element electrically connects the gate wiring and the third extended part, and such that the fourth contact element electrically connects the gate wiring and the fourth extended part.The method for manufacturing the semiconductor device according to claim 12, wherein in step (e), the resistance element is formed such that each width of the first to fourth extended parts in the second direction in plan view is larger than each width of the fifth to seventh extended parts in the first direction in plan view.The method for manufacturing the semiconductor device according to claim 12, wherein in step (g), the fifth to eighth contact members separate from the sixth and seventh extended parts by at least a predetermined distance in the first direction.The method for manufacturing the semiconductor device according to claim 11, wherein in step (g), the first to eighth contact members are formed to have a length within a predetermined range in the first direction.The method for manufacturing the semiconductor device according to claim 11, wherein in the steps (c) to (e), a plurality of the trenches, a plurality of the insulating films, and a plurality of the resistor elements are formed, wherein in the step (g), the semiconductor device is configured to include a plurality of sets of the insulating film, the resistor element, and the first to eighth contact elements by forming a plurality of the first to eighth contact elements, the sets being separated from each other in the second direction in plan view, wherein in the step (h), the gate pad is formed such that the gate pad includes a gate pad wiring and such that the gate pad wiring overlaps the first and second contact elements in each of the plurality of the sets in plan view, wherein in step (h), the gate wiring is formed to overlap the third and fourth contact elements in each of the plurality of sets in plan view, and wherein in step (h), the first conductive element is formed to overlap the fifth to eighth contact elements in each of the plurality of sets in plan view.The method for manufacturing the semiconductor device according to claim 11, wherein in step (g), the ninth to twelfth contact elements are further formed that penetrate the interlayer insulating film and reach the resistor element, wherein in step (h), a second conductive element is further formed on the interlayer insulating film, wherein in step (e), the resistor element is formed such that the first connection part includes: eighth and ninth extended parts extending in the first direction, separating from each other in the second direction, and being disposed between the first and second extended parts in plan view; a tenth extended part extending in the second direction and electrically connecting an end of the first extended part to an end of the eighth extended part; an eleventh extended part extending in the second direction and electrically connecting an end of the second extended part and an end of the ninth extended part; and a twelfth extended part extending in the second direction and electrically connecting the other end of the eighth extended part and the other end of the ninth extended part, and wherein in steps (g) and (h), the ninth to twelfth contact elements and the second conductive element are formed such that the ninth contact element electrically connects the second conductive element and the first extended part, such that the tenth contact element electrically connects the second conductive element and the eighth extended part, such that the eleventh contact element electrically connects the second conductive element and the ninth extended part, and such that the twelfth contact element electrically connects the second conductive element and the second extended part.The method for manufacturing the semiconductor device according to claim 11, wherein in step (h), the gate pad is formed such that the gate pad includes a gate pad wiring and such that the gate pad wiring has a width of at least a first predetermined length in the first direction in plan view, and the gate wiring is formed such that the gate wiring has a width of at least a second predetermined length in the first direction in plan view.The method for manufacturing the semiconductor device according to claim 11, wherein in step (g), a well contact element penetrating the interlayer insulating film and reaching the well region is further formed, wherein in step (h), an emitter electrode is further formed on the interlayer insulating film, and wherein the well contact element electrically connects the emitter electrode and the well region.

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