SCREENBOARD AND DISPLAY DEVICE CONTAINING IT

Abstract

Embodiments disclose a display panel comprising a plurality of pixels and a gate line and a data line connected to the plurality of pixels, wherein each of the plurality of pixels comprises a 1-1 sub-pixel and a 1-2 sub-pixel of a first color, a 2-1 sub-pixel and a 2-2 sub-pixel of a second color, and a 3-1 sub-pixel and a 3-2 sub-pixel of a third color, wherein each of the 2-1 sub-pixel and the 2-2 sub-pixel comprises a light-emitting element and a compensation circuit, and the compensation circuit of the 2-1 sub-pixel and the compensation circuit of the 2-2 sub-pixel are connected to a data line, and a display device including them.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0192978, filed on December 27, 2023. BACKGROUND 1. Field of the invention

[0002] The present disclosure relates to a display panel and a display device incorporating the same. 2. Discussion of the state of the art

[0003] Organic light-emitting displays (OLEDs) display images by emitting light in response to an input image signal from an organic light-emitting diode (OLED) arranged in each pixel. This organic light-emitting display can exhibit fast response time, high luminance, high luminance, and a wide viewing angle. It can display a black gray level as perfect black, thus exhibiting excellent contrast ratio and color gamut. This organic light-emitting display does not require a backlight unit.

[0004] In recent years, microdisplay devices that use light-emitting diodes (LEDs), which are inorganic light-emitting elements manufactured in micro sizes of approximately 100 µm or less, as the light-emitting elements in a pixel, have been gaining attention as next-generation display devices. The LEDs are made of inorganic materials and therefore do not require a separate encapsulation layer to protect organic materials from moisture. They are highly reliable and have a longer lifespan than OLEDs. Furthermore, the LEDs can be switched on and off quickly and exhibit high light-emitting efficiency and impact resistance.

[0005] The problem with these microdisplays is that two LEDs are arranged in parallel within a single subpixel. So if one of the LEDs experiences a short-circuit failure and dims, the other LED will also dim. SUMMARY OF THE INVENTION

[0006] The present disclosure aims to provide a display panel that allows the other light-emitting element to emit light even when one light-emitting element in one of a plurality of sub-pixels is darkened, and a display device incorporating the same.

[0007] The present disclosure also aims to provide a display panel in which a light-emitting element can be repaired and a display device incorporating the same.

[0008] The objects of the present disclosure are not limited to the objects described above, and other objects not described above will be apparent to those skilled in the art from the following description.

[0009] The object is achieved by the features of the independent claims. Preferred embodiments are specified in the dependent claims.

[0010] According to one aspect of the present invention, there is provided a display panel comprising: a plurality of pixels; and gate lines and data lines connected to the pixels, wherein a pixel comprises: a plurality of sub-pixels providing different colors, each sub-pixel comprising a light-emitting element and a compensation circuit, wherein the compensation circuits of at least two of the sub-pixels providing the same color are connected to a data line.

[0011] According to one aspect of the present invention, there is provided a display panel comprising a plurality of pixels and a gate line and a data line connected to the plurality of pixels, wherein each of the plurality of pixels comprises a 1-1 sub-pixel and a 1-2 sub-pixel of a first color, a 2-1 sub-pixel and a 2-2 sub-pixel of a second color, and a 3-1 sub-pixel and a 3-2 sub-pixel of a third color, wherein each of the 2-1 sub-pixels and the 2-2 sub-pixels comprises a light-emitting element and a compensation circuit, and the compensation circuit of the 2-1 sub-pixel and the compensation circuit of the 2-2 sub-pixel are connected to a data line.

[0012] In one or more embodiments, the display panel comprises a plurality of pixels; and gate lines and data lines connected to the plurality of pixels, each pixel comprising: a 1-1 sub-pixel and a 1-2 sub-pixel of a first color; a 2-1 sub-pixel and a 2-2 sub-pixel of a second color; and a 3-1 sub-pixel and a 3-2 sub-pixel of a third color.

[0013] In one or more embodiments, each of the 2-1 sub-pixels and the 2-2 sub-pixels may include a light-emitting element and a compensation circuit.

[0014] In one or more embodiments, the 2-1 sub-pixel compensation circuit and the 2-2 sub-pixel compensation circuit may be connected to a data line.

[0015] In one or more embodiments, the 1-1 sub-pixel may include a first compensation circuit connected to a first data line, and the 1-2 sub-pixel may include a second compensation circuit connected to a second data line.

[0016] In one or more embodiments, the 3-1 sub-pixel and the 3-2 sub-pixel may each include a compensation circuit, and the compensation circuits of the 3-1 sub-pixel and the 3-2 sub-pixel may be connected to a data line.

[0017] In one or more embodiments, the first color may be red, the second color may be green, and the third color may be blue.

[0018] In one or more embodiments, the 2-1 sub-pixel and a 2-2 sub-pixel providing the color green include a light-emitting element and a compensation circuit, and the compensation circuit of the 2-1 sub-pixel and the compensation circuit of the 2-2 sub-pixel are connected to a data line.

[0019] In one or more embodiments, the plurality of pixels may include a first pixel in which both the 2-1 sub-pixel and the 2-2 sub-pixel emit light when a data voltage is applied; and a second pixel in which only one of the 2-1 sub-pixel and the 2-2 sub-pixel emits light when the data voltage is applied.

[0020] In one or more embodiments, a data voltage applied to the 2-1 sub-pixel and the 2-2 sub-pixel of the second pixel may be greater than a data voltage applied to the 2-1 sub-pixel and the 2-2 sub-pixel of the first pixel.

[0021] In one or more embodiments, the plurality of pixels may include a third pixel in which both the 3-1 sub-pixel and the 3-2 sub-pixel emit light when a data voltage is applied; and a fourth pixel in which only one of the 3-1 sub-pixel and the 3-2 sub-pixel emits light when the data voltage is applied.

[0022] In one or more embodiments, a data voltage applied to the 3-1 sub-pixel and the 3-2 sub-pixel of the fourth pixel may be greater than a data voltage applied to the 3-1 sub-pixel and the 3-2 sub-pixel of the third pixel.

[0023] In one or more embodiments, the display panel may include a first gate line to which the 1-1 sub-pixel, the 2-1 sub-pixel, and the 3-1 sub-pixel are connected; and a second gate line to which the 1-2 sub-pixel, the 2-2 sub-pixel, and the 3-2 sub-pixel are connected.

[0024] In one or more embodiments, each sub-pixel may include an anode and a cathode for applying a voltage to the light-emitting element.

[0025] In one or more embodiments, the anodes of the sub-pixels may be separated from each other and the cathodes of the sub-pixels may be separated from each other.

[0026] In one or more embodiments, the compensation circuit of the 2-1 sub-pixel and the compensation circuit of the 2-2 sub-pixel may have the same structure.

[0027] In one or more embodiments, the plurality of pixels may include a plurality of first pixels arranged in a first pixel row and a plurality of second pixels arranged in a second pixel row adjacent to the first pixel row.

[0028] In one or more embodiments, the 2-1 sub-pixel of the first pixel may include a first low-potential power supply line connected to a first cathode of the 2-1 sub-pixel of the first pixel, and the 2-1 sub-pixel of the second pixel may include a second low-potential power supply line connected to a second cathode of the 2-1 sub-pixel of the second pixel.

[0029] In one or more embodiments, the first low-potential power supply line may extend toward the second cathode.

[0030] In one or more embodiments, the second low-potential power supply line may extend toward the first cathode.

[0031] In one or more embodiments, the first low-potential power supply line and the second low-potential power supply line may be electrically connected to each other.

[0032] In one or more embodiments, the first low-potential power supply line of the 2-1 sub-pixel of the second pixel may be electrically connected to the compensation circuit of the 2-1 sub-pixel of the first pixel.

[0033] In one or more embodiments, the first compensation circuit of the 1-1 sub-pixel may be connected between the first data line and a first low-potential power supply line.

[0034] In one or more embodiments, the second compensation circuit of the 1-2 sub-pixel may be connected between the second data line and a second low-potential power supply line.

[0035] In a further aspect, a display device is provided which comprises a display panel as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other objects, features and advantages of the present invention will become more apparent to those skilled in the art when exemplary embodiments thereof are described in detail with reference to the accompanying drawings, in which: Fig. 1 is a block diagram schematically showing a configuration of a display device according to an embodiment of the present disclosure; Fig. 2 is a partial cross-sectional view showing a pad electrode and a side line arranged at an outer edge of a display panel according to an embodiment of the present disclosure; Fig. 3 is a perspective view showing a tiled display device according to an embodiment of the present disclosure; Fig. 4 is a plan view showing a plane structure of the display panel according to an embodiment of the present disclosure; Fig. 5 is a cross-sectional view showing a cross-sectional structure of the display panel according to an embodiment of the present disclosure; Fig. 6 is a diagram showing a pixel structure of an embodiment of the present disclosure; Fig. 7 is a diagram showing a red subpixel of an embodiment of the present disclosure; Fig. 8 is a diagram showing a green subpixel of an embodiment of the present disclosure; Fig. 9 is a diagram showing a blue subpixel of an embodiment of the present disclosure; Fig. 10 is a diagram showing cathodes of the red, green and blue subpixels; Fig. 11 is a circuit diagram schematically illustrating a pixel circuit according to an embodiment of the present disclosure; Fig. 12 is a circuit diagram showing a pixel circuit of another embodiment of the disclosure; Fig. 13 is a waveform diagram of the pixel circuit of another embodiment of the disclosure; Fig. 14 is a diagram showing a pixel with parallel-connected subpixels; Fig. 15 a representation showing the subpixel of Fig. 14 shows; and Fig. 16 and Fig. 17 are diagrams showing a repair method in a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0037] Advantages and features of the invention disclosed in the present description, as well as methods for achieving them, will become more clearly understood from the embodiments described below with reference to the accompanying drawings. The present invention is not limited to the following embodiments, but may be implemented in various forms. The embodiments are only intended to complete the present invention and to fully convey the category of the present invention to those skilled in the art to which the present invention belongs, and the present invention is defined by the appended claims.

[0038] In describing the present invention, detailed descriptions of known technologies are omitted if it is determined that they may unnecessarily obscure the essence of the present invention.

[0039] Terms such as "comprising," "comprising," and "consisting of," as used herein, are intended to allow for the addition of other elements, unless the terms are used with the term "only." When a component is expressed in the singular form, it may be construed as a plural form unless expressly stated otherwise.

[0040] When the positional or connecting relationship between two components is described with terms such as "on", "over", "under", "beside", "connecting or coupling", "crossing or intersecting" and the like, one or more other components may be inserted between the two components, provided that the terms are not used with the term "immediate" or "direct".

[0041] When the temporal sequence relationship is described with terms such as "after", "subsequent", "next", "before" and the like, a case that is not continuous may be included unless the term "immediate" or "direct" is used.

[0042] Although ordinal numbers such as first, second, and the like are used to distinguish between components, the functions or structures of these components are not limited by the ordinal numbers before the component or the component name.

[0043] The following embodiments may be partially or fully coupled or combined with one another and may interact and be implemented in technically diverse ways. Each of the embodiments may operate independently of one another and may be implemented together in relation to one another.

[0044] In the embodiment of the present disclosure, pixels and a display panel drive circuit include transistors. The transistors are three-electrode elements including a gate, a source, and a drain. The source is an electrode that supplies charge carriers to the transistor. The charge carriers in the transistor start flowing from the source. The drain is an electrode through which the charge carriers are discharged from the transistor to the outside. In the transistor, the charge carriers flow from the source to the drain. In the case of an n-channel transistor, charge carriers are electrons, and therefore, a source voltage is lower than a drain voltage, so that the electrons flow from the source to the drain. In the n-channel transistor, current flows from the drain to the source. In the case of a p-channel transistor, charge carriers are holes, and therefore, a source voltage is higher than a drain voltage, so that the holes flow from the source to the drain.Since holes flow from the source to the drain in a p-channel transistor, current flows from the source to the drain. Note that the source and drain of the transistor are not fixed in position. For example, the source and drain are interchangeable depending on the applied voltage. Accordingly, the present disclosure is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor are referred to as the first electrode and the second electrode.

[0045] A gate signal can fluctuate between a gate on voltage and a gate off voltage. The transistor is turned on in response to the gate on voltage and turned off in response to the gate off voltage. In the case of an n-channel transistor, the gate on voltage can be a gate high voltage VGH, and the gate off voltage can be a gate low voltage VGL. In the case of a p-channel transistor, the gate on voltage can be the gate low voltage VGL, and the gate off voltage can be the gate high voltage VGH.

[0046] The term “line” mentioned in the embodiments of the present document can be interpreted as wiring to which a signal or voltage is applied.

[0047] The terms used in the embodiments of the present disclosure (including technical and scientific terms) may be interpreted to have meanings commonly understood by those skilled in the art unless specifically defined and described, and commonly used terms, such as terms defined in a dictionary, may be understood taking into account their contextual meanings in the art.

[0048] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0049] With reference to Fig. 1, a display device 100 comprises a display panel PN having a display area AA in which a plurality of pixels are arranged. The display device 100 may further comprise a display panel drive circuit configured to drive the pixels. The drive circuit may be arranged in an area outside the display area.

[0050] The display panel PN may be a rectangular structure panel having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction, but the disclosure is not limited thereto. Each of the pixels includes a plurality of sub-pixels SP with different colors. The display area AA on which an input image is displayed in the display panel PN may be a screen viewable from the front side of the display panel PN.

[0051] The display panel drive circuit may include a data driver DD, a gate driver GD, and a timing controller TC configured to control the gate driver GD and the data driver DD.

[0052] An input image is displayed by the subpixels SP arranged in the display area AA of the display panel PN. Each of the subpixels SP includes a light-emitting element and a pixel circuit configured to drive the light-emitting element. The light-emitting element can be a light-emitting diode (LED) or a micro-LED.

[0053] On the display panel PN, several gate lines SL and several data lines DL are arranged so that they cross each other. Each of the subpixels SP is connected to a gate line SL and a data line DL. Fig. 1 omitted power supply lines may be connected to each of the sub-pixels SP. In the display panel PN, a non-display area NA may be arranged outside the display area AA.

[0054] The gate driver GD supplies a gate signal to the gate lines SL in response to a gate control signal supplied from the timing controller TC. The gate driver GD may be arranged at least in the non-display area NA of the display panel PN, as shown in Fig. 1, or may be arranged in the display area AA.

[0055] The data driver DD converts image data received from the timing controller TC into a gamma compensation voltage in response to a data control signal supplied from the timing controller TC to output a data voltage. The data voltage output from the data driver DD is supplied to the data lines DL.

[0056] The timing controller TC aligns externally input image data and supplies the image data to the data driver DD. The timing controller TC can generate the gate control signal and the data control signal based on timing signals synchronized with the input image signal, such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal. The timing controller TC supplies the gate control signal and the data control signal to the gate driver GD and the data driver DD, respectively, to control the operating timings of the gate driver GD and the data driver DD.

[0057] Connecting lines and pad electrodes for transmitting signals to the sub-pixels SP of the display area AA may be arranged in the non-display area NA. One or more gate driver ICs incorporating circuits of the gate driver GD and a data driver IC incorporating circuits of the data driver DD may be arranged in the non-display area NA. The non-display area NA may include a rear surface of the display panel PN, i.e., the rear surface on which no sub-pixels SP are present. The non-display area NA may be minimized to such an extent that the non-display area NA is not visible when an image is displayed on the display panel PN.

[0058] The display panel drive circuit may be connected to the display panel PN in various ways to drive the pixels. For example, the gate driver GD may be disposed in the non-display area NA by a gate-in-panel (GIP) method or disposed between the plurality of sub-pixels SP in the display area AA by a gate-in-display area (GIA) method. The data driver DD and the timing controller TC may be formed on a separate flexible film and a printed circuit board (PCB) and may be electrically connected to the display panel PN by connecting terminals of the flexible film to pad electrodes formed in the non-display area NA of the display panel PN. The flexible film connected to the display panel PN may be connected to the PCB on which circuit elements are mounted and leads are formed.

[0059] One or more side lines for connecting one or more signal lines on a front surface of the display panel PN to one or more pad electrodes on the rear surface of the display panel PN may be formed on an outer peripheral side surface of the display panel PN. The method of electrically connecting the front and rear surfaces of the display panel PN through the side line can minimize the non-display area NA as viewed from the front surface of the display panel PN. Fig. 2, “SRL” represents the side line. When the gate driver GD, the data driver DD, and the timing controller TC are electrically connected to the display panel PN by the method described above, a substantially bezel-less screen can be implemented on the display panel PN.

[0060] With reference to Fig. 2, a plurality of pad electrodes for transmitting various signals to the sub-pixels SP are arranged in the non-display region NA of the display panel PN. For example, a first pad electrode PAD1 configured to transmit signals to the sub-pixels SP may be arranged in the non-display region NA located on the front surface of the display panel PN. A second pad electrode PAD2 electrically connected to circuit elements such as the flexible film and the PCB is arranged in the non-display region NA located on the rear surface of the display panel PN. The non-display region NA, which is located at an outer edge of the front surface of the display panel PN and on which an image is displayed, can be minimized in size by disposing only one pad region in which the first pad electrode PAD1 is arranged.

[0061] Various signal lines connected to the sub-pixels SP, such as the gate line SL or the data line DL, may extend to the non-display region NA to be electrically connected to the first pad electrode PAD1. Here, the first pad electrode PAD1 may include a plurality of pads.

[0062] The display panel PN may include a side line SRL disposed on the outer peripheral side surface of the display panel PN. The side line SRL may electrically connect the first pad electrode PAD1 disposed on the outer periphery of the front surface of the display panel PN to the second pad electrode PAD2 disposed on the outer periphery of the rear surface of the display panel PN across the side surface of the display panel PN. Signals output from the circuit elements disposed on the rear surface of the display panel PN may be transmitted to the sub-pixels SP in the display area AA and the gate driver GD via the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1.Accordingly, an area of the non-display region NA on the front surface of the display panel PN can be minimized by forming one or more signal transmission paths crossing the outer peripheries of the front, side, and rear surfaces of the display panel PN.

[0063] Multiple display modules may be combined on a single plane to form a large-screen tile display device. Each of the display modules may be implemented as a single display device, and the combination of the multiple display modules may be implemented as a large-screen tile display device. Each of the display modules includes a display panel PN, a display panel PN drive circuit, and circuit elements and module cover elements coupled to the rear surface of the display panel PN.

[0064] With reference to Fig. 3, a large-screen tile display device TD includes a plurality of display modules arranged on an XY plane. Each of the display modules includes the display panel PN that displays an input image. When the non-display area NA at the outer edge of the front surface of each of the display panels PN is minimized, a large-screen image can be displayed without a visible seam between the adjacent display panels PN.

[0065] The display panels PN may be assembled on a plane such that a distance D1 between an outermost pixel PX of one display panel PN and an outermost pixel PX of another display panel PN adjacent to the one display panel PN is substantially equal to a distance D2 between the adjacent pixels PX in the display area AA of the display panel PN. As a result, the distances D1 and D2 between the adjacent pixels PX are the same in all large-screen display areas of the tile display device TD, thereby ensuring that a seam area is not visually discernible.

[0066] In the tile display device TD, the multiple display modules may share a timing controller TC. A host system may be connected to multiple timing controllers TC to transmit a video signal to be displayed on all display panels PN implementing the large-screen display device TD to the timing controllers TC and synchronize the timing controllers TC.

[0067] Fig. 4 is a plan view schematically showing a plane structure of the display panel according to an embodiment of the present disclosure.

[0068] With reference to Fig. 4, the display panel PN includes a substrate SUBS on which a pixel array and the circuits of the gate driver GD are arranged. The display panel PN may be a panel having a rectangular structure with a length in a row direction (an X-axis direction), a width in a column direction (a Y-axis direction), and a thickness in a thickness direction (a Z-axis direction), but the present disclosure is not limited thereto.

[0069] The substrate SUBS may be an insulating substrate that supports components arranged on an upper portion of the display device. The substrate SUBS may have a structure in which multiple substrates are stacked. The substrate SUBS may be made of a glass, polymer resin, or plastic substrate.

[0070] On one surface (or a front surface) of the substrate SUBS, the display area AA may include a plurality of pixel areas UPA, a plurality of gate drive areas GA, and a plurality of pad areas PA1 and PA2. One or more pixels PX may be arranged in each of the pixel areas UPA. The pixel areas UPA may be arranged along a plurality of row rows and a plurality of column rows. Each of the pixels PX includes a plurality of sub-pixels SP of different colors. Each of the sub-pixels SP includes a light-emitting element and a pixel circuit, and thus can independently emit light. The sub-pixels SP may include a red sub-pixel, a blue sub-pixel, a green sub-pixel, and the like, but the present disclosure is not limited thereto. Therefore, a white sub-pixel may also be provided.

[0071] The plurality of gate drive regions GA include the circuits of the gate driver GD. The gate drive region GA may be formed between the plurality of pixel regions UPA in the row direction and / or column direction. The gate driver GD formed in the gate drive region GA may supply a gate signal to the plurality of gate lines SL. The gate drive region GA may be arranged between the adjacent pixel regions UPD in the row direction (the X-axis direction).

[0072] A first pad region PA1 includes a plurality of first pad electrodes PAD1 arranged at an outer edge of the front surface of one side (or a top) of the display panel PN. The first pad electrodes PAD1 can transmit various signals to various lines extending in the column direction in the display region AA. The first pad electrodes PAD1 include data pads DP connected to the data lines DL for transmitting the data voltage output from the data driver DD to the data lines DL, and gate pads GP connected to the gate driver GD for transmitting a clock signal, a start signal, a gate low voltage, a gate high voltage, and the like to the gate driver GD to drive the gate driver GD.The clock signal, start signal, gate low voltage, gate high voltage, and the like for driving the gate driver GD can be generated by the timing controller TC and applied to the gate pads GP via a level shifter and the PCB. The first pad electrodes PAD1 can include a plurality of power supply lines to which a direct current (DC) voltage (or constant voltage) is applied.

[0073] The substrate SUBS of the display panel PN includes gate drive lines connected to the gate pads GP in the column direction and a plurality of gate drive lines GVL extending in the row direction. The gate drive lines in the column direction may be connected to the gate drive lines GVL in the row direction via contact holes extending through an insulating film. The gate drive lines GVL transmit signals required to drive the gate driver GD distributed in the gate drive regions GA, such as the clock signal, the start signal, the gate high voltage, the gate low voltage, and the like, to the gate driver GD circuits.

[0074] A second pad region PA2 includes a plurality of second pad electrodes PAD2 arranged at an outer edge of the front surface of the other side (or a bottom side) of the display panel PN. The second pad region PA2 may include a plurality of low-voltage power pads VP2.

[0075] A DC voltage applied to the power supply lines may be output by a power circuit (omitted from the drawing) and applied to power pads VP1 and VP2 connected to the power supply lines via the PB. The power circuit may be a DC-DC converter arranged on the PCB or control boards CTB1 and CTB2 on the rear surface of the display panel PN, which converts an input DC voltage output from a main power supply into a DC voltage suitable for driving the display panel PN.

[0076] The power pads VP1 and VP2 connected to the power supply lines may include a plurality of high-potential power pads VP1 arranged on the first pad region PA1 to transmit a high-potential power voltage to a high-potential power supply line VL1, and the plurality of low-potential power pads VP2 arranged on the second pad region PA2 to transmit a low-potential power voltage to a low-potential power supply line VL2.

[0077] The data pads DP, which are connected one-to-one to the data lines DL, may each have a relatively narrow width, and the power pads VP1 and VP2 and the gate pads GP may each have a relatively large width. The low-potential power pads VP2 may each have a larger width than each of the high-potential power pads VP1.

[0078] To minimize the outermost non-display area NA of the display panel PN, the pixel array, wiring, and pads are formed on the front surface of the substrate of the display panel PN, and then the outermost portion beyond a scribe line SCL indicated by a dotted line is removed, so that a substrate SUBS with a minimized non-display area NA can be manufactured. After the scribe process, rough edges on an outer edge of the substrate SUBS can be ground or laser trimmed. Short pad electrodes PAD1 and PAD2 remain at the outer edge of the front surface of the substrate SUBS, whose size has been reduced accordingly.

[0079] The data lines DL may extend in the column direction (Y direction) on the substrate SUBS and overlap the pixel region UPA. The data lines DL supply the data voltage to the pixel circuit of each of the sub-pixels SP. The gate lines SL may extend in the row direction (X direction) on the substrate SUBS of the display panel PN and overlap the pixel region UPA and the gate drive region GA. The gate lines SL may cross the pixel regions UPA and the gate drive regions GA and supply the gate signal output from the gate driver GD to the pixel circuit of each of the sub-pixels SP.

[0080] High-potential power supply lines VL1 extend in the column direction (Y direction), and one or more of them are connected in a mesh structure to auxiliary high-potential power supply lines AVL1 extending in the row direction (X direction). The auxiliary high-potential power supply lines AVL1 are connected to the sub-pixels SP arranged in the row direction (X direction). Accordingly, the high-potential power voltage applied to the high-potential power supply lines VL1 can be transmitted to the sub-pixels SP via the auxiliary high-potential power supply lines AVL1.

[0081] Low-potential power supply lines VL2 extend in the column direction (Y direction), and one or more of them are connected in a mesh structure to auxiliary low-potential power supply lines AVL2 extending in the row direction (X direction). The auxiliary low-potential power supply lines AVL2 are connected to the sub-pixels SP arranged in the row direction (X direction). Accordingly, the sub-pixels SP are connected to the auxiliary low-potential power supply lines AVL2, to which the low-potential power voltage is applied.

[0082] Due to the mesh structure of the power supply lines, a resistance of the power supply line can be reduced, which can reduce a voltage drop across the high-potential power voltage and fluctuations of the power voltage within the display range AA.

[0083] The substrate SUBS of the display panel PN may include one or more alignment keys AK1 and AK2 arranged between the pixel regions UPA. The alignment keys AK1 and AK2 may be used for alignment during the manufacturing process of the display panel PN. A first alignment key AK1 may be arranged in the gate drive region GA. The first alignment key AK1 may be used to check an alignment position of each of the light-emitting elements. The first alignment key AK1 may be formed in a cross pattern, but the present disclosure is not limited thereto. A second alignment key AK2 may overlap the high-potential power supply line HL.The high-potential power supply line HL can be distinguished from the second alignment key AK2 by having a hole formed at a position overlapping the second alignment key AK2. The second alignment key AK2 can be used to align the display panel PN with a donor substrate. The donor substrate is an intermediate medium for attaching light-emitting elements to the substrate SUBS of the display panel PN. A plurality of light-emitting elements fabricated on a semiconductor wafer can be attached to and transferred to the donor substrate, and the light-emitting elements attached to the donor substrate can be transferred to the substrate SUBS. The second alignment key AK2 can be formed in a circular or annular pattern, but the present disclosure is not limited thereto.

[0084] Fig. 5 is a cross-sectional view showing a cross-sectional structure of the display panel according to an embodiment of the present invention.

[0085] With reference to Fig. 5, a pixel circuit for driving a light-emitting element ED is arranged in each of the plurality of sub-pixels SP on the first substrate SUBS1. The pixel circuit may include a plurality of thin-film transistors and one or more capacitors. For simplicity, a driving element DT, a first capacitor C1, and a second capacitor C2 used in the pixel circuit will be described, but the display panel PN may further include other circuit elements.

[0086] A pattern of a first metal layer may be disposed on the first substrate SUBS1. The pattern of the first metal layer may include a light-blocking layer BSM. The light-blocking layer BSM may minimize leakage current by blocking light incident on an active layer ACT of the driving element DT. The light-blocking layer BSM may be formed of an opaque conductive material, such as a metal such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), an alloy of these metals, or a multilayer metal layer.

[0087] A buffer layer BUF can be disposed on the light-blocking layer BSM. The buffer layer BUF can block the penetration of moisture or contaminants through the first substrate SUBS1. The buffer layer BUF can be formed from silicon oxide (SiOx), silicon nitride (SiNx), or multilayer insulating layers.

[0088] The drive element DT, which comprises the active layer ACT, a gate electrode GE, a source electrode SE and a drain electrode DE, can be arranged on the buffer layer BUF.

[0089] The active layer ACT may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but the present invention is not limited thereto. A gate insulating layer GI electrically insulates the active layer ACT from the gate electrode GE of the drive element DT. The gate insulating layer GI may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or multilayer insulating layers.

[0090] A pattern of a second metal layer may be disposed on the gate insulating layer GI. The pattern of the second metal layer may include the gate electrode GE of the drive element DT. The second metal layer may be formed from copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or multilayer metal layers.

[0091] A first interlayer insulating layer IID1 and a second interlayer insulating layer IID2 are disposed on the gate electrode GE. Contact holes for the source electrode SE and drain electrode DE of the drive element DT, respectively, are formed in the first interlayer insulating layer IID1 and the second interlayer insulating layer IID2 to establish a connection with the active layer ACT. Each of the first interlayer insulating layer IID1 and the second interlayer insulating layer IID2 can be formed from silicon oxide (SiOx), silicon nitride (SiNx), or multilayer insulating layers.

[0092] A pattern of a third metal layer may be disposed on the second interlayer insulating layer IID2. The pattern of the third metal layer may include the source electrode SE and the drain electrode DE, which overlap the active layer ACT and are connected to the active layer ACT through the contact holes extending through the interlayer insulating layers IID1 and IID2. The source electrode SE may be connected to the capacitors C1 and C2 and a first electrode E1 of the light-emitting element ED. The third metal layer may be formed of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or multilayer metal layers.

[0093] The first capacitor C1 includes a first capacitor electrode C1a and a second capacitor electrode C1b. The first capacitor electrode C1a may be formed as a pattern of the second metal layer disposed on the gate insulating layer GI. The second capacitor electrode C1b is formed as a pattern of a fourth metal layer disposed on the first interlayer insulating layer IID1 and overlaps the first capacitor electrode C1a with the first interlayer insulating layer IID1 interposed therebetween. The second capacitor electrode C1b may be connected to the source electrode SE of the drive element DT. The fourth metal layer may be formed of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or multilayer metal layers.

[0094] The second capacitor C2 includes a third capacitor electrode C2a overlapping the first capacitor electrode C1a, with the buffer layer BUF and the gate insulating layer GI interposed therebetween. The third capacitor electrode C2a may be formed as a pattern of the first metal layer disposed on the first substrate SUBS1.

[0095] The second capacitor C2 is electrically connected between the source electrode SE of the driving element DT and the light-emitting element ED to increase a capacitance of the light-emitting element ED, which can increase the brightness when the light-emitting element ED emits light.

[0096] A first passivation layer PAS1 covers the pattern of the third metal layer and the second interlayer insulating layer ILD2 to overlay the pattern of the third metal layer. The first passivation layer PAS1 can be formed of silicon oxide (SiOx), silicon nitride (SiNx), or multilayer insulating layers.

[0097] A first planarization layer PLN1 is disposed on the first passivation layer PAS1. The first planarization layer PLN1 covers the first passivation layer PAS1 to planarize the surface on which the light-emitting element is disposed. The first planarization layer PLN1 can be a thick, single-layer or multi-layer organic insulating layer made of benzocyclobutene or acrylic-based organic material.

[0098] A pattern of a fifth metal layer may be disposed on the first planarization layer PLN1. The pattern of the fifth metal layer may include a reflective layer RF. The reflective layer RF reflects light from the light-emitting element ED toward the front surface of the display panel PN to increase light efficiency and may be used as an electrode to connect the light-emitting element ED to the pixel circuit or power supply line. The reflective layer RF may be electrically connected to the source electrode SE of the drive element DT and the first capacitor C1 via a contact hole CH1 passing through the first planarization layer PLN1 and the first passivation layer PAS1.Furthermore, the reflective layer RF may be electrically connected to the first electrode E1 of the light-emitting element ED via an anode AND, or electrically connect a second electrode E2 of the light-emitting element ED to an auxiliary high-potential power supply line HL. The fifth metal layer may be formed of silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), a transparent electrode material such as indium tin oxide (ITO), or multilayer metal layers.

[0099] A second passivation layer PAS2 covers the pattern of the fifth metal layer and the first planarization layer PLN1. The second passivation layer PAS2 can be formed from silicon oxide (SiOx), silicon nitride (SiNx), or multilayer insulating layers.

[0100] An adhesive layer AD may be disposed on the second passivation layer PAS2 to fix the light-emitting element ED. The adhesive layer AD may be formed of a photocurable resin that can be cured by light. The adhesive layer AD may be formed of an acrylic-based material containing a photosensitive agent, but the present invention is not limited thereto. The adhesive layer AD may be formed on the entire surface of the first substrate SUBS1 except for the pad regions PA1 and PA2 where the first pad electrode PAD1 is to be disposed.

[0101] The light-emitting element ED of each of the sub-pixels SP can be arranged on the adhesive layer AD. Each of the light-emitting elements ED can emit light using a current from the driving element DT. The light-emitting elements ED can include a red light-emitting element ED, a green light-emitting element ED, and a blue light-emitting element ED. The light-emitting element ED can be an LED or a micro-LED.

[0102] Each of the light-emitting elements ED comprises a first semiconductor pattern SEM1, a light-emitting layer EM, a second semiconductor pattern SEM2, the first electrode E1 and the second electrode E2.

[0103] The first semiconductor pattern SEM1 is disposed on the adhesion layer AD, and the second semiconductor pattern SEM2 is disposed on the first semiconductor pattern SEM1. The first semiconductor pattern SEM1 and the second semiconductor pattern SEM2 may be semiconductor patterns obtained by doping a semiconductor material with n-type and p-type impurities. For example, the first semiconductor pattern SEM1 and the second semiconductor pattern SEM2 may each be a layer formed by doping materials such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), and the like with n-type or p-type impurities. Furthermore, the p-type impurities may be magnesium, zinc (Zn), beryllium (Be), or the like, and the n-type impurities may be silicon (Si), germanium, tin (Sn), or the like, but the present invention is not limited thereto.

[0104] The light-emitting layer EM is arranged between the first semiconductor pattern SEM1 and the second semiconductor pattern SEM2. The light-emitting layer EM can emit light by receiving holes and electrons from the first semiconductor pattern SEM1 and the second semiconductor pattern SEM2. The light-emitting layer EM can be formed as a single layer or as a multiple quantum well (MQW) structure and can be formed, for example, from indium gallium nitride (InGaN), gallium nitride (GaN), or the like.

[0105] The first electrode E1 is disposed on the first semiconductor pattern SEM1. The first electrode E1 electrically connects the drive element DT and the first semiconductor pattern SEM1. The first semiconductor pattern SEM1 may be formed of a semiconductor layer doped with n-type impurities. The first electrode E1 may be an anode of the light-emitting element ED, which is disposed on the first semiconductor pattern SEM1 and electrically connected to the drive element DT and the capacitors C1 and C2 via the reflective layer RF. The first electrode E1 may be disposed on an upper surface of a first semiconductor layer SEM1. The first electrode E1 may be formed of a conductive material such as a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof.

[0106] The second electrode E2 is arranged on the second semiconductor pattern SEM2. The second electrode E2 electrically connects the high-potential power supply line HL and a second semiconductor layer SEM2. The second semiconductor layer SEM2 may be formed as a semiconductor layer doped with p-type impurities. The second electrode E2 may be a cathode CAT of the light-emitting element ED. The second electrode E2 may be formed of a conductive material such as a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof.

[0107] The light-emitting element ED may include an encapsulation layer ENS. The encapsulation layer ENS covers the semiconductor patterns SEM1 and SEM2 and the electrodes E1 and E2 to protect the light-emitting element ED. The encapsulation layer ENS and a third planarization layer PLN3 have contact holes exposing the first electrode E1 and the second electrode E2. The anode AND is connected to the reflective layer RF through a first contact hole passing through the encapsulation layer ENS and the third planarization layer PLN3. The cathode CAT is connected to the second electrode E2 through a second contact hole passing through the encapsulation layer ENS and the third planarization layer PLN3. Meanwhile, a portion of a side surface of the first semiconductor pattern SEM1 may be exposed because the encapsulation layer ENS is not present thereon.

[0108] A second planarization layer PLN2 and the third planarization layer PLN3 may cover the adhesive layer AD and the light-emitting element ED. The second planarization layer PLN2 contacts a lower end of a side surface of the light-emitting element ED and fixes the light-emitting element ED. The third planarization layer PLN3 covers the light-emitting element ED on the second planarization layer PLN2. The third planarization layer PLN3 has contact holes exposing the first electrode E1 and the second electrode E2 of the light-emitting element ED. The second planarization layer PLN2 and the third planarization layer PLN3 may be formed from a single or multiple layers of an organic insulating material, for example, photoresist or an organic acrylic-based material.

[0109] A pattern of a sixth metal layer may be disposed on the third planarization layer PLN3. The sixth metal layer may include the anode AND and the cathode CAT. The anode AND electrically connects the first electrode E1 of the light-emitting element ED and the reflective layer RF. The anode AND may be connected to the first electrode E1 of the light-emitting element ED through the contact holes extending through the insulating layers PLN3 and ENS, and may be connected to the reflective layer RF through contact holes extending through the insulating layers PAS2, AD, PLN2, and PLN3.

[0110] The cathode CAT is connected to the second electrode E2 of the light-emitting element ED via contact holes extending through the insulating layers PLN3 and ENS. The cathode CAT can be connected to a low-potential power supply line CL.

[0111] According to the embodiment, the light-emitting element ED is illustrated with a horizontal structure in which the electrodes are connected to the upper surfaces of the first semiconductor pattern SEM1 and the second semiconductor pattern SEM2, but the present invention is not necessarily limited to this. For example, the light-emitting element ED may have a vertical structure in which the anode AND is arranged below the first semiconductor pattern SEM1.

[0112] A bank pattern BB may be disposed on the second planarization layer PLN2. The bank pattern BB may be spaced a certain distance from the light-emitting element ED. The bank pattern BB may cover a portion of the anode AND present in the contact hole passing through the insulating layers PLN2 and PLN3. The bank pattern BB may prevent optical crosstalk between the sub-pixels SP to reduce color mixing between the sub-pixels SP. For this purpose, the bank pattern BB may be formed of a black resin, but the present invention is not limited thereto.

[0113] A first protective layer CPA may cover the sixth metal layer, the bank pattern BB, the second planarization layer PLN2, and the third planarization layer PLN3. The first protective layer CPA may be formed from a single layer of transparent epoxy, silicon oxide (SiOx), or silicon nitride (SiNx), a multilayer insulating layer, or the like.

[0114] Each of the first pad electrodes PAD1 arranged in the pad regions PA1 and PA2 of the first substrate SUBS1 may have a multilayer metal layer structure. For example, each of the first pad electrodes PAD1 may include a first pad metal layer PE1a, a second pad metal layer PE1b, and a third pad metal layer PE1c stacked on the outermost edge of a front surface of the first substrate SUBS1.

[0115] The pattern of the third metal layer disposed on the second interlayer insulating layer IID2 may further include the first pad metal layer PE1a. The first pad metal layer PE1a may be formed of the same metal as the source electrode SE and the drain electrode DE of the drive element DT, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or multilayer metal layers.

[0116] The pattern of the fifth metal layer disposed on the first planarization layer PLN1 may further include the second pad metal layer PE1b. The second pad metal layer PE1b may be formed of the same metal as the reflective layer RF, such as silver (Ag), aluminum (Al), molybdenum (Mo), or multilayer metal layers.

[0117] The sixth metal layer pattern disposed on the third planarization layer PLN3 may further include the third pad metal layer PE1c. The third pad metal layer PE1c may be formed of the same conductive material as the anode AND and the cathode CAT, such as a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a multilayer metal layer.

[0118] A first metal layer ML1, a second metal layer ML2, and a plurality of insulating layers may be disposed under the first pad electrodes PAD1. By disposing the first and second metal layers ML1 and ML2 and the plurality of insulating layers under the first pad electrode PAD1, a step difference of the first pad electrode PAD1 can be adjusted. For example, the buffer layer BUF, the gate insulating layer GI, the first metal layer ML1, the first interlayer insulating layer ILD1, and the second metal layer ML2 may be sequentially disposed between the first pad electrode PAD1 and the first substrate SUBS1. The pattern of the second metal layer disposed on the gate insulating layer GI may include the first metal layer ML1. The pattern of the fourth metal layer disposed on the first interlayer insulating layer ILD1 may include the second metal layer ML2.The multiple insulating layers and the metal layers ML1 and ML2 under the first pad electrodes PAD1 are not limited to the layers shown in . Fig. 5 shown.

[0119] A second substrate SUBS2 may be disposed on a rear surface of the first substrate SUBS1. A bonding layer BDL is disposed between the first substrate SUBS1 and the second substrate SUBS2. The bonding layer BDL is cured by various curing methods to bond the first substrate SUBS1 and the second substrate SUBS2. The bonding layer BDL may be disposed only in a partial area or in the entire area between the first substrate SUBS1 and the second substrate SUBS2. The first substrate SUBS1 and the second substrate SUBS2 may be scribed and ground simultaneously, so that side surfaces of the first substrate SUBS1 and the second substrate SUBS2 can be formed without steps.

[0120] A plurality of second pad electrodes PAD2 may be arranged at the outermost edge of a rear surface of the second substrate SUBS2. The second pad electrodes PAD2 are electrically connected to side lines SRL and the first pad electrode PAD1 to transmit signals from circuit elements arranged on the rear surface of the second substrate SUBS2 to the sub-pixels SP arranged on an upper surface of the first substrate SUBS1.

[0121] Each of the second pad electrodes PAD2 may have a multilayer metal layer structure. For example, each of the second pad electrodes PAD2 may include a first pad metal layer PE2a, a second pad metal layer PE2b, and a third pad metal layer PE2c stacked at the outermost edge of the rear surface of the second substrate SUBS2. Each of the first and second pad metal layers PE2a and PE2b may be formed of copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or a multilayer metal layer. The third pad metal layer PE2c may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0122] A second protective layer BCL may be disposed on the rear surface of the second substrate SUBS2. The second protective layer BCL may cover various lines except for the second pad electrodes PAD2 on the rear surface of the second substrate SUBS2. The second protective layer BCL may be made of an organic insulating material such as benzocyclobutene or an acrylic-based organic insulating material.

[0123] Circuit elements such as a plurality of flexible films, a PCB, and the like may be disposed on a rear surface of the second substrate SUBS2. Output terminals of the flexible film are electrically connected to the second pad electrode PAD2, and input terminals of the flexible film are electrically connected to output terminals of the PCB. Thus, signals or voltages output from the PCB can be transmitted to the sub-pixel SP disposed on the front surface of the first substrate SUBS1 via the flexible film, the second pad electrode PAD2, the side line SRL, the plurality of first pad electrodes PAD1, and lines connected to the first pad electrode PAD1.

[0124] The side lines SRL cross the side surfaces of the first substrate SUBS1 and the second substrate SUBS2 and electrically connect the first pad electrodes PAD1 and the second pad electrodes PAD2. The side lines SRL can be formed on the side surfaces of the first substrate SUBS1 and the second substrate SUBS2 by a pad printing method using conductive ink containing silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), or the like.

[0125] A side insulating layer SDI may cover the side lines SRL formed on the outermost edges of the top, side, and rear surfaces of the first substrate SUBS1 and the second substrate SUBS2, which are connected to each other. When the side lines SRL are made of metal, external light may be reflected by the side lines SRL, or light emitted from the light-emitting element ED may be reflected by the side lines SRL and visually recognized by a user. To improve the deterioration of image quality caused by such reflected light, the side insulating layer SDI may contain a black material that absorbs external light. For example, the side insulating layer SDI may be formed on the outermost edges of the first substrate SUBS1 and the second substrate SUBS2 using black ink that can be applied by printing.

[0126] A sealing layer SS may cover the side insulating layer SDI to protect the display panel PN from external shocks, moisture, oxygen, and the like. For example, the sealing layer SS may be made of black ink, polyimide (PI), polyurethane (PU), epoxy, an acrylic-based insulating material, and the like. The sealing layer SS may be a concept that includes the side insulating layer SDI. That is, the sealing layer SS and the side insulating layer SDI may be formed as one layer.

[0127] A cover film MF may cover the front surface of the display panel PN. The cover film MF may include one or more various functional films such as an anti-scattering film, an anti-glare film, an anti-reflective film, a low-reflective film, a controllable transmittance film for organic light-emitting diodes (OLEDs), a color difference compensation film, a polarizing plate, and the like. The anti-scattering film prevents substrate fragments or particles from scattering when the display panel PN breaks. By extensively adhering the sealing layer SS to the front surface of the first substrate SUBS1 and then cutting along a cutting line overlapping the sealing layer SS, the cover film MF can be cut and removed together with the outer portion of the sealing layer SS.As a result, the exposed outermost side surfaces of the cover film MF and the sealing layer SS can form the same plane without step.

[0128] Fig. 6 is a diagram showing a pixel according to an embodiment of the present disclosure. Fig. 7 is a diagram showing a red subpixel according to an embodiment of the present disclosure. Fig. 8 is a diagram showing a green subpixel according to an embodiment of the present disclosure. Fig. 9 is a diagram showing a blue subpixel according to an embodiment of the present disclosure. Fig. 10 is a diagram showing cathodes of the red sub-pixel, the green sub-pixel, and the blue sub-pixel.

[0129] With reference to Fig. 6, the pixel may include six sub-pixels. For example, the pixel may include two red sub-pixels R1 and R2, two green sub-pixels G1 and G2, and two blue sub-pixels B1 and B2. Each of the sub-pixels may include a light-emitting element and a pixel circuit including a compensation circuit. The compensation circuit is a circuit for compensating a threshold voltage of a driving element, and the pixel circuit may be a circuit including the light-emitting element, the driving element, and the compensation circuit. When a sub-pixel includes two light-emitting elements and a compensation circuit, the sub-pixel may be defined as a sub-pixel.

[0130] According to the embodiment, each of the sub-pixels R1, R2, G1, G2, B1, and B2 can be driven independently or simultaneously. A plurality of sub-pixels R1, R2, G1, G2, B1, and B2 can be driven simultaneously by sharing a gate line. However, the present invention is not necessarily limited to this, and a plurality of gate lines can be configured so that a first pixel group of pixels R1, G1, and B1 connected to a first gate line SCAN1 and a second pixel group of pixels R2, G2, and B2 connected to a second gate line SCAN2 can be driven independently.

[0131] The two red subpixels R1 and R2 can be connected to the data lines VdataR1 and VdataR2, respectively. On the other hand, the two green subpixels G1 and G2 can share a data line VdataG, and the two blue subpixels B1 and B2 can share a data line VdataB. Accordingly, the number of data lines can be reduced.

[0132] Thus, two subpixels of one color are connected to two separate data lines. Other pairs of subpixels of the same color each share a data line.

[0133] The red sub-pixels R1 and R2 have relatively low efficiency and can therefore be controlled independently to adjust their luminance, while the green sub-pixels G1 and G2 and the blue sub-pixels B1 and B2 have relatively high efficiency and can therefore emit light simultaneously using one data line.

[0134] Since two light-emitting elements are simultaneously turned on by a data voltage in this case, it is advantageous to output a desired luminance even when a data voltage is lowered. However, the present invention is not necessarily limited to this, and the green sub-pixels and the blue sub-pixels may also be separately connected to the data lines and driven independently of each other.

[0135] With reference to Fig. 7, the red sub-pixels may include a first red sub-pixel (1-1 sub-pixel) R1 and a second red sub-pixel (1-2 sub-pixel) R2. The first red sub-pixel R1 may include a first red light-emitting element ED11 and a first red compensation circuit PC11. The first red light-emitting element ED11 may be connected to an anode AND connected to a high-potential power supply line HL and a cathode CAT connected to a low-potential power supply line CL1. The first red compensation circuit PC11 may be connected between a first data line VdataR1 and the low-potential power supply line CL1.

[0136] The second red sub-pixel R2 may include a second red light-emitting element ED12 and a second red compensation circuit PC12. The second red light-emitting element ED12 may have an anode connected to the high-potential power supply line HL and a cathode connected to a low-potential power supply line CL2. The second red compensation circuit PC12 may be connected between a second data line VdataR2 and the low-potential power supply line CL2.

[0137] According to the embodiment, the first red sub-pixel R1 and the second red sub-pixel R2 are connected to the first data line VdataR1 and the second data line VdataR2, respectively, and can thus be driven independently of each other. When the voltage levels applied to the first data line VdataR1 and the second data line VdataR2 are set to be different, the first red light-emitting element ED11 and the second red light-emitting element ED12 can emit light with different luminances. That is, the luminances of the first red light-emitting element ED11 and the second red light-emitting element ED12 can be controlled independently of each other according to the total luminance of the red light to be output from the pixel. Alternatively, the first red light-emitting element ED11 and the second red light-emitting element ED12 can be driven alternately.However, the present invention is not necessarily limited to this, and the first red sub-pixel R1 and the second red sub-pixel R2 may be driven simultaneously via a data line. Since the first red sub-pixel R1 and the second red sub-pixel R2 are each formed as independent pixels, even if one of the first red sub-pixel R1 and the second red sub-pixel R2 experiences a short-circuit failure, this failure may not affect the other.

[0138] With reference to Fig. 8, the green sub-pixels may include a first green sub-pixel (2-1 sub-pixel) G1 and a second green sub-pixel (2-2 sub-pixel) G2. The first green sub-pixel G1 may include a first green light-emitting element ED21 and a first green compensation circuit PC21. The first green light-emitting element ED21 may have an anode connected to the high-potential power supply line HL and a cathode connected to a low-potential power supply line CL3. The first green compensation circuit PC21 may be connected between a third data line VdataG and the low-potential power supply line CL3.

[0139] The second green sub-pixel G2 may include a second green light-emitting element ED22 and a second green compensation circuit PC22. The second green light-emitting element ED22 may have an anode connected to the high-potential power supply line HL and a cathode connected to a low-potential power supply line CL4. The second green compensation circuit PC22 may be connected between the third data line VdataG and the low-potential power supply line CL4.

[0140] According to the embodiment, the first green sub-pixel G1 and the second green sub-pixel G2 are commonly connected to the third data line VdataG and can thus be driven simultaneously. Accordingly, the data voltage can be set relatively low. For example, if a data voltage to be applied to output a predetermined luminance for the green sub-pixel in the corresponding frame is 1 V, since two green light-emitting elements emit light, even if the data voltage is lowered to 0.5 V and applied, a desired luminance of green light can be output.

[0141] For example, in the case of a second pixel where one of the first green sub-pixel G1 and the second green sub-pixel G2 has failed, only one sub-pixel is used to adjust the luminance, and therefore it is necessary to apply twice the data voltage compared to a first pixel where both sub-pixels emit light in order to perform the adjustment to achieve the same luminance.

[0142] According to the embodiment, the anode of the first green light-emitting element ED21 and the anode of the second green light-emitting element ED22 can be electrically isolated from each other, and the cathode of the first green light-emitting element ED21 and the cathode of the second green light-emitting element ED22 can be electrically isolated from each other. Therefore, even if a high-potential voltage VDD and a low-potential voltage VSS are short-circuited due to a failure in the first green light-emitting element ED21, and the first green light-emitting element ED21 is dimmed, the adjacent second green light-emitting element ED22 is not affected.

[0143] Failure in the first green light-emitting element ED21 may be due to a defect at the electrode pad or a failure due to an inherent defect in the semiconductor layer itself. Micro-sized light-emitting diodes are small and therefore susceptible to static electricity. They are fabricated on a micro-scale wafer and then transferred to a panel and are therefore subject to a high failure rate for various reasons.

[0144] Accordingly, in a case where the first green light-emitting element ED21 and the second green light-emitting element ED22 are connected in series or parallel, if one of the light-emitting elements experiences a short-circuit failure in which the high-potential voltage VDD and the low-potential voltage VSS are short-circuited and dims, the adjacent normal light-emitting element may also become a dark spot due to the flow of a short-circuit current. However, according to the embodiment, since the anode and cathode of the first green light-emitting element ED21 are separated from the anode and cathode of the second green light-emitting element ED22, even if one of the light-emitting elements experiences a short-circuit failure, the adjacent light-emitting element can be prevented from dimming. Accordingly, the adjacent light-emitting elements can operate normally.

[0145] With reference to Fig. 9, the blue sub-pixels may include a first blue sub-pixel (3-1 sub-pixel) B1 and a second blue sub-pixel (3-2 sub-pixel) B2. The first blue sub-pixel B1 may include a first blue light-emitting element ED31 and a first blue compensation circuit PC31. The first blue light-emitting element ED31 may have an anode connected to the high-potential power supply line HL and a cathode connected to a low-potential power supply line CL5. The first blue compensation circuit PC31 may be connected between a fourth data line VdataB and the low-potential power supply line CL5.

[0146] The second blue sub-pixel B2 may include a second blue light-emitting element ED32 and a second blue compensation circuit PC32. The second blue light-emitting element ED32 may have an anode connected to the high-potential power supply line HL and a cathode connected to a low-potential power supply line CL6. The second blue compensation circuit PC32 may be connected between the fourth data line VdataB and the low-potential power supply line CL6.

[0147] According to the embodiment, the first blue sub-pixel B1 and the second blue sub-pixel B2 are commonly connected to the fourth data line VdataB and can thus be driven simultaneously. Accordingly, the data voltage can be set lower than a voltage level for a blue light-emitting element to emit light with a desired luminance.

[0148] For example, in the case of a fourth pixel where one of the first blue sub-pixel B1 and the second blue sub-pixel B2 has failed, only one sub-pixel is used to adjust the luminance, and therefore it is necessary to apply twice the data voltage compared to a third pixel where both sub-pixels emit light in order to perform the adjustment to achieve the same luminance.

[0149] Furthermore, the anode of the first blue light-emitting element ED31 and the anode of the second blue light-emitting element ED32 can be electrically isolated from each other, and the cathode of the first blue light-emitting element ED31 and the cathode of the second blue light-emitting element ED32 can be electrically isolated from each other. Thus, even if one of the light-emitting elements experiences a short-circuit failure, the case where the adjacent light-emitting element is also darkened can be prevented.

[0150] With reference to Fig. 10, in the pixel, an anode And1 of the first red sub-pixel R1, an anode And2 of the second red sub-pixel R2, an anode And3 of the first green sub-pixel G1, an anode And4 of the second green sub-pixel G2, an anode And5 of the first blue sub-pixel B1, and an anode And6 of the second blue sub-pixel B2 may be electrically separated from each other.

[0151] In addition, a cathode Cat1 of the first red sub-pixel R1, a cathode Cat2 of the second red sub-pixel R2, a cathode Cat3 of the first green sub-pixel G1, a cathode Cat4 of the second green sub-pixel G2, a cathode Cat5 of the first blue sub-pixel B1 and a cathode Cat6 of the second blue sub-pixel B2 may be electrically separated from each other.

[0152] Furthermore, a plurality of high-potential power supply lines HL, each connected to the anodes And1 to And6, may be separated from each other, and a plurality of low-potential power supply lines CL, each connected to the cathodes Cat1 to Cat6, may also be separated from each other. Accordingly, it is possible to prevent the light-emitting element of the adjacent sub-pixel from being darkened due to a short-circuit failure in the light-emitting element of one of the plurality of sub-pixels.

[0153] Fig. 11 is a circuit diagram showing a schematic pixel circuit according to an embodiment of the present disclosure. Fig. 12 is a circuit diagram showing a pixel circuit according to an embodiment of the present disclosure.

[0154] With reference to Fig. 11, subpixels SP1 and SP2 of the same color each include a light-emitting element ED, a drive element DT, a first switching element M1, and a compensation circuit PC. The subpixels SP1 and SP2 of the same color may be green or blue subpixels.

[0155] Since the two sub-pixels SP1 and SP2 have the same structure with a data line PL2 arranged therebetween, to which a data voltage Vdata is applied, a pixel circuit arrangement of each sub-pixel is described with the same reference numerals. The following descriptions are based on a second sub-pixel SP2 arranged on the right.

[0156] The second sub-pixel SP2 may include the light-emitting element ED, the drive element DT, the first switching element M1, and the compensation circuit PC. The light-emitting element ED, the drive element DT, and the first switching element M1 may be connected in series between a high-potential power supply line VDD and a low-potential power supply line VSS.

[0157] The drive element DT adjusts a current flowing through a drain-source channel according to a gate-source voltage. The gate-source voltage of the drive element DT varies depending on the data voltage Vdata of pixel data applied to a gate electrode of the drive element DT. Accordingly, the current flowing through the drive element DT varies according to the data voltage Vdata. The light-emitting element ED can be driven by the current flowing from the drive element DT to emit light. A capacitor C can be connected between the gate electrode and a first electrode of the drive element DT. The capacitor C is charged with the gate-source voltage of the drive element DT.

[0158] The drive element DT may be connected between the light-emitting element ED and the first switching element M1. In this case, the drive element DT includes the gate electrode to which the data voltage Vdata is applied, the first electrode connected to a cathode of the light-emitting element ED, and a second electrode connected to a first electrode of the first switching element M1.

[0159] The first switching element M1 switches a current path between the high-potential voltage VDD and the low-potential voltage VSS. The first switching element M1 can be turned on in response to a gate-on voltage of one of the gate signals GATE1 and GATE2, and can be turned off in response to a gate-off voltage of one of the gate signals GATE1 and GATE2. When the first switching element M1 is turned on, the drive element DT and the light-emitting element ED are electrically connected to each other, so that a current can be supplied to the light-emitting element ED. When the first switching element M1 is turned off, the current path between the high-potential voltage VDD and the low-potential voltage VSS is blocked, and thus no current is supplied to the light-emitting element ED.

[0160] The first switching element M1 may be connected between the drive element DT and a cathode voltage VSS. In this case, the first switching element M1 includes a gate electrode connected to a first gate line, the first electrode connected to the second electrode of the drive element DT, and a second electrode connected to a node to which the cathode voltage VSS is applied.

[0161] The pixel circuit may further include a second switching element M2. The second switching element M2 is connected between the cathode and an anode of the light-emitting element ED and can be turned on in response to the gate signal applied via the compensation circuit. When the second switching element M2 is turned on, the cathode and the anode of the light-emitting element ED are short-circuited, and thus the light-emitting element ED does not emit light. The second switching element M2 can prevent the light-emitting element ED from emitting light when the pixel circuit is initialized and a threshold voltage of the drive element DT is sensed. The second switching element M2 includes a gate electrode connected to a second gate line, a first electrode connected to the anode of the light-emitting element ED, and a second electrode connected to the cathode of the light-emitting element ED.

[0162] The first switching element M1 can be turned on in response to a gate-on voltage of a light-emitting signal and turned off in response to a gate-off voltage of the light-emitting signal, but the present invention is not limited thereto. The second switching element M2 can be turned on in response to a gate-on voltage of a first scanning signal and turned off in response to a gate-off voltage of the first scanning signal, but the present invention is not limited thereto.

[0163] The compensation circuit PC is connected to a data line to which the data voltage Vdata is applied, a gate line to which one or more scanning signals SCAN1 and SCAN2 are applied, the gate electrode of the drive element DT, and the gate electrode of the first switching element M1. One or more scanning signals SCAN1 and SCAN2 can be applied to the compensation circuit.

[0164] The compensation circuit transmits the data voltage Vdata to the gate electrode of the drive element DT using multiple transistors. The compensation circuit senses the threshold voltage of the drive element DT to the capacitor C and compensates a gate voltage of the drive element DT by the threshold voltage of the drive element DT. The compensation circuit can compensate the threshold voltage of the drive element DT using a source follower or a diode connection circuit.

[0165] With reference to Fig. 12, the pixel circuit may include a drive element DT connected to a light-emitting element ED, a plurality of switching elements M1 to M6, and a plurality of capacitors C1 to C3. The drive element DT and the plurality of switching elements M1 to M6 may be P-channel transistors, but the present invention is not necessarily limited thereto.

[0166] The drive element DT may have a gate electrode G connected to a first node n1, a source electrode S connected to a second node n2, and a drain electrode D connected to a third node n3.

[0167] The light-emitting element ED may be arranged between the second node n2 and a high-potential voltage VDD. The light-emitting element ED may be a micro-LED, but the present invention is not necessarily limited thereto. The source electrode S of the drive element DT may be connected to a cathode of the light-emitting element ED.

[0168] The first switching element M1 may be connected between the third node n3 of the drive element DT and a low-potential voltage VSS. When the first switching element M1 is turned on in response to a gate-on voltage of a light emission signal EM, the first switching element M1 may connect the third node n3 and the low-potential voltage VSS.

[0169] The second switching element M2 is connected between the cathode and an anode of the light-emitting element ED and can be turned on by a gate-on voltage of a first scanning signal SCAN1. When the second switching element M2 is turned on, the light-emitting element does not emit light.

[0170] A third switching element M3 is connected between a reference voltage line PL1 and a fourth node n4, and when the third switching element M3 is turned on in response to the gate-on voltage of the light emission signal EM, a reference voltage Vref can be applied to the fourth node n4.

[0171] A fourth switching element M4 is arranged between the third node n3 and the first node n1, and when the fourth switching element M4 is turned on in response to the gate-on voltage of the first scanning signal SCAN1, the third node n3 can be connected to the first node n1.

[0172] A fifth switching element M5 is arranged between the reference voltage line PL1 and a fifth node n5, and when the fifth switching element M5 is turned on in response to a gate-on voltage of a second scanning signal SCAN2, the reference voltage Vref can be applied to the fifth node n5.

[0173] A sixth switching element M6 is arranged between the data line PL2 and the fourth node n4, and when the sixth switching element M6 is turned on in response to the gate-on voltage of the first scanning signal SCAN1, a data voltage Vdata can be applied to the fourth node n4.

[0174] A first capacitor C1 may be arranged between the first node n1 and the fourth node n4, a second capacitor C2 may be arranged between the first node n1 and the second node n2, and a third capacitor C3 may be arranged between the second capacitor C2 and the anode of the light-emitting element ED. A threshold voltage of the drive element and the data voltage may be stored in the second capacitor C3 and the third capacitor C3, respectively.

[0175] With reference to Fig. 13, in a first initialization period INI1, the first scanning signal SCAN1 may be output as the gate off voltage VGH, and the second scanning signal SCAN2 may be output as the gate on voltage VGL. The fifth switching element M5, to which the second scanning signal SCAN2 is applied, may be turned on, and the reference voltage may be applied to the third node n3. The reference voltage Vref applied during an emission period of a previous frame may remain at the first node n1, and the reference voltage Vref may be applied to the third node n3.

[0176] In a second initialization period INI2, both the first scanning signal SCAN1 and the second scanning signal SCAN2 are output as gate-on voltages VGL, so that the second switching element M2, the fourth switching element M4, the fifth switching element M5, and the sixth switching element M6 can be turned on. Accordingly, the data voltage Vdata can be charged to the first node n1, and the reference voltage Vref can be charged to the first node n1, so that the first capacitor C1 can be initialized. Furthermore, the gate electrode of the drive element DT can be initialized to the reference voltage Vref. In this case, since the second switching element M2 is turned on, the cathode and the anode of the light-emitting element ED may be short-circuited, and therefore the light-emitting element ED may not emit light.

[0177] In a sampling period SAM, the first sampling signal SCAN1 has the gate-on voltage VGL and the second sampling signal SCAN2 has the gate-off voltage VGH, so that the sixth switching element M6, the fourth switching element M4, and the second switching element M2 can be turned on. Thus, a voltage VDD+Vth can be stored at the first node n1.

[0178] During a hold period HOL, the first scanning signal SCAN1, the second scanning signal SCAN2, and the light emission signal EM all have the gate-off voltage VGH, and thus all switching elements can be turned off. Accordingly, the voltage of VDD+Vth can remain at the first node n1.

[0179] During an emission period EMI, the first scanning signal SCAN1 and the second scanning signal SCAN2 may have the gate off voltage VGH, and the light emission signal EM may have the gate on voltage VGL. The first switching element M1 and the third switching element M3 may be turned on. Accordingly, the reference voltage Vref may be applied to the first node n1, and due to the capacitor coupling, a voltage VDD+Vth-(Vdata-Vref) may be applied to the first node n1.

[0180] A current Ids flowing through the drive element DT can be defined as k(IVgsl-lVthl)2. Given k(VDD-VDD-Vth+Vdata-Vref+Vth)2, the expression can thus be simplified to k(Vdata-Vref)2. Accordingly, the threshold voltage of the drive element can be compensated.

[0181] Fig. Figure 14 is a diagram showing a pixel with subpixels connected in parallel. Fig. 15 is a diagram showing the subpixel of Fig. 14 shows.

[0182] With reference to Fig. 14 and Fig. 15, the pixel may include four subpixels R1, R2, G, and B. That is, the pixel may include a first red subpixel R1, a second red subpixel R2, a green subpixel G, and a blue subpixel B.

[0183] The first red sub-pixel R1 and the second red sub-pixel R2 may each comprise a light-emitting element ED and a compensation circuit PC in the same structure as shown in Fig. 7. However, the green sub-pixel G may have two green light-emitting elements ED arranged in parallel, and the two green light-emitting elements ED may share a compensation circuit PC. Furthermore, the red sub-pixel R may have two red light-emitting elements ED arranged in parallel, and the two red light-emitting elements ED may share a compensation circuit PC. With this structure, the number of compensation circuits can be reduced, thereby increasing the aperture ratio.

[0184] However, since two green light-emitting elements ED1 and ED2 are connected in parallel, there is a problem that if one of the light-emitting elements experiences a short-circuit failure and is dimmed, the adjacent light-emitting element will also be short-circuited and dimmed. Accordingly, there is a problem that all green light-emitting elements ED1 and ED2 in the corresponding pixel are dimmed.

[0185] Fig. 16 and Fig. 17 are diagrams showing a process for repairing sub-pixels.

[0186] With reference to Fig. 16, a plurality of pixels may include a first pixel PIXEL(N) arranged on a first pixel row and a second pixel PIXEL(N+1) arranged on a second pixel row. The first pixel PIXEL(N) may include a first sub-pixel SP1 and a second sub-pixel SP2 of the same color, and the second pixel PIXEL(N+1) may include a third sub-pixel SP3 and a fourth sub-pixel SP4 of the same color. The first pixel row and the second pixel row may be adjacent to each other in the column direction (the Y-axis direction), but the present invention is not limited thereto.

[0187] The first sub-pixel SP1, the second sub-pixel SP2, the third sub-pixel SP3 and the fourth sub-pixel SP4 each include a light-emitting element ED, a compensation circuit PC and a high-potential power supply line HL and a low-potential power supply line CL.

[0188] The first sub-pixel SP1 may be arranged to face the third sub-pixel SP3 in the column direction, and the second sub-pixel SP2 may be arranged to face the fourth sub-pixel SP4 in the column direction.

[0189] A low-potential power supply line CL11 arranged in the first sub-pixel SP1 may extend toward the third sub-pixel SP3, and a low-potential power supply line CL13 arranged in the third sub-pixel SP3 may extend toward the first sub-pixel SP1. Furthermore, a low-potential power supply line CL12 arranged in the second sub-pixel SP2 may extend toward the fourth sub-pixel SP4, and a low-potential power supply line CL14 arranged in the fourth sub-pixel SP4 may extend toward the second sub-pixel SP2.

[0190] A welding portion WP may be formed at one end of each of the low-potential power supply lines CL11, CL12, CL13, and CL14 extending outside each sub-pixel. The welding portion WP includes metal layers that overlap each other with an insulating layer interposed therebetween and can be selectively connected in a welding process.

[0191] With reference to Fig.17, when the compensation circuit PC of the fourth sub-pixel SP4 fails, a repair portion WP2 can be formed by connecting the welding portion WP of the low-potential power supply line CL14 of the fourth sub-pixel SP4 to the welding portion WP of the low-potential power supply line CL12 of the second sub-pixel SP2. Thus, in this case, the welding portion WP can be connected after electrically disconnecting the light-emitting element ED from the compensation circuit PC in the fourth sub-pixel SP4. With this configuration, when the compensation circuit of each sub-pixel fails, the compensation circuit can be connected to the compensation circuit of the adjacent sub-pixel and operate normally.

[0192] A display device according to the embodiment of the present disclosure may be applied to a mobile device, a video phone, a smart watch, a watch phone, a wearable device, a foldable device, a rollable device, a bendable device, a flexible device, a curved device, a sliding device, a variable device, an electronic organizer, an electronic book, a portable multimedia player (PMP), a personal digital assistant (PDA), an MP3 player, a mobile medical device, a desktop PC, a laptop PC, a netbook computer, a workstation, a navigation system, a navigation system for a vehicle, a display device for a vehicle, a device for a vehicle, a cinema device, a cinema display device, a television, a billboard device, a signage device, a game device, a notebook, a monitor, a camera,a camcorder, an entertainment electronic device and the like.

[0193] According to the present disclosure, the remaining light-emitting elements can emit light even when one of the light-emitting elements of a plurality of sub-pixels is darkened. Accordingly, the number of dark spots in the light-emitting elements of a display device can be reduced. Furthermore, low-power operation becomes possible.

[0194] In addition, using a pixel structure that enables the improvement of dark spots, a display panel can be implemented, which is beneficial for process optimization, high efficiency, high luminance and long service life.

[0195] It should be noted that the advantageous effects of the present disclosure are not limited to the effects described above, and other effects not described here will be apparent to those skilled in the art from the following descriptions.

[0196] Although the embodiments of the present disclosure and their advantages have been described in detail with reference to the accompanying drawings, it will be apparent to those skilled in the art to which the present disclosure belongs that various changes, substitutions, and modifications can be made therein without departing from the scope of the present disclosure. Accordingly, the scope of the present disclosure is defined by the following claims rather than by the foregoing detailed description, and all changes and modifications that come within the meaning and scope of the claims and their equivalents are intended to be within the scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] KR 10-2023-0192978

[0001]

Claims

[1] Scoreboard, which includes: multiple pixels; and Gate lines (SCAN) and data lines (Vdata) connected to the pixels, where a pixel comprises: a plurality of sub-pixels (SP) providing different colors, each sub-pixel (SP) comprising a light-emitting element (ED) and a compensation circuit (PC), the compensation circuits (PC) of at least two of the sub-pixels (G1, G2) providing the same color being connected to a data line (Vdata). [2] A display panel according to claim 1, comprising a 1-1 subpixel (R1) and a 1-2 subpixel (R2) of a first color; a 2-1 subpixel (G1) and a 2-2 subpixel (G2) of a second color; and a 3-1 subpixel (B1) and a 3-2 subpixel (B2) of a third color, wherein each of the 2-1 sub-pixel (G1) and the 2-2 sub-pixel (G2) comprises a light-emitting element (ED) and a compensation circuit (PC), and the compensation circuit (PC) of the 2-1 sub-pixel (G1) and the compensation circuit of the 2-2 sub-pixel (G2) are connected to a data line (VdataG). [3] The display panel according to claim 2, wherein the 1-1 sub-pixel (R1) comprises a first compensation circuit (PC11) connected to a first data line (VdataR1), and the 1-2 sub-pixel (R2) comprises a second compensation circuit (PC12) connected to a second data line (VdataR2), and / or each of the 3-1 sub-pixel (B1) and the 3-2 sub-pixel (B2) comprises a compensation circuit (PC31, PC32), and the compensation circuits (PC31, PC32) of the 3-1 sub-pixel (B1) and the 3-2 sub-pixel (B2) are connected to a data line (VdataB). [4] A display panel according to any one of the preceding claims, wherein the first color is red, the second color is green and the third color is blue. [5] A display panel according to any one of the preceding claims, wherein the plurality of pixels comprise: a first pixel in which both the 2-1 sub-pixel (G1) and the 2-2 sub-pixel (G2) emit light when a data voltage is applied; and a second pixel in which only one of the 2-1 sub-pixel (G1) and the 2-2 sub-pixel (G2) emits light when the data voltage is applied, wherein preferably a data voltage applied to the 2-1 sub-pixel (G1) and the 2-2 sub-pixel (G2) of the second pixel is greater than a data voltage applied to the 2-1 sub-pixel (G1) and the 2-2 sub-pixel (G2) of the first pixel. [6] A display panel according to claim 5, wherein the plurality of pixels comprise: a third pixel in which both the 3-1 sub-pixel (B1) and the 3-2 sub-pixel (B2) emit light when a data voltage is applied; and a fourth pixel in which only one of the 3-1 sub-pixel (B1) and the 3-2 sub-pixel (B2) emits light when the data voltage is applied, wherein preferably a data voltage applied to the 3-1 sub-pixel (B1) and the 3-2 sub-pixel (B2) of the fourth pixel is greater than a data voltage applied to the 3-1 sub-pixel (B1) and the 3-2 sub-pixel (B2) of the third pixel. [7] A display panel according to any one of the preceding claims, comprising a first gate line (SCAN1) to which the 1-1 sub-pixel (R1), the 2-1 sub-pixel (G1) and the 3-1 sub-pixel (B1) are connected; and a second gate line (SCAN2) to which the 1-2 sub-pixel (R2), the 2-2 sub-pixel (G2) and the 3-2 sub-pixel (B2) are connected. [8] A display panel according to any one of the preceding claims, wherein each sub-pixel (SP) comprises an anode (AND) and a cathode (CAT) for applying a voltage to the light-emitting element (ED), preferably the anodes (AND) of the sub-pixels (SP) being separated from each other and / or the cathodes (CAT) of the sub-pixels (CAT) being separated from each other. [9] A display panel according to any one of the preceding claims, wherein the compensation circuit (PC21) of the 2-1 sub-pixel (G1) and the compensation circuit (PC22) of the 2-2 sub-pixel (G2) have the same structure. [10] A display panel according to any one of the preceding claims, wherein the plurality of pixels comprises a plurality of first pixels (PIXEL(N)) arranged in a first pixel row and a plurality of second pixels (PIXEL(N+1)) arranged in a second pixel row adjacent to the first pixel row. [11] A display panel according to any one of the preceding claims, wherein the 2-1 sub-pixel (G1) of the first pixel comprises a first low-potential power supply line (CL3) connected to a first cathode (Cat3) of the 2-1 sub-pixel (G1) of the first pixel, the 2-1 sub-pixel (G1) of the second pixel comprises a second low-potential power supply line (CL4) connected to a second cathode (Cat4) of the 2-1 sub-pixel (G1) of the second pixel, the first low-potential power supply line (CL3) extends towards the second cathode (Cat3), the second low-potential power supply line (CL4) extends towards the first cathode (Cat3), and the first low-potential power supply line (CL3) and the second low-potential power supply line (CL4) are electrically connected to each other. [12] A display panel according to claim 11, wherein the first low-potential power supply line of the 2-1 sub-pixel (G1) of the second pixel is electrically connected to the compensation circuit (PC21) of the 2-1 sub-pixel (G1) of the first pixel. [13] Display panel according to one of the preceding claims, wherein the first compensation circuit (PC11) of the 1-1 sub-pixel (R1) is connected between the first data line and a first low-potential power supply line, and the second compensation circuit (PC12) of the 1-2 sub-pixel (R2) is connected between the second data line and a second low-potential power supply line. [14] A display device comprising a display panel according to any one of the preceding claims.

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