Semiconductor device and method of manufacturing the same

Abstract

The present application relates to a semiconductor device comprising a device structure in a semiconductor body having a first load terminal on a first side of the semiconductor body; a lower insulating layer on the first side of the semiconductor body; a conductive track in a lowermost metallization layer on the first side of the semiconductor body; a load pad in an uppermost metallization layer on the first side of the semiconductor body; wherein the uppermost metallization layer comprises a copper layer and the lowermost metallization layer comprises a tungsten layer, wherein the conductive track is arranged in a trench in the lower insulating layer.

Description

TECHNICAL FIELDThe present disclosure relates to a semiconductor device and a method of manufacturing the same.BACKGROUNDThe semiconductor device may include a device structure in a semiconductor body that may be contacted via metallization on a first side of the semiconductor body. The metallization may comprise a load pad for contact formation, for example a source pad in the case of an FET. The device structure may include a load terminal at the first side of the semiconductor body, for example a source region of the FET. It may also comprise a control terminal at the first side of the semiconductor body, e.g. a gate electrode.US 2008 / 0 023 836 A1 discloses a semiconductor device having a semiconductor substrate over which an insulating film is formed. An electrode pad is formed over the insulating film. Further, a first interlayer insulating film is formed over the insulating film, and a second interlayer insulating film is formed over the first interlayer insulating film. A sealing layer is formed over the second interlayer insulating film. An electrode column is embedded in an opening of the sealing layer. The electrode column is connected to the electrode pad via a second redistribution layer partially disposed in the sealing layer and via a first redistribution layer partially disposed in the second interlayer insulating film.SUMMARYExamples of the present application are directed to a semiconductor device.In the embodiment of claim 1, the semiconductor device comprises a lower insulating layer on the first side of the semiconductor body, a conductive trace in a lowermost metallization layer on the first side of the semiconductor body, and a load pad in an uppermost metallization layer on the first side of the semiconductor body. The lowermost metallization layer comprises a tungsten layer and the uppermost metallization layer comprises a copper layer, for example for contact formation by wire bonding and / or soldering. The conductive path formed in the lowermost metallization layer is arranged in an opening or a trench in the lower insulating layer, e.g. embedded in the lower insulating layer. The semiconductor device further includes an upper insulating layer on the lower insulating layer. The upper insulating layer is locally cut by a vertical load connection providing an electrical connection between the load pad and the first load terminal. The vertical load connection is connected to the first load terminal via a lower load connection, wherein the lower load connection intersects the lower insulating layer.The conductive trace may improve a lateral distribution of a control signal, for example a gate signal, and avoid interruption of the load pad. Embedding the conductive trace in the lower insulating layer may reduce a topology, for example a passivation layer and / or in an imide layer on the top metallization layer (see in detail below). A reduced topology may have advantages in subsequent handling steps, e.g. mounting and / or contacting steps, for example.Embodiments and features are provided throughout the disclosure, which relates to device aspects, but also to method and use aspects. For example, when describing a device manufactured in a particular manner, this is also a disclosure of a respective manufacturing process and vice versa. In general words, one approach of this application is to provide a semiconductor device having a lowermost metallization layer in addition to an uppermost metallization layer above, wherein a conductive trace formed in the lowermost metallization layer is embedded in a lower insulating layer, for example for control / gate signal amplification.Although they are different layers, e.g. deposited in subsequent process steps, the embedded conductive track or lowermost metallization layer may be arranged at the same vertical height as the lower insulating layer, e.g. in a common lateral plane. A respective layer may be patterned, e.g. the conductive trace formed in the lowermost metallization layer and the trench formed in the lower insulating layer, such that at least where the conductive trace is embedded in the lower insulating layer, the lowermost metallization layer and the lower insulating layer may be arranged at the same vertical height. In other words, a respective layer denotes a material layer that can only partially cover the first side of the semiconductor, such that different layers can be arranged in a common horizontal plane (conversely, the term layer is not intended to denote a horizontal plane that completely covers the first side of the semiconductor body). In summary, the lowermost metallization layer and the lower insulating layer deposited in different process steps differ in their respective material and not necessarily in their vertical position at or vertically distance from the first side of the semiconductor body.The embedded conductive path may be laterally enclosed in the lower insulating layer, for example with respect to a transverse direction that is perpendicular to a longitudinal direction of the conductive path. The conductive path may extend, for example, continuously, e.g. without interruption, from below a control pad next to the load pad to below the load pad, for example from below a gate pad to below the source pad. Its longitudinal direction may be parallel to the control or gate electrode arranged underneath, for example, in order to improve the control signal distribution along the gate electrode.Generally, in this disclosure, "below" and "above" refer to the vertical direction that is perpendicular to the lateral directions, where "below" means closer to the semiconductor body and "above" at a greater distance therefrom (which applies in a stack on the semiconductor body). Vertically, the trench in the lower insulating layer may completely intersect the lower insulating layer, e.g. extend between an upper end and a lower end of the lower insulating layer. The lower insulating layer may be doped or undoped silicon oxide, for example.The lowermost metallization layer in which the conductive track is formed may comprise a tungsten layer, which may be the only layer of the lowermost metallization layer or a sub-layer in a layer stack. The tungsten layer may have advantages in terms of corrosion or mechanical stiffness, for example compared to an aluminum layer. The lowermost metallization layer may comprise a metallic barrier layer or layers below the tungsten layer, for example at least one of a titanium, titanium nitride or titanium tungsten layer. The barrier layer may have a thickness of at least 5 nm and not more than 50 nm, 30 nm or 15 nm and / or the tungsten layer may have a thickness of at least 100 nm or at least 130 nm, wherein possible upper limits are, for example, not more than 300 nm or 200 nm.The uppermost metallization layer in which the load pad and, for example, a control pad may be formed may have a thickness of at least 3 μm, 4 μm or 5 μm, for example (possible upper limits are, for example, 20 μm or 15 μm). It may comprise the copper layer, which may be the only layer of the uppermost metallization layer or a sub-layer in a layer stack. The uppermost metallization layer may additionally comprise a metallic barrier layer and / or a metallic adhesion layer under the copper layer, see in detail further below.The semiconductor device may be a power device, e.g. having a breakdown voltage of at least 10 V, 20 V or 30 V, with possible upper limits of, for example, no more than 800 V, 600 V, 400 V or 200 V. For example, in the case of a FET, it may have a source region and a drain region as well as a body region. The source region may be the first load terminal on the first side of the semiconductor body, wherein the drain region (second load terminal) may also be arranged on the first side or on a vertically opposite second side of the semiconductor body. Regardless of these details, the load pad formed in the uppermost metallization layer may be connected to the first load terminal of the device structure, for example, it may be a source plate connected to the source region.In an embodiment, the embedded conductive trace lies flush in the lower insulating layer. In other words, an upper end of the conductive path and an upper end of the lower insulating layer are disposed at the same vertical height. After filling the trench with the metal material of the lower metallization layer, a planarization step may be applied, wherein a top surface of the conductive trace is then in a plane with a top surface of the lower insulation layer, for example. As discussed above, the layers differ in their respective material and due to the respective structuring (conductor track versus trench) in their lateral extension and shape, but they may be arranged at the same vertical position (the conductor track being embedded in the lower insulating layer).In an embodiment, the upper insulating layer may be adjacent to the lower insulating layer with respect to the vertical direction, e.g., may be deposited directly on the lower insulating layer. The upper insulating layer is disposed below the uppermost metallization layer (e.g., except for openings / interconnects), for example, below the load pad formed in the uppermost metallization layer.In an embodiment, the upper insulating layer is made of a harder material than the lower insulating layer. The upper insulating layer may serve as a hard passivation of the device, for example protecting or sealing the device structure, e.g. against ion diffusion. In other words, the hard passivation may be integrated under the load pad / the uppermost metallization layer. The upper insulating layer may be made of silicon nitride, for example, in combination with a lower insulating layer made of silicon oxide.The upper insulating layer is locally cut by a vertical load connection providing an electrical connection between the load pad and the first load terminal of the device structure, e.g. between the source pad and the source region. The vertical load connection may be formed in the uppermost metallization layer, e.g. filled by the layer or sub-layers (layer stacks) of the uppermost metallization system. In other words, the same metallic barrier layer and / or metallic adhesion layer and / or copper layer deposited for the load pad may fill or form the vertical load connection. This also applies to a vertical control connection, which may connect a control pad, e.g. gate pad, next to the load pad in the uppermost metallization layer to the underlying conductive track.The lower load connection intersects the lower insulating layer and connects the first load pad to the first load terminal of the device structure. In detail, the lower load connection may be vertically connected between the vertical load connection and the first load terminal. The lower load connection may be made of the same metallic material as the conductive trace, e.g., comprising a tungsten layer and optionally an underlying barrier layer. In other words, the lower load connection and the conductor track can be produced in the same process step or the same process steps.In an embodiment, the conductive trace under the load pad is completely covered by the upper insulating layer. Alternatively or additionally, the conductive path laterally between the load pad and a control pad, e.g. gate pad, may be completely covered by the upper insulating layer. Where the conductive path is completely covered, the upper insulating layer is not interrupted over the conductive path, for example. Laterally beside it, it may be interrupted, for example where a vertical load connection is formed.In an embodiment, the lowermost metallization layer and the uppermost metallization layer are the only metallization layers on the first side of the semiconductor body. Each of these two metallization layers may comprise different metal sub-layers, but no additional metal layer isolated from the top and bottom metallization layers is to be interposed therebetween. In other words, the front side metallization consists of two metallization layers, namely the lowermost and the uppermost metallization layers. The vertical load connection may be directly connected to the lower load connection and / or the vertical control connection may be directly connected to the conductive track and / or a lower load connection may be directly connected to the load terminal and / or the conductive track may be directly connected to the control electrode, e.g. gate electrode. Independently thereof, a metallization may be provided on the second side of the semiconductor body, namely a rear side metallization.As mentioned, the uppermost metallization layer may comprise a barrier layer below the copper layer, wherein the barrier layer may comprise, among other elements, for example titanium nitride and / or tungsten (for example TiN LAYER+W layer). In one embodiment, the barrier layer is set back laterally inward, wherein a lateral edge of the barrier layer is covered by the copper layer. For example, viewed in a vertical cross section perpendicular to the lateral edge of the barrier layer, a lateral distance between this lateral edge of the barrier layer and a lateral edge of the copper layer may be at least 1 μm or 2 μm (possible upper limits are, for example, 25 μm, 15 μm or 10 μm). If an adhesive layer is provided between the barrier layer and the copper layer, the barrier layer may also be recessed laterally inward with respect to the adhesive layer. In other words, a respective lateral edge of the adhesion layer and of the copper layer may be arranged at substantially the same lateral position, wherein the barrier layer is recessed inwardly and laterally enclosed by the adhesion and / or copper layer. Considering the upper metallization layer as a whole, this may allow for a defined lateral edge, for example.In an embodiment, the device structure comprises a second load terminal at a second side of the semiconductor body. This may be, for example, a drain region (see above), wherein the device structure has its source region at the first side and its drain region at the second side of the semiconductor body. A body region may be arranged therebetween, which comprises a channel region to which the gate electrode capacitively couples via a gate dielectric. The source and drain region may be made of a first doping type and the body region may be made of a second doping type, wherein the first type is n-type and the second type is p-type, for example.In an embodiment, the device or device structure comprises a gate electrode in a trench extending from the first side into the semiconductor body and having an elongated lateral extension. Alternatively or additionally, the device or device structure may comprise a field electrode in a trench extending from the first side into the semiconductor body and having an elongated lateral extension. Separate trenches may be provided for the gate and field electrodes, alternatively the gate and field electrodes may be arranged in a common trench. Regardless of this detail, the field electrode may be arranged adjacent to a drift region of the device structure, e.g. made of the same doping type but with a lower doping concentration compared to the drain region.In an embodiment, the conductive trace is stacked over the gate electrode, e.g., extends parallel to the elongated trench with the gate electrode. The gate electrode and the conductive path may be made of different materials, for example the gate electrode of polysilicon. The conductive path above may be formed directly adjacent to the gate electrode, e.g. to improve the lateral gate signal distribution along the gate electrode.In one embodiment, a method of manufacturing a semiconductor device, for example the device according to any of the device claims, is provided. It may comprise:i) forming the lower insulating layer on the first side of the semiconductor body;ii) etching the trench into the lower insulating layer;iii) filling the trench with a tungsten material.For possible details of the apparatus, reference is made to the disclosure as a whole.Prior to the tungsten material deposition, a barrier layer may be formed covering a bottom of the trench, for example. The tungsten material may be deposited in excess, wherein excess tungsten material extends over and covers, for example, a top surface of the lower insulating layer. The excess tungsten material, e.g. together with the barrier layer lying on the surface of the lower insulating layer, may be removed by planarization, for example by chemical mechanical polishing (CMP). As a result, the conductive path may be flush in the lower insulating layer.In an embodiment, the conductive trace and a lower load connection that can later connect the load pad to the first load terminal are simultaneously formed. With the tungsten material deposition for the conductive trace, possibly in combination with a barrier layer deposition prior thereto, the conductive trace and also the lower load connection may be formed.BRIEF DESCRIPTION OF THE DRAWINGSThe semiconductor device and the method for manufacturing the same will be explained in more detail below by way of exemplary embodiments. The individual features may also be relevant to the disclosure in another combination. FIG. 1 shows a semiconductor device in a cross-sectional view; FIG. 2 shows a section of the device of FIG. 1 in a sectional plane perpendicular to the drawing plane of FIG. 1 ; FIG. 3 shows further details of the semiconductor device in a cross-sectional view; FIG. 4 shows a detailed view of a lateral edge of an uppermost metallization layer with a copper layer; FIG. 5 summarizes some manufacturing steps in a flow chart; Figures 6a-f illustrate some fabrication steps in more detail.DETAILED DESCRIPTIONFIG. 1 shows a semiconductor device 10 in a cross-sectional view. It comprises a device structure 20 in a semiconductor body 30, wherein the device structure 20 has a first load terminal 21 on a first side 30.1 and a second load terminal 25 on a second side 30.2 of the semiconductor body 30. The load terminals 21, 25 are only schematically shown in FIG. 1, and reference is made to FIG. 3 for further details of the device structure 20.On the first side 30.1 of the semiconductor body 30 a lower insulating layer 40 is arranged, which in the example shown is made of silicon oxide. A conductive path 65 is embedded in the lower insulating layer 40, namely, is disposed in a trench 45 in the lower insulating layer 40. The conductive path 65 lies flush in the lower insulating layer 40, which can be obtained in a planarization step (see FIG. 6 d / e in detail). The conductive trace 65 is formed in a lowermost metallization layer 60 embedded at least locally in the lower insulating layer 40 (disposed at the same vertical position as discussed above). The lowermost metallization layer 60 includes a tungsten layer 160 and a barrier layer 162 thereunder, for example a titanium nitride layer (or a TiN+W layer stack). In the example shown, the barrier layer 162 has a thickness of about 10 nm and the tungsten layer 160 has a thickness of about 150 nm.An upper insulating layer 50 is disposed on the lower insulating layer 40 and covers the conductive line 65. the upper insulating layer 50 is made of a harder material than the lower insulating layer 40, which in this example is silicon nitride. On the upper insulating layer 50, an uppermost metallization layer 70 is disposed. It comprises a copper layer 170 having a thickness of about 7 μm in this example. Subsequently, further layers are arranged (not referenced here), see FIG. 4 in further detail. In the uppermost metallization layer 70, a load pad 75, which may be a source pad, is formed. The load pad 75 may be covered by a passivation layer 80 and / or an imide layer 90, leaving a central portion of the load pad 75 open for contact formation during back-end-of-line processing.A vertical load connection 56 intersects the upper insulating layer 50 and connects the load pad 75 to the first load terminal 21, A respective opening 57 in the upper insulating layer 50 is filled with the uppermost metallization layer 70 forming the vertical load connection 56. Below this, an opening 47 in the lower insulating layer 40 is filled with the stack of the lowermost metallization layer 60, namely with the barrier layer 162 and the tungsten layer 160.Below the conductive path 65, a gate electrode 115 is arranged in a trench 215. Perpendicular to the drawing plane, it has an elongate lateral extent, wherein the conductor track 65 extends parallel thereto. This is illustrated in more detail in Figure 2, which shows a cross-section perpendicular to the drawing plane of Figure 1 (see A-A for illustration). In the active area of the device structure 20, e.g., below the load pad 75, the conductive trace 65 is stacked on the gate electrode 115 and extends in parallel. The gate electrode 115 terminates below the load pad 75 and the conductive trace 65 forms an electrical connection with a control pad 78 adjacent the load pad 75.Below the load pad 75 and between the load pad 75 and the control pad 78, the conductive path 65 is covered by the upper insulating layer 50. Via a vertical control connection 58 below the control pad 78, the conductor track 65 is connected to the control pad 78.FIG. 3 illustrates the device structure 20 in more detail. Generally, in this disclosure, the same reference numerals indicate the same elements or elements having the same function, and reference is also made to the description of the other figures. In the case of the FET illustrated in FIG. 3, the first load terminal 21 is a source region 22 on the first side 30.1 of the semiconductor body 30. the second load terminal 25 on the vertically opposite second side 30.2 is a drain region 26, with a body region 23 arranged therebetween, optionally in combination with a drift region 24. in the example shown, the source region 22, the drift region 24 and the drain region 25 are n-doped, wherein the body region 23 is p-doped.The lowermost and uppermost metallization layers 60, 70 and respective interconnects are only schematically shown in FIG. 3. The lower load connection 46 and the vertical load connection 56 connect the load pad 75, e.g. the source plate, to the source region 22.FIG. 4 illustrates the uppermost metallization layer 70 in detail. In addition to the copper layer 170, it comprises an adhesive layer 171 and a barrier layer 172 thereunder. The adhesion layer 171 may also be a copper layer, for example sputter deposited compared to the copper layer 170 obtained by bath deposition. The barrier layer 172 may be a titanium nitride layer. With respect to the copper layer 170 and the adhesion layer 171, the barrier layer 172 is recessed laterally inward. A lateral edge 172 aof the barrier layer 172 may be covered laterally and vertically in the stack, for example. A vertical distance 185 between the lateral edge 172 aof the barrier layer 172 and a lateral edge 171 aof the adhesion layer 171 and / or a lateral edge 170 aof the copper layer 170 is approximately 10 μm in this example.FIG. 5 summarizes some manufacturing steps in a flow chart. The method may include forming 301 the lower insulating layer on the first side of the semiconductor body, etching 302 the trench into the lower insulating layer and filling 303 the trench with tungsten material.Figures 6a-f illustrate some fabrication steps in more detail. FIG. 6 ashows the semiconductor body 30, wherein the device structure 20 has already been formed (e.g. doped regions and gate trenches). Then, the lower insulating layer 40 is formed on the first side 30.1 of the semiconductor body 30 by depositing silicon oxide 140, see FIG. 6b. In the step shown in FIG. 6 c, the trenches 45 (for the conductor tracks) and the opening 47 (for the lower load connection) were etched into the lower insulating layer 40. For this etching step, a patterned mask may be provided on the lower insulating layer 40, which is not shown in detail here.FIG. 6 d shows the structure after deposition of the lowermost metallization layers 60, wherein only the tungsten material 260 is shown (not the thin barrier layer underneath). The tungsten material 260 fills the trenches 45 and the opening 47, with excess tungsten material 260.1 covering the top of the lower insulating layer 40.FIG. 6e shows the structure after planarization, namely after removal of the excess tungsten material from the top surface of the lower insulating layer 40 by chemical mechanical polishing. Likewise, the lower metallization layer 60, e.g., the conductive traces 65 and the lower load connection 46, are embedded in the lower insulating layer 40. Subsequently, the upper insulating layer 50 may be formed by depositing silicon nitride 150, see FIG. 6 f. In a subsequent step, not shown here, the silicon nitride 150 may be opened locally to form the contacts to the uppermost metallization layer later, see FIGS. 1-3 for comparison.Embodiments and features of the present application may be summarized in the form of the following examples: 1. semiconductor device (10) comprising:a device structure (20) in a semiconductor body (30) having a first load terminal (21) on a first side (30.1) of the semiconductor body (30);a lower insulating layer (40) on the first side (30.1) of the semiconductor body (30);a conductor track (65) in a lowermost metallization layer (60) on the first side (30.1) of the semiconductor body (30);a load pad (75) in an uppermost metallization layer (70) on the first side (30.1) of the semiconductor body (30); wherein the uppermost metallization layer (70) comprises a copper layer (170) and the lowermost metallization layer (60) comprises a tungsten layer (160), wherein the conductive track (65) is arranged in a trench (45) in the lower insulation layer (40). 2. semiconductor device (10) according to Example 1, wherein the conductor track (65) lies flush in the lower insulating layer (40). 3. the semiconductor device (10) of Example 1 or 2, comprising:an upper insulating layer (50) on the lower insulating layer (40).4. The semiconductor device (10) according to Example 3, wherein the upper insulating layer (50) is made of a harder material than the lower insulating layer (40). 5. semiconductor device (10) according to example 3 or 4, wherein the upper insulating layer (50) is locally cut by a vertical load connection (56) providing an electrical connection between the load pad (75) and the first load terminal (21), wherein the vertical load connection (56) is formed in the uppermost metallization layer (70). 6.The semiconductor device (10) according to Example 5, wherein the vertical load connection (56) is connected to the first load terminal (21) via a lower load connection (46), wherein the lower load connection (46) intersects the lower insulating layer (40) and is made of the same tungsten layer (160) as the conductive path (65). 7. semiconductor device (10) according to any of Examples 3 to 6, wherein the conductive path (65) under the load pad (75) and / or laterally between the load pad (75) and a control pad (78) is completely covered by the upper insulating layer (50). 8. semiconductor device (10) according to one of the preceding examples, wherein the lowermost metallization layer (60) and the uppermost metallization layer (70) are the only metallization layers on the first side (30.1) of the semiconductor body (30). 9. semiconductor device (10) according to any of the preceding examples, wherein the uppermost metallization layer comprises a barrier layer (172) below the copper layer (170), wherein the barrier layer (172) is laterally inwardly recessed, wherein a lateral edge (172a) of the barrier layer (172) is covered by the copper layer (170). 10. semiconductor device (10) according to one of the preceding examples, wherein the device structure (20) comprises a second load terminal (25) on a second side (30.2) of the semiconductor body (30), which is vertically opposite the first side (30.1). 11.Semiconductor device (10) according to one of the preceding examples, wherein the device structure (20) comprises a gate electrode (115) and / or a field electrode arranged in a trench (215) extending from the first side (30.1) into the semiconductor body (30) and having an elongated lateral extension. 12th semiconductor device (10) according to Example 11, wherein the conductive path (65) extends parallel to the trench (215) and to the gate electrode (115) arranged in the trench (215), wherein the conductive path (65) is stacked over the gate electrode (115). 13.A method of manufacturing a semiconductor device (10) comprising:i.) forming (301) a lower insulating layer (40) on a first side (30.1) of a semiconductor body (30);ii.) etching (302) a trench (45) into the lower insulating layer (40);iii.) filling (303) the trench (45) with a tungsten material (260).14. The method of example 13 for manufacturing the semiconductor device (10) of example 2, wherein in step iii.) the tungsten material (260) is deposited in excess, wherein excess tungsten material (260.1) is subsequently removed by planarization. 15. The method of Example 13 or 14 of manufacturing the semiconductor device (10) of Example 6, wherein the lower load connection (46) and the conductive trace (65) are simultaneously formed.

Claims

A semiconductor device (10) comprising: a device structure (20) in a semiconductor body (30) having a first load terminal (21) on a first side (30.1) of the semiconductor body (30); a lower insulating layer (40) on the first side (30.1) of the semiconductor body (30); a conductive trace (65) in a lowermost metallization layer (60) on the first side (30.1) of the semiconductor body (30); a load pad (75) in an uppermost metallization layer (70) on the first side (30.1) of the semiconductor body (30); wherein the uppermost metallization layer (70) comprises a copper layer (170) and the lowermost metallization layer (60) comprises a tungsten layer (160), wherein the conductive trace (65) is arranged in a trench (45) in the lower insulating layer (40); wherein the semiconductor device (10) further comprises: an upper insulating layer (50) on the lower insulating layer (40), wherein the upper insulating layer (50) is locally cut by a vertical load connection (56) providing an electrical connection between the load pad (75) and the first load terminal (21), and wherein the vertical load connection (56) is connected to the first load terminal (21) via a lower load connection (46), wherein the lower load connection (46) cuts the lower insulating layer (40).The semiconductor device (10) according to claim 1, wherein the conductive path (65) is flush in the lower insulating layer (40).The semiconductor device (10) according to claim 1 or 2, wherein the upper insulating layer (50) is made of a harder material than the lower insulating layer (40).The semiconductor device (10) according to any of the preceding claims, wherein the vertical load connection (56) is formed in the uppermost metallization layer (70).The semiconductor device (10) according to any one of the preceding claims, wherein the lower load connection (46) is made of the same tungsten layer (160) as the conductive path (65).The semiconductor device (10) according to any of the preceding claims, wherein the conductive path (65) under the load pad (75) and / or laterally between the load pad (75) and a control pad (78) is completely covered by the upper insulating layer (50).The semiconductor device (10) according to any of the preceding claims, wherein the lowermost metallization layer (60) and the uppermost metallization layer (70) are the only metallization layers on the first side (30.1) of the semiconductor body (30).The semiconductor device (10) according to any one of the preceding claims, wherein the uppermost metallization layer comprises a barrier layer (172) and an adhesion layer (171) under the copper layer (170), wherein the barrier layer (172) is laterally recessed inwardly with respect to the copper layer (170) and the adhesion layer (171), wherein a lateral edge (172a) of the barrier layer (172) is covered by the adhesion layer (171).The semiconductor device (10) according to any of the preceding claims, wherein the device structure (20) comprises a second load terminal (25) at a second side (30.2) of the semiconductor body (30) vertically opposite to the first side (30.1).The semiconductor device (10) according to any of the preceding claims, wherein the device structure (20) comprises a gate electrode (115) and / or a field electrode arranged in a trench (215) extending from the first side (30.1) into the semiconductor body (30) and having an elongated lateral extension.The semiconductor device (10) of claim 10, wherein the conductive path (65) extends parallel to the trench (215) and to the gate electrode (115) disposed in the trench (215), the conductive path (65) being stacked over the gate electrode (115).A semiconductor device (10) comprising: a device structure (20) in a semiconductor body (30) having a first load terminal (21) on a first side (30.1) of the semiconductor body (30); a lower insulating layer (40) on the first side (30.1) of the semiconductor body (30); a conductive trace (65) in a lowermost metallization layer (60) on the first side (30.1) of the semiconductor body (30); a load pad (75) in an uppermost metallization layer (70) on the first side (30.1) of the semiconductor body (30); wherein the uppermost metallization layer (70) comprises a copper layer (170) and the lowermost metallization layer (60) comprises a tungsten layer (160), wherein the conductive track (65) is arranged in a trench (45) in the lower insulating layer (40), wherein the uppermost metallization layer comprises a barrier layer (172) and an adhesion layer (171) below the copper layer (170), wherein the barrier layer (172) is set back laterally inward with respect to the copper layer (170) and the adhesion layer (171), wherein a lateral edge (172a) of the barrier layer (172) is covered by the adhesion layer (171).The semiconductor device (10) according to claim 12, wherein the conductive path (65) is flush in the lower insulating layer (40).The semiconductor device (10) according to claim 12 or 13, further comprising: an upper insulating layer (50) on the lower insulating layer (40).The semiconductor device (10) according to claim 14, wherein the upper insulating layer (50) is made of a harder material than the lower insulating layer (40).The semiconductor device (10) according to any one of claims 12 to 15, wherein the lowermost metallization layer (60) and the uppermost metallization layer (70) are the only metallization layers on the first side (30.1) of the semiconductor body (30).

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