METHOD FOR MANUFACTURING A SUPERCONDUCTING INTEGRATED CIRCUIT DEVICE

Abstract

A method of forming a superconducting integrated circuit device, comprising providing a Josephson junction (JJ) structure disposed on a first patterned superconducting layer, wherein the first patterned superconducting layer is formed from a first superconducting material disposed on a substrate. A cap layer comprising a first component and a second component is formed over the first patterned superconducting layer.Forming the cap layer comprises forming the first component from a sacrificial material in a first region of the cap layer, the first component surrounding the JJ structure, wherein at least a portion of a top surface of the JJ structure facing away from the substrate is uncovered by the sacrificial material, and forming the second component from a first dielectric material in a second region of the cap layer different from the first region. A via is formed in the cap layer over a portion of the first patterned superconducting layer. A second patterned superconducting layer made of a second superconducting material is formed overlying the top surface of the JJ structure and the via. The sacrificial material is removed. Thus, the JJ structure is not in contact with any dielectric material, thereby reducing dielectric losses.

Description

TECHNICAL FIELDThis disclosure relates generally to the field of superconducting integrated circuits and, more particularly, to integration concepts for Josephson junctions on substrates.BACKGROUNDElectronic devices including a superconducting integrated circuit are used in the art in various technical fields. For example, quantum computing devices that operate one or more superconducting quantum bits (qubits) rely on superconducting integrated circuits. Quantum computing based on these superconducting circuits forms a leading platform in an effort to implement quantum hardware capable of performing useful computations that are out of range of classical supercomputers. Circuits with up to several tens of superconducting qubits (and in some cases several hundred) have been used to demonstrate proof-of-concept computations within the current era of mid-scale noisy quantum (NISQ) technology, in which non-error corrected, error prone physical qubits are used to perform quantum simulations and quantum algorithms. First concept demonstrations of quantum error correction - the curative Gral in the field of quantum computations - have been achieved recently, but the requirements for higher coherence physical qubits have been further emphasized. One approach to implementing circuits for such a quantum computer is to generate qubits that include superconducting Josephson junctions and capacitors. Superconducting integrated circuits including Josephson junctions are also used in single-flow quantum (SFQ) devices and traveling wave parametric amplifiers (TWPAs).A central source of error in superconducting qubits is the dielectric loss. It occurs when electric fields of the circuit penetrate a dielectric material containing microscopic defects - so-called two-plane systems (TLS). Their origin is not fully understood, but they are often visualized as an atom or group of atoms oscillating between two spatial configurations in the amorphous dielectric. The dipole moment of a TLS couples to the electric field of the quantum circuit, resulting in a lifetime reduction of qubits. Since single low energy excitations are used to encode quantum states into qubits, such TLS interactions significantly affect the performance of physical qubits.Electric fields in superconducting qubit circuits occur between separate conductors at different electric potentials, such as in designed or parasitic circuit capacitors. A typical location where parasitic capacitors are present is in the immediate vicinity of three-layered Josephson junctions formed by two superconducting electrodes separated by a thin dielectric barrier (for example, alumina). While the Josephson junction itself has intrinsic capacitance due to its parallel plate configuration, additional parasitic capacitance arises from the fringe fields surrounding the Josephson junction and entering regions often filled with lossy dielectrics forming a dielectric cladding. Dielectric loss occurring in these regions degrades the performance of qubits built with such Josephson junctions.SUMMARYAccording to an aspect of the disclosure, a method of a superconducting integrated circuit device includes providing a Josephson Junction, JJ, structure disposed on a first patterned superconducting layer, the first patterned superconducting layer being formed of a first superconducting material disposed on a substrate. A capping layer including a first component and a second component is formed over the first patterned superconducting layer. Forming the capping layer includes forming the first component of a sacrificial material in a first region of the capping layer, the first component surrounding the JJ structure, at least a portion of an upper surface of the JJ structure facing away from the substrate being uncovered by the sacrificial material, and forming the second component of a first dielectric material in a second region of the capping layer different from the first region. A via is formed in the capping layer over a portion of the first patterned superconducting layer. A second patterned superconducting layer of a second superconducting material is formed overlying the top surface of the JJ structure and the via. The sacrificial material is removed.Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSThe elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments may be combined unless they are mutually exclusive and / or may be selectively omitted unless described as necessarily required. Embodiments are illustrated in the drawings and will be detailed in the following description by way of example. FIGS. 1, 2 a, 3- 4, 5 a, 6 a, and 7 aare schematic cross-sectional views illustrating stages of a method of manufacturing a superconducting integrated circuit device according to a first embodiment. FIGS. 2 b, 5 b, 6 band 7 bare schematic plan views further illustrating the steps of a method of manufacturing a superconducting integrated circuit device according to the first embodiment. FIGS. 8 to 11 are schematic cross-sectional views illustrating stages of a method of manufacturing a superconducting integrated circuit device according to a second embodiment.DETAILED DESCRIPTIONThe words "over" or "under" or similar words with respect to a portion, element, or material layer formed or disposed or placed "over" or "under" a surface may be used herein to mean that the portion, element, or material layer is "directly on" or "directly under" the implied surface (e.g., placed, formed, disposed, disposed, etc.), e.g., in direct contact therewith. However, the word "over" or "under" or similar words used with respect to a portion, element, or material layer formed or disposed or placed "over" or "under" a surface may be used herein to mean that the portion, element, or material layer is "indirectly on" or "indirectly under" the implied surface (e.g., placed, formed, disposed, deposited, etc.), with one or more additional portions, elements, or layers being disposed between the implied surface and the portion, element, or material layer.The following description exemplarily relates to methods of manufacturing a superconducting integrated circuit device including a Josephson junction. Superconducting integrated circuits (or devices) using a Josephson junction are examples of superconducting quantum circuits (or devices) because the Josephson effect is based on a quantum mechanical tunneling process.For example, the methods may be used to implement quantum computing devices. However, the disclosure is not limited to methods of manufacturing quantum computing devices. Rather, the disclosure covers basically all methods of manufacturing a superconducting integrated circuit device including a Josephson junction, i.e., a superconducting Josephson junction quantum circuit.In some examples, the superconducting integrated circuit may include, for example, a resonant circuit or may be a resonant circuit. A resonant circuit typically includes (at least) a capacitor and an inductor. The resonant circuit may be a linear resonant circuit (e.g., harmonic oscillator) or a nonlinear resonant circuit (e.g., anharmonic oscillator). In quantum devices, such resonant circuits are also referred to as quantum oscillators (QOs).One known technique used in quantum computing, for example, is to use a Josephson junction to make a resonant circuit nonlinear (or, in other words, the oscillator potential harmonic). In quantum computing devices, quantum-harmonic oscillators are used to "form" qubits. In other words, a non-linear resonant circuit may "form" a qubit (or operate as a qubit). Qubits generated by one or more (non-linear) Josephson junctions in a (thus non-linear) resonant circuit are sometimes also referred to in the art as "Josephson qubits".Other examples of superconducting Josephson junction quantum circuits are parametric Josephson amplifiers or parametric traveling wave amplifiers (TWPAs). These devices provide high gain with a bandwidth of several GHz, a high dynamic range, and (near) quantum limited noise. For example, to build a quantum processor with multiple qubits on a large scale, qubit readout by multiplexing is desirable, which requires amplifiers with a large bandwidth, a high dynamic range and a low additional noise. Such capability is provided by traveling wave parametric amplifiers (TWPAs).Other examples of electronic devices including a superconducting integrated circuit are single-flow quantum (SFQ) devices. Such devices are devices in which voltage pulses generated by Josephson junctions in the superconducting electronic (quantum) circuit (instead of the voltage levels generated by transistors in the semiconductor electronics) are used to encode, process and carry (classical) digital information. A superconducting integrated circuit including a plurality of SFQ devices enables formation of (R)SFQ logic ((fast) single-flow quanta).Referring to FIG. 1, a substrate 110 is provided. The substrate 110 may comprise or be, for example, a sapphire substrate or a silicon substrate, in particular a highly resistive crystalline silicon substrate. The substrate 110 serves as a support for a superconducting integrated circuit to be fabricated thereon. The substrate 110 may be unstructured or unprocessed, for example. Specifically, for example, no integrated circuits or integrated devices are formed in the substrate 110.A first patterned superconducting layer 120 of a first superconducting material is formed over the substrate 110. The first patterned superconducting layer 120 may be obtained by patterning an unpatterned continuous layer of the first superconducting material, which may be deposited on the entire substrate 110, for example. For example, the unstructured continuous layer of the first superconducting material may be deposited using a CVD process (chemical vapor deposition) or a PVD process (physical vapor deposition), in particular by sputtering. The first superconducting material is a material which can become superconducting at the operating temperature of the superconducting integrated circuit to be formed. Thus, the term "superconductive" refers to the conductivity state of the material at the operating temperature of the circuit. The superconducting material may comprise or consist of Al, Nb or Ta, for example.The unpatterned continuous layer of the first superconducting material may then be patterned to form the first patterned superconducting layer 120. The first patterned superconducting layer 120 includes a first superconducting structure 121 and a second superconducting structure 122 made of the first superconducting material. The superconducting structures 121, 122 may be electrically and / or structurally separated from one another, for example.For example, the first patterned superconducting layer 120 may be obtained by a patterning process using, e.g., a photolithography mask, a photoresist (not shown), and an etching process applied to the unpatterned continuous layer of the first superconducting material. Other patterning processes that may be compatible with semiconductor fabrication may also be used.A Josephson junction (JJ) layer stack 130 is formed over the first patterned superconducting layer 120 (which is already patterned into the superconducting structures 121, 122 in this embodiment). The JJ layer stack 130 may be a continuous, unstructured layer stack shown by the dot-dash line in FIG. 1. The JJ layer stack 130 may extend over, i.e. cover, the entire substrate 110, for example.The JJ layer stack 130 includes a JJ barrier layer (not shown). The JJ blocking layer is the functional layer of the JJ layer stack 130 providing a JJ tunnel.For example, the JJ layer stack 130 may include or consist of a three-layered stack of a superconducting / tunnel barrier / superconducting material, for example. Possible three layers include, among other things, Al / AlOx / Al, Nb / AlOx / Nb or Ta / AlOx / Ta layer stacks. For example, barrier layers other than AlOx(such as MgOx, etc.) may be used, and other combinations of superconducting materials may also be used.The JJ layer stack 130 may be deposited by sputtering or any other suitable deposition process. The JJ layer stack 130 may have a topography (i.e. be non-planar) due to (one) preceding patterning process(s) and optional additional patterned layers disposed on the substrate 110 and / or the first patterned superconducting layer 120, such as a patterned dielectric base layer.With continued reference to FIG. 1, the JJ layer stack 130 is then patterned to form a JJ structure 131. In particular, the portions of the JJ layer stack 130 overlying (overlapping) the optional first patterned dielectric base layer may be completely removed.Patterning the JJ layer stack 130 may include etching processes. For example, reactive ion etching (RIE) may be used for metal and dielectric etching of the JJ layer stack 130 to form the JJ structure 131. RIE is anisotropic and therefore suitable for forming the JJ structure 131 with (approximately) vertical sidewalls. As shown in FIG. 1, the JJ structure 131 is electrically contacted at its bottom with a structure of the first patterned superconducting layer 120, e.g., the second superconducting structure 122.Referring to FIG. 2 a, a first component 211 of a capping layer 210 is then formed in a first region, the first region extending over and around the JJ structure 131. In other words, the first component 211 of the cover layer 210 completely surrounds previously uncovered surfaces of the JJ structure 131. The first component 211 of the capping layer 210 may be obtained by patterning an unstructured continuous layer, which may e.g. cover the entire substrate 110, as illustrated by the dot-dash line in FIG. 2 a. The first component 211 of the capping layer 210 may be formed of a sacrificial material to be removed at a later stage, and may include or consist of one of the following: a photoresist, carbon, silicon oxide, silicon nitride, or a combination (oxynitride) of these materials. The material of the first component 211 of the cap layer 210 may be different from a material of the optional base dielectric layer (and thus may be selectively patterned). The material of the first component 211 may fill gaps between structures 121, 122 of the first patterned superconducting layer 120.FIG. 2 b illustrates a schematic top view of the intermediate product after forming the first component 211.As shown, the first component has a greater lateral extent than the JJ structure 131, such that it is completely surrounded by the first component 211 on an upper surface facing away from the first structured superconducting layer 120 and on side surfaces of the JJ structure 131. The first component may further cover a portion of the first and / or second superconducting structures 121, 122 of the first structured superconducting layer 120, as illustrated in FIGS. 2 aand 2 b.Referring to FIG. 3, a second component 311 of the cover layer 210 is then formed in a second region of the cover layer 210 that is different from the first region. For example, the second component 311 completely covers the portion of the first patterned superconducting layer 120 not covered by the first component 211. In other words, the capping layer 210 including the first component 211 and the second component 311 completely covers the substrate 110. In still other words, the second component 311 may be formed in or surround the same layer, i.e. the capping layer 210, adjacent to the sacrificial material of the first component 211, and may be an interlayer dielectric material. The second component 311 may be contiguous, e.g. laterally surrounding the first component 211, or divided by the first component 211 within the cover layer 210. The material of the second component 311 may fill gaps between structures 121, 122 of the first structured superconducting layer 120.The material of the second component 311 may be a dielectric material such as silicon oxide, silicon nitride or a combination (oxynitride) of these materials. In particular, the materials of the first and second components 211, 311 are such that the first component 211 can be selectively etched against the material of the second component 311 (and other involved materials such as a material of the JJ structure 131 or all materials forming the JJ structure 131 and the first structured superconducting layer 120). Thus, the first component 211 may be formed of a photoresist or carbon, while the second component 311 may be formed of, e.g., silicon nitride.With continued reference to FIG. 3, the capping layer 210 is thinned (e.g., polished back to the JJ structure 131 by chemical mechanical polishing (CMP)). The thinning may be performed before or after depositing the material forming the second component 311. The result of the thinning step is a (substantially) flat top surface (the surface facing away from the substrate 110) of the capping layer 120, with the top surface of the JJ structure 131 exposed at this stage of the fabrication process. In other words, a thickness of the first component 211 and the second component 311 may correspond to a thickness of the JJ structure 131 at least in the vicinity thereof, measured in a vertical direction perpendicular to a main extension plane of the substrate 110.Referring to FIG. 4, an opening 410 is formed in the capping layer 210 at a selected location, e.g., within the second component 311, adjacent to the first component 211, as illustrated. The opening 410 exposes a portion of a structure of the first patterned superconducting layer 120. Specifically, the opening 410 exposes a portion of the first superconducting structure 121 that is not in contact with the lower surface of the JJ structure 131. Forming the opening 410 of the capping layer 210 on the top surface of the JJ structure 212 may be performed by a dedicated via etch process, e.g., using RIE.Further openings may be formed in the capping layer at further selected locations for exposing portions of the first superconducting layer 120, e.g. for forming contact pads.Referring to FIG. 5 a, the opening 410 is filled with a superconducting material forming a via 511 in contact with the exposed portion of the first patterned superconducting layer 120, in particular, the first superconducting structure 121. As for the first superconducting material of the first patterned superconducting layer 120, the superconducting material for filling the opening 410 and thus forming the via 511 may include Al, Nb or Ta. The superconducting material of the via 511 may be the same as the first superconducting material.With continued reference to FIG. 5 a, a second patterned superconducting layer 510 of a second superconducting material is formed over the substrate cap layer 210 that overlies (overlaps) at least the top surface of the JJ structure 131 and the via 511. The second patterned superconducting layer 510, like the first patterned superconducting layer 120, may be obtained by patterning an unpatterned continuous layer of the second superconducting material, which may be deposited, e.g., on the entire cap layer 210. For example, the unstructured continuous layer of the second superconducting material may be deposited using a CVD process (chemical vapor deposition) or a PVD process (physical vapor deposition), in particular by sputtering. As for the first superconducting material of the first patterned superconducting layer 120, the second superconducting material may include or consist of, e.g., Al, Nb, or Ta. The superconducting material of the second patterned superconducting layer 510 may be the same as the first superconducting material or the superconducting material of the via 511.The unpatterned continuous layer of the second superconducting material may then be patterned to form the second patterned superconducting layer 510. The second patterned superconducting layer 510 forms an electrical connection between the JJ pattern 131 and the via 511. In other words, the second patterned superconducting layer 510 provides a third superconducting structure 512 connected to the upper surface of the JJ structure 131 and to the via 511, thereby effectively forming, e.g., an upper contact of the JJ structure 131 connected to the first superconducting structure 121.Forming the via 511 and the second patterned superconducting layer 510 (or depositing the unpatterned continuous layer from the second superconducting material) may be performed in a single step, e.g., the second superconducting material may fill the opening 410 and be deposited on the cap layer 210 in a single deposition process. Thus, the via 511 and the second patterned superconducting layer 510 may form a third superconducting structure 512 connecting the first superconducting structure 121 and the JJ structure 131, in particular the upper surface of the JJ structure 131, to each other after patterning.FIG. 5 b illustrates a schematic top view of the intermediate product after forming the second patterned superconducting layer 510. For illustrative purposes, the second component 311 of the cover layer 210 is excluded from this figure. As shown, the second patterned superconducting layer 510 covers the top surface of the JJ structure 131 and the via 511. Thus, the first superconducting structure 121 is electrically contacted to the upper surface of the JJ structure 131 through the via 511 and the second patterned superconducting layer 510.Forming the second patterned superconducting layer 510 exposes a portion of the first component 211 of the cap layer 210. In other words, a portion of the upper surface of the first component 211 of the cap layer 210 is not covered by, i.e., is free of, the second patterned superconducting layer 510. This facilitates the later removal of the sacrificial material of the first component 211, for example by means of an etching.Referring to FIG. 6 a, a patterned encapsulation layer 610 is formed. The patterned encapsulation layer 610 may be formed of a continuous, unstructured layer, for example, which may cover the entire arrangement before the patterning. The patterned encapsulation layer 610 covers the second patterned superconducting layer 510 and a portion of the first component 211 of the cap layer 210. The patterned encapsulation layer 610 may further cover a portion of the second component 311 of the cap layer 210, e.g. in areas where the second patterned superconducting layer 510 does not cover the first component 211. The patterned encapsulation layer 610 is formed from a second dielectric material, which may be one of the aforementioned dielectric materials, in particular from a low-loss dielectric material, such as silicon nitride. For example, the second dielectric material is the same as the first dielectric material of the second component 311 of the cap layer 210.In this exemplary embodiment, the second patterned superconducting layer 510 and the via 511 form the third superconducting structure 512 as described above, e.g., because these elements are formed of the same superconducting material and / or during the same processing step.FIG. 6 b illustrates a schematic top view of the intermediate product after forming the patterned encapsulation layer 610. For illustrative purposes, the second component 311 of the cover layer 210 is excluded from this figure. As shown, the patterned encapsulation layer 610 covers the top surface of the third superconducting structure 512 (or the second patterned superconducting layer 510). Thus, the third superconducting structure 512 is encapsulated by the patterned encapsulation layer 610.Forming the patterned encapsulation layer 610 exposes a portion of the first component 211 of the capping layer 210. In other words, a portion of the upper surface of the first component 211 of the cover layer 210 is not covered by, i.e. is free of, the structured encapsulation layer 610. This facilitates the later removal of the sacrificial material of the first component 211, for example by means of an etching.Referring to FIG. 7 a, the first component 211 of the capping layer 210 formed of the sacrificial material is removed. In other words, the sacrificial material forming the first component 211 is removed. The removal of the first component 211 may be achieved, for example, by means of a selective etch. Therein, an etchant used has a significantly higher etch rate with respect to the sacrificial material than an etch rate of the first dielectric material, the second superconducting material and the JJ structure 131 - typically also referred to as selectivity of the etch.Since a portion of the first component 211 is left free after forming the second patterned superconducting layer 510 and the optional patterned encapsulation layer 610, such exposed regions facilitate the etching process for removing the sacrificial material of the first component 211.After removing the sacrificial material of the first component 211, a cavity is formed instead of the first component 211. This means that the JJ structure 131 is laterally surrounded by the cavity after the removal of the sacrificial material. In other words, after removal, the JJ structure 131 is in vertical contact at its lower surface with the first patterned superconducting layer 120, e.g., the second superconducting structure 122, and at its upper surface with the second patterned superconducting layer 510, e.g., the third superconducting structure 512, while side surfaces of the JJ structure 131 are in contact with the cavity and thereby exposed to air. In particular, the JJ structure is not in contact with any dielectric material, e.g. the first dielectric material of the second component 311 of the cap layer 210 and the second dielectric material of the patterned encapsulation layer 610. Similarly, the JJ structure 131 is not in contact with any additional dielectric layers, such as the optional base layer as described above.FIG. 7 b illustrates a schematic top view of the intermediate product after removing the first component 211 of the cover layer 210.FIGS. 7 aand 7 b illustrate the superconducting integrated circuit device 10 according to this disclosure. It should be appreciated that this disclosure is intended to illustrate the formation of a JJ structure with a dielectric-free environment. Further processing methods and steps may be applied to the device, e.g. further formation of openings and layers for forming further contact pads and / or circuit elements.In the embodiment exemplified by FIGS. 1-7b, forming the capping layer 210 resulted in the latter being characterized by a planarized surface as illustrated in FIG. 3. This can be achieved by means of the aforementioned CMP step. In other embodiments, the cover layer 210 may be formed in alternative ways.In this regard, referring to FIGS. 8 to 11 illustrating exemplary stages of a second embodiment for manufacturing a superconducting integrated circuit device, the JJ structure 131 is formed on a first patterned superconducting layer 120 and encapsulated by the first component 211 of the cap layer 210, e.g., as described in connection with FIGS. 1, 2 aand 2 b. Reference is made to the above description to avoid repetition.Referring to FIG. 8, a second component 311 of the cover layer 210 is then formed in a second region of the cover layer 210 that is different from the first region. For example, the second component 311 completely covers the portion of the first patterned superconducting layer 120 not covered by the first component 211. In other words, the capping layer 210 including the first component 211 and the second component 311 completely covers the substrate 110. The second component 311 may be contiguous, e.g. laterally surrounding the first component 211, or divided by the first component 211 within the cover layer 210. The material of the second component 311 may fill gaps between structures 121, 122 of the first structured superconducting layer 120.The material of the second component 311 may be a dielectric material such as silicon oxide, silicon nitride or a combination (oxynitride) of these materials. In particular, the materials of the first and second components 211, 311 are such that the first component 211 can be selectively etched against the material of the second component 311 (and other involved materials such as materials forming the JJ structure 131 and the first patterned superconducting layer 120). Thus, the first component 211 may be formed of, e.g., a photoresist or carbon, while the second component 311 may be formed of, e.g., silicon nitride.It should be noted that, in this exemplary embodiment, the capping layer 210 is not necessarily planarized prior to further processing and may therefore have topographical features on its top surface, e.g., in a transition region between the first component 211 and the second component 311, as illustrated. A height of the topographical features may be characterized by a thickness of the first component 211 and a thickness of the second component 311.Referring to FIG. 9, a first opening 910 is formed in the capping layer 910 at a first selected location. The first opening 910 exposes at least a portion of the top surface of the JJ structure 131. A second opening 920 for exposing a portion of the first patterned superconducting layer 120 is formed analogous to the opening 410 described with reference to FIG. 4 of the first embodiment. The first and second openings 910, 920 may be formed in separate etching steps. Alternatively, the first and second openings 910, 920 may be simultaneously formed in a single etching step, wherein an etchant used is non-selective with respect to the sacrificial material of the first component 211 and the first dielectric material of the second component 311, and is selective with respect to the first superconducting material of the first patterned superconducting layer 120. Still alternatively, the first and second openings 910, 920 may both extend through the first component 211.Referring to FIG. 10, a third superconducting structure 1010 is formed in an analogous manner to the third superconducting structure 512 described with reference to FIG. 5 a. Forming the third superconducting structure 1010 may include filling the second opening 920 with a superconducting material to form a via and forming a second patterned superconducting layer of a second superconducting material covering the top surface of the JJ structure and the via. The superconducting material of the via and the second superconducting material may be the same as described above. They may be the same as the first superconducting material of the first patterned superconducting layer 120, respectively, or both. Forming the third superconducting structure 1010 exposes a portion of the first component 211.Referring to FIG. 11, a patterned encapsulation layer 1110 is formed in an analogous manner as the patterned encapsulation layer 610 described with reference to FIG. 6 a. The patterned encapsulation layer 1110 covers, e.g., completely covers, the third superconducting structure 1010 and partially covers the first component 211 so that a portion of the first component 211 is exposed.Subsequently, the sacrificial material of the first component 211 is removed in a similar manner to the removal described with reference to FIG. 7 a.The disclosure thus proposes various embodiments of a technique for forming three-layer Josephson junctions without close-by dielectrics. The fringe fields surrounding this dielectric-free three-layer Josephson junction during its operation are instead in the cavity surrounding the JJ structure, e.g. a vacuum, in which lossy defect TLS do not prevail. This significantly reduces the net budget for dielectric losses of the three-layer Josephson junction.Although specific examples have been illustrated and described herein, it will be understood by those of ordinary skill in the art that a variety of alternative and / or equivalent implementations may replace the specific examples shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, it is intended that this invention be limited only by the claims and their equivalents.It should be noted that the methods and apparatuses, including preferred embodiments thereof, as set forth herein may be used alone or in combination with the other methods and apparatuses disclosed herein. In addition, the features set out in connection with a device can also be applied to a corresponding method and vice versa. Moreover, all aspects of the methods and apparatus set forth in the present document may be combined as desired. In particular, the features of the patent claims can be combined with one another in any desired manner.It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements which, although not expressly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Moreover, all examples and embodiments set forth herein are intended to be expressly for illustrative purposes only in the nature of aid the reader in understanding the principles of the proposed methods and systems. Moreover, all statements herein providing principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.The following examples relate to further aspects of the disclosure:Aspect 1: Method of manufacturing a superconducting integrated circuit device, comprising:providing a Josephson junction, JJ, structure disposed on a first patterned superconducting layer, the first patterned superconducting layer being formed of a first superconducting material disposed on a substrate;forming a capping layer having a first component and a second component over the first patterned superconducting layer, wherein forming the capping layer comprises:forming the first component from a sacrificial material in a first region of the capping layer, the first component surrounding the JJ structure, wherein at least a portion of an upper surface of the JJ structure facing away from the substrate is uncovered by the sacrificial material; andforming the second component from a first dielectric material in a second region of the cover layer, which is different from the first region;forming a via in the cap layer over a portion of the first patterned superconducting layer;forming a second patterned superconducting layer of a second superconducting material overlying the top surface of the JJ structure and the via; andremoving the first component.Aspect 2: The method of Aspect 1, wherein forming the via comprises forming an opening in the capping layer at a selected location, thereby exposing the portion of the first patterned superconducting layer, and filling the opening with a superconducting material, in particular the first or second superconducting material, that interconnects the patterned first and second superconducting layers.Aspect 3: The method of Aspect 1 or 2, wherein the first and second superconducting materials are the same material.Aspect 4: The method of any of aspects 1 to 3, further comprising, prior to removing the first component, forming a patterned encapsulation layer of a second dielectric material over the second patterned superconducting layer and over a portion of the first component of the cap layer.Aspect 5: The method of Aspect 4, wherein the first and second dielectric materials are the same material.Aspect 6: The method of any of aspects 1 to 5, wherein forming the capping layer comprises performing a chemical mechanical polishing, CMP, step.Aspect 7: The method of any of aspects 1 to 6, wherein the sacrificial material is a material having the ability to be selectively etched with respect to the first dielectric material and a material of the JJ structure.Aspect 8: The method of any of aspects 1 to 7, wherein the sacrificial material is one of: a photoresist, an oxide, and carbon.Aspect 9: The method according to any one of aspects 1 to 8, wherein the first dielectric material is a nitride, in particular silicon nitride.Aspect 10: The method of any of aspects 1 to 9, wherein forming the second patterned superconducting layer comprises leaving a portion of the first component of the cap layer exposed.Aspect 11: The method of any of aspects 1 to 10, wherein forming the capping layer comprises filling a cavity in the first patterned superconducting layer with the sacrificial material or the first dielectric material.Aspect 12: The method of any of aspects 1 to 11, wherein forming the first component of the capping layer comprises laterally surrounding the JJ structure with the sacrificial material.Aspect 13: The method of any of aspects 1 to 12, wherein providing the JJ structure comprises:forming a first superconducting layer of the first superconducting material over the substrate;forming a JJ layer stack including a JJ blocking layer over the first superconducting layer;patterning the first superconducting layer to form the first patterned superconducting layer; andstructuring the JJ layer stack to form the JJ structure.Aspect 14: The method of aspect 13, wherein the patterning of the JJ layer stack is performed adjacent to the patterning of the first superconducting layer.Aspect 15: The method of any one of aspects 1 to 14, wherein the first patterned superconducting layer comprises a first superconducting structure contacting the via and a second superconducting structure connected to a bottom surface of the JJ structure facing the substrate.Aspect 16: The method of any of aspects 1 to 15, wherein the via and the second patterned superconducting layer form a third superconducting structure that interconnects the top surface of the JJ structure and the first patterned superconducting layer.Aspect 17: The method of any of aspects 1 to 16, wherein the first patterned superconducting layer provides a first superconducting structure, the second patterned superconducting layer provides a second superconducting structure, and wherein the second superconducting structure is connected to the JJ structure and to the first superconducting structure.Aspect 18: The method of any of aspects 1 to 17, wherein removing the sacrificial material provides a cavity laterally surrounding the JJ structure.Aspect 19: The method of any of aspects 1 to 18, wherein forming the capping layer comprises partially covering the top surface of the JJ structure with the sacrificial material.Aspect 20: The method of any one of aspects 1 to 19, wherein the first superconducting material and the second superconducting material each comprise one of Al, Nb, and Ta.Aspect 21: A superconducting integrated circuit device (10) comprising:a substrate;a first patterned superconducting layer disposed on the substrate;a Josephson junction, JJ, structure disposed on the first patterned superconducting layer in a first region;a cap layer disposed on the first patterned superconducting layer in a second region different from the first region; anda bonding structure that bonds a top surface of the JJ structure facing away from the substrate and a portion of the first patterned superconducting layer to each other;wherein the JJ structure is laterally surrounded by a cavity.

Claims

A method of manufacturing a superconducting integrated circuit device (10), the method comprising: - providing a Josephson Junction, JJ, structure (131) disposed on a first patterned superconducting layer (120), wherein the first patterned superconducting layer (120) is formed of a first superconducting material disposed on a substrate (110); forming a capping layer (210) having a first component (211) and a second component (311) over the first patterned superconducting layer (120), wherein forming the capping layer (210) comprises: forming the first component (211) of a sacrificial material in a first region of the capping layer (210), wherein the first component (211) surrounds the JJ structure (131), wherein at least a portion of an upper surface of the JJ structure (131) facing away from the substrate (110) is uncovered by the sacrificial material; and forming the second component (311) of a first dielectric material in a second region of the capping layer (210) different from the first region; forming a via (511) in the capping layer (210) over a portion of the first patterned superconducting layer (120); forming a second patterned superconducting layer (510) of a second superconducting material overlying the top surface of the JJ structure (131) and the via (511); and removing the first component (211).The method of claim 1, wherein the first and second superconducting materials are the same material.The method of claim 1 or 2, further comprising, prior to removing the first component (211), forming a patterned encapsulation layer (610) of a second dielectric material over the second patterned superconducting layer (510) and over a portion of the first component (211) of the capping layer (210).The method of claim 3, wherein the first and second dielectric materials are the same material.The method of any of claims 1 to 4, wherein forming the capping layer (210) comprises performing a chemical mechanical polishing, CMP, step.The method of any of claims 1 to 5, wherein the sacrificial material is a material having the ability to be selectively etched with respect to the first dielectric material and a material of the JJ structure (131).The method of any one of claims 1 to 6, wherein the sacrificial material is one of: a photoresist, an oxide, or carbon.The method of any one of claims 1 to 7, wherein the first dielectric material is a nitride.The method of any one of claims 1 to 8, wherein forming the second patterned superconducting layer (510) comprises leaving a portion of the first component (211) of the capping layer (210) exposed.The method of any of claims 1 to 9, wherein forming the capping layer (210) comprises filling a cavity in the first patterned superconducting layer (120) with the sacrificial material or the first dielectric material.The method of any of claims 1 to 10, wherein forming the first component (211) of the capping layer (210) comprises laterally surrounding the JJ structure (131) with the sacrificial material.The method of any of claims 1 to 11, wherein providing the JJ structure (131) comprises: forming a first superconducting layer of the first superconducting material over the substrate (110); forming a JJ layer stack including a JJ barrier layer over the first superconducting layer; patterning the first superconducting layer to form the first patterned superconducting layer (120); and patterning the JJ layer stack to form the JJ structure (131).The method of claim 12, wherein the patterning of the JJ layer stack is performed adjacent to the patterning of the first superconducting layer.The method of any one of claims 1 to 13, wherein the first patterned superconducting layer (120) comprises a first superconducting structure (121) contacting the via (511) and a second superconducting structure (122) connected to a bottom surface of the JJ structure (131) facing the substrate (110).The method of any one of claims 1 to 14, wherein the via (511) and the second patterned superconducting layer (510) form a third superconducting structure (512) interconnecting the top surface of the JJ structure (131) and the first patterned superconducting layer (120).The method of any one of claims 1 to 15, wherein the first patterned superconducting layer (120) provides a first superconducting structure (121), the second patterned superconducting layer (510) provides a second superconducting structure (512), and wherein the second superconducting structure (512) is connected to the JJ structure (131) and to the first patterned superconducting layer (120).The method of any of claims 1 to 16, wherein removing the sacrificial material provides a cavity laterally surrounding the JJ structure (131).The method of any of claims 1 to 17, wherein forming the capping layer (210) comprises partially covering the top surface of the JJ structure (131) with the sacrificial material.The method of any one of claims 1 to 18, wherein the first superconducting material and the second superconducting material each comprise one of Al, Nb or Ta.A superconducting integrated circuit device (10) comprising: - a substrate (110); - a first patterned superconducting layer (120) disposed on the substrate (110); - a Josephson Junction, JJ, structure (131) disposed on the first patterned superconducting layer (120) in a first region; - a cap layer (210) disposed on the first patterned superconducting layer (120) in a second region different from the first region; and - a connection structure (512) connecting an upper surface of the JJ structure (131) facing away from the substrate (110) and a portion of the first patterned superconducting layer (120) to each other; - wherein the JJ structure (131) is laterally surrounded by a cavity.

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