Dual-gate power semiconductor device and method for controlling a dual-gate power semiconductor device

Abstract

A dual-gate IGBT (1) is presented, wherein the active region (1-2) comprises a first section (1-21) and a second section (1-22). Both sections can be controlled by two control signals (13-21, 13-22). For example, the active region (1-2) or a second section (1-22) of the active region (1-2) includes a second barrier region (115). For example, a first section (1-21) exhibits a first characteristic transfer curve, load current, as a function of the voltage of the first control signal (13-21), and the second section (1-22) exhibits a second characteristic transfer curve, load current, as a function of the voltage of the first control signal (13-21), wherein at least the second characteristic transfer curves are modifiable based on the voltage of the second control signal (13-22).

Description

Technical field

[0001] This specification relates to embodiments of a power semiconductor device and to embodiments of a method for manufacturing a power semiconductor device. In particular, this specification relates to a power semiconductor device having an IGBT configuration with differently designed IGBT regions and being controllable by two control signals, and to embodiments of a corresponding control method. background

[0002] Many functions of modern devices in automotive, consumer, and industrial applications, such as converting electrical energy and driving an electric motor or machine, rely on power semiconductor switches. For example, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes, to name a few, have been used for various applications, including but not limited to switches in power supplies and power converters.

[0003] A power semiconductor device typically comprises a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device.

[0004] Furthermore, in the case of a controllable power semiconductor device, e.g., a transistor, the load current path can be controlled by means of an insulated electrode, commonly referred to as the gate electrode. For example, upon receiving a corresponding control signal from, e.g., a driver unit, the control electrode can switch the power semiconductor device between a forward conducting state and a reverse conducting state.

[0005] The load current is typically conducted through an active region of the power semiconductor device. The active region is typically surrounded by an edge termination region, which is itself terminated by an edge of the chip.

[0006] To achieve specific switching behavior and / or charge carrier distributions in the semiconductor, e.g., in connection with the optimization of switching energies and / or saturation voltages, secondary control electrodes can be provided, which allow the device to be controlled in addition to the primary control electrodes. Such devices are typically referred to as dual-gate transistors or multi-gate transistors.

[0007] An IGBT with two separately controllable electrodes and an n-doped barrier region is known from publication DE 10 2014 117 364 A1. SUMMARY

[0008] The subject matter of the independent claims is presented. Features of exemplary embodiments are defined in the dependent claims.

[0009] According to one embodiment, a power semiconductor device comprises a semiconductor body coupled to a first load terminal and a second load terminal, and a drift region of a first conductivity type within the semiconductor body between the first load terminal and the second load terminal. The power semiconductor device further comprises an active region with a first section and a second section, both configured to conduct a load current between the first load terminal and the second load terminal. The power semiconductor device further comprises a plurality of first control electrodes in both the first section and the second section, the first control electrodes being electrically isolated from the first load terminal and the second load terminal.The power semiconductor device further comprises a plurality of second control electrodes in both the first and second sections, wherein the second control electrodes are electrically isolated from the first load terminal, the second load terminal, and the first control electrodes. The power semiconductor device further comprises a plurality of semiconductor channel structures within the semiconductor body in both the first and second sections. Each of the plurality of channel structures is associated with one of the first control electrodes. Each of the first control electrodes is configured to induce an inversion channel for conducting a portion of the load current in the associated semiconductor channel structure. The power semiconductor device further comprises a second-type barrier region in the second section beneath the semiconductor channel structures.The second barrier region is located between the semiconductor channel structures and the drift region. For example, the power semiconductor device includes the second barrier region of the second conductivity type only in the second section. The first section may be free of the second barrier region.

[0010] According to one embodiment, a power semiconductor device comprises a semiconductor body coupled to a first load terminal and a second load terminal, and a drift region of a first conductivity type within the semiconductor body between the first load terminal and the second load terminal. The power semiconductor device further comprises an active region with a first section and a second section, both configured to conduct a load current between the first load terminal and the second load terminal. The power semiconductor device further comprises a plurality of first control electrodes in both the first section and the second section, the first control electrodes being electrically isolated from the first load terminal and the second load terminal.The power semiconductor device further comprises a plurality of second control electrodes in both the first and second sections, wherein the second control electrodes are electrically isolated from the first load terminal, the second load terminal, and the first control electrodes. The power semiconductor device further comprises a plurality of semiconductor channel structures within the semiconductor body in both the first and second sections. Each of the plurality of channel structures is associated with one of the first control electrodes. Each of the first control electrodes is configured to induce an inversion channel for conducting a portion of the load current in the associated semiconductor channel structure. The power semiconductor device further comprises a second-type conductivity barrier region extending beneath the semiconductor channel structures in both the first and second sections.The second barrier region is located between the semiconductor channel structures and the drift region. The average dopant concentration of the second barrier region in the second section is greater than the average dopant concentration of the second barrier region in the first section. The average dopant concentration can be defined as the integral of the dopant concentration of the second barrier region in the respective section divided by the area of ​​that section.

[0011] According to one embodiment, a power semiconductor device comprises a semiconductor body coupled to a first load terminal and a second load terminal, and a drift region of a first conductivity type within the semiconductor body between the first load terminal and the second load terminal. The power semiconductor device further comprises an active region with a second section configured to conduct a load current between the first load terminal and the second load terminal. The power semiconductor device further comprises a plurality of first control electrodes in the active region, the first control electrodes being electrically isolated from the first load terminal and the second load terminal.The power semiconductor device further comprises a plurality of second control electrodes in the active region, wherein the second control electrodes are electrically isolated from the first load terminal, the second load terminal, and the first control electrodes. The power semiconductor device further comprises a plurality of semiconductor channel structures in the semiconductor body in the second section, wherein each of the plurality of channel structures is associated with one of the first control electrodes, and each of the first control electrodes is configured to induce an inversion channel for conducting a portion of the load current in the associated semiconductor channel structure. The power semiconductor device further comprises a second barrier region of the second conductivity type in the second section beneath the semiconductor channel structures. For example, the second section occupies the entire active region.For example, the second section occupies the entire active region, separating it from a reverse-conducting (RC) region, such as a reverse-conducting diode. For instance, the second section might be the only section of the power semiconductor device that incorporates an IGBT configuration. Alternatively, the power semiconductor device could also include the first section, which also features an IGBT configuration. The second barrier region is located between the semiconductor channel structures and the drift region.

[0012] According to one embodiment, a power semiconductor device comprises a semiconductor body coupled to a first load terminal and a second load terminal, and a drift region of a first conductivity type within the semiconductor body between the first load terminal and the second load terminal. The power semiconductor device further comprises a plurality of first control electrodes in the active region, wherein the first control electrodes are electrically isolated from the first load terminal and the second load terminal. The power semiconductor device further comprises a plurality of second control electrodes in the active region, wherein the second control electrodes are electrically isolated from the first load terminal, the second load terminal, and the first control electrodes.The power semiconductor device further comprises a plurality of source regions of the first conductivity type, which are electrically connected to the first load terminal in the active region. The power semiconductor device further comprises a body region of the second conductivity type, which separates the source regions from the drift region. The power semiconductor device further comprises a second barrier region of the second conductivity type in the active region, located below and separate from the body region. The second barrier region either divides the drift region into an upper section and a lower section, which is located below trench bottoms of the power semiconductor device, or it is located between the drift region and a first barrier region of the first conductivity type.

[0013] For example, the proportion of the area of ​​the first segment overlapping the second barrier region is smaller than the proportion of the area of ​​the second segment overlapping the second barrier region. Alternatively or additionally, the second barrier region may have a lower dopant concentration in the first segment compared to the second segment. For example, the second barrier region may be implanted with a lower dose in the first segment compared to the second segment. Each of these features—the smaller proportion of the respective segment overlapping the second barrier region and the lower dopant concentration—results in a lower average dopant concentration in the second barrier region in the first segment compared to the second segment.

[0014] Each of the first and second control electrodes can be arranged in a trench extending from a front face into the semiconductor body. The trenches encompassing one of the first control electrodes can be called first control trenches. The trenches encompassing one of the second control electrodes can be called second control trenches.

[0015] For example, the second section surrounds the first section.

[0016] For example, the first section contains a multitude of source trenches, each containing a source electrode electrically connected to the first load terminal. Similarly, the second section contains a multitude of source trenches, each containing a source electrode electrically connected to the first load terminal.

[0017] The first section can contain a greater number of source trenches per unit area than the second section. For example, the average number of source trenches arranged between adjacent semiconductor channel structures in the first section is greater than the average number of source trenches arranged between adjacent semiconductor channel structures in the second section.

[0018] Each pair of trenches defines a mesa. For example, semiconductor channel structures can be located within their respective mesas. Mesas containing a semiconductor channel structure can be referred to as active mesas because they contribute to the device's load current. Mesas free of a semiconductor channel structure can be referred to as inactive mesas because they do not contribute to the device's load current.

[0019] Each semiconductor channel structure can be located adjacent to a first control trench. Each channel structure can include a first conductivity-type source region connected to the first load terminal and a second conductivity-type body region, or a portion thereof. A first pn junction is formed between the source region and the body region. A second pn junction can be formed between the body region and the drift region. In the case of an optional first conductivity-type barrier region, the second pn junction can be formed between the body region and the first barrier region. In a conductive state of the semiconductor device, a conductive channel is formed across the channel structures by creating an inversion channel in the body region. The inversion channel connects the source region to the drift region in the conductive state.The semiconductor channel structures are associated with the (first or second) control trench, which is configured to induce the inversion channel into the respective semiconductor channel structure. Each (first or second) control trench and its associated semiconductor channel structure can be located adjacent to each other.

[0020] For example, all semiconductor channel structures can be located adjacent to a first control trench (in the active region, first section, or second section). For example, all semiconductor channel structures are associated with one of the first control electrodes. For example, no semiconductor channel structure is associated with one of the second control electrodes. In this case, no semiconductor channel structure can be located adjacent to one of the second control trenches. For example, (in the active region, first section, or second section) any mesa bounded by one of the second control trenches can be free of a semiconductor channel structure.Alternatively or additionally, in the active region or first section or second section, a semiconductor channel structure may be arranged adjacent to the first control trench but spaced apart from the second control trench in each mesa bounded by one of the first control trenches and one of the second control trenches.

[0021] According to one embodiment, a power semiconductor device comprises: a semiconductor body coupled to a first load terminal and a second load terminal; an active region with a first section and a second section, both configured to conduct a load current between the first load terminal and the second load terminal; electrically isolated from the first load terminal and the second load terminal; a plurality of first control electrodes in both the first section and the second section; and a plurality of second control electrodes in both the first section and the second section. The first control electrodes are configured to be exposed to a first control signal. The second control electrodes are configured to be exposed to a second control signal.A plurality of semiconductor channel structures are located in the semiconductor body and extend into both the first and second sections, each of the plurality of channel structures being associated with at least one of the first control electrodes, the respective at least one of the first control electrodes being configured to induce an inversion channel to the load current conduction in the associated semiconductor channel structure; wherein, in a forward bias state, the first section exhibits a first characteristic transfer curve, load current, as a function of the voltage of the first control signal; and the second section exhibits a second characteristic transfer curve, load current, as a function of the voltage of the first control signal, wherein at least the second characteristic transfer curves are modifiable based on the voltage of the second control signal.For a given voltage of the first control signal, corresponding to a forward conduction state of the power semiconductor device, the change in load current in the first section observed for a given change in the voltage of the second control signal is smaller compared to the corresponding change in load current in the second section. Optionally, both the first and second characteristic transfer curves can be modified based on the voltage of the second control signal.

[0022] The different characteristic transmission curves of the first and second sections may at least partially stem from the differences between the two sections with respect to the second barrier region.

[0023] For example, changing the voltage of the second control signal is a change from a voltage that corresponds to a blocking state between V th,p and V th,n, e.g. 0 V, corresponds to a voltage that corresponds to another blocking state below V th,p , e.g. -15 V, corresponds to, or vice versa. For example, V th,n A control threshold voltage, necessary to induce an inversion channel in the body region, can be, for example, 6 V. Furthermore, V th,p another control threshold, e.g. a negative voltage, under which a hole channel is induced around the respective trench, i.e. an inversion channel in the drift region, and can be, for example, -4 V or -1 V.

[0024] For example, the load current change in the first section is less than 30%, while the load current change in the second section is greater than 30%.

[0025] For example, the rate of change of the first characteristic output curve is positive regardless of the voltage of the second control signal, and the rate of change of the second characteristic output curve is positive or negative depending on the voltage of the second control signal.

[0026] According to a further embodiment, a power semiconductor device comprises: a semiconductor body coupled to a first load terminal and a second load terminal; an active region comprising a first section and a second section, both configured to conduct a load current between the first load terminal and the second load terminal; electrically isolated from the first load terminal and the second load terminal; a plurality of first control electrodes in both the first section and the second section; a plurality of second control electrodes in both the first section and the second section; and a plurality of semiconductor channel structures in the semiconductor body extending into both the first section and the second section, each of the plurality of channel structures being associated with at least one of the first control electrodes.wherein at least one of the first control electrodes is configured to induce an inversion channel to the load current conduction in the associated semiconductor channel structure. In the first section, a first average effective distance between (i) the channel structures controlled by the first control electrodes and (ii) the second control electrodes is greater than a corresponding second average effective distance in the second section.

[0027] According to another embodiment, a power semiconductor device comprises: a semiconductor body coupled to a first load terminal and a second load terminal; an active region with a first section and a second section, both configured to conduct a load current between the first load terminal and the second load terminal; electrically isolated from the first load terminal and the second load terminal; a plurality of first control electrodes in both the first section and the second section; and a plurality of second control electrodes in both the first section and the second section. The first control electrodes are configured to be exposed to a first control signal. The second control electrodes are configured to be exposed to a second control signal.A plurality of semiconductor channel structures are located within the semiconductor body and extend into both the first and second sections, each of which is associated with at least one of the first control electrodes. Each of these first control electrodes is configured to induce an inversion channel to the load current in the associated semiconductor channel structure. In the second section, the voltage of the second control signal influences the inversion channels controlled by the first control electrodes.

[0028] For example, the second barrier region is defined as a contiguous region within the second section. The second barrier region extends over at least 75% or at least 90% of the area of ​​the second section.

[0029] For example, the second barrier region is configured as a contiguous region with openings within the second section. The second barrier region is omitted within these openings. For example, the openings occupy at most 25% or at most 10% of the area of ​​the second section. The openings may, for example, extend laterally across at most one mesa or at most three mesas. For example, the openings have a lateral extent perpendicular to the trenches of at most 20% of the semiconductor body thickness. For example, the openings have a lateral extent perpendicular to the trenches of at most 30 µm or at most 15 µm. For example, all openings are in lateral overlap with only the first control trenches or only the second control trenches.

[0030] The first section can extend laterally over at least five mesas, or at least ten mesas, or at least twenty mesas. The first section can extend laterally over at least half the thickness of the semiconductor body, or over at least 50 µm.

[0031] The second section can extend laterally over at least five mesas, or at least 10 mesas, or at least 20 mesas. The second section can extend laterally over at least half the thickness of the semiconductor body, or over at least 50 µm.

[0032] For example, the second section is laterally segmented into a multitude of sections, with the sections of the second section literally separated from each other by sections of the first section.

[0033] The second barrier region is located beneath the semiconductor channel structures. The second barrier region is separated from the body region. For example, the optional first barrier layer and / or a portion of the drift zone and / or any other n-doped region can be located between the body region and the second barrier region. For example, the second barrier region is located within the drift region of the power semiconductor device, and the second barrier region is of the opposite conductivity type to the drift region. The second barrier region can divide the drift region into an upper section and a lower section beneath the trench bottoms. The upper section can be located between the channel structures and the second barrier region. Instead of the upper section of the drift region, the first barrier region of the first conductivity type can be located between the channel structures and the second barrier region.The first barrier region can have a higher dopant concentration than the drift region. The first barrier region can have a lower dopant concentration than the body region. The second barrier region can have a dopant concentration of 5e14 to 5e17, e.g., 1e15 cm. -3 up to 2e16xx cm -3 .

[0034] For example, the semiconductor body includes a rear-side emitter region of the second conductivity type in direct contact with the second load terminal.

[0035] For example, the influence of the voltage of the second control signal on the inversion channels controlled by the first control electrodes in the second section is greater than the corresponding influence in the first section.

[0036] For example, the number of second control electrodes per unit area in the second section, G2 / A2, is greater than the number of second control electrodes per unit area in the first section, G2 / A1.

[0037] For example, the total area of ​​the second section is at least 20% of the total area of ​​the active region.

[0038] For example, the total area of ​​the first section is at least 20% of the total area of ​​the active region. For example, the total area of ​​the first section is at least 30% of the remaining total area of ​​the active region not occupied by the second section.

[0039] According to another embodiment, a power semiconductor device comprises: a semiconductor body coupled to a first load terminal and a second load terminal; an active region with a second section configured to conduct a load current between the first load terminal and the second load terminal; electrically isolated from the first load terminal and the second load terminal; a plurality of first control electrodes in the second section; and a plurality of second control electrodes in the second section. The first control electrodes are configured to be exposed to a first control signal. The second control electrodes are configured to be exposed to a second control signal.A plurality of semiconductor channel structures are located in the semiconductor body and extend into the second section, each of the plurality of channel structures being associated with at least one of the first control electrodes, the respective at least one of the first control electrodes being configured to induce an inversion channel to the load current line in the associated semiconductor channel structure; wherein in the second section the voltage of the second control signal influences the inversion channels controlled by the first control electrodes.

[0040] For example, the second section features a second characteristic transfer curve, load current, as a function of the voltage of the first control signal, wherein the second characteristic transfer curve is variable based on the voltage of the second control signal. For a given voltage of the first control signal corresponding to a forward conduction state of the power semiconductor device, the resulting load current according to the second characteristic transfer curve has (i) a first value for the second control signal with the same value as the first control signal, and (ii) a second value for the second control signal with a value corresponding to the additive inverse of the first control signal, wherein (iii) the second value of the resulting load current is at most half or even at most one-third of the first value of the resulting load current.In some embodiments, the influence of the second control signal on the inversion channels controlled by the first control electrodes can be even greater, resulting in a second value of the resulting load current being at most 1 / 4 or at most 1 / 8 or even at most 1 / 12 of the first value of the resulting load current.

[0041] The aforementioned transfer curves for the first and second sections can lead to a characteristic overall transfer curve for the entire power semiconductor device, load current, as a function of the voltage of the first control signal, whereby the characteristic overall transfer curve is variable based on the voltage of the second control signal. For a given voltage of the first control signal, which corresponds to a forward conduction state of the power semiconductor device (e.g.,If the voltage corresponds to 15 V, the resulting load current, according to the characteristic overall transfer curve, (i) has a first value for the second control signal with the same value as the first control signal, and (ii) has a second value for the second control signal with a value corresponding to the additive inverse of the first control signal, wherein (iii) the second value of the resulting load current is at most 90%, or even at most 80%, or even at most 70% of the first value of the resulting load current. In some embodiments, the influence of the second control signal on the inversion channels controlled by the first control electrodes may be even greater, resulting in a second value of the resulting load current being at most 1 / 4, or at most 1 / 8, or even at most 1 / 12 of the first value of the resulting load current.

[0042] Furthermore, in one example, the second section has a second characteristic transfer curve, load current, as a function of the voltage of the first control signal, wherein the second characteristic transfer curve is variable based on the voltage of the second control signal 13-22.

[0043] It should be noted that for each characteristic transfer curve described in this application, the following two preconditions are defined: (i) sufficient Vce between the first load terminal and the second load terminal (e.g., Vce > 10 V or Vce > 20 V or Vce = Vge); and (ii) the control signals (first and second control electrodes) are set to an “operating gate voltage” or “nominal ON voltage” (e.g., 15 V, 5 V, 1.5 V).

[0044] For example, the first control electrodes are arranged in first control trenches and insulated from the semiconductor body by a first trench insulator. For example, the second control electrodes are arranged in second control trenches and insulated from the semiconductor body by a second trench insulator. For example, the semiconductor channel structures are arranged in mesas of the semiconductor body, the mesas being laterally bounded at least by the control trenches.

[0045] For example, in the second section at least some of the mesas are laterally bounded by one of the first and one of the second tax ditches.

[0046] For example, the semiconductor channel structures comprise a source region of a first conductivity type that is electrically connected to the first load terminal, with the source regions in the second section being located adjacent to the first control electrodes and spatially offset from the second control electrodes. Therefore, within the second section or in the entire active area, no source region can be located adjacent to either of the second control electrodes.

[0047] For example, the first barrier region is located between the semiconductor channel structures and a drift region of the power semiconductor device, wherein the first barrier region is of the same conductivity type as the drift region, and wherein the average dopant concentration of the first barrier region in the first section is greater than the average dopant concentration of the first barrier region in the second section. For example, the first barrier region is located between the semiconductor channel structures and the second barrier region.

[0048] For example, the average distance between each of the first control electrodes and each of the second control electrodes in the first section is greater than the corresponding average distance in the second section.

[0049] For example, the semiconductor body is formed in a single semiconductor chip.

[0050] For example, the active region further includes a third section containing a subset of the second control electrodes, with the third section forming a diode section, so that the power semiconductor device has an RC-IGBT configuration.

[0051] According to a further embodiment, a method for operating a half-bridge circuit is presented, comprising a first power semiconductor device with a configuration as described in the preceding paragraph and a second power semiconductor device with a configuration as described in the preceding paragraph. The method comprises: providing a first control signal to the multiple first control electrodes of the first power semiconductor device and providing a second control signal to the multiple second control electrodes of the first power semiconductor device; and providing a further first control signal to the multiple first control electrodes of the second power semiconductor device and providing a further second control signal to the multiple second control electrodes of the second power semiconductor device.

[0052] The expert will recognize additional features and advantages upon reading the following detailed description and upon examining the accompanying drawings. Brief description of the drawings

[0053] The parts in the figures are not necessarily to scale; instead, the focus is on illustrating the principles of the invention. Furthermore, identical reference numerals in the figures denote corresponding parts. The drawings show: Fig. 1 schematically and by way of example a section of a horizontal projection of a power semiconductor device according to one or more embodiments; Fig. 2 schematically and by way of example three variants (A), (B) and (C) of a section of a horizontal projection of a power semiconductor device according to some embodiments; Fig. 3 schematically and by way of example a respective section of a vertical cross-section of a first section of an active region of power semiconductor devices according to at least three embodiments; Fig. 4 schematically and by way of example two variants (A) and (B) of a section of a vertical cross-section of a second section of an active region of power semiconductor devices according to one or more embodiments; Fig. 5 schematic and exemplary characteristic transfer curves with respect to a first section and a second section of an active region of a power semiconductor device according to one or more embodiments; Fig. 6 schematically and by way of example a section of a vertical cross-section of a second section of an active region of power semiconductor devices according to one or more embodiments; Fig. 7 schematically and by way of example a section of a horizontal projection of a power semiconductor device according to one or more embodiments; Fig. 8. A schematic and exemplary diagram of a half-bridge circuit according to one or more embodiments; Fig. 9. A schematic and exemplary method for controlling a half-bridge circuit according to one or more embodiments; Fig. 10 schematically and by way of example a section of a vertical cross-section of a power semiconductor device according to one or more embodiments; Fig. 11. A schematic and exemplary method for controlling a power semiconductor device according to one or more embodiments; Fig. 12 schematically and by way of example two variants (A), (B) of a section of a horizontal projection of a power semiconductor device according to some embodiments; Fig. 13. Schematically and by way of example, eight different exemplary forms of a second barrier region according to one or more embodiments in a section of a vertical cross-section; and Fig. 14 schematically and by way of example in a section of a vertical cross-section four different exemplary contact schemes of an IGBT according to one or more embodiments. Detailed description

[0054] The following detailed description refers to the accompanying drawings, which form a part thereof and in which specific embodiments in which the invention can be implemented are shown for illustration.

[0055] In this respect, directional terminology such as "above," "below," "under," "front," "back," "leading," "trailing," "over," etc., may be used with reference to the orientation of the described figures. Since parts of embodiments can be positioned in a number of different orientations, the directional terminology is used for illustrative purposes and is in no way limiting. It is understood that other embodiments may be used and structural or logical modifications may be made without deviating from the scope of protection of the present invention. The following detailed description is therefore not to be understood as limiting, and the scope of protection of the present invention is defined by the accompanying claims.

[0056] Various embodiments will now be discussed in detail, one or more examples of which are illustrated in the figures. Each example is provided for illustrative purposes and is not intended to limit the invention. For example, features illustrated or described as part of one embodiment may be used in or in combination with other embodiments to produce yet another embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only.For the sake of clarity, the same elements or manufacturing steps in the different drawings have been designated with the same reference symbols, unless otherwise specified.

[0057] The term "horizontal," as used in this specification, is intended to describe an orientation essentially parallel to a horizontal surface of a semiconductor substrate or structure. This could be, for example, the surface of a semiconductor wafer, die, or chip. For example, both the first lateral direction X and the second lateral direction Y mentioned below can be horizontal directions, with the first lateral direction X and the second lateral direction Y being perpendicular to each other.

[0058] The term "vertical," as used in this specification, is intended to describe an orientation that is essentially perpendicular to the horizontal surface, i.e., parallel to the normal direction of the semiconductor wafer / chip / die's surface. For example, the extension direction Z mentioned below can be an extension direction that is perpendicular to both the first lateral direction X and the second lateral direction Y.

[0059] In this specification, n-doped is referred to as the "first conductivity type," while p-doped is referred to as the "second conductivity type." Alternatively, opposite doping relationships can be used, so that the first conductivity type can be p-doped and the second conductivity type can be n-doped.

[0060] In the context of this specification, the terms "in ohmic contact," "in electrical contact," "in ohmic connection," and "electrically connected" are intended to describe the existence of a low-resistance electrical connection or current path between two regions, sections, zones, segments, or parts of a semiconductor device, or between different terminals of one or more devices, or between a terminal or metallization or electrode and a section or part of a semiconductor device, where "low resistance" may mean that the properties of the respective contact are not substantially affected by the ohmic resistance. Furthermore, in the context of this specification, the term "in contact" is intended to describe the existence of a direct physical connection between two elements of the respective semiconductor device; e.g.,A transition between two elements that are in contact with each other cannot include any further intermediate element or the like.

[0061] Additionally, in the context of this specification, unless otherwise stated, the term "electrical isolation" is used in its generally accepted sense and is intended to describe a situation where two or more components are positioned separately and there is no ohmic connection between them. However, components that are electrically isolated from each other may still be coupled, for example, mechanically coupled and / or capacitively coupled and / or inductively coupled and / or electrostatically coupled (for example, in the case of a junction). To give an example, two electrodes of a capacitor may be electrically isolated from each other and simultaneously mechanically and capacitively coupled, for example, by means of an insulator such as a dielectric.

[0062] Specific embodiments described in this specification relate, but are not limited to, a power semiconductor device, such as a power semiconductor device that can be used within a power converter or power supply. Thus, in one embodiment, such a device may be configured to carry a load current that is to be supplied to a load or that is provided by a power source. For example, the power semiconductor device may comprise one or more active power semiconductor unit cells, such as a monolithically integrated diode cell, a derivative of a monolithically integrated diode cell (e.g., a monolithically integrated cell of two anti-series connected diodes), a monolithically integrated transistor cell, e.g., a monolithically integrated MOSFET or IGBT cell, and / or derivatives thereof.Such diode / transistor cells can be integrated into a power semiconductor module. A multitude of such cells can form a cell array that is arranged with an active region of the power semiconductor device.

[0063] The term "blocking state" of a power semiconductor device can refer to conditions when the semiconductor device is in a state configured to block current flow through it while an external voltage is applied. Specifically, the semiconductor device can be configured to block forward current flow while a forward voltage bias is applied. Conversely, the semiconductor device can be configured to conduct forward current in a "conducting state" when a forward voltage bias is applied. A transition between the blocking and conducting states can be controlled by a control electrode or, more specifically, by the potential of the control electrode.

[0064] The term "power semiconductor device," as used in this specification, is intended to describe a semiconductor device on a single chip with high voltage blocking and / or high current carrying capacities. In other words, such a power semiconductor device is designed for high currents, typically in the ampere range, e.g., up to several tens or hundreds of amperes, and / or high voltages, typically above 15 V, typically 100 V and above, e.g., up to at least 400 V or even more, e.g., up to at least 3 kV or even up to 10 kV or more, depending on the specific application.

[0065] For example, the term "power semiconductor device" as used in this specification does not refer to logic semiconductor devices used, for example, for storing data, calculating data and / or other types of semiconductor-based data processing.

[0066] The present specification relates in particular to a power semiconductor device designed as an IGBT or as an RC-IGBT, i.e. a bipolar power semiconductor transistor or a derivative thereof.

[0067] For example, the power semiconductor device described below can be implemented on a single semiconductor chip, which may have a strip cell configuration (or a cell / needle cell configuration) and can be configured to be used as a power component in a low, medium and / or high voltage application.

[0068] Fig. Figure 1 illustrates a section of a horizontal projection of a power semiconductor device 1 according to one or more embodiments. Fig. Figure 10 illustrates a corresponding section of a (simplified) vertical cross-section. The power semiconductor device 1 can, for example, have a MOSFET or an IGBT configuration and comprises a semiconductor body 10 coupled to a first load terminal 11 and a second load terminal 12. The power semiconductor device 1 includes an active region 1-2. With reference to Fig. 2 (A) The active region 1-2 of the power semiconductor device 1 has a first section 1-21 and a second section 1-22, both sections 1-21 and 1-22 being configured to carry a load current between the first load terminal 11 and the second load terminal 12. With reference to Fig. 2 (B) The active region 1-2 of the power semiconductor device 1 has a second section 1-22, wherein the second section 1-22 is configured to conduct a load current between the first load terminal 11 and the second load terminal 12. In the embodiment of Fig. 2 (B) the active region 1-2 of the power semiconductor device 1 is free from the first section 1-21.

[0069] As in Fig. As illustrated in Figure 10, the semiconductor body 10 can be sandwiched between the first load terminal 11 and the second load terminal 12. Therefore, the power semiconductor device 1 can have a vertical configuration such that the load current in both sections 1-21 and 1-22 follows a path substantially parallel to the vertical direction Z.

[0070] The active area 1-2, which includes both sections 1-21 and 1-22, may be bounded by a boundary 1-20, with the active area 1-2 transitioning into a boundary closure region 1-3, which in turn is closed by a chip boundary 1-4.

[0071] Here, the terms active region and edge termination region are used in a technical context that a person skilled in the art typically associates with these terms. Accordingly, the purpose of the active region is primarily to ensure the conduction of the load current, whereas the edge termination region 1-3 is configured to reliably terminate the active region 1-2, e.g., with respect to the electric field profiles during the conduction state and during the blocking state.

[0072] With further reference to Fig. 3, Fig. 4 and Fig. 6 further comprises the power semiconductor device 1, electrically insulated from the first load terminal 11 and the second load terminal 12, a plurality of first control electrodes 141 in both the first section 1-21 and the second section 1-22 and a plurality of second control electrodes 151 in both the first section 1-21 and the second section 1-22 (see Fig. 3 for the first section 1-21 and Fig. 4 and Fig. 6 for the second section 1-22).

[0073] In the context of power semiconductor devices with an IGBT configuration, these control electrodes are typically referred to as gate electrodes. The control signal can be generated by applying a voltage, e.g., between the first load terminal 11 and a control / gate terminal (see Figure 1). Fig. 8, connections 13-1A, 13-2A, 13-1B and 13-2B).

[0074] For example, each of the multitude of first control electrodes 141 is electrically connected to at least one first control terminal 13-1A (see Fig. 8), and each of the plurality of second control electrodes 151 is electrically connected to at least one second control terminal 13-2A, wherein each of the at least one first control terminal 13-1A is electrically isolated from each of the at least one second control terminal 13-2A. This allows the first control electrodes 141 to be subjected to a first control voltage independently of the second control electrodes 151, which can be subjected to a second control voltage. For example, the first control voltage is generated as a voltage between the first control electrodes 141 (or the first control terminal(s) 13-1A) and the first load terminal 11, and the second control voltage is generated as a voltage between the second control electrodes 151 (or the second control terminal(s) 13-2A) and the first load terminal 11. The first control voltage may differ from the second control voltage.In another embodiment, the second control electrodes 151 are coupled to the first control electrodes 141 via an RC structure which has defined ohmic and capacitive properties, so that the second control signal can be derived from the first control signal and only one gate connection is required for both the first control electrodes 141 and the second control electrodes 151.

[0075] The power semiconductor device 1 further comprises a plurality of semiconductor channel structures in the semiconductor body 10, extending into both the first section 1-21 and the second section 1-22. Each of the plurality of channel structures is associated with at least one of the first control electrodes 141, the respective at least one of the first control electrodes 141 being configured to induce an inversion channel to the load current line in the associated semiconductor channel structure.

[0076] Each channel structure can comprise a source region 101 of the first conductivity type and a body region 102 of the second conductivity type, both electrically connected to the first load terminal 11, wherein the body region 102 isolates the source region 101 from a drift region 100 of the power semiconductor device 1, as described in the Fig. 3 and Fig. 4 below is explained in more detail. The inversion channel in the respective associated channel structure can be induced by subjecting the respective first control electrode 141 to the first control voltage.

[0077] The first section 1-21 of the active region 1-2 exhibits a first characteristic transfer curve, i.e., a characteristic load current, as a function of the voltage of the first control signal 13-21 during the forward bias state. An example of the first characteristic transfer curve is shown in Fig. 5, left part, illustrated.

[0078] The second section 1-22 of the active region 1-2 exhibits a first characteristic transfer curve, i.e., a characteristic load current, as a function of the voltage of the first control signal 13-21 during the forward bias state. An example of the second characteristic transfer curve is shown in Fig. 5, right part, illustrated.

[0079] Since in one embodiment (see Fig. 2(A)) the second control electrodes 152 are present in both the first section 1-21 and the second section 1-22, at least the second characteristic transfer curves are modifiable based on the voltage of the second control signal 13-22. Optionally, both the first and the second characteristic transfer curves can be modifiable based on the voltage of the second control signal 13-22.

[0080] In one embodiment, for a given voltage of the first control signal, corresponding to a forward conduction state of the power semiconductor device, the change in load current in the first section observed for a given change in the voltage of the second control signal 13-22 is smaller compared to the corresponding change in load current in the second section 1-22. This exemplary difference between the first section 1-21 and the second section 1-22 is shown in Fig. Figure 5 illustrates a transition temperature of 25 °C. Accordingly, the change in the voltage of the second control signal 13-22 (V) can be GE2 ) a change in voltage that results in a blocking state between V th,p and V th,n , e.g. 0 V, corresponds to a voltage that corresponds to another blocking state below V th,p , e.g. -15 V or -8 V, or vice versa.

[0081] If available, see section 1-21 (left part of) Fig. 5) such a change in the second control signal 13-22 (V GE2 ) comparatively little influence on the first characteristic transfer curve; the threshold voltage is increased slightly and the rate of change of the load current I C about the voltage of the first control signal 13-21 (V GE1 ) is reduced compared to the case where the second control signal 13-22 (V GE2 ) regarding the voltage value with the first control signal 13-21 (V GE1 ) or 0 V is identical.

[0082] In contrast, due to the design of the second section 1-22, examples of which are explained below, such a change in the voltage of the second control signal 13-22 (V) GE2 ) from e.g. 0 V to -15 V has a significant influence on the second characteristic transfer curve: There, the rate of change of the current I reaches Cabout the voltage of the first control signal 13-21 (V GE1 ) a maximum, and then the load current I increases C only slightly with increasing voltage of the first control signal 13-21 (V GE1 For example, for a given voltage of the first control signal 13-21 (V GE1 ), e.g. 15 V, the load current change in the first section 1-21 is less than 40%, e.g., less than 30% or 20%, and the load current change in the second section 1-22 is greater than 30% or even greater than 40%, e.g., greater than 75%, e.g., greater than 100%. The load current change of the entire structure (1-21 and 1-22) is greater than 10% or even greater than 20% or even greater than 35%.

[0083] With regard to the above, it is understood that the change in the voltage of the second control signal 13-22 (V GE2 ) from 0 V to the value of the voltage of the first control signal 13-21 (V GE1 ), i.e. V GE2 = V GE1, was an illustrative example. For both sections 1-21 and 1-22, source regions 101 can be arranged adjacent to the second control signal; if the voltage of the second control signal 13-22 (V GE2 ) the threshold value V th,n If the limit is exceeded, further electrons can be injected, which may be desirable in some applications and should be avoided in others. Accordingly, in Fig. 4, variant (A), the source region 101 is arranged adjacent to both the first control trench 14 and the second control trench 15 (with a corresponding influence of the voltage of the second control signal 13-22 (V) GE2 ) on electron injection), in Fig. In variant 4 (B), the source region 101 in Mesa 18 is located only adjacent to the first control trench 14, but not adjacent to the second control trench 15 (with a correspondingly reduced influence of the voltage of the second control signal 13-22 (V)).GE2 ) on electron injection).

[0084] More generally speaking, with reference to Fig. 5, right part / second section 1-22, the second section 1-22 in one embodiment a second characteristic transfer curve (i.e. load current as a function of the voltage of the first control signal 13-21 (V GE1 )) on, where the second characteristic transfer curve is based on the voltage of the second control signal 13-22 (V GE2 ) is variable. For a given voltage of the first control signal 13-21 (V GE1 ), which corresponds to a forward conduction state of the power semiconductor device, the resulting load current according to the second characteristic transfer curve (i) has a first value for the second control signal with the same value as the first control signal (V). GE1 = V GE2), and (ii) a second value for the second control signal with a value corresponding to the additive inverse of the first control signal (e.g. V GE2 = -V GE2 , cf. lower dashed line), where (iii) the second value of the resulting load current is at most half or even at most one-third of the first value of the resulting load current, as exemplified in Fig. 5 illustrates.

[0085] In one embodiment, a first average effective distance in the first section 1-21 between (i) the channel structures controlled by the first control electrodes 141 and (ii) the second control electrodes 151 is greater than a corresponding second average effective distance in the second section 1-22. This allows the effect of the voltage of the second control signal 13-21 (V) to be GE2The effects observed in the second section (1-22) are reduced in the first section (1-21) compared to the effect observed in the second section (1-22), for example, in a manner as described above. More specific implementation examples are described below.

[0086] With reference to Fig. In variants (A) and (B), the mean effective distances depend on the width of the mesa 18; the wider the mesa 18, the greater the distance between the channel structures (in body region 102) controlled by the first control electrodes 141 and the second control electrode 151. For example, the width of the mesa 18 (i.e., the mean distance between the adjacent trench insulators 142, 152 along the first lateral direction X) can be less than 2 µm, less than 1.5 µm, or even less than 700 nm. Alternatively or additionally, the mean effective distances can be modified based on the dopant concentration in the mesa 18, e.g., by increasing the concentration of the dopant in the mesa 18. B. based on the provision of the first barrier region 105 of the first conductivity type, which can be implemented optionally and can have a dopant concentration that is significantly larger than the dopant concentration of the drift region 100.The higher the dopant concentration of the first barrier region 105, the greater the average effective distance between the source region 101 and the second control electrode. For example, the dose of the first barrier region 105 can be 1 × 10⁻⁵. 13 cm -2 If such a first barrier region is present, the above-mentioned physical mesa widths (“less than 2 µm, less than 1.5 µm or even less than 700 nm”) could be reduced to less than 1.5 µm, less than 700 nm or even less than 400 nm without changing the average effective distance compared to the case in which no first barrier region 105 is implemented.

[0087] In another embodiment, the voltage of the second control signal 13-22 (V) influences the second section 1-22. GE2 ) the inversion channels, which are controlled by the first control electrodes 141, e.g. as described above and in Fig. 5, right part, illustrated. For example, the influence of the voltage of the second control signal 13-22 (V) is shown. GE2 ) on the inversion channels controlled by the first control electrodes 141 in the second section 1-22, greater than the corresponding influence in the first section 1-21. The inversion channels can refer to the hole channels around the first and second control trenches 14, 15 in the drift region 100.

[0088] For example, the total area of ​​the second section 1-22 is at least 10%, at least 20%, 30%, or at least 45% of the total area of ​​active region 1-2. Or the total area of ​​the second section 1-22 is within the range of 70% to 130% of the total area of ​​the first section 1-21. The total area of ​​the first section 1-21 can be at least 30% of the remaining total area of ​​active region 1-2 not occupied by the second section 1-22. The second section 1-22 can surround the first section 1-21, as shown in Fig. 2 illustrated.

[0089] It should be noted that, in addition to sections 1-21 and 1-22, the power semiconductor device may include further sections 1-2 within its active region, e.g., sections configured similarly to section 1-22, but where the difference compared to section 1-21 is implemented to a lesser or greater extent. For example, in a first variation of the second section 1-22, the maximum rate of change of the current I is C about the voltage of the first control signal 13-21 (V GE1 ) at 20% of the nominal load current I C reached, and in a second variation of the second section 1-22, the maximum of the rate of change of the current I is determined. C about the voltage of the first control signal 13-21 (V GE1 ) at 50% of the nominal load current I C reached, and in a third variation of the second section 1-22, the maximum of the rate of change of the current I is reached. Cabout the voltage of the first control signal 13-21 (V GE1 ) at 150% of the nominal load current I C reached.

[0090] The embodiments described above include the following features: The active region 1-2 of the power semiconductor device 1 can be subdivided into one or more first sections 1-21 and one or more second sections 1-22, these spatially distinct sections being configured differently to achieve desirable switching characteristics of the power semiconductor device 1. Both sections 1-21 and 1-22 are controlled based on both control signals, with the second control signal having less effect on the first section 1-21 compared to the second section 1-22, for example, if the value of the voltage of the second control signal is increased by V th,p, e.g., from 0 V to -8 V or vice versa. According to some embodiments, both sections 1-21 and 1-22 are controlled based on both control signals, with the second control signal having less effect on the first section 1-21 compared to the second section 1-22, for example, when the value of the voltage of the second control signal is above V th,n e.g. from 0 V to V GE2 = V GE1 or vice versa. For example, by providing the first and second control signals not completely synchronously, but with a time delay, an advantageous switching behavior can be achieved, as explained in more detail below.

[0091] According to the in Fig. 3 and Fig. In the four illustrated embodiments, the first control electrodes 141 are arranged in first control trenches 14 and are insulated from the semiconductor body 10 by a respective first trench insulator 142. Similarly, the second control electrodes 151 are arranged in second control trenches 15 and are insulated from the semiconductor body 10 by a respective second trench insulator 152.

[0092] Furthermore, the semiconductor channel structures are arranged in mesas 18 of the semiconductor body 10, wherein the mesas 18 are laterally bounded at least by the control trenches 14, 15.

[0093] As further illustrated, the power semiconductor device 1 according to these embodiments comprises a plurality of source trenches 16 in at least the first section 1-21 and optionally also the second section 1-22, wherein each source trench 16 comprises a source electrode 161 which is electrically connected to the first load terminal 11 and is insulated from the semiconductor body 10 by a respective third trench insulator 162.

[0094] The trench-mesa pattern, which is shown in the simplified illustration of Fig. The mesa 10, which is not shown, is configured on a front face 110. The mesas 18, which comprise the channel structures, are electrically connected to the first load terminal 11, e.g., via first contact plugs 111. For example, in each mesa 18, the contact plug 111 is electrically connected to both the source region 101 and the body region 102.

[0095] In addition to the mesas 18, the trench-mesa pattern can include a second-type mesa 19 that does not include a source region 101 and that can be connected to the first load connection 11 (see Fig. 3, variants (1) to (3)) or not (cf. Fig. 3, variant (2), middle mesa 19). However, the second type of mesa 19 can also be equipped with a section of body region 102, as illustrated.

[0096] Optionally, a first barrier region 105 can be arranged between the body region 102 and the drift region 100. Both the first barrier region 105 and the drift region 100 are of the first conductivity type, whereby the dopant concentration of the first barrier region 105 can be higher than that of the drift region.

[0097] Briefly also with reference to Fig. 10 the drift region 100 extends along the vertical direction Z until it is connected to the emitter region 108 of the second conductivity type, which is electrically connected to the second load terminal 12, according to one or more embodiments.

[0098] The trench-mesa pattern in the first section 1-21 can be configured in various ways, some examples of which are presented below: For example, with reference to Fig. Variant 3 (1) defines Mesa 18 laterally bounded by one of the first control ditches 14 and one of the source ditches 16, but not by one of the second control ditches 15. Together with the source ditch 16, the second control ditch 15 laterally bounds Mesa 19 of the second type. Mesa 19 of the second type may or may not include a source region 101. Similarly, in Variant 2, Mesa 18 is laterally bounded by one of the first control ditches 14 and one of the source ditches 16, but not by one of the second control ditches 15. Together with the first control ditch 14, the second control ditches bound Mesa 19 of the second type, which is not electrically connected to the first load terminal 11 (i.e., acts as a dummy mesa), and together with the source ditch, they bound Mesa 19 of the second type, which is electrically connected to the first load terminal 11.Variant (3) corresponds to variant (1), except that the positions of the first control trench 14 and the source trench 16 are reversed. In each of the three variants shown, the second control electrode 151 is not located adjacent to the mesa 18, where the inversion channel is induced by the first control electrode 141. According to the figures in . Fig. In the three illustrated embodiments, the mesa 18 of the first type includes the source region 101 to allow the injection of charge carriers of the first conductivity type, e.g., electrons in the case of an n-type source region 101, into the inversion channel adjacent to the first control electrode 141. Within the mesa 19 of the second type, another conductive channel can be formed when the voltage of the second control signal (V) GE2 ) at the second control electrode 151 has a value corresponding to a low level (e.g. -15 V) of the second control signal V GE2This corresponds to the further conductive channel, which can consist at least predominantly of charge carriers of the second conductivity type, e.g. holes.

[0099] In the second section 1-22, as in Fig. Figure 4 illustrates how both one of the first control trenches 14 and one of the second control trenches 15 laterally delimit the mesa 18. Due to the smaller distance between the inversion channel and the second control electrode 151, the influence of the second control signal 13-22 on the shape of the second characteristic transfer curve of the second section 1-22 is greater than its influence on the shape of the first characteristic transfer curve of the first section 1-21.

[0100] In one embodiment, the number of second control electrodes 151 per unit area in the second section 1-22, G2 / A2, is greater than the number of second control electrodes (151) per unit area in the first section 1-21, G2 / A1. For example, this measure can provide that in the first section 1-21, the first average effective distance between (i) the channel structures controlled by the first control electrodes 141 and (ii) the second control electrodes 151 is greater than a corresponding second average effective distance in the second section 1-22.

[0101] Another option to achieve the reduced influence of the second control signal within the first section 1-21 is to structure the first barrier region 105 laterally as described above. Fig. 4 was explained. For example, the average dopant concentration of the first barrier region 105 in the first section 1-21 is greater than the average dopant concentration of the first barrier region 105 in the second section 1-22. Since the first barrier region 105 can be considered to be located “between” the inversion channel in the mesa 18 and the second control electrode 152, a higher dopant concentration of the first barrier region 105 results in a higher resistivity for the holes and consequently an increase in the effective distance between (i) the channel region in the source region 101 adjacent to the first control electrode 141 and (ii) the second control electrode 151 in the second control trench 15.Another option to achieve the reduced influence of the second control signal within the first section 1-21 is to ensure that the average distance between each of the first control electrodes 141 and each of the second control electrodes 151 in the first section 1-21 is greater than the corresponding average distance in the second section 1-22. A further option is to ensure that the average number of source trenches 16 arranged between adjacent semiconductor channel structures in the first section 1-21 is greater than the average number of source trenches 16 arranged between adjacent semiconductor channel structures in the second section 1-22.Another option for modulating the extent of the influence of the second control signal is to ensure that the average ratio between the trench insulator thicknesses 142 and 152 is lower in the first section 1-21 compared to the second section 1-22. For example, in the second section 1-22, the thickness of the second trench insulator 152 can be smaller than in the first section 1-22, and the thickness of the first trench insulator 142 in the second section 1-22 can be the same as in the first section 1-21.

[0102] With reference to Fig. 6. In the second section 1-22, the first control electrode 141 and the second control electrode 151 can even be provided in the same trench 1415. Since the first control electrode 141 is exposed to the first control signal 13-21 and the second control electrode 151 is exposed to the second control signal 13-22, which differs from the first control signal 13-21, the isolation of the two control electrodes 141, 151 within the trench 1415 must be ensured based on a corresponding configuration of the first and second trench insulators 142, 152. The first control electrode 141 is located in an upper section of the trench 1415 near the source region 101. The second control electrode 152 is located below the first control electrode 141. For example, the boundary between the two control electrodes 141, 151 can be arranged on the vertical plane, where the body region 102 meets the first barrier region 105 (if present) oris connected to drift region 100 (if no first barrier region 105 is implemented).

[0103] Referring to each of the Fig. 3, Fig. 4 and Fig. 6 An insulating layer 191 can be provided on the first side 110 for local electrical insulation between the first load terminal 11 and the semiconductor body 10.

[0104] In one embodiment, with reference to Fig. 7, the active region 1-2 can further comprise a third section 1-23 containing a subset of the second control electrodes 151. For example, the third section 1-23 forms a diode section, such that the power semiconductor device (1) has an RC-IGBT configuration. In a region on the second side 120, corresponding to a vertical projection of the illustrated third section 1-23, the semiconductor body 10 can be configured accordingly, for example, by having first-type conductivity regions instead of the second-type conductivity emitter region 108, which are electrically connected to the second load terminal 12. Therefore, in addition to the first section(s) 1-21 and the second section(s) 1-22, different diode sections can be provided in the active region 1-2, for example, to provide the device 1 with improved reverse conductivity (RC) characteristics.Depending on the application, such different diode sections can constitute at least 10 to 35% of the active region 1-2. For example, the third section 1-23 is controlled exclusively based on the second control signal 13-22.

[0105] The embodiment of Fig. Variant 2 (B) (where there is no first section 1-21) can also contain a third section 1-23 in the active region 1-2, cf. Fig. 2 (C). In the embodiment of Fig. 2 (C) The active region 1-2 can include the second section 1-22 and the third section 1-23, resulting, for example, in an RC-IGBT as described above. For example, the embodiment can be free of the first region 1-21.

[0106] Regardless of whether the power semiconductor device 1 includes the first section 1-21 and / or the third section 1-23 in the active region 1-2, the device can be controlled based on the first control signal 13-21 (V GE1 ) and the second control signal 13-22 (V GE2 ) are controlled, as exemplified in Fig. 11 is shown. For example, to switch on the power semiconductor device 1, the voltage of the first control signal 13-21 (V) is used. GE1 ) from the low level (e.g., -8 V or -15 V) to the high level (e.g., 15 V), leading to the induction of inversion channels in body regions 102. A little later, with an initial time delay, t delay, 1 also the voltage of the second control signal 13-22 (V GE2 ) from the low level (e.g., -8 V or -15 V) to the high level (e.g., 15 V). The first time delay t delay, 1For example, it can be 3 µs. This leads to another electron injection. The delayed "switching on" of the second control signal can be used for short-term detection. Alternatively, t delay, 1 The voltage should be zero / near zero to reduce turn-on losses. Before the device is completely switched off, the voltage of the second control signal 13-22 (V) GE2 ) from the high level (e.g., 15 V) to the low level (e.g., -8 V or -15 V), which leads to desaturation of device 1 before complete shutdown and thus a reduction in switching losses. With a second time delay, t delay, 2 Following the first time delay, which may or may not be identical, comes the first control signal, i.e., it is also changed from the high level (e.g., 15 V) to the low level (e.g., -8 V or -15 V), which leads to the interruption of the load current.

[0107] Referring to each of the Fig. 12 to Fig. 14 The semiconductor device 1 comprises a second barrier region 115 of the second conductivity type. In order to obtain the different properties of the characteristic transfer curve between the first section 1-21 and the second section 1-22, the second barrier region 115 can have a different shape between sections 1-21 and 1-22.

[0108] In the example of Fig. 12 (A) The second barrier region 115 extends only into the second section 1-22, while the first section 1-21 is free of the second barrier region 115. The second barrier region 115 extends over at least 90% of the area of ​​the second section 1-22. The second barrier region 115 may include small openings that together occupy less than 10% of the area of ​​the second section 1-22. The openings occupy at most 10% of the area of ​​the second section.

[0109] In the example of Fig. 12 (B) The second barrier region 115 extends into both sections 1-21 and 1-22. The proportion of each section overlapped by the second barrier region 115 is smaller in the first section 1-21 compared to the second section 1-22. Additionally, the second barrier region 115 may have a smaller dopant dose in section 1-21 compared to section 1-22, resulting in a lower dopant concentration of the second barrier region 115 in the first section 1-21 compared to the second section 1-22.

[0110] Now, with reference to Fig. 8 and Fig. Section 9 describes an exemplary specific method for operating a half-bridge 2. The half-bridge circuit 2 comprises a first power semiconductor device 1-A, hereinafter referred to as the first RC-IGBT 1-A, and a second power semiconductor device 1-B, hereinafter referred to as the second RC-IGBT 1-B. The first RC-IGBT 1-A and the second RC-IGBT 1-B can be configured identically, e.g., according to one of the embodiments described above. Therefore, the Fig. 8 and Fig. The reference numerals used in section 9 are the same as those used above and are additionally marked with an "A" if the first RC-IGBT 1-A is addressed, and with a "B" if the second RC-IGBT 1-B is addressed. In addition to the load terminals 11-A, 12-A, 11-B and 12-B, control terminals 13-1A, 13-2A, 13-1B and 13-2B are illustrated. These terminals are electrically connected to the respective first or second control electrodes.

[0111] In general, the procedure comprises: providing a first control signal 13-21A to the multiple first control electrodes 141 of the first RC-IGBT 1-A and providing a second control signal 13-22A to the multiple second control electrodes 151 of the first RC-IGBT 1-A, and providing another first control signal 13-21B to the multiple first control electrodes 141 of the second RC-IGBT 1-B and providing another second control signal 13-22B to the multiple second control electrodes 151 of the second RC-IGBT 1-B.

[0112] For example, the first control signal 13-21A is provided as a voltage between the first control terminal 13-1A of the first RC-IGBT 1-A and the first load terminal 11-A of the first RC-IGBT 1-A. For example, the first control signal 13-21A is a first gate signal, provided, for example, by a (not illustrated) driver unit.

[0113] For example, the second control signal 13-22A is provided as a voltage between the second control terminal 13-2A ​​of the first RC-IGBT 1-A and the first load terminal 11-A of the first RC-IGBT 1-A. For example, the second control signal 13-22A is a second gate signal for the first RC-IGBT 1-A, provided, for example, by the (not illustrated) driver unit.

[0114] For example, the additional first control signal 13-21B is provided as a voltage between the first control terminal 13-1B of the second RC-IGBT 1-B and the first load terminal 11-B of the second RC-IGBT 1-B. Alternatively, the second control signal 13-21B can be a first gate signal for the second RC-IGBT 1-B, provided, for example, by another (not illustrated) driver unit.

[0115] For example, the additional second control signal 13-22B is provided as a voltage between the second control terminal 13-2B of the second RC-IGBT 1-B and the first load terminal 11-B of the second RC-IGBT 1-B. This additional second control signal 13-22B is, for example, a second gate signal for the second RC-IGBT 1-B, provided by the additional (not illustrated) driver unit.

[0116] Based on the control, the half-bridge circuit provides a current I L ready for an inductive load 21. For example, the half-bridge circuit 2 can be part of a full-bridge circuit or another circuit topology and is used to invert a DC input signal (e.g., the voltage across the second load terminal 12-A of the first RC-IGBT 1-A and the first load terminal 11-B of the second RC-IGBT 1-B) into an AC output signal, e.g., the current I L , configured. For example, it is located in each half-cycle of the load current I. LOne of the two RC-IGBTs 1-A, 1-B is in diode / reverse operation and the other is in IGBT / forward operation; after each half cycle, the operation changes from diode / reverse operation to IGBT / forward operation or from IGBT / forward operation to diode / reverse operation.

[0117] ZB is located in each half-cycle of current I. L One of the two RC-IGBTs 1-A, 1-B is in diode / reverse operation and the other is in IGBT / forward operation; after each half cycle, the operation changes from diode / reverse operation to IGBT / forward operation or from IGBT / forward operation to diode / reverse operation.

[0118] For example, the RC-IGBT 1-A / 1-B of the half-bridge circuit 2, which is in IGBT / forward operation, can be controlled in a conventional manner, e.g., at least based on the first control signal 13-21A or at least based on the second first control signal 13-21B. Additionally, the RC-IGBT 1-A / 1-B of the half-bridge circuit 2, which is in IGBT / forward operation, can also be controlled based on the second control signal 13-22A or based on the second second control signal 13-22B.

[0119] Furthermore, according to the embodiments described herein, the second control signal 13-22A and the further second control signal 13-22B can be controlled depending on the current direction of the half-bridge current I. Lcan be provided. For example, the RC-IGBT 1-A / 1-B of the half-bridge circuit 2, which is in diode / reverse operation, can be controlled at least on the basis of the second control signal 13-22A or at least on the basis of the further second control signal 13-22B, both of which depend on a current direction of the current I. L can be generated. In addition, the RC-IGBT 1-A / 1-B of the half-bridge circuit 2, which is in diode / reverse operation, can also be controlled based on the first control signal 13-21A or based on the further first control signal 13-21B.

[0120] The method can therefore also detect the direction of a half-bridge load current I L and include providing both the first plasma control signal 13-22A and the second plasma control signal 13-22B depending on the detected load current direction.

[0121] The in Fig. The nine illustrated control schemes refer to the case where the first RC-IGBT 1-A is operating in diode mode and the second RC-IGBT 1-B is operating in IGBT mode. For example, the second control signal 13-22A can be provided to trigger desaturation operation before the end of a one-pulse defined by the first control signal 13-21A.

[0122] For example, the desaturation operation is triggered based on a single pulse of the second control signal 13-22A. Fig. Figure 18 shows some variants (1)-(3) of such a single pulse (which can therefore be considered a desaturation pulse). For example, the single pulse of the first plasma control signal 13-22A lies within a time frame defined by the single pulse of the first control signal 13-21A (see variant (1), variant (2)-(i) and variant (3)-(i)). For example, the duration of the single pulse of the second control signal 13-22A is less than 30% or less than 10% of the duration of the single pulse of the first IGBT control signal 13-21A (see all variants in Figure 18). Fig. 9).

[0123] The desaturation times can depend on the thickness of the semiconductor body 10. For example, the desaturation time in µs ranges from the semiconductor body thickness d (in µm) divided by 50 to the semiconductor body thickness d (in µm) divided by ten.

[0124] Furthermore, the on-pulse of the second control signal 13-22A can terminate at the same time as the on-pulse of the first control signal 13-21A (see variant (1), variant (2)-(i), and variant (3)-(i)). Additionally, the on-pulse of the second control signal 13-22A can have the same amplitude as the on-pulse of the first control signal 13-21A. Or, the on-pulse of the second control signal 13-22A can replace a time frame defined by the on-pulse of the first control signal 13-21A (variant (2)-(ii) and variant (3)-(ii)) and / or have a smaller amplitude (e.g., less than 70% or less than 55%) than the on-pulse of the first control signal 13-21A (see variant (2)-(i) and variant (2)-(ii)).

[0125] According to one or more embodiments, the half-bridge circuit 2 is operated at a switching frequency, whereby the relationships between the control signals 13-21A / B, 13-22A / B, as described above, are observed in each period of the switching frequency. The switching frequency can be within the range of 100 Hz to 100 kHz.

[0126] According to embodiments of the method described herein, both RC-IGBTs 1-A and 1-B, when in IGBT / forward mode, can be controlled conventionally based at least on their respective first control signal 13-21A / B. Optionally, when both RC-IGBTs 1-A and 1-B are also in IGBT / forward mode, they can also be controlled based on the second control signal 13-22A / B, for example, to desaturate the respective RC-IGBT 1-A / B before or after turn-off. For example, the first control signal 13-21A triggers the desaturation, and the second control signal 13-22A initializes the turn-off process.In IGBT mode, both the respective first control signal 13-21A / B and the respective second control signal 13-22A / B can have essentially identical pulse widths, with the optional difference being in the time delays, whereby, as described above, synchronous signal waveforms are also possible, whereby the respective first control signal 13-21A / B and the second control signal 13-22A / B are therefore identical to each other.

[0127] According to embodiments of the method described herein, both RC-IGBTs 1-A and 1-B, when in diode / reverse mode, can be controlled in a conventional manner based at least on their respective first control signal 13-21A / B. For example, the first control signal 13-21A is an inverted version of the second first control signal 13-21B (which observes dead times). Optionally, it is also possible to control both RC-IGBTs 1-A and 1-B, when in diode / reverse mode, based on their respective second control signal 13-22A / B, e.g., to desaturate the respective RC-IGBT 1-A / B for the turn-off time (see [reference]). Fig. 9) In diode mode, the respective first control signal 13-21A / B and the respective second control signal 13-22A / B can have substantially different pulse widths. For example, the pulse width of the second control signal is less than 50%, less than 30%, or even less than 10% of the pulse width of the first control signal. Not only can the pulse width be smaller, but also the amplitude range of the second control signal compared to the IGBT control signal. The pulse of the second control signal can occur at various times around the turn-off time defined by the first control signal. That is, during diode operation, and based on the second control signal, a defined desaturation operation can be performed around the turn-off time (based on the first control signal) of the RC-IGBT. The shape of the desaturation pulse can be set based on the configuration of the RC-IGBT.

[0128] The method can detect the operating type (diode operation or IGBT operation) based on the half-bridge load current (see reference numeral I). L ) and the provision of the respective second control signal either according to the IGBT operating scheme or according to the diode operating scheme (e.g. Fig. 9) depending on the detected half-bridge load flow direction.

[0129] The differently configured sections 1-21 and 1-22 further enable improved handling of a short-circuit situation when the device 1 is in forward mode. For example, if a sudden increase in the (chip) load current is detected, the second control signal 13-22 can initially be set to a value corresponding to the device's blocking state (e.g., a negative voltage), thus limiting the load current. The first control signal 13-21 is then only set to a value corresponding to the device's blocking state (e.g., a negative voltage) if the fault detection clearly indicates that a short circuit has been detected and that, therefore, the sudden increase in load current is not due to another cause, such as load current oscillation.

[0130] This document also presents embodiments of a method for manufacturing a power semiconductor device:

[0131] In one embodiment, a method for manufacturing a power semiconductor device comprises forming the following components: a semiconductor body coupled to a first load terminal and a second load terminal; a drift region of a first conductivity type within the semiconductor body between the first load terminal and the second load terminal; an active region comprising a first section and a second section, both configured to conduct a load current between the first load terminal and the second load terminal; electrically isolated from the first load terminal and the second load terminal, a plurality of first control electrodes in both the first section and the second section;electrically isolated from the first load terminal, the second load terminal and the first control electrodes; a plurality of second control electrodes in both the first section and the second section; a plurality of semiconductor channel structures in the semiconductor body extending into both the first section and the second section, each of the plurality of channel structures being associated with one of the first control electrodes, each of the first control electrodes being configured to induce an inversion channel for conducting a portion of the load current in the associated semiconductor channel structure; and a second barrier region of the second conductivity type in the second section.

[0132] In one embodiment, a method for manufacturing a power semiconductor device comprises forming the following components: a semiconductor body coupled to a first load terminal and a second load terminal; a drift region of a first conductivity type within the semiconductor body between the first load terminal and the second load terminal; an active region comprising a first section and a second section, both configured to conduct a load current between the first load terminal and the second load terminal; electrically isolated from the first load terminal and the second load terminal, a plurality of first control electrodes in both the first section and the second section;electrically isolated from the first load terminal, the second load terminal and the first control electrodes, a plurality of second control electrodes in both the first section and the second section, a plurality of semiconductor channel structures in the semiconductor body extending into both the first section and the second section, each of the plurality of channel structures being associated with one of the first control electrodes, each of the first control electrodes being configured to induce an inversion channel for conducting a portion of the load current in the associated semiconductor channel structure;and a second barrier region of the second conductivity type, extending into both the first section and the second section, wherein an average dopant concentration of the second barrier region in the second section is greater than an average dopant concentration of the second barrier region in the first section.

[0133] Fig. Figure 13 shows a schematic section of a mesa within the second section 1-22. The mesa is bounded by a first control trench, which includes the first trench electrode 141, and a second control trench, which includes the second trench electrode 151. Variants (A) to (E3) show different embodiments of the second barrier region 115.

[0134] With further reference to Fig. A conductive channel 1011, which contributes to the load current between the first load terminal 11 and the second load terminal 12, is formed adjacent to the first control electrode 141 and adjoining the trench insulator 142. The conductive channel 1011 is formed in the body region 102, or more specifically in section 102-1 of the body region, which is part of the channel structure. The conductive channel 1011 conducts 90% of the majority charge carriers of the device 1, e.g., electrons in the case of an npnp-IGBT. The conductive channel 1011 carries a portion of the load current of the semiconductor device 1 and remains constant in a stable on-state of the semiconductor device 1.

[0135] With further reference to Fig. In a desaturation phase prior to the actual turn-off of the IGBT, a desaturation channel 1021 is formed when the gate signal VGE2 is below Vth,p (e.g., -8 V or -15 V). It provides a path for the holes under the cell structure, e.g., under the channel structure, to exit the device towards the first load terminal 11. This leads to a reduction of the hole-electron charge carrier plasma in the drift region 100, enabling rapid turn-off of the IGBT. The p-barrier region 115 provides a path for the holes away from the conductive channel 1011 and towards the desaturation channel 1021. In other words, the 1021 spatially extends the low-conductivity paths for the holes from the Si-oxide interface at 152 into the mesa and / or under the cell structure. It effectively brings the two trenches closer together, thereby practically reducing the distance between adjacent trenches for the holes.Due to the high hole conductivity towards the emitter, the electrical potential at the end of the n-inversion channel is pinned. This limits the channel current, leading to current saturation even at a moderate current level.

[0136] Fig. Variant 14 (A) shows an exemplary configuration of IGBT cells within the first section 1-21 free from barrier region 115. Fig. Variants (B) to (C) show various exemplary configurations of IGBT cells within the second section 1-22, each encompassing the second barrier region 115. For the sake of brevity, further details are not explained again, and reference is made to the preceding examples.

[0137] In one embodiment, a method for fabricating a power semiconductor device comprises forming the following components: a semiconductor body coupled to a first load terminal and a second load terminal; an active region comprising a first section and a second section, both configured to conduct a load current between the first load terminal and the second load terminal; electrically isolated from the first load terminal and the second load terminal; a plurality of first control electrodes in both the first section and the second section; and a plurality of second control electrodes in both the first section and the second section. The first control electrodes are configured to be exposed to a first control signal. The second control electrodes are configured to be exposed to a second control signal.A plurality of semiconductor channel structures are located in the semiconductor body and extend into both the first and second sections, each of the plurality of channel structures being associated with at least one of the first control electrodes, the respective at least one of the first control electrodes being configured to induce an inversion channel to the load current conduction in the associated semiconductor channel structure; wherein, in a forward bias state, the first section exhibits a first characteristic transfer curve, load current, as a function of the voltage of the first control signal; and the second section exhibits a second characteristic transfer curve, load current, as a function of the voltage of the first control signal, wherein at least the second characteristic transfer curves are modifiable based on the voltage of the second control signal.For a given voltage of the first control signal, corresponding to a forward conduction state of the power semiconductor device, the change in load current in the first section observed for a given change in the voltage of the second control signal is smaller compared to the corresponding change in load current in the second section. Optionally, both the first and second characteristic transfer curves can be modified based on the voltage of the second control signal.

[0138] In a further embodiment, a method for manufacturing a power semiconductor device comprises forming the following components: a semiconductor body coupled to a first load terminal and a second load terminal; an active region comprising a first section and a second section, both configured to conduct a load current between the first load terminal and the second load terminal; electrically isolated from the first load terminal and the second load terminal; a plurality of first control electrodes in both the first section and the second section; and a plurality of second control electrodes in both the first section and the second section; and a plurality of semiconductor channel structures in the semiconductor body extending into both the first section and the second section, each of the plurality of channel structures being associated with at least one of the first control electrodes.wherein at least one of the first control electrodes is configured to induce an inversion channel to the load current conduction in the associated semiconductor channel structure. In the first section, a first average effective distance between (i) the channel structures controlled by the first control electrodes and (ii) the second control electrodes is greater than a corresponding second average effective distance in the second section.

[0139] In a further embodiment, a method for fabricating a power semiconductor device comprises forming the following components: a semiconductor body coupled to a first load terminal and a second load terminal; an active region with a second section configured to conduct a load current between the first load terminal and the second load terminal; electrically isolated from the first load terminal and the second load terminal; a plurality of first control electrodes in the second section; and a plurality of second control electrodes in the second section. The first control electrodes are configured to be exposed to a first control signal. The second control electrodes are configured to be exposed to a second control signal.A plurality of semiconductor channel structures are located in the semiconductor body and extend into the second section, each of the plurality of channel structures being associated with at least one of the first control electrodes, the respective at least one of the first control electrodes being configured to induce an inversion channel to the load current line in the associated semiconductor channel structure; wherein in the second section the voltage of the second control signal influences the inversion channels controlled by the first control electrodes.

[0140] In yet another embodiment, a method for fabricating a power semiconductor device comprises forming the following components: a semiconductor body coupled to a first load terminal and a second load terminal; an active region comprising a first section and a second section, both configured to conduct a load current between the first load terminal and the second load terminal; electrically isolated from the first load terminal and the second load terminal; a plurality of first control electrodes in both the first section and the second section; and a plurality of second control electrodes in both the first section and the second section. The first control electrodes are configured to be exposed to a first control signal. The second control electrodes are configured to be exposed to a second control signal.A plurality of semiconductor channel structures are located within the semiconductor body and extend into both the first and second sections, each of which is associated with at least one of the first control electrodes. Each of these first control electrodes is configured to induce an inversion channel to the load current in the associated semiconductor channel structure. In the second section, the voltage of the second control signal influences the inversion channels controlled by the first control electrodes.

[0141] Further embodiments of the methods described above correspond to the embodiments of the power semiconductor device described above. Reference is made to the foregoing in this respect.

[0142] The foregoing described embodiments relating to a power semiconductor device, such as MOSFETs, IGBTs, RC-IGBTs, and derivatives thereof, and corresponding processing and control methods. For example, these power semiconductor devices are based on silicon (Si). Accordingly, a monocrystalline semiconductor region or layer, e.g., the semiconductor body and its regions / zones, can be a monocrystalline Si region or Si layer. In other embodiments, polycrystalline or amorphous silicon can be used.

[0143] However, it is understood that the semiconductor body and its regions / zones can be made from any semiconductor material suitable for manufacturing a semiconductor device. Examples of such materials include, but are not limited to, elemental semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary, or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name just a few. to name.The aforementioned semiconductor materials are also referred to as "homo-junction semiconductor materials." When two different semiconductor materials are combined, a hetero-junction semiconductor material is formed. Examples of hetero-junction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x), and silicon-SiGe hetero-junction semiconductor materials. Si, SiC, GaAs, and GaN materials are currently the most commonly used for power semiconductor switching applications.

Claims

[1] Power semiconductor device (1) comprising: - a semiconductor body (10) coupled to a first load terminal (11) and a second load terminal (12); - a drift region (100) of a first conductivity type within the semiconductor body (10) between the first load terminal (11) and the second load terminal (12); - an active region (1-2) with a first section (1-21) and a second section (1-22), both configured to carry a load current between the first load terminal (11) and the second load terminal (12); - electrically isolated from the first load terminal (11) and the second load terminal (12), a plurality of first control electrodes (141) in both the first section (1-21) and the second section (1-22); - electrically insulated from the first load terminal (11), the second load terminal (12) and the first control electrodes (141), a plurality of second control electrodes (151) in both the first section (1-21) and the second section (1-22), - a plurality of semiconductor channel structures in the semiconductor body (10) in both the first section (1-21) and the second section (1-22), wherein each of the plurality of channel structures is associated with one of the first control electrodes (141) or one of the second control electrodes (151), each of the first control electrodes (141) being configured to induce an inversion channel for conducting a portion of the load current in the associated semiconductor channel structure; and - a second barrier region (115) of a second conductivity type in the second section (1-22) under the semiconductor channel structures, wherein the second barrier region (115) is located between the semiconductor channel structures and the drift region (100). [2] Power semiconductor device (1) according to claim 1, wherein the first section (1-21) is free from the second barrier region (115). [3] Power semiconductor device (1) comprising: - a semiconductor body (10) coupled to a first load terminal (11) and a second load terminal (12); - a drift region (100) of a first conductivity type within the semiconductor body (10) between the first load terminal (11) and the second load terminal (12); - an active region (1-2) with a first section (1-21) and a second section (1-22), both configured to carry a load current between the first load terminal (11) and the second load terminal (12); - electrically isolated from the first load terminal (11) and the second load terminal (12), a plurality of first control electrodes (141) in both the first section (1-21) and the second section (1-22); - electrically insulated from the first load terminal (11), the second load terminal (12) and the first control electrodes (141), a plurality of second control electrodes (151) in both the first section (1-21) and the second section (1-22); - a plurality of semiconductor channel structures in the semiconductor body (10) in both the first section (1-21) and the second section (1-22), wherein each of the plurality of channel structures is associated with one of the first control electrodes (141), each of the first control electrodes (141) being configured to induce an inversion channel for conducting a portion of the load current in the associated semiconductor channel structure; and - a second barrier region (115) of a second conductivity type below the semiconductor channel structures, extending into both the first section (1-21) and the second section (1-22), wherein an average dopant concentration of the second barrier region (115) in the second section (1-22) is greater than an average dopant concentration of the second barrier region (115) in the first section (1-21), wherein the second barrier region (115) is located between the semiconductor channel structures and the drift region (100). [4] Power semiconductor device (1) according to one of the preceding claims, wherein the second section (1-22) is laterally segmented into a plurality of sections, wherein the sections of the second section (1-22) are separated from each other by sections of the first section (1-21). [5] Power semiconductor device (1) according to any of the preceding claims, wherein the first section (1-21) is a contiguous region. [6] Power semiconductor device (1) according to any of the preceding claims, wherein the number of second control electrodes (151) per unit area in the second section (1-22), G2 / A2, is greater than the number of second control electrodes (151) per unit area in the first section (1-21), G2 / A1. [7] Power semiconductor device (1) according to any of the preceding claims, wherein the total area of ​​the first section (1-21) is at least 20% of the total area of ​​the active region (1-2). [8] Power semiconductor device (1) according to one of the preceding claims, further comprising a plurality of source trenches (16) in the first section (1-21) and in the second section (1-22), wherein each source trench (16) comprises a source electrode (161) electrically connected to the first load terminal (11), wherein an average number of source trenches (16) arranged between adjacent semiconductor channel structures in the first section (1-21) is greater than an average number of source trenches (16) arranged between adjacent semiconductor channel structures in the second section (1-22). [9] Power semiconductor device (1) according to one of the preceding claims, further comprising a first barrier region (105) of the first conductivity type, wherein an average dopant concentration of the first barrier region (105) in the first section (1-21) is greater than an average dopant concentration of the first barrier region (105) in the second section (1-22). [10] Power semiconductor device (1) according to one of the preceding claims, wherein an average distance between each of the first control electrodes (141) and each of the second control electrodes (151) in the first section (1-21) is greater than a corresponding average distance in the second section (1-22). [11] Power semiconductor device (1) comprising: - a semiconductor body (10) coupled to a first load terminal (11) and a second load terminal (12); - a drift region (100) of a first conductivity type within the semiconductor body (10) between the first load terminal (11) and the second load terminal (12); - an active region (1-2) with a second section (1-22) configured to carry a load current between the first load terminal (11) and the second load terminal (12); - electrically isolated from the first load terminal (11) and the second load terminal (12), a plurality of first control electrodes (141) in the second section (1-22); - electrically isolated from the first load terminal (11), the second load terminal (12) and the first control electrodes (141), a plurality of second control electrodes (151) in the second section (1-22); - a plurality of semiconductor channel structures in the semiconductor body (10) in the second section (1-22), wherein each of the plurality of channel structures is associated with one of the first control electrodes (141), each of the first control electrodes (141) being configured to induce an inversion channel for conducting a portion of the load current in the associated semiconductor channel structure; and - a second barrier region (115) of the second conductivity type in the second section (1-22), wherein the second barrier region (115) is located between the semiconductor channel structures and the drift region (100). [12] Power semiconductor device (1) according to one of the preceding claims, wherein all of the semiconductor channel structures are assigned to one of the first control electrodes (141) and / or no semiconductor channel structure is assigned to one of the second control electrodes (151). [13] Power semiconductor device (1) according to one of the preceding claims, wherein each of the semiconductor channel structures comprises a respective source region (101) of a first conductivity type, which is electrically connected to the first load terminal (11), and a part of a body region (102) of the second conductivity type, which separates the source region (101) from the drift region (100), wherein the respective source region (101) is arranged adjacent to the first control electrode (141) or the second control electrode (141) to which the semiconductor region is assigned. [14] Power semiconductor device (1) according to one of the preceding claims, wherein each of the semiconductor channel structures comprises a respective source region (101) of a first conductivity type which is electrically connected to the first load terminal (11), wherein in the second section (1-22) the source regions (101) are arranged adjacent to the first control electrodes (141) and spatially offset from the second control electrodes (151). [15] Power semiconductor device (1) according to one of the preceding claims, wherein within the second section (1-22) the second barrier region (115) is formed as a continuous region, wherein the second barrier region (115) comprises openings, where the second barrier region (115) is omitted. [16] Power semiconductor device (1) according to one of the preceding claims, wherein the semiconductor body (10) comprises a rear emitter region of the second conductivity type in direct contact with the second load terminal (12). [17] Power semiconductor device (1) according to any of the preceding claims, wherein - the first control electrodes (141) are arranged in first control trenches (14) and are insulated from the semiconductor body (10) by a first trench insulator (142); - the second control electrodes (151) are arranged in second control trenches (15) and are insulated from the semiconductor body (10) by a second trench insulator (152); - the semiconductor channel structures are arranged in mesas (18) of the semiconductor body (10), wherein the mesas (18) are laterally bounded at least by the control grooves (14, 15). [18] Power semiconductor device (1) according to claim 17, wherein in the second section (1-22) at least some of the mesas (18) are laterally bounded by one of the first control trenches (14) and by one of the second control trenches (15). [19] Power semiconductor device (1) according to one of claims 17 or 18, wherein a unit cell is defined by a pattern of the mesas (18) and the first control trenches (14) and the second control trenches (15), wherein the pattern within the unit cell is identical in the first section (1-21) and the second section (1-22). [20] Power semiconductor device (1) according to any of the preceding claims except claim 8, further comprising a plurality of source trenches (16) in the first section (1-21) and / or in the second section (1-22), wherein each source trench (16) comprises a source electrode (161) which is electrically connected to the first load terminal (11). [21] Power semiconductor device (1) according to one of claims 8 or 20, wherein at least within the second section (1-22) at least one of the source trenches (16) is arranged between one of the first control trenches (14) and the nearest second control trench (15), wherein a hole path extending between the respective first and second control trench is formed by the second barrier region (115). [22] Power semiconductor device (1) according to one of the preceding claims, wherein the total area of ​​the second section (1-22) is at least 20% of the total area of ​​the active region (1-2). [23] Power semiconductor device (1) according to one of the preceding claims, further comprising a first barrier region (105) arranged between the semiconductor channel structures and the second barrier region (115), wherein the first barrier region (105) is of the same conductivity type as the drift region (100). [24] Power semiconductor device (1) according to any of the preceding claims, wherein - the second section (1-22) has a second characteristic transfer curve, load current, as a function of the voltage of the first control signal (13-21), wherein the second characteristic transfer curve is variable based on the voltage of the second control signal (13-22), wherein - for a given voltage of the first control signal (13-21), which corresponds to a forward conduction state of the power semiconductor device (1), the resulting load current according to the second characteristic transfer curve ◯ a first value for the second control signal (13-22) equal to 0 V and ◯ has a second value for the second control signal (13-22) with a value corresponding to the additive inverse of the first control signal (13-21), wherein ◯ the second value of the resulting load current is 85% or even at most 50% of the first value of the resulting load current. [25] Power semiconductor device (1) according to one of the preceding claims, wherein the first control electrodes (141) are electrically isolated from the second control electrodes (151). [26] Power semiconductor device (1) according to any of the preceding claims, wherein - the first control electrodes (141) are arranged in first control trenches (14) and are insulated from the semiconductor body (10) by a first trench insulator (142); - the second control electrodes (151) are arranged in second control trenches (15) and are insulated from the semiconductor body (10) by a second trench insulator (152); - the semiconductor channel structures are arranged in mesas (18) of the semiconductor body (10), wherein the mesas (18) are laterally bounded at least by the control grooves (14, 15). [27] Power semiconductor device (1) according to claim 19, wherein in the second section (1-22) at least some of the mesas (18) are laterally bounded by one of the first control trenches (14) and by one of the second control trenches (15). [28] Power semiconductor device (1) comprising: - a semiconductor body (10) coupled to a first load terminal (11) and a second load terminal (12); - a drift region (100) of a first conductivity type within the semiconductor body (10) between the first load terminal (11) and the second load terminal (12); - an active region (1-2) with a second section (1-22) configured to carry a load current between the first load terminal (11) and the second load terminal (12); - electrically isolated from the first load terminal (11) and the second load terminal (12), a plurality of first control electrodes (141) in the active region (1-2); - electrically isolated from the first load terminal (11), the second load terminal (12) and the first control electrodes (141), a plurality of second control electrodes (151) in the active region (1-2); - a plurality of source regions (101) of the first conductivity type that are electrically connected to the first load terminal (11) in the active region (1-2); - a body region (102) of the second conductivity type, separating the source regions (101) from the drift region (100); and - a second barrier region (115) of the second conductivity type in the active region (1-2) below the body region (102) and separate from the body region (102), wherein the second barrier region (115) o either divides the drift region (100) into an upper section and a lower section, which is arranged below trench bottoms of the power semiconductor device (1), or o is located between the drift region (100) and a first barrier region (105) of the first conductivity type. [29] Power semiconductor device (1) according to the preceding claim, wherein the second barrier region (115) is designed as a continuous region, and wherein the second barrier region (115) comprises openings, where the second barrier region (115) is omitted. [30] Power semiconductor device (1) according to one of the preceding claims, wherein the semiconductor body (10) is formed in a single semiconductor chip. [31] Power semiconductor device (1) according to one of the preceding claims, wherein the active region (1-2) further comprises a third section (1-23) containing a subset of the second control electrodes (151), wherein the third section (1-23) forms a diode section, such that the power semiconductor device (1) has an RC-IGBT configuration. [32] Method for operating a half-bridge circuit (2) comprising a first power semiconductor device (1-A) according to one of the preceding claims and a second power semiconductor device (1-B) according to one of the preceding claims, comprising: - Providing a first control signal (13-21A) to the multiple first control electrodes (141) of the first power semiconductor device (1-A) and providing a second control signal (13-22A) to the multiple second control electrodes (151) of the first power semiconductor device (1-A); and - Providing a further first control signal (13-21B) to the multiple first control electrodes (141) of the second power semiconductor device (1-B) and providing a further second control signal (13-22B) to the multiple second control electrodes (151) of the second power semiconductor device (1-B).

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