Method for operating an N-level inverter, data processing system, computer program and computer-readable medium

Abstract

Method (20) for operating an N-level inverter (7), comprising the following steps: - Receiving data that is representative of a defect in the N-level inverter (7) or in an electrical energy source that supplies the N-level inverter (7) with electrical energy and that comprises two series-connected battery strings (6a, 6b) where N≥3, - Detecting a defect in the N-level inverter (7) or in the power source depending on the received data, - Initiating operation of the N-level inverter (7) as an X-level inverter, in response to the detection of the defect, wherein X

Description

Technical field

[0001] The invention relates to a method for operating an N-level inverter, a data processing system, a computer program and a computer-readable medium. State of the art

[0002] Documents US 2010 / 0039843A1, EP 2770624A1, and WO 2023 / 175116A1 disclose 3-level inverters with a t-form architecture. This also applies to the subsequently published document DE 102023127375A1, which proposes disconnecting a supply potential by an inverter transistor in the event of a fault. Document US 2014 / 0247634A1 also concerns a 3-level inverter, but it does not provide for disconnecting the external potentials of the supply voltage in the event of a fault. Document CN 115955097A describes the use of thyristors to apply a supply voltage to parts of an inverter circuit in the event of a fault, but does not describe disconnecting the supply voltage. The printed materials have in common that no dedicated separation from the external supply potential is provided, and thus, in the event of a fault, the control of semiconductor switches establishes a desired deactivation state.However, this requires a very low level of fault tolerance in the semiconductor control (including drivers, etc.), which may need to be achieved with additional control means.

[0003] A particular disadvantage of the devices in the prior art is that considerable effort is required to ensure functional reliability in such inverters. Description of the invention, problem, solution, advantages

[0004] The object of the present invention is to provide an alternative technical solution which is characterized in particular by its simple and cost-effective functional reliability.

[0005] The problem is solved by the subject matter of the independent claims. One embodiment of the invention relates to a method according to claim 1. The method is preferably a method for operating an N-level inverter, comprising the following steps: - Receiving data that is representative of a defect in one or the N-level inverter or in an electrical power source supplying the N-level inverter with electrical power, where N≥3, - Detecting a defect in the N-level inverter or the power source depending on the received data, - Initiating operation of the N-level inverter as an X-level inverter in response to the detection of the defect, where X <N sowie X≥2 entspricht.

[0006] In this way, the functional components of the electrical circuit or the power source can be used to continue operating the inverter. This implements a particularly cost-effective operational reliability for the inverter.

[0007] Preferably, the operation of the N-level inverter as an X-level inverter serves as a backup operation and / or a functional safety operation. For example, a vehicle with an electric drive could benefit from such a method by using the method according to the invention when a defect occurs, thereby ensuring the functional safety of the inverter and of an electric drive powered by the inverter.

[0008] The defect could, for example, be a short-circuited or unintentionally opened power semiconductor switch of the N-level inverter, or a short-circuited or open electrical line from the N-level inverter to the electrical power source.

[0009] Preferably, the defects are detected using sensors or at least one sensor.

[0010] It is particularly advantageous if the method is a computer-implemented method.

[0011] Furthermore, it is preferred if the numbers suitable for the variables N and X are natural numbers, especially greater than 0.

[0012] It is also advantageous if the data is available as analog or digital data.

[0013] A preferred embodiment is characterized in that the defect in the N-level inverter is a defect in a half-bridge of the N-level inverter or in a power semiconductor switch of a half-bridge of the N-level inverter.

[0014] In the case that the N-level inverter is a 3-level inverter with a t-form architecture, it is preferred if the half-bridge is a main half-bridge or if the power semiconductor switch is a power semiconductor switch of a power semiconductor switch pair in the t-branch of the t-form architecture.

[0015] The energy source is a DC voltage source, in particular a battery, comprising at least two battery strings connected in series, each comprising at least one battery pack. A neutral node of the battery is preferably arranged between the strings, allowing a medium voltage to be defined. Preferably, if the N-level inverter is a 3-level inverter with a T-shaped architecture, the three power semiconductor pairs are electrically connected to the neutral node, in order to tap the medium voltage of the battery, particularly preferably from a functioning battery string.

[0016] It is also preferable if the energy source is a rechargeable energy source, DC power source or battery.

[0017] Another preferred embodiment is characterized in that the defect in the energy source is a defect in a battery pack, a battery string of the energy source, a fuse, a cable, a connector, and an intermediate circuit capacitor, in particular each belonging to the supply of electrical energy by means of the electrical energy source. The defects, in particular the defects in the battery pack or the battery string, can be detected, for example, by means of a battery management system or other sensors or monitoring devices.

[0018] Another preferred embodiment is characterized in that the N-level inverter is a 3-level inverter and the X-level inverter is a 2-level inverter. This is a particularly simple embodiment of the invention to implement.

[0019] Another preferred embodiment is characterized in that the 3-level inverter is a 3-level inverter with a t-shaped architecture. This is a particularly simple embodiment of a 3-level inverter to implement.

[0020] Another preferred embodiment is characterized in that the 3-level inverter comprises three main half-bridges, each with two power semiconductor switches, wherein one of the two power semiconductor switches in each half-bridge is configured as a high-side switch and, in particular, is electrically connected to a positive electrical potential of the power source, and wherein the other power semiconductor switches are configured as low-side switches and, in particular, are electrically connected to a negative electrical potential of the voltage source. In other words, the main half-bridges are arranged such that the battery voltage of the power source is applied to them.

[0021] It is also preferable if the power semiconductor switches, instead of being designed in this way, are arranged in this way or are additionally arranged in this way.

[0022] Furthermore, it is advantageous if three windings of a three-phase winding of an electric machine can be energized by means of the three main half-bridges. It is also conceivable that the winding is a multi-phase winding with more than three phases. Preferably, the N-level inverter has more than three main bridges for this purpose. It is particularly preferred if the number of main bridges corresponds to the number of phase windings. The winding can preferably be a delta winding or a star winding.

[0023] Another preferred embodiment is characterized in that the 3-level inverter in the t-branch of the t-shaped architecture comprises three pairs of power semiconductor switches, wherein the three pairs of power semiconductor switches are each connected in anti-series to each other, wherein the pairs of power semiconductor switches are each electrically connected to a neutral node of the power source, wherein the first pair of power semiconductor switches of the three pairs of power semiconductor switches is electrically connected to a first node, wherein the first node is electrically located between two power semiconductor switches of the first main half-bridge, wherein the second pair of power semiconductor switches of the three pairs of power semiconductor switches is electrically connected to a second node, wherein the second node is electrically located between two power semiconductor switches of the second main half-bridge.wherein the third power semiconductor switch pair of the three power semiconductor switch pairs is electrically connected to a third node, the third node being electrically located between two power semiconductor switches of the third main half-bridge. The power semiconductor switch pairs are preferably MOSFETs, in particular with a body diode.

[0024] The term "anti-series connection" of the power semiconductor switch pairs preferably means that the power semiconductor switches of a power semiconductor switch pair are connected anti-series, i.e., in opposite directions to each other. This applies to each power semiconductor switch pair. In other words, one power semiconductor switch of a power semiconductor switch pair is electrically connected to the neutral node of the power source and simultaneously connected anti-series, i.e., in opposite directions, to the other power semiconductor switch of the same power semiconductor switch pair, with the second power semiconductor switch of the power semiconductor switch pair being electrically connected to its corresponding node.

[0025] The nodes preferably refer to electrical contacts or connections.

[0026] Preferably, half the battery voltage exists between the neutral node and the negative or positive potential of the battery. Half the battery voltage preferably refers to the mid-voltage or the mid-voltage.

[0027] Another preferred embodiment is characterized in that the operation as an X-level inverter, in response to the detection of a defect in a battery string of the power source, or the supply of electrical energy to the X-level inverter by means of the power source or a power semiconductor switch of the main half-bridges, comprises the following: - In particular, arranging for an electrical disconnection of the defective battery string from the N-level inverter, such that the N-level inverter is supplied only with the medium voltage of the energy source by means of a functioning battery string, - Initiating the operation of the N-level inverter as an X-level inverter by means of three alternative half-bridges, wherein the alternative half-bridges are formed by at least one power semiconductor switch of each of the three power semiconductor switch pairs and one power semiconductor switch of each of the three main half-bridges of the N-level inverter.

[0028] If a fault is detected in a power semiconductor switch, disconnecting the battery train is not strictly necessary, but merely optional. It could even be detrimental, as other electrical components in the vehicle are often also supplied via the contactor.

[0029] In the event of a defect in a power semiconductor switch, it is preferred to prevent uncontrolled current flow via the phase terminals into the electrical machine operated by the inverter. Preferably, operation as an X-level inverter is only possible under these conditions.

[0030] In the event of an open-circuit fault (OC) being detected at a power semiconductor switch of the main half-bridges, it is sufficient to open the corresponding power semiconductor switches of the other main half-bridges to interrupt the current flow. The corresponding power semiconductor switches preferably refer to the high-side power semiconductor switches of the other main half-bridges if an OC fault is detected at a high-side power semiconductor switch of a main half-bridge. Conversely, they refer to the low-side power semiconductor switches if an OC fault is detected at a low-side power semiconductor switch of a main half-bridge.

[0031] If a short-circuit defect (SC defect) is detected in one of the power semiconductor switches of the main half-bridges, electrical isolation via an additional isolating element, such as a contactor, is advantageous. This electrical isolation disconnects a defective high-side power semiconductor switch from the positive terminal of the power source along with the other high-side power semiconductor switches of the other main half-bridges, and similarly, disconnects a defective low-side power semiconductor switch from the negative terminal of the power source along with the other low-side power semiconductor switches of the other main half-bridges.

[0032] It is also preferable to tap the medium voltage via the neutral node. In other words, the N-level inverter, operating as an X-level inverter, is powered by the medium voltage tapped at the neutral node.

[0033] Furthermore, it is advantageous if the low-side switches of the three main half-bridges are used to form the alternative half-bridges when a defect is detected in a high-side switch of the three main half-bridges. Alternatively or additionally, it is advantageous if the high-side switches of the three main half-bridges are used to form the alternative half-bridges when a defect is detected in a low-side switch of the three main half-bridges. It is generally preferred that the power semiconductor switches of the main half-bridges not used to form the alternative half-bridges are opened. "Opened" preferably means that the current flow through the power semiconductor switches is interrupted.Furthermore, it is preferred if the associated battery string, which is electrically separated between the neutral node and the power semiconductor switches not used for the alternative half-bridge, is electrically separated from the N-level inverter and / or the unused power semiconductors of the main half-bridges.

[0034] Alternatively or additionally, it is advantageous if the low-side switches of the three main half-bridges are used to form the alternative half-bridges when a defect is detected in the battery string electrically connected between the neutral node and the high-side switches of the three main half-bridges. Alternatively or additionally, it is advantageous if the high-side switches of the three main half-bridges are used to form the alternative half-bridges when a defect is detected in the battery string electrically connected between the neutral node and the low-side switches of the three main half-bridges. It is generally preferred if the power semiconductor switches of the main half-bridges not used to form the alternative half-bridges are opened. "Opened" preferably means that current flow through the power semiconductor switches is interrupted.Furthermore, it is provided that the defective battery string is electrically disconnected from the N-level inverter. This can also be disconnected from the unused power semiconductor of the main half-bridges.

[0035] Electrical isolation is achieved by means of a designated contactor and / or an electrical switch, in particular an electrical contactor.

[0036] Another preferred embodiment is characterized in that the operation as an X-level inverter, in response to the detection of a defect in the medium-voltage supply or a power semiconductor switch of the power semiconductor switch pairs, comprises the following: - Arranging for an electrical separation of the medium voltage supply from the N-level inverter, such that the N-level inverter is supplied only with the battery voltage of the energy source, - In particular, cause the three pairs of power semiconductor switches to open in such a way that no current can conduct through the three pairs of power semiconductor switches, - Initiating the operation of the N-level inverter as an X-level inverter using only the three main half-bridges of the N-level inverter.

[0037] In other words, only the main half-bridges of the N-level inverter are used to operate the N-level inverter as an X-level inverter, while the power semiconductor switch pairs are deactivated, i.e., open. "Open" means that no current flows through the power semiconductor switch pairs. This approach is particularly advantageous when there is an open-circuit defect on one of the power semiconductors in the power semiconductor pairs.

[0038] Preferably, an additional electrical isolation can be achieved by means of a switch or a contactor to disconnect the electrical connection of the power semiconductor pairs to the neutral node of the battery.

[0039] In the event that one of the power semiconductors of the power semiconductor pairs has a switching-switch defect, it is conceivable to close the power semiconductors of the other power semiconductor pairs, which have the same electrical arrangement as the defective power semiconductor switch, in such a way that current flows through them, while the other power semiconductors of the power semiconductor pairs together with power semiconductors of the main half-bridges, which have the same electrical arrangement as the other power semiconductors of the power semiconductor pairs, form the alternative half-bridges.

[0040] The same or identical electrical arrangement refers to the arrangement in relation to the current flow.

[0041] Preferably, the nominal voltage of the energy source can be meant instead of the battery voltage.

[0042] It is also preferable if the electrical separation of the medium voltage supply from the N-level inverter is achieved by opening an electrical switch or contactor that is electrically located between the neutral node of the battery and the three pairs of power semiconductor switches.

[0043] Opening the switch or contactor creates an electrical separation, so that no current can flow between the neutral node and the three pairs of power semiconductor switches.

[0044] Alternatively or additionally, if a short circuit is detected in one of the power semiconductor switch pairs, the power semiconductor switches of the other power semiconductor switch pairs, which have the same electrical orientation as the defective power semiconductor switch, are actively closed to enable operation as an X-level inverter.

[0045] Preferably, the energy source supplies the n-level inverter with electrical energy by electrically connecting the positive terminal, i.e., the positive potential of the energy, to the high-side switches and electrically connecting the negative terminal, i.e., the negative potential of the energy source, to the low-side switches.

[0046] Preferably, the positive pole of the energy source can be electrically disconnected from the high-side switches and the negative pole can be electrically disconnected from the low-side switches by means of a contactor or switch.

[0047] Preferably, all power semiconductor switches and the three contactors can be switched using the control unit.

[0048] Another technical solution to the problem is provided by a system according to claim 11. The system is preferably a data processing system comprising means for carrying out the method according to the invention. The system offers the same advantages as the method according to the invention.

[0049] It is also preferable if the system includes a control unit and / or a driver circuit and / or the N-level inverter, in particular a 3-level inverter with a t-form architecture, and / or the battery, in particular having two battery strings with a neutral node, and / or the electric machine that can be driven by the inverter, and / or the sensor system or sensors for detecting defects.

[0050] It is preferred if the neutral node is electrically located between the two battery strings of the battery.

[0051] It is preferred that the sensors or sensor array send the data to the control unit, which receives the data and, by means of the driver circuit, initiates the switching of the power semiconductor switches and / or the electrical switches of the inverter. In other words, the method according to the invention is carried out on the control unit.

[0052] Furthermore, it is conceivable that the inventive method detects the defects by means of the sensors or the sensor technology and / or initiates the process by means of the driver circuit.

[0053] Furthermore, it is preferred that an electrical conductor connecting the neutral node to the power semiconductor switch pairs is rated for a lower electrical power than an electrical conductor connecting the positive terminal of the battery to the high-side switches of the main half-bridges. Alternatively or additionally, it is preferred that the electrical conductor connecting the neutral node to the power semiconductor switch pairs is rated for a lower electrical power than an electrical conductor connecting the negative terminal of the battery to the low-side switches of the main half-bridges.

[0054] Another technical solution to the problem is provided by a computer program according to claim 12. In particular, the computer program is a computer program that includes instructions which, when executed by a computer, cause the computer to execute the method according to the invention. The computer program offers the same advantages as the method and the computer program according to the invention.

[0055] Another technical solution to the problem is provided by a computer-readable medium according to claim 13. The computer-readable medium is, in particular, a computer-readable medium comprising instructions which, when executed by a computer, cause it to execute the method according to the invention. Alternatively, in other words, it is a computer-readable medium on which the computer program according to the invention is stored. The computer-readable medium offers the same advantages as the method, system, and computer program according to the invention.

[0056] It is also preferable if the computer-readable medium is a non-volatile storage medium, in particular a storage medium.

[0057] Advantageous embodiments of the present invention are described in the dependent claims and in the following description of the figures. Brief description of the drawings

[0058] The invention will now be explained in detail using exemplary embodiments and with reference to the drawings. The drawings show: Fig. 1 an embodiment of the system according to the invention, and Fig. 2 a flowchart of an embodiment of the method according to the invention. Preferred embodiment of the invention

[0059] The Fig. Figure 1 shows vehicle 16 with an embodiment of the system 1 according to the invention. The system 1 comprises an embodiment of the computer program 5 according to the invention, which is stored on an embodiment of the storage medium 4 according to the invention. The storage medium 4 is a non-volatile memory. The computer program 5 comprises instructions which, when executed by a computer, cause the computer to execute an embodiment of the method according to the invention, as described in Fig. Figure 2 is to be executed. In this embodiment, the computer is a control unit 2, which is configured to operate the system 1. The system 1 further comprises an electric motor 14, which is designed as a permanent magnet synchronous machine and forms the drive for the vehicle 16. The electric motor 14 comprises a 3-phase winding 14a, which is accommodated by the stator of the electric motor 14. The 3-phase winding 14a is energized by an n-level inverter 7, which is configured as a 3-level inverter. The n-level inverter 7 is a 3-level inverter with a t-shape architecture, also called a t-shape inverter or t-type inverter.

[0060] The n-level inverter 7 comprises three main half-bridges 10, each containing two power semiconductor switches 11a-11f. One power semiconductor switch 11a-11c of each of the three main half-bridges 10 forms a high-side switch, while the remaining power semiconductors 11d-11f form low-side switches. Electrically, three nodes 15a-15c are arranged between the respective high-side and low-side switches, each of which is electrically connected to a separate pair of power semiconductor switches 9. The three pairs of power semiconductor switches 9 form the t-branch 8 of the n-level inverter 7.

[0061] The three pairs of power semiconductor switches 9 each comprise two power semiconductor switches 11g-11l connected in anti-series. Each of the three pairs of power semiconductor switches 9 is electrically connected to one of its power semiconductor switches 11h, 11j, 11l via one of the three nodes 15a-15c. Furthermore, each of the three pairs of power semiconductor switches 9 is electrically connected to the other power semiconductor switch 11g, 11i, 11k via an electrical line 3 to a neutral node 13 of a rechargeable battery 6 and can be electrically disconnected from it by means of a contactor 12b. The rechargeable battery 6 preferably has a nominal voltage of 800 V and comprises two battery strings 6a, 6b connected in series, each of which has a nominal voltage of 400 V. The neutral node 13 is electrically located between the two battery strings 6a, 6b.Battery 6 supplies electrical energy to the n-level inverter 7 by connecting its positive terminal to the high-side switches and its negative terminal to the low-side switches. Two contactors, 12a and 12c, allow the positive terminal to be electrically disconnected from the high-side switches and the negative terminal from the low-side switches. The power semiconductor switches 11a-11l and the three contactors 12a-12c can be switched by means of the control unit 2.

[0062] The Fig. Figure 2 shows a flowchart of an embodiment of the method 20 according to the invention, which relates to the embodiment of the system according to the invention consisting of Fig. 1 refers to. As the first process step 21, the inventive method is initialized. Subsequently, data representative of a defect in the 3-level inverter or in the battery that powers the 3-level inverter is received. Fig. 1. The vehicle is supplied with electrical energy. The second step involves detecting a defect in the 3-level inverter or the battery based on the received data. The defect could be, for example, a fault in one of the battery strings or in a power semiconductor switch of the 3-level inverter. If no defect is detected based on the received data, the data is received again, preferably at regular intervals, as long as the vehicle is powered on. Fig. 1 is in operation. As a fourth process step, if a defect has been detected, the 3-level inverter is switched to 2-level operation in response to the detection of the defect. Afterwards, for example, after the vehicle is out of operation... Fig. Once procedure 1 has been discontinued, procedure 20 will be terminated as the fifth procedural step.

[0063] The examples of implementation of Fig. 1 and Fig. In particular, paragraphs 2 do not have a restrictive character and merely serve to clarify the inventive idea. Reference symbol list 1 system 2 Control unit 3 electrical lines 4. Computer-readable medium 5 Computer program 6 Energy source 6a Battery string 6b Battery string 7 N-Level Inverters 8 t-branch 9 Power semiconductor switch pair 10 main semi-bridges 11a Power semiconductor switch 11b Power semiconductor switch 11c Power semiconductor switch 11d Power semiconductor switch 11e Power semiconductor switch 11f Power semiconductor switch 11g power semiconductor switch 11h Power semiconductor switch 11i Power semiconductor switch 11j Power semiconductor switch 11k power semiconductor switch 11l power semiconductor switch 12a Schütz 12b Schütz 12c Schütz 13 neutral nodes 14 Electric motor 14a 3-phase winding 15a first node 15b second node 15c third knot 16 vehicles 20 procedures 21 first procedural step 22 second procedural step 23 third procedural step 24 fourth procedural step 25 fifth procedural step

Claims

[1] Method (20) for operating an N-level inverter (7) comprising the following steps: - Receiving data that is representative of a defect in the N-level inverter (7) or in an electrical energy source that supplies the N-level inverter (7) with electrical energy and that comprises two series-connected battery strings (6a, 6b) where N≥3, - Detecting a defect in the N-level inverter (7) or in the power source depending on the received data, - Initiating operation of the N-level inverter (7) as an X-level inverter, in response to the detection of the defect, wherein X <N sowie X≥2 entspricht, wobei bei einem Defekt an einem der Batteriestränge (6a, 6b) der defekte Batteriestrang elektrisch vom dem N-Level- Inverter (7) und / oder von nicht verwendeten Leistungshalbleitern von Haupt-Halbbrücken des N-Level-Inverters getrennt wird, wobei die elektrische Trennung mittels eines dafür vorgesehenen Schützes (12a, 12b, 12c) ausgeführt wird. [2] Method (20) according to claim 1, wherein the defect in the N-level inverter (7) is a defect in a half-bridge of the N-level inverter (7) or a power semiconductor switch (11a-11f) of a half-bridge of the N-level inverter (7). [3] Method (20) according to claim 1 or 2, wherein the energy source is a DC voltage source comprising at least two series-connected battery strings (6a, 6b), each comprising at least one battery pack (6). [4] Method (20) according to one of the preceding claims, wherein the defect in the energy source is a defect in a battery pack (6) or battery string (6a, 6b) of the energy source. [5] Method (20) according to any of the preceding claims, wherein the N-level inverter (7) is a 3-level inverter and wherein the X-level inverter is a 2-level inverter. [6] Method (20) according to claim 5, wherein the 3-level inverter (7) is a 3-level inverter with t-form architecture. [7] Method (20) according to one of claims 5 or 6, wherein the 3-level inverter comprises three main half-bridges (10) each with two power semiconductor switches (11a-11f), wherein each of the two power semiconductor switches (11a, 11b, 11c) is designed as a high-side switch and is electrically connected to a positive electrical potential of the energy source, wherein the other power semiconductor switches (11d, 11e, 11f) are configured as low-side switches and are each electrically connected to a negative electrical potential of the energy source. [8] Method (20) according to claim 6 or 7, wherein the 3-level inverter in the t-branch of the t-form architecture comprises three pairs of power semiconductor switches (9), wherein the three power semiconductor switch pairs (9) are each connected in anti-series to each other, wherein the power semiconductor switch pairs (9) are each electrically connected to a neutral node (13) of the power source, wherein the first power semiconductor switch pair (9) of the three power semiconductor switch pairs (9) is electrically connected to a first node (15a), wherein the first node (15a) is electrically located between two power semiconductor switches (11a, 11d) of the first main half-bridge (10), wherein the second power semiconductor switch pair (9) of the three power semiconductor switch pairs (9) is electrically connected to a second node (15b), wherein the second node (15b) is electrically located between two power semiconductor switches (11b, 11e) of the second main half-bridge (10), wherein the third power semiconductor switch pair (9) of the three power semiconductor switch pairs (9) is electrically connected to a third node (15c), wherein the third node (15c) is electrically located between two power semiconductor switches (11c, 11f) of the third main half-bridge (10). [9] Method (20) according to one of the preceding claims, wherein the operation as an X-level inverter (7), in response to the detection of a defect in a battery string (6a, 6b) of the power source, a supply of electrical energy to the X-level inverter (7) by means of the power source or a power semiconductor switch (11a-11f) of the main half-bridges (10), comprises the following: - Causing an electrical disconnection of the defective battery string from the N-level inverter (7) such that the N-level inverter (7) is supplied only with the medium voltage of the energy source by means of a functioning battery string (6a, 6b), - Initiating the operation of the N-level inverter (7) as an X-level inverter by means of three alternative half-bridges (8), wherein the alternative half-bridges (8) are formed by at least one power semiconductor switch (11g-11f) of each of the three power semiconductor switch pairs (9) and one power semiconductor switch (11a-11f) of each of the three main half-bridges (10) of the N-level inverter (7). [10] Method (20) according to any of the preceding claims, wherein the operation as an X-level inverter, in response to the detection of a defect in the medium voltage supply or a power semiconductor switch (11g-11f) of the power semiconductor switch pairs (9), comprises: - Arranging for an electrical separation of the medium voltage supply from the N-level inverter (7) such that the N-level inverter (7) is supplied only with the battery voltage of the energy source, - Causing the three pairs of power semiconductor switches (9) to open in such a way that no current can conduct through the three pairs of power semiconductor switches (9), - Initiating the operation of the N-level inverter (7) as an X-level inverter using only the three main half-bridges (10) of the N-level inverter (7). [11] Method (20) according to claim 6 or 7, wherein the 3-level inverter in the t-branch of the t-form architecture comprises three bidirectionally switchable power semiconductor switches (11g - 11l) includes wherein the bidirectionally switchable power semiconductor switches (11g - 11l) are each electrically connected on one side to a neutral node (13) of the power source, wherein the first bidirectionally switchable power semiconductor switch (11g - 11l) of the three bidirectionally switchable power semiconductor switches (11g - 11l) is electrically connected on the other side to a first node (15a), wherein the first node (15a) is electrically located between two power semiconductor switches (11a, 11d) of the first main half-bridge (10), wherein the second bidirectionally switchable power semiconductor switch (11g - 11l) is electrically connected to a second node (15b), wherein the second node (15b) is electrically located between two power semiconductor switches (11b, 11e) of the second main half-bridge (10), wherein the third bidirectionally switchable power semiconductor switch (11g - 11l) is electrically connected to a third node (15c), wherein the third node (15c) is electrically located between two power semiconductor switches (11c, 11f) of the third main half-bridge (10). [12] Method (20) according to claim 11, wherein the operation as an X-level inverter, in response to the detection of a defect in a battery string (6a, 6b) of the power source, supplying the X-level inverter with electrical energy by means of the power source or a power semiconductor switch (11a-11f) of the main half-bridges (10), comprises the following: - Causing an electrical disconnection of the defective battery string from the N-level inverter (7) such that the N-level inverter (7) is supplied only with the medium voltage of the energy source by means of a functioning battery string (6a, 6b), - Initiating the operation of the N-level inverter (7) as an X-level inverter by means of three alternative half-bridges (8), wherein the alternative half-bridges (8) are formed by one of the bidirectionally switchable power semiconductor switches (11g - l) and one of the power semiconductor switches (11a-11f) of the three main half-bridges (10) of the N-level inverter (7). [13] Method (20) according to claim 11 or 12, wherein the operation as an X-level inverter, in response to the detection of a fault in the medium voltage supply or one of the bidirectionally switchable power semiconductor switches (11g-11l), comprises: - Arranging for an electrical separation of the medium voltage supply from the N-level inverter (7) such that the N-level inverter (7) is supplied only with the battery voltage of the energy source, - Causing the opening of the three bidirectionally switchable power semiconductor switches (11g - 111) such that no current can conduct through the three bidirectionally switchable power semiconductor switches (11g - 111), - Initiating the operation of the N-level inverter (7) as an X-level inverter using only the three main half-bridges (10) of the N-level inverter (7). [14] System (1) for data processing, comprising means for carrying out the method (20) according to any of the preceding claims. [15] Computer program (5) comprising instructions which, when the program (5) is executed by a computer, cause it to execute the method (20) according to any one of claims 1 to 13. [16] Computer-readable medium (4) comprising instructions which, when executed by a computer, cause it to execute the method (20) according to any one of claims 1 to 13.

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