INDICATOR DEVICE AND METHOD FOR MAKING AN INDICATOR DEVICE

Abstract

[Problem] To provide high-resolution display devices. [Means to solve the problem] A display device comprises an oxide semiconductor layer with a polycrystalline structure, a gate insulating layer on the oxide semiconductor layer, a gate electrode opposite the oxide semiconductor layer on the gate insulating layer, a first silicon nitride layer in contact with the gate electrode, source wiring in contact with the first silicon nitride layer and electrically connected to the oxide semiconductor layer, a second silicon nitride layer in contact with the source wiring and the first silicon nitride layer, a first transparent conductive layer in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer, and a third silicon nitride layer in contact with the first transparent conductive layer and the second silicon nitride layer, wherein a channel length of the gate electrode is 2.0 µm or less.

Description

TECHNICAL FIELD

[0001] One embodiment of the present invention relates to a display device and a method for manufacturing the display device. More specifically, one embodiment of the present invention relates to a display device using a transistor with an oxide semiconductor and a method for manufacturing the display device. STATE OF THE ART

[0002] Recently, a transistor has been developed that uses an oxide semiconductor for a channel instead of amorphous silicon, low-temperature polysilicon, and single-crystal silicon (see, for example, Patent Literatures 1 and 2). Similar to the transistor that uses amorphous silicon for a channel, the transistor that uses the oxide semiconductor for the channel is simply patterned and formed by low-temperature processing. The transistor that uses the oxide semiconductor for the channel is known to have higher mobility and much lower off-state current than the transistor that uses amorphous silicon for the channel.

[0003] In addition, in recent years, high resolution of display devices has been demanded, and the reduction of pixel size has been promoted. In conjunction with the reduction of pixel size, the reduction of wiring width and transistor size has also been studied. However, this reduction is limited, and the aperture ratio is reduced due to the arrangement of a metal layer and a semiconductor layer that constitute a pixel circuit. Therefore, a transistor in which the oxide semiconductor layer is used for the channel has been developed for use in a transistor of the pixel circuit, which can have sufficient characteristics to drive the pixel circuit even when the transistor size is small. CITATION LISTPATENT LITERATURE Patent Literature 1: Japanese Laid-Open Patent Publication No. 2014-146819 Patent Literature 2: Japanese Patent Laid-Open Publication No. 2015-159315 SUMMARY OF THE INVENTION TECHNICAL PROBLEM

[0004] It is known that a transistor using an oxide semiconductor is strongly influenced by hydrogen contained in an insulating film and located around the oxide semiconductor. With the reduction of pixel sizes in a display device, the size of the transistor (a channel length L) must be reduced. If the channel length L is 2.0 µm or less, there is a possibility that hydrogen will penetrate not only into the source and drain regions but also into the channel region, which may lead to transistor failure.

[0005] An object of an embodiment of the present invention is to provide a high resolution display device. SOLUTION TO THE PROBLEM

[0006] A display device according to an embodiment of the present invention includes an oxide semiconductor layer having a polycrystalline structure, a gate insulating layer on the oxide semiconductor layer, a gate electrode opposite to the oxide semiconductor layer on the gate insulating layer, a first silicon nitride layer in contact with the gate electrode, a source wiring in contact with the first silicon nitride layer and electrically connected to the oxide semiconductor layer, a second silicon nitride layer in contact with the source wiring and the first silicon nitride layer, a first transparent conductive layer in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer, and a third silicon nitride layer in contact with the first transparent conductive layer and the second silicon nitride layer, wherein a channel length of the gate electrode is 2.0 μm or less.

[0007] A display device according to an embodiment of the present invention comprises an oxide semiconductor layer having a polycrystalline structure, a gate insulating layer provided on the oxide semiconductor layer, a gate electrode opposite the oxide semiconductor layer on the gate insulating layer, a first silicon nitride layer provided in contact with the gate electrode, a silicon oxide layer provided in contact with the first silicon nitride layer, a source wiring provided in contact with the silicon oxide layer and electrically connected to the oxide semiconductor layer, and a second silicon nitride layer provided in contact with the source wiring and the first silicon nitride layer, a first transparent conductive layer provided in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer, and a third silicon nitride layer,which is provided in contact with the first transparent conductive layer and the second silicon nitride layer, wherein a channel length of the gate electrode is less than 2.0 µm and a thickness of the silicon oxide layer is less than a thickness of the first silicon nitride layer, a thickness of the second silicon nitride layer, and a thickness of the third silicon nitride layer, respectively.

[0008] A method of manufacturing a display device according to an embodiment of the present invention, the method comprising the steps of: forming an oxide semiconductor layer having a polycrystalline structure; depositing a gate insulating layer on the oxide semiconductor layer; forming a gate electrode opposite the oxide semiconductor layer on the gate insulating layer; depositing a first silicon nitride layer in contact with the gate electrode; forming a source wiring in contact with the first silicon nitride layer and electrically connected to the oxide semiconductor layer; forming a second silicon nitride layer in contact with the source wiring and the first silicon nitride layer; forming a first transparent conductive layer in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer;and depositing a third silicon nitride layer in contact with the first transparent conductive layer and the second silicon nitride layer. A channel length of a channel region overlapping the gate electrode in the oxide semiconductor layer is 2.0 µm or less, and a deposition temperature of the first silicon nitride layer, the second silicon nitride layer, and the third silicon nitride layer is 150°C or more and 250°C or less, respectively. BRIEF DESCRIPTION OF THE CHARACTERS Fig. 1 is a schematic plan view showing a configuration of a display device according to an embodiment of the present invention. Fig. 2 is a schematic plan view showing a circuit configuration of a display device according to an embodiment of the present invention. Fig. 3 is a circuit diagram showing a pixel circuit of a pixel of a display device according to an embodiment of the present invention. Fig. 4 is a cross-sectional view showing an outline of a display device according to an embodiment of the present invention. Fig. 5 is a plan view showing a configuration of a pixel of a display device according to an embodiment of the present invention. Fig. 6 is a plan view showing a configuration of a pixel of a display device according to an embodiment of the present invention. Fig. 7 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present invention. Fig. 8 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present invention. Fig. 9 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present invention. Fig. 10 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present invention. Fig. 11 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present invention. Fig. 12 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present invention. Fig. 13 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present invention. Fig. 14 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present invention. Fig. 15 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present invention. Fig. 16 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present invention. Fig. 17 is a cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present invention. Fig. 18 is a cross-sectional view showing an outline of a display device according to an embodiment of the present invention. Fig. 19 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present invention. Fig. 20 is a cross-sectional view showing a method of manufacturing a display device according to an embodiment of the present invention. Fig. 21 is a cross-sectional view showing a method of manufacturing a display device according to an embodiment of the present invention. Fig. 22 is a cross-sectional view showing an outline of a display device according to an embodiment of the present invention. Fig. 23 is a cross-sectional view showing a method of manufacturing a display device according to an embodiment of the present invention. Fig. 24 is a cross-sectional view showing a method of manufacturing a display device according to an embodiment of the present invention. Fig. 25 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present invention. Fig. 26 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present invention. DESCRIPTION OF EMBODIMENTS

[0009] Embodiments of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. A configuration that a person skilled in the art can easily devise by appropriately changing the configuration of the embodiment while maintaining the gist of the invention is of course included in the scope of the present invention. For clarity, the drawings may be schematically illustrated with respect to widths, film thicknesses, shapes, etc. of the respective portions in comparison with actual embodiments. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In the present configurations and drawings, the same components are assigned the same reference numerals as those assigned to the corresponding previously described components in the respective previously described drawings.Their detailed description can therefore be omitted if necessary.

[0010] A "semiconductor device" is a device that functions by exploiting the properties of a semiconductor. A transistor and a semiconductor circuit are two types of semiconductor devices. For example, a semiconductor device can be an integrated circuit (IC) such as a display device or a microprocessor unit (MPU), or a transistor used in a memory circuit.

[0011] A "display device" is a structure that displays an image using an electro-optical layer. For example, the term "display device" may refer to a display panel containing the electro-optical layer or to a structure with other optical elements (e.g., a polarized element, a backlight, a touch panel, and the like) connected to a display cell. An "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, or an electrophoretic layer, unless technically contradictory.Although a liquid crystal display device including the liquid crystal layer and an organic EL display device including the organic EL layer are used as examples for explaining the display device in the embodiments described later, the structure according to the embodiment can be applied to a display device including the other electro-optical layers described above.

[0012] In the embodiments of the present invention, a direction from a substrate toward an oxide semiconductor layer is referred to as above or above. Conversely, a direction from the oxide semiconductor layer to the substrate is referred to as below or below. For convenience of explanation, the term "above" or "below" is used, but, for example, the substrate and the oxide semiconductor layer may be arranged so that the relationship between above and below differs from the drawings. For example, in the following explanation, the term "oxide semiconductor layer on the substrate" only describes the above / below relationship between the substrate and the oxide semiconductor layer as described above, and another member may be arranged between the substrate and the oxide semiconductor layer.The terms "over" or "under" refer to a stacking order in which multiple layers are stacked, and may represent a positional relationship where the transistor does not overlap with a pixel electrode in a plan view when expressed as a pixel electrode above the transistor. On the other hand, when expressed as a pixel electrode vertically above the transistor, it represents a positional relationship where the transistor overlaps the pixel electrode in a plan view.

[0013] In this specification, the expressions "α includes A, B, or C," "α includes any one of A, B, and C," "α includes a selection from a group consisting of A, B, and C," and the like do not exclude the case where α includes a plurality of combinations of A to C, unless otherwise specified. Furthermore, these expressions do not exclude the case where α includes other elements.

[0014] Furthermore, the following embodiments can be combined with each other, provided there is no technical contradiction. [First embodiment]

[0015] A display device 10 according to an embodiment of the present invention will be described with reference to Fig. 1 to Fig. 26 described. [1. Overview of the display device]

[0016] Based on Fig. 1 and Fig. 2 an overview of the display device 10 is given. Fig. 1 is a schematic plan view showing a configuration of the display device 10. Fig. Fig. 2 is a schematic plan view showing a circuit configuration of the display device 10. For example, the display device 10 is a liquid crystal display device.

[0017] As in Fig. 1 or Fig. 2, the display device 10 includes an array substrate 100, a sealing member 200, a counter substrate 190, a flexible printed circuit board (FPC) 300, and an IC chip 400. The array substrate 100 and the counter substrate 190 are connected to each other by the sealing member 200.

[0018] Furthermore, the display device 10 comprises a display area 122 and an edge area 121 surrounding the display area 122. The edge area 121 comprises a sealing area 124 and the outer side of the sealing area 124 surrounding the sealing area 124. The outer side of the sealing area 124 has an exposed area 126.

[0019] A plurality of pixels 180 are arranged in a matrix in a first direction D1 and a second direction D2 in the display area 122. The display area 122 is an area that, in a plan view, overlaps a liquid crystal layer (not shown) containing liquid crystal molecules.

[0020] A shielding part 192 is arranged in the edge region 121, overlapping the array substrate 100 and the counter substrate 190. The sealing part 200 is arranged in the sealing region 124. The sealing region 124 is a region that overlaps the sealing part 200 in a plan view.

[0021] The exposed area 126 is an area where the array substrate 100 is exposed from the counter substrate 190. An FPC connector part 150 is arranged in the exposed area 126. A part of the FPC 300, the IC chip 400, and a wiring part 115 are arranged in the exposed area 126.

[0022] The sealing area 124, the outside of the sealing area 124 and the exposed area 126 may be collectively referred to as the frame area in the display device 10.

[0023] The FPC connector part 150 includes a plurality of FPC connectors. The wiring part 115 includes a plurality of data signal source lines 116. The shielding part 192 overlaps the sealing part 200, a first driver circuit 110, a second driver circuit 120, a part of the wiring part 115, and a common wiring 145, and functions to conceal the sealing part 200, the first driver circuit 110, the second driver circuit 120, a part of the wiring part 115, the common wiring 145, and the like.

[0024] The case where the shape of the array substrate 100 of the display device 10 and the shape of the display area 122 are octagonal will be described. Furthermore, the shape of the array substrate 100 of the display device 10 and the shape of the display area 122 are not limited to octagonal shapes and may be rectangular or circular. [2. Circuit configuration of the display device 10]

[0025] Next, a circuit configuration of the display device 10 will be described with reference to Fig. 2. Same or similar configurations as in Fig. are described as needed.

[0026] As in Fig. As shown in Figure 2, the FPC connector 150 connected to the FPC 300 is connected to the IC chip 400 and the second driver circuit 120 through a connecting wiring 141. The IC chip 400 is connected to the first driver circuit 110 using the plurality of data signal source lines 116.

[0027] The first driver circuit 110 is arranged parallel to the first direction D1 of the display area 122. Furthermore, the second driver circuit 120 is arranged parallel to the second direction D2 of the display area 122. The first driver circuit 110 and the second driver circuit 120 overlap the sealing area 124 ( Fig. ). The area in which the sealing area 124 overlaps the first driver circuit 110 and the second driver circuit 120 is an example and not limited to the Fig. 1. The area where the sealing area 124 overlaps the first driver circuit 110 and the second driver circuit 120 may be an area outside an area where a pixel circuit 182 (see Fig. 3) the plurality of pixels 180 is arranged.

[0028] For example, the first driver circuit 110 is a source driver and includes a plurality of multiplexer circuits 111 for selecting a data signal. The multiplexer circuit 111 includes a plurality of analog switches (ASW) 112. The plurality of ASWs 112 are electrically connected between a plurality of data signal lines 131 and the plurality of data signal source lines 116 and have the function of electrically connecting the corresponding data signal line 131 and the data signal source line 116, respectively. For the sake of simplicity, the number of ASWs 112 in the multiplexer circuit 111 shown in Fig. 2, for example, two. The number of ASWs 112 included in the multiplexer circuit 111 may be greater than two.

[0029] For example, the second driver circuit 120 is a gate driver circuit. Furthermore, the IC chip 400 provides, for example, a control signal for driving the pixel circuit 182 to at least one of the first driver circuits 110 and the second driver circuits 120.

[0030] For example, each of the plurality of pixels 180 may correspond to a subpixel R, a subpixel G, and a subpixel B. The pixel 180 is the smallest unit that forms part of the images displayed in the display area 122. Each of the pixels 180 comprises a display element. In the Fig. In the example shown in Figure 1, the display element is a liquid crystal element 170 (see Fig. 3). The color corresponding to the subpixel is determined by the properties of the liquid crystal element 170 or a color filter (not shown) arranged in the subpixel. Furthermore, the color filter can be arranged in the counter substrate 190 or the array substrate 100.

[0031] For example, subpixel R may include a red color filter that emits red, subpixel G may include a green color filter that emits green, and subpixel B may include a blue color filter that emits blue.

[0032] A plurality of data signal lines, including data signal line 131, extend from first driver circuit 110 in the second direction D2 and are connected to the plurality of pixels 180 arranged in the second direction D2. A plurality of scan signal lines, including scan signal line 129, extend from second driver circuit 120 in the first direction D1 and are connected to the plurality of pixels 180 arranged in the first direction D1.

[0033] For example, the common wiring 145 overlaps the peripheral region 121 and is arranged within the outer peripheral region of the peripheral region 121. A common voltage is supplied to the common wiring 145 from an external device. For example, the common voltage may be a voltage between a voltage of the positive side voltage amplitude of the data signal and a voltage of the negative side voltage amplitude of the data signal, may be a voltage as a reference of the voltage amplitude, may be 0 V, or may be a ground voltage. The common wiring 145 may be electrically connected to a common electrode (not shown) formed in the counter substrate 190 via a plurality of connection portions 143, and may be electrically connected to a common electrode 146 (see Fig. 3) be connected.

[0034] When the FPC 300 is connected to the FPC connector 150, the display device 10 is connected to an external device (not shown) connected to the FPC 300, and a signal from the external device is supplied to, for example, the IC chip 400, the first driver circuit 110, the second driver circuit 120, and each pixel 180. The display device 10 controls the pixel circuit 182 arranged in the display device 10 using a signal from the external device and control signals generated by the IC chip 400, the first driver circuit 110, and the second driver circuit 120. [3. Configuration of pixel circuit 182 of pixel 180]

[0035] A configuration of the pixel circuit 182 will be described with reference to Fig. 3 described. Fig. 3 is a schematic diagram showing a configuration of the pixel circuit 182 of the pixel 180 in the display device 10. The same or similar configurations as in Fig. 1 and Fig. 2 will be described as needed.

[0036] For example, the pixel circuit 182 includes a transistor 160, the liquid crystal element 170, and a capacitance element 168. Although details will be described later, for example, a first electrode of the capacitance element 168 is a pixel electrode PTCO, and a second electrode of the capacitance element 168 is grounded. Similar to the capacitance element 168, a first electrode of the liquid crystal element 170 is the pixel electrode PTCO, and a second electrode of the liquid crystal element 170 is a common electrode CTCO. Furthermore, the first electrode and the second electrode of the capacitance element 168 are interchangeable. The first electrode and the second electrode of the liquid crystal element 170 are interchangeable. The second electrode of the liquid crystal element 170 is the common electrode 146. Furthermore, the second electrode of the capacitance element 168 may be the common electrode CTCO or the common electrode 146.The transistor 160 includes a first gate electrode 161, a first source electrode 163, and a first drain electrode 164. The first gate electrode 161 is connected to the scan signal line 129. The first source electrode 163 is connected to the data signal line 131. The first drain electrode 164 is connected to the first electrode of the capacitance element 168 and the first electrode of the liquid crystal element 170. Furthermore, in this specification and the like, for the sake of simplicity, the first source electrode 163 may be referred to as the source electrode, and the first drain electrode 164 may be referred to as the drain electrode, and the function as the source and the function as the drain of each electrode may be replaced by the voltage supplied (applied) to the source electrode and the drain electrode of the transistor 160.

[0037] Any signal (voltage or current) is supplied to the pixel circuit 182 of each of the three subpixels of the display device 10, and the display device 10 can display an image. For example, the IC chip 400, the first driver circuit 110, the second driver circuit 120, and the external device supply a current or voltage to each of the pixel electrodes and the common electrode 146 included in the pixel circuit 182, thereby changing the alignment state of the liquid crystal molecules included in the liquid crystal element 170. This allows the display device 10 to display an image. [4. Configuration of the display device 10]

[0038] With reference to Fig. 4 to Fig. 6, an overview of the display device 10 according to an embodiment of the present invention is described. Fig. 4 is a cross-sectional view showing a configuration of the display device 10 according to an embodiment of the present invention. Fig. The cross-sectional view shown in Figure 4 shows a transistor Tr2 in the peripheral region 121 and a transistor Tr1 in the circuit of the pixel circuit 182 side by side. In practice, the pixel circuit 182 is included in the display region 122 and a peripheral circuit is included in the peripheral region 121. Therefore, it is needless to say that the pixel circuits and the peripheral circuit shown in Fig. 4 are shown side by side, are arranged separately in the display device 10. In addition, the Fig. 4 shows the edge of an opening of pixel 180 and a portion of a transmission area (opening area) that contributes to image display. For example, transistor Tr2 and transistor Tr1 are thin-film transistors. The same or similar configurations as in Fig. 1 to Fig. 3 will be described as needed.

[0039] In addition, Fig. 5 and Fig. 6 are plan views showing a configuration of the pixels of the display device 10 according to an embodiment of the present invention. Fig. 5 shows a layout from a light shielding layer LS to a passivation layer PAS3, and Fig. 6 shows a layout from the passivation layer PAS3 to the common electrode CTCO.

[0040] As in Fig. As shown in Figure 4, each layer included in the display device 10 is arranged above a substrate SUB1 (a third direction D3). The display device 10 includes the transistor Tr1, the transistor Tr2, a wiring group W including a plurality of wirings, a connection electrode ZTCO, the pixel electrode PTCO, a common auxiliary electrode CMTL, and the common electrode CTCO. TCO is an abbreviation for "Transparent Conductive Oxide." The transistor Tr1 is a transistor included in the pixel circuit 182 of the pixel 180 of the display device 10. The transistor Tr2 is a transistor included in the peripheral circuit, such as the first driver circuit 110 or the second driver circuit 120. For example, the wiring group W includes a wiring W1, a wiring W2, and a wiring W3. [4-1. Configuration of transistor Tr1]

[0041] As in Fig. 4, the transistor Tr1 is arranged above the substrate SUB1. The transistor Tr1 includes at least an oxide semiconductor layer POS, a first gate insulating layer GI1, a gate wiring GL1 (also referred to as a gate electrode), a passivation layer PAS1, the wiring W3, a passivation layer PAS2, and the connection electrode ZTCO (also referred to as a connection electrode). The transistor Tr1 may further include the passivation layer PAS3 on the terminal electrode ZTCO. The transistor Tr1 may further include a second insulating layer IL2 and the light-shielding layer LS between the oxide semiconductor layer POS and the substrate SUB1. In addition, the transistor Tr1 may further include a metal oxide layer MO1 containing aluminum as a main component, which is arranged in contact with the oxide semiconductor layer POS between the oxide semiconductor layer POS and the second insulating layer IL2. Although in Fig. 4 describes an example in which the metal oxide layer MO1 is arranged below the oxide semiconductor layer POS, an embodiment of the present invention is not limited to this, and the oxide semiconductor layer POS may be in contact with the second insulating layer IL2 (see Fig. 24).

[0042] The gate wiring GL1 faces the oxide semiconductor layer POS. The first gate insulating layer GI1 is disposed between the oxide semiconductor layer POS and the gate wiring GL1. Although a top-gate transistor in which the oxide semiconductor layer POS is positioned closer to the substrate SUB1 than the gate wiring GL1 is illustrated as the transistor Tr1 in the present embodiment, a bottom-gate transistor in which the positional relationship between the gate wiring GL1 and the oxide semiconductor layer POS is reversed may also be used. Furthermore, the configuration from the substrate SUB1 to the passivation layer PAS3 can be referred to as a semiconductor device.

[0043] The oxide semiconductor layer POS has a polycrystalline structure containing a multitude of crystal grains. Although details will be described later, the oxide semiconductor layer POS with a polycrystalline structure can be formed using a poly-OS (polycrystalline oxide semiconductor) technique. Hereinafter, the oxide semiconductor with a polycrystalline structure may be referred to as poly-OS.

[0044] Although details will be described later, the oxide semiconductor layer POS contains two or more metal elements, including indium, and the proportion of indium in the two or more metal elements is 50% or more. Metal elements other than indium include gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanides. However, it is sufficient for the oxide semiconductor layer POS to contain the poly-OS, and metal elements other than those mentioned above may also be included.

[0045] The oxide semiconductor layer POS includes a channel region OS1 and a low-resistance region OS2. The channel region OS1 is an oxide semiconductor layer located in a region that overlaps the gate wiring GL1 in a plan view. The channel region OS1 is switched between a conducting and a non-conducting state depending on the voltage applied to the gate wiring GL1. The low-resistance region OS2 is a region with a lower resistance than the channel region OS1. The low-resistance region OS2 functions as a source or drain region. For example, the resistance of the low-resistance region OS2 is reduced by ion implanting an impurity into the oxide semiconductor layer POS.

[0046] As in Fig. As shown in Figure 5, the gate wiring GL1 is arranged along the first direction D1. A region of the gate wiring GL1 that overlaps the oxide semiconductor layer POS is referred to as the gate electrode. The oxide semiconductor layer POS is arranged to cross the gate wiring GL1. In addition, a region that overlaps the gate wiring GL1 is the channel region OS1 in the oxide semiconductor layer POS. Fig. 5, in the channel region OS1, a width of the gate wiring GL1 (length in the second direction D2) corresponds to a channel length L. Moreover, the oxide semiconductor layer POS (length in the first direction D1) corresponds to the channel width W in the channel region OS1. In the present embodiment, a width (channel length L) of the gate wiring GL1 is 2.0 µm or less, preferably 1.5 µm or less.

[0047] The first gate insulating layer GI1 is disposed on the oxide semiconductor layer POS. The passivation layer PAS1 is disposed on the first gate insulating layer GI1. The wiring W3 is disposed on the passivation layer PAS1. As shown in Fig. 5 in a plan view, the wiring W3 is arranged along the second direction D2 and functions as a source wiring. The wiring W3 is connected to the low-resistance region OS2 via an opening part SCON1 arranged in the first gate insulating layer GI1 and the passivation layers PAS1. The passivation layer PAS2 is arranged on the passivation layer PAS1 and the wiring W3. The terminal electrode ZTCO is arranged on the passivation layer PAS2. The connection electrode ZTCO is connected to the low-resistance region OS2 via an opening part ZCON arranged in the first gate insulating layer GI1 and the passivation layers PAS1 and PAS2. The connection electrode ZTCO is in contact with the low-resistance region OS2 at the bottom of the opening part ZCON. A region where the connection electrode ZTCO contacts the low-resistance region OS2 is called a contact region CON1.

[0048] The second insulating layer IL2 and the light-shielding layer LS are arranged between the oxide semiconductor layer POS and the substrate SUB1. As shown in Fig. 5, the light-shielding layer LS is arranged in a plan view along the first direction D1 and is arranged in an area overlapping the gate wiring GL1. Moreover, the light-shielding layer LS is arranged so as to intersect the oxide semiconductor layer POS. In other words, the light-shielding layer LS is arranged in a plan view in an area overlapping the channel region OS1. The light-shielding layer LS prevents light incident from the substrate SUB1 side from reaching the channel region OS1. In the case where a conductive layer is used as the light-shielding layer LS, a voltage is applied to the light-shielding layer LS to control the channel region OS1. In the case where a voltage is supplied to the light-shielding layer LS, the light-shielding layer LS and the gate wiring GL1 may be electrically connected.In a plan view, the contact area CON1 is arranged in an area that does not overlap the light shielding layer LS.

[0049] In the case where the display device 10 is required to have high light transmittance, one of the source electrode and the drain electrode may be formed of a metallic conductive layer, and the other of the source electrode and the drain electrode may be formed of a transparent conductive layer. For example, when the transparent conductive layer such as ITO is formed to contact a silicon layer, a surface of the silicon layer is oxidized due to process gases and oxygen ions at the time of ITO deposition. Since the oxide layer formed on the silicon layer has high resistance, the contact resistance between the silicon layer and the transparent conductive layer increases. This results in poor electrical contact between the silicon layer and the transparent conductive layer.On the other hand, even if the transparent conductive layer is formed in contact with the oxide semiconductor layer, the high-resistance oxide layer, as described above, is not formed on the oxide semiconductor layer. Therefore, no defects occur in the electrical contacts between the oxide semiconductor layers and the transparent conductive layer.

[0050] To realize a high-resolution display device 10, the width (channel length L) of the gate electrode of the transistor using the oxide semiconductor layer must be 2 µm or less. Given the variations in the gate electrode width due to a photolithography process and an etching process in the manufacturing process of the display device 10, it is necessary that the display device 10 can be driven as a transistor even if the width is 1.5 µm or less.

[0051] It is known that oxygen deficiencies occur in oxide semiconductors due to processing damage such as etching. When hydrogen is trapped in the oxygen deficiencies, the resistance of the oxide semiconductor can be reduced, allowing it to function as a conductor. On the other hand, supplying oxygen to the oxygen deficiencies to increase the resistance of the oxide semiconductor enables it to function as a semiconductor. That is, for satisfactory operation as a transistor, it is preferable to increase the resistance of the oxide semiconductor in the channel region by supplying oxygen to the oxygen deficiencies, and to decrease the resistance of the oxide semiconductor in the source region or drain region by supplying hydrogen to the oxygen deficiencies.

[0052] The properties of a transistor using an oxide semiconductor are strongly influenced by hydrogen and oxygen contained in an insulating film arranged around the oxide semiconductor. If excessive oxygen is supplied to the oxide semiconductor, the excess oxygen will produce a defect level different from that caused by oxygen deficiencies, resulting in a reduction in transistor reliability and a decrease in field-effect mobility. Furthermore, if too much hydrogen is supplied to the oxide semiconductor and the channel region is also supplied with hydrogen, the transistor will become depleted and malfunction.

[0053] Therefore, in order to miniaturize the transistor using the oxide semiconductor, oxygen and hydrogen must be appropriately supplied to the channel region OS1 with a channel length of 2.0 µm or less and the low-resistance region OS2.

[0054] In one embodiment of the present invention, hydrogen is suitably supplied to the oxide semiconductor layer POS, thereby reducing the resistance of the low-resistance region OS2 acting as the source region and drain region and suppressing the diffusion of hydrogen into the channel region OS1.

[0055] In the present embodiment, a silicon nitride layer is used as passivation layers PAS1 to PAS3. The silicon nitride layer contains more hydrogen than silicon oxide. When exposed to heat above 250°C, the hydrogen contained in the silicon nitride layer diffuses. Therefore, the silicon nitride layer is formed as passivation layers PAS1 to PAS3 at 150°C or more and 250°C or less. This can suppress the diffusion of a large amount of hydrogen contained in the silicon nitride layer and prevent excessive supply of hydrogen into the low-resistance region OS2. Therefore, it is possible to prevent depletion of the transistor Tr1. The structure of the passivation layers PAS1 to PAS3 will be described later. [4-2. Configuration of transistor Tr2]

[0056] The transistor Tr2 includes a p-type transistor Tr2-1 and an n-type transistor Tr2-2. When the transistor Tr2 is not distinguished, the transistor included in the peripheral region 121 is expressed as transistor Tr2. When the transistor Tr2 is distinguished, the transistor Tr2 is expressed as the p-type transistor Tr2-1, the n-type transistor Tr2-2, or the like.

[0057] Each of the p-type transistors Tr2-1 and n-type transistors Tr2-2 includes a gate electrode GL2, a second gate insulating layer GI2, and a semiconductor layer S. The gate electrode GL2 faces the semiconductor layer S. The second gate insulating layer GI2 is disposed between the semiconductor layer S and the gate electrode GL2. For example, the transistor Tr2 of the display device 10 is a top-gate transistor in which the gate electrode GL2 is disposed above the semiconductor layer S. The transistor Tr2 may be a bottom-gate transistor in which the positional relationship between the semiconductor layer S and the gate electrode GL2 is reversed.

[0058] A first insulating layer IL1 is arranged on the substrate SUB1. The first insulating layer IL1 acts as a base layer. The arrangement of the first insulating layer IL1 makes it possible to suppress the penetration of contaminants from the substrate SUB1 into the semiconductor layer S.

[0059] The semiconductor region S of the p-type transistor Tr2-1 includes the semiconductor regions S1 and S2. The semiconductor region S of the n-type transistor Tr2-2 includes the semiconductor regions S1, S2, and S3. The semiconductor region S1 is a semiconductor in a region that overlaps the gate electrode GL2 in a plan view. The semiconductor region S1 functions as the channel region of the transistor Tr2-1. The semiconductor region S2 functions as a conductor. The semiconductor region S3 functions as a conductor with higher resistance than the semiconductor region S2. The semiconductor region S3 suppresses the degradation of hot carriers by attenuating hot carriers entering the semiconductor region S1.

[0060] The second insulating layer IL2 and the first gate insulating layer GI1 are disposed on the gate electrode GL2. The wiring W2 is disposed on these insulating layers. The wiring W2 functions as the source electrode and drain electrode of the transistor Tr2. The wiring W2 is connected to the semiconductor region S via an opening portion SCON2 disposed in the second insulating layer IL2, the first gate insulating layer GI1, and the second gate insulating layer GI2. Furthermore, the wiring W2 is connected to the wiring W1 via an opening WC1 disposed in the second insulating layer IL2 and the first gate insulating layer GI1. The passivation layer PAS1 is disposed on the wiring W2. The wiring W3 is disposed on the passivation layer PAS1. The wiring W3 is connected to the wiring W2 via an opening WC2 disposed in the passivation layer PAS1.

[0061] The gate electrode GL2 is formed in the same layers as the wiring W1 and the light-shielding layer LS. The wiring W2 is formed in the same layers as the gate wiring GL1. "Same layer" means that a single layer is structured to form multiple elements. [4-3. Other display device configurations]

[0062] Next, a layer structure disposed on the transistor Tr1 and the transistor Tr2 will be described. In the display region 122, a color filter CF is disposed on the passivation layer PAS3. The positional deviation between the color filter CF and the pixel circuit can be suppressed by disposing the color filter CF on the substrate SUB1 side. In addition, a third insulating layer IL3 is disposed on the color filter CF and the passivation layer PAS3. Since the color filter CF is not disposed in the peripheral region 121, the third insulating layer IL3 is disposed on the passivation layer PAS3. The third insulating layer IL3 functions as a planarization film.

[0063] The pixel electrode PTCO is arranged on the third insulating layer IL3 in the display area 122. The pixel electrode PTCO is connected to the connection electrode ZTCO via an opening part PCON arranged in the third insulating layer IL3. As shown in Fig. 5 and Fig. As shown in Figure 6, the pixel electrode PTCO overlaps the gate wiring GL1, the oxide semiconductor layer POS, and the connection electrode ZTCO between two adjacent wirings W3. The pixel electrode PTCO contacts the connection electrode ZTCO at the opening part PCON, which overlaps the gate wiring GL1.

[0064] A fourth insulating layer IL4 is disposed in the display region 122 and the peripheral region 121. In the display region 122, the fourth insulating layer IL4 is disposed to cover the pixel electrode PTCO and the third insulating layer IL3. Furthermore, in the peripheral region 121, the fourth insulating layer IL4 is disposed on the third insulating layer IL3. Furthermore, the fourth insulating layer IL4 is in contact with the third insulating layer IL3 at an end portion of the peripheral region 121 (the end portion of the substrate SUB1). This allows moisture contained in the third insulating layer IL3 to be sealed.

[0065] The common auxiliary electrode CMTL and the common electrode CTCO are arranged on the fourth insulating layer IL4 in the display area 122. As shown in Fig. As shown in Figure 6, the common auxiliary electrode CMTL and the common electrode CTCO are arranged in a grid pattern so as to overlap the gate wiring GL and the wiring W3. That is, the common auxiliary electrode CMTL is commonly arranged for a plurality of pixels. In other words, the common auxiliary electrode CMTL has an opening OP. The opening OP is arranged so as to expose the pixel electrode PTCO. The pattern of the opening OP is arranged within the pattern of the pixel electrode PTCO. Moreover, a region where the opening OP is arranged corresponds to the opening part of an opening of the pixel. That is, the opening part ZCON (the first contact area CON1) is included in the opening part of the pixel. The opening part of the pixel is a region that allows a user to see the light of the pixel.For example, a region shielded by the metal layer and invisible to the user is not included in the opening part of the pixel. That is, the opening part of the pixel can be referred to as a “translucent region.” In addition, a region extending along the direction D1 of the auxiliary common electrode CMTL overlaps the opening part PCON. In the display area 122, the auxiliary common electrode CMTL also functions as a black matrix. In addition, the auxiliary common electrode CMTL and the common electrode CTCO are arranged in the opening part PCON. Although in . Fig. 4 describes the case where the common electrode CTCO is arranged on the common auxiliary electrode CMTL, the common auxiliary electrode CMTL can be arranged on the common electrode CTCO. Here, as shown in Fig. As shown in Figure 4, the pixel electrode PTCO connects to the common electrode CTCO via the fourth insulating layer IL4. A region where the pixel electrode PTCO overlaps the common electrode CTCO via the fourth insulating layer IL4 functions as a storage capacitor.

[0066] A spacer SP is disposed on the common electrode CTCO to fill the opening portion PCON. The spacer SP protrudes toward a counter substrate SUB2. Through the spacer SP, the spacer SP of a liquid crystal layer LC is disposed not only in the display region 122 but also in the peripheral region 121. In the display region 122 and the peripheral region 121, an alignment film OF1 is disposed on the third insulating layer IL3, the common electrode CTCO, and the spacer SP.

[0067] A black matrix BM is disposed on the counter substrate SUB2 in the peripheral region 121. An overcoat layer OC is disposed in the peripheral region 121 and the display region 122. An alignment film OF2 is disposed to cover the overcoat layer OC. The substrate SUB1 and the counter substrate SUB2 are arranged so that the alignment film OF1 and the alignment film OF2 face each other and are connected to each other by the sealing member 200 disposed in the peripheral region 121. The liquid crystal layer LC is disposed in a region surrounded by the sealing member 200. [5. Method for manufacturing the display device 10]

[0068] A method of manufacturing the display device 10 according to an embodiment of the present invention will be described. Fig. 7 and Fig. 8 are flowcharts illustrating a method of manufacturing the display device 10 according to an embodiment of the present invention. Fig. 9 to Fig. 17 are cross-sectional views illustrating a manufacturing method for the display device 10 according to an embodiment of the present invention.

[0069] First, the first insulating layer IL1, a semiconductor region S and the second gate insulating layer GI2 are formed on the substrate SUB1 (see step S1001 in Fig. 7 and Fig. 9).

[0070] A rigid substrate with light transmission, such as a glass substrate, a quartz substrate, or a sapphire substrate, is used as the substrate SUB1. When the substrate SUB1 needs to be flexible, a substrate containing an organic resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, is used. When the substrate containing an organic resin is used as the substrate SUB1, an impurity element can be introduced into the organic resin to improve the heat resistance of the substrate SUB1.

[0071] The first insulating layer IL1 is formed by a CVD (chemical vapor deposition) method or a sputtering method. For example, an inorganic insulating material such as silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride (SiNx), or silicon nitride oxide (SiNxOy) is used as the first insulating layer IL1. SiOxNy is a silicon compound containing a smaller proportion (x > y) of nitrogen (N) than of oxygen (O). SiNxOy is a silicon compound containing a smaller proportion (x > y) of oxygen than of nitrogen. The first insulating layer IL1 can be a single-layer structure using the above-described inorganic insulating material or a stacked structure.

[0072] In addition, polysilicon is used as the semiconductor region S. Furthermore, the second gate insulating layer GI2 uses the same deposition method and the same inorganic insulating material as for the first insulating layer IL1.

[0073] Next, the light shielding layer LS is formed on the gate insulating layer GI2 (see step S1002 in Fig. 7 and see Fig. 9).

[0074] For example, the light-shielding layer LS is formed by processing a conductive layer formed by the sputtering method. A typical metal material is used as the light-shielding layer LS. Examples of materials used as the light-shielding layer LS include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and an alloy or compound thereof. Furthermore, the light-shielding layer LS can be a single-layer structure using the materials described above or a stacked structure.

[0075] Next, the second insulating layer IL2 is formed on the light shielding layer LS (see step S1003 in Fig. 7 and see Fig. 9). The second insulating layer IL2 uses the same deposition method and the same inorganic insulating material as for the first insulating layer IL1.

[0076] Furthermore, the second insulating layer IL2 may be a single-layer structure using the above-described inorganic insulating material or a stacked structure. In the case where the second insulating layer IL2 is a stacked structure, it is preferable that a nitrogen-containing insulating material and an oxygen-containing insulating material are formed in this order from the substrate SUB1. For example, an impurity that diffuses from the substrate SUB1 toward the oxide semiconductor layer POS can be blocked by using the nitrogen-containing insulating material. In addition, oxygen may be released during heat treatment by using oxygen-containing insulating materials. For example, the heat treatment temperature at which the oxygen-containing insulating material releases oxygen is 600°C or less, 500°C or less, 450°C or less, or 400°C or less.This means, for example, that the oxygen-containing insulating material releases oxygen at a heat treatment temperature carried out in a manufacturing process of the display device when a glass substrate is used as the substrate SUB1. In the present embodiment, the insulating material is formed, for example, from silicon nitride containing nitrogen. Furthermore, the insulating material is formed, for example, from oxygen-containing silicon oxide.

[0077] Next, the metal oxide layer MO1 containing aluminum as a main component is formed on the second insulating layer IL2 (see step S1004 in Fig. 7 and see Fig. 10).

[0078] The metal oxide layer MO1 is formed using a sputtering process. For example, an inorganic insulating material such as aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum nitride oxide (AlNxOy), or aluminum nitride (AlNx) is used as the metal oxide layer MO1, which contains aluminum as its main component. AlOxNy is an aluminum compound that contains a smaller proportion (x > y) of nitrogen (N) than of oxygen (O). AlNxOy is an aluminum compound that contains a smaller proportion (x > y) of oxygen than of nitrogen.

[0079] "Metal oxide layer containing aluminum as the main component" means that the proportion of aluminum contained in the metal oxide layer MO1 is 1% or more of the total amount of the metal oxide layer MO1. The proportion of aluminum contained in the metal oxide layer MO1 can be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the total amount of the metal oxide layer MO1. The ratio can be a mass ratio or a weight ratio.

[0080] For example, the thickness of the metal oxide layer MO1 is 1 nm or more and 10 nm or less, 1 nm or more and 4 nm or less, or 1 nm or more and 3 nm or less. In the present embodiment, aluminum oxide is used as the metal oxide layer MO1. Aluminum oxide has a high gas barrier property.

[0081] Next, an amorphous oxide semiconductor layer AOS is formed on the metal oxide layer MO1 (see step S1005 in Fig. 7 and Fig. 10).

[0082] The oxide semiconductor layer AOS is deposited by a sputtering method or an atomic layer deposition (ALD) method. For example, the thickness of the oxide semiconductor layer AOS is 5 nm or more and 50 nm or less, preferably 10 nm or more and 40 nm or less, and more preferably 10 nm or more and 30 nm or less.

[0083] A metal oxide with semiconductor properties can be used as the oxide semiconductor layer AOS. For example, an oxide semiconductor containing two or more metals, including indium (In), is used as the oxide semiconductor layer AOS. Moreover, the proportion of indium in the two or more metals is 50% or more. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), or lanthanides can be used as the oxide semiconductor layer AOS. Elements other than those described above can also be used as the oxide semiconductor layer AOS. In the present embodiment, a metal oxide containing indium (In) and gallium (Ga) is used as the oxide semiconductor layer AOS.

[0084] In the case where the oxide semiconductor layer is crystallized by an OS annealing treatment described later, the oxide semiconductor layer AOS after deposition and before the OS annealing treatment is preferably amorphous (a state in which the oxide semiconductor has few crystalline components). That is, it is preferable that the oxide semiconductor layer AOS not be crystallized as much as possible immediately after deposition in the deposition process of the oxide semiconductor layer AOS. For example, when the oxide semiconductor layer AOS is deposited by the sputtering method, the oxide semiconductor layer AOS is deposited while controlling the temperature of an object on which a film is to be formed (the substrate SUB1 and a structure formed thereon).

[0085] When deposition is performed on the object to be filmed by the sputtering method, ions generated in the plasma and atoms reflected from a sputtering target collide with the object to be filmed, so that the temperature of the object to be filmed rises during the deposition process. If the temperature of the object on which the film is to be formed rises during the deposition process, microcrystals AOS are contained in the oxide semiconductor layer immediately after deposition, and crystallization by the subsequent OS annealing treatment is prevented. To control the temperature of the object to be filmed as described above, for example, deposition can be performed while the object to be filmed is being cooled.For example, the object to be filmed may be cooled from the surface opposite to the surface to be filmed so that the temperature of the surface to be filmed of the object to be filmed (hereinafter referred to as "deposition temperature") is 100°C or less, 70°C or less, 50°C or less, or 30°C or less. As described above, depositing the oxide semiconductor layer AOS while simultaneously cooling the object to be filmed enables the formation of the oxide semiconductor layer AOS having few crystalline components immediately after deposition.

[0086] Next, a pattern of the oxide semiconductor layer AOS is formed (see step S1006 in Fig. 7). Although not shown, a resist mask is formed on the oxide semiconductor layer AOS, and the oxide semiconductor layer AOS is etched using the resist mask. Wet etching or dry etching can be used to etch the oxide semiconductor layer AOS. Etching can be performed using an acidic etchant as a wet etching. Oxalic acid or hydrofluoric acid, for example, can be used as the etchant.

[0087] The oxide semiconductor layer (AOS) is preferably patterned before OS annealing. If the oxide semiconductor layer (AOS) is crystallized by OS annealing, it tends to be difficult to etch. Even if the oxide semiconductor layer (AOS) is damaged by etching, the damage can be repaired by OS annealing, which is preferable.

[0088] After the pattern of the oxide semiconductor layer AOS is formed, the oxide semiconductor layer AOS is subjected to a heat treatment (OS annealing treatment) (see step S1007 shown in Fig. 7 and Fig. 11). In the OS annealing treatment, the oxide semiconductor layer AOS is held at a predetermined reaching temperature for a predetermined period of time. The predetermined reaching temperature is 300°C or more and 500°C or less, preferably 350°C or more and 450°C or less. Moreover, the holding time at the reaching temperature is 15 minutes or more and 120 minutes or less, preferably 30 minutes or more and 60 minutes or less. By performing the OS annealing treatment, the oxide semiconductor layer AOS is crystallized, and the oxide semiconductor layer POS having a polycrystalline structure is formed.

[0089] Next, a pattern of the metal oxide layer MO1 is formed using the oxide semiconductor layer POS as a mask (see step S1008 in Fig. 7 and see Fig. 12). The metal oxide layer MO1 is etched using the crystallized oxide semiconductor layer POS as a mask. Wet etching or dry etching can be used to etch the metal oxide layer MO1. For example, dilute hydrofluoric acid (DHF) is used as a wet etching agent. The crystallized oxide semiconductor layer POS exhibits etching resistance to dilute hydrofluoric acid compared to the amorphous oxide semiconductor layer AOS. Therefore, the metal oxide layer MO1 can be etched using the oxide semiconductor layer POS as a mask. This eliminates the need for a photolithography process.

[0090] Next, the first gate insulating layer GI1 is formed on the oxide semiconductor layer POS (see step S1009 in Fig. 7 and see Fig. 13).

[0091] The deposition method of the first gate insulating layer GI1 and the insulating material can be taken from the description of the second insulating layer IL2. For example, the thickness of the first gate insulating layer GI1 is 50 nm or more and 300 nm or less, preferably 60 nm or more and 200 nm or less, and more preferably 70 nm or more and 150 nm or less.

[0092] An oxygen-containing insulating material is preferably used as the first gate insulating layer GI1. Furthermore, an insulating layer with few defects is preferably used as the first gate insulating layer GI1. For example, when comparing the oxygen composition ratio in the second insulating layer GI1 with the oxygen composition ratio in an insulating layer (hereinafter referred to as "another insulating layer"), the oxygen composition ratio in the first gate insulating layer GI1 is closer to the stoichiometric ratio than the oxygen composition ratio in the other insulating layer.For example, when silicon oxide (SiOx) is used for the first gate insulating layer GI1 and the second gate insulating layer GI2, the oxygen composition ratio in the silicon oxide used as the first gate insulating layer GI1 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio in the silicon oxide used as the second gate insulating layer GI2. For example, a layer in which no defects are observed when analyzed by electron paramagnetic resonance (ESR) can be used as the first gate insulating layer GI1.

[0093] To form the low-defect insulating layer as the first gate insulating layer GI1, the first gate insulating layer GI1 may be deposited at a deposition temperature of 350°C or higher. Furthermore, after the formation of the first gate insulating layer GI1, an oxygen implantation process may be performed on a portion of the first gate insulating layer GI1. In the present embodiment, silicon oxide is formed at a deposition temperature of 350°C or higher to form a low-defect insulating layer as the first gate insulating layer GI1.

[0094] Next, a metal oxide layer MO2 containing aluminum as a main component is formed on the first gate insulating layer GI1 (see step S1010 in Fig. 7 and see Fig. 13).

[0095] A description of the deposition method of the metal oxide layer MO2 and the insulating material can be found in the description of the metal oxide layer MO1. By depositing the metal oxide layer MO2, oxygen is implanted into the first gate insulating layer GI1. For example, a thickness of the metal oxide layer MO2 is 5 nm or more and 100 nm or less, 5 nm or more and 50 nm or less, 5 nm or more and 30 nm or less, or 7 nm or more and 15 nm or less. In the present embodiment, alumina is used as the metal oxide layer MO2. Aluminum oxide has a high barrier property against gas. In the present embodiment, the alumina used as the metal oxide layer MO2 prevents the oxygen implanted into the first gate insulating layer GI1 from diffusing to the outside during the deposition of the metal oxide layer MO2.

[0096] For example, when the metal oxide layer MO2 is formed by the sputtering process, the process gas used during sputtering remains in the film of the first gate insulating layer GI1. For example, if Ar is used as the process gas for sputtering, Ar may remain in the film of the first gate insulating layer GI1. The remaining Ar can be detected by SIMS (secondary ion mass spectrometry) analysis on the first gate insulating layer GI1.

[0097] A heat treatment (oxidation annealing treatment) for supplying oxygen to the oxide semiconductor layer POS is performed while the first gate insulating layer GI1 is formed on the oxide semiconductor layer POS and the metal oxide layer MO2 is formed on the first gate insulating layer GI1 (see step S1011 in Fig. 7).

[0098] During the process from the deposition of the oxide semiconductor layer POS to the deposition of the first gate insulating layer GI1 on the oxide semiconductor layer POS, many oxygen deficiencies appear on the top surface and side surfaces of the oxide semiconductor layer POS. Therefore, the number of oxygen deficiencies formed near the top surface of the oxide semiconductor layer POS is greater than the number of oxygen deficiencies formed near the bottom surface of the oxide semiconductor layer POS. That is, the oxygen deficiencies in the oxide semiconductor layer POS are not uniformly present in the thickness direction of the oxide semiconductor layer POS, but are unevenly distributed in the thickness direction of the oxide semiconductor layer POS. In particular, the number of oxygen deficiencies in the oxide semiconductor layer POS is smaller on the bottom surface side of the oxide semiconductor layer POS, but larger on the top surface side of the oxide semiconductor layer POS.

[0099] In the case where an oxygen supply process is uniformly performed on the oxide semiconductor layer POS with the oxygen defect distribution as described above, oxygen is excessively supplied to the lower surface side of the oxide semiconductor layer POS when oxygen is supplied to repair the oxygen deficiencies formed on the upper surface side of the oxide semiconductor layer POS. This creates a defect level that differs from the oxygen deficiencies on the lower surface side due to the excess oxygen. As a result, phenomena such as a change in characteristics during reliability tests or a decrease in field effect mobility occur. Therefore, to suppress such a phenomenon, oxygen must be supplied to the upper surface side of the oxide semiconductor layer POS while suppressing the oxygen supply to the lower surface side of the oxide semiconductor layer POS.

[0100] The oxidation annealing is performed in a state where the metal oxide layer MO1 is disposed under the oxide semiconductor layer POS, and the oxide semiconductor layer MO2 is disposed on the oxide semiconductor layer POS. As a result, in the above-described oxidation annealing treatment, the oxygen implanted into the first gate insulating layer GI1 is blocked by the metal oxide layer MO2, so that the release of oxygen into the atmosphere is suppressed. Moreover, the oxygen released from the second insulating layer IL2 is supplied to the upper surface and side surfaces of the oxide semiconductor layer POS. Furthermore, the metal oxide layer MO1 can suppress the supply of excessive oxygen below the oxide semiconductor layer POS. This efficiently supplies oxygen to the oxide semiconductor layer POS, thereby repairing the oxygen deficiencies.

[0101] Next, after the oxidation annealing treatment, the metal oxide layer MO2 is etched (removed) (see step S1012 in Fig. 7 and see Fig. 14). Wet etching or dry etching can be used to etch the metal oxide layer MO2. For example, dilute hydrofluoric acid (DHF) is used as a wet etching method. Etching removes the metal oxide layer MO2 formed over the entire surface. In other words, the metal oxide layer MO2 is removed without using a mask. In other words, etching removes the entire metal oxide layer MO2 in a region overlapping the oxide semiconductor layer POS, which is formed in a specific pattern at least in a plan view.

[0102] Next, the gate wiring GL1 is formed on the first gate insulating layer GI1 (see step S1013 in Fig. 7 and see Fig. 15). The deposition process of the wiring GL and the conductive material can be found in the description of the light-shielding layer LS.

[0103] Next, an impurity is added to the oxide semiconductor layer POS using the gate wiring GL1 as a mask (see step S1014 in Fig. 7 and see Fig. 15). Although the present embodiment describes the case where the impurity is added by ion implantation, this can also be done by an ion doping method.

[0104] Specifically, an impurity element is added to the oxide semiconductor layer POS by ion implantation through the first gate insulating layer GI1, thereby forming the low-resistance region OS2. Furthermore, the region overlapping the gate wiring GL1 becomes the channel region OS1 in the oxide semiconductor layer POS. Argon (Ar), phosphorus (P), or boron (B), for example, can be used as the impurity element. Furthermore, when boron (B) is added by the ion implantation method, the acceleration energy can be set to 20 keV or more and 40 keV or less, and the implantation amount of boron (B) can be set to 1×10 14 cm - 2 or more and 1×10 16 cm -2 or less.

[0105] The concentration of the impurity element in the low-resistance region OS2 is preferably 1×10 18 cm -3 or more and 1×10 21 cm-3 or less, as measured by SIMS spectrometry (secondary ion mass spectrometry). In addition, in the case where the low-resistivity region OS2 is 1 ×10 18 cm -3 or more and 1×10 21 cm -3 or less, it is assumed that the impurity element was intentionally added by the ion implantation process or the doping process.

[0106] When the impurity is implanted into the oxide semiconductor layer POS by ion implantation, oxygen deficiencies form in the low-resistance region OS2, and defects also form in the metal oxide layer MO1 and the second insulating layer IL2 located beneath the low-resistance region OS2. In a subsequent process, the resistance of the low-resistance region OS2 can be further reduced by supplying hydrogen to the oxygen deficiencies. For example, using a silicon nitride layer as a passivation layer can be a method for supplying hydrogen to the oxygen deficiencies. Since the silicon nitride layer contains a large amount of hydrogen at the time of deposition, the resistance of the low-resistance region OS2 can be reduced by trapping the hydrogen contained in the silicon nitride layer into the oxygen deficiencies of the low-resistance region OS2.Furthermore, hydrogen is trapped in the defects formed by ion implantation in the metal oxide layer MO1 and the second insulating layer IL2, preventing more hydrogen from being supplied to the channel region OS1 than necessary. However, if a large amount of hydrogen diffuses during the formation of the silicon nitride layer, the oxygen deficiencies of the low-resistance region OS2 and the defects in the metal oxide layer MO1 and the second insulating layer IL2 cannot capture all of the hydrogen. If hydrogen is supplied to the oxygen deficiencies of the low-resistance region OS2, hydrogen is diverted from the low-resistance region OS2 to the channel region OS1, and the transistor becomes depleted.

[0107] Silicon oxide can be used in combination as a passivation layer to prevent excessive hydrogen from being introduced into the low-resistance region OS2. However, during the formation of the silicon oxide film, dust (particles) can be generated by reactive gas. Because the dust is difficult to remove and hinders the subsequent manufacturing process, using a thick silicon oxide layer as a passivation layer is less desirable.

[0108] Therefore, in the present embodiment, a silicon nitride layer is used as the passivation layers PAS1 to PAS3 formed on the gate wiring GL1, and the silicon nitride layer is formed at 150°C or more and 250°C or less. This prevents the diffusion of large amounts of hydrogen during the deposition of the silicon nitride layer and avoids excessive hydrogen supply to the low-resistance region OS2. This can prevent depletion of the transistor Tr1. A deposition method of the passivation layers PAS1 to PAS3 is described below.

[0109] Next, the passivation layer PAS1 is deposited on the first gate insulating layer GI1 and the gate wiring GL1 (see step S1015 in Fig. 8 and Fig. 16). The passivation layer PAS1 is deposited using a silicon nitride layer. The thickness of the passivation layer PAS1 is 200 nm or more and 600 nm or less. Furthermore, the thickness of the passivation layer PAS1 is preferably greater than the thickness of the passivation layers PAS2 and PAS3. This can reduce the parasitic capacitance generated in the wiring W3. The source gas at the time of deposition of the silicon nitride layer contains a large amount of hydrogen. Therefore, if the deposition temperature exceeds 250°C, hydrogen diffuses and penetrates the oxide semiconductor layer POS. Therefore, when the silicon nitride layer is deposited as the passivation layer PAS1, the deposition is preferably carried out at 150°C or more and 250°C or less.

[0110] Next, the opening part SCON1 is formed in the passivation layer PAS1, which reaches the low-resistance region OS2. Then, the wiring W3 is formed on the passivation layer PAS1, and the wiring W3 is connected to the low-resistance region OS2 via the opening part SCON1 (see step S1016 in Fig. 8 and see Fig. 16). Regarding the deposition method of the wiring W3 and the conductive material, reference is made to the description of the light-shielding layer LS. The deposition temperature of the wiring W3 is preferably a temperature that does not exceed the deposition temperature of the passivation layer PAS1. This is because hydrogen is released from the passivation layer PAS1 and the hydrogen diffuses into the channel region OS1 when the film is formed at a temperature significantly higher than the deposition temperature of the wiring W3. Thus, it is preferable that the deposition temperature of the passivation layer PAS1 does not exceed the deposition temperature of the wirings, electrodes, and insulating layers formed on the passivation layer PAS1.

[0111] Next, the passivation layer PAS2 is deposited on the passivation layer PAS1 and the wiring W3 (see step S1017 in Fig. 8 and Fig. 16). The passivation layer PAS2 is formed using a silicon nitride layer. The thickness of the passivation layer PAS2 is 50 nm or more and 350 nm or less. Similar to the passivation layer PAS1, the silicon nitride layer of the passivation layer PAS2 is preferably formed at 150°C or more and 250°C or less. As a result, the diffusion of hydrogen contained in the source gas can be suppressed during the formation of the passivation layer PAS2, and the diffusion of hydrogen contained in the silicon nitride layer on the passivation layer PAS1 can be suppressed.

[0112] Next, the opening part ZCON is formed in the passivation layer PAS2, which reaches the low-resistance region OS2. Then, the connection electrode ZTCO is formed on the passivation layer PAS2, and the connection electrode ZTCO is connected to the low-resistance region OS2 via the opening part ZCON (see step S1018 in Fig. 8 and see Fig. 16).

[0113] The ZTCO connecting electrode is formed by processing a translucent oxide conductive layer produced by sputtering. A transparent conductive material, such as a mixture of indium oxide and tin oxide (ITO) or a mixture of indium oxide and zinc oxide (IZO), can be used as the ZTCO connecting electrode. A transparent conductive material other than the one mentioned above can also be used as the ZTCO connecting electrode.

[0114] Next, the passivation layer PAS3 is deposited using a silicon nitride layer in contact with the terminal electrode ZTCO (see step S1019 in Fig. 8 and see Fig. 17). The passivation layer PAS3 is deposited using a silicon nitride layer. The thickness of the passivation layer PAS3 is 50 nm or more and 300 nm or less. Similar to the passivation layer PAS1, the silicon nitride layer of the passivation layer PAS3 is preferably deposited at 150°C or higher and 250°C or lower. As a result, the diffusion of hydrogen contained in the source gas can be suppressed during the deposition of the passivation layer PAS3, and the diffusion of hydrogen contained in the silicon nitride layer of the passivation layers PAS1 and PAS2 can be suppressed.

[0115] In addition, the silicon nitride layer PAS3 is deposited as a passivation layer at 150°C or more and 250°C or less, which suppresses the reduction of the ZTCO connection electrode during deposition. This makes it possible to suppress the occurrence of unevenness on the surface of the ZTCO connection electrode. Short circuits of the ZTCO connection electrode caused by unevenness on the surface of the ZTCO connection electrode and a reduction in light transmittance can be suppressed.

[0116] As described above, in the present embodiment, the silicon nitride film is used as the passivation layers PAS1 to PAS3 formed on the gate wiring GL1, and the deposition temperature of the silicon nitride film is set to 150°C or more and 250°C or less. As a result, since excessive diffusion of hydrogen can be suppressed during the deposition of the passivation layers PAS1 to PAS3, it is possible to adequately supply hydrogen to the low-resistance region OS2. In addition, since silicon oxide is not used as the passivation layers PAS1 to PAS3, the influence of dust can be reduced. Furthermore, since the passivation layers PAS1 to PAS3 are formed only of the silicon nitride film, the adhesion of the passivation layers PAS1 to PAS3 to each other can be improved.Furthermore, forming the silicon nitride layer as passivation layers PAS1 to PAS3 at 150 °C or more and 250 °C or less suppresses the generation of compressive stress in the silicon nitride layer. This makes it possible to prevent delamination of the silicon nitride layer and the terminal electrode ZTCO, as well as warpage of the substrate SUB1.

[0117] Next, the color filter CF is formed on the passivation layer PAS3 (see step S1020 in Fig. 8 and see Fig. 4). In the present embodiment, the color filter CF includes the colors red, green, and blue. The color filters CF of the respective colors are arranged along the second direction D2.

[0118] Next, the third insulating layer IL3 is formed on the color filter CF (see step S1021 in Fig. 8 and see Fig. 4). The third insulating layer IL3 is formed using an organic resin material. By forming the third insulating layer IL3 on the color filter CF, the unevenness caused by the color filter CF and the transistor Tr1 formed underneath can be reduced.

[0119] Since it is difficult to align the color filter formed on the counter substrate with the pixel circuit of the array substrate in high-resolution displays, it is preferable to place the color filter on the array substrate side. In addition, to flatten the surface where the liquid crystal is driven, a planarization film is applied to the color filter. The color filter and the planarization film are made of an organic insulating material, but the organic insulating material contains a large amount of moisture. If such a large amount of moisture penetrates the oxide semiconductor layer, the function of the transistor will be severely affected, so moisture penetration into the oxide semiconductor layer must be prevented.

[0120] In the present embodiment, a silicon nitride layer formed at 150°C or more and 250°C or less is used as the passivation layer PAS1 to PAS3. The silicon nitride layer can prevent the moisture contained in the color filter CF and the third insulating layer IL3 from penetrating into the oxide semiconductor layer POS.

[0121] Next, the opening part PCON reaching the connection electrode ZTCO is formed in the third insulating layer IL3 and the color filter CF. Then, the pixel electrode PTCO is formed on the third insulating layer IL3, and the pixel electrode PTCO is connected to the connection electrode ZTCO via the opening part PCON (see step S1022 in Fig. 8 and see Fig. 4). The pixel electrode PTCO is deposited using an inorganic insulating material and the deposition process described for the connection electrode ZTCO.

[0122] Next, the fourth insulating layer IL4 is formed on the third insulating layer IL3 and the pixel electrode PTCO (see step S1023 in Fig. 8 and see Fig. 4). The fourth insulating layer IL4 is deposited using the inorganic insulating material and the deposition method described for the first insulating layer IL1. Since the fourth insulating layer IL4 functions as a capacitance of the capacitance element 168, it is preferably formed using, for example, a silicon nitride layer.

[0123] Next, the common auxiliary electrode CMTL is formed on the fourth insulating layer IL4 (see step S1024 in Fig. 8 and see Fig. 4). For an explanation of the deposition method and conductive material of the common auxiliary electrode CMTL, refer to the description of the light-shielding layer LS. After the conductive film is formed on the fourth insulating layer IL4, the conductive film is processed to cover the gate wiring GL1 and the wiring W3, forming the common auxiliary electrode CMTL arranged in a grid pattern.

[0124] Next, the common electrode CTCO is formed on the common auxiliary electrode CMTL (see step S1025 in Fig. 8 and see Fig. 4). For an explanation of the deposition process of the common electrode CTCO and the transparent conductive material, refer to the description of the connecting electrode ZTCO. After the transparent conductive film is deposited on the fourth insulating layer IL4 and the auxiliary common electrode CMTL, the transparent conductive film is processed to overlap the auxiliary common electrode CMTL, thereby forming the common electrode CTCO arranged in a grid pattern. The common electrode CTCO and the auxiliary common electrode CMTL serve as the common circuit. Since the common electrode CTCO is made of a transparent conductive material, the resistance is higher. However, the resistance can be reduced by placing the auxiliary common electrode CMTL in contact with the common electrode CTCO. In addition, since the auxiliary common electrode CMTL has a light-shielding effect, it also functions as a black matrix.

[0125] Next, the spacer SP is formed in the opening part PCON (see step S1026 in Fig. 8 and see Fig. 4). The spacer SP is formed using an organic resin, so that the organic resin protrudes from the substrate. The spacer SP may not be formed throughout the opening portion PCON. If the spacer SP is not formed, the organic resin is embedded in the opening portion PCON, and the organic resin must not protrude from the surface.

[0126] Next, the alignment film OF1 is formed on the substrate SUB1, and the sealing member 200 is applied to surround the display area 122, and a liquid crystal is dropped thereon. The counter substrate SUB2, on which the black matrix BM or the like is formed, and the substrate SUB1 are bonded to face each other, and the sealing member 200 is cured. Through the above steps, the display device 10 can be manufactured.

[0127] In the present embodiment, a silicon nitride layer is used as the passivation layers PAS1 to PAS3 formed on the gate wiring GL1. Therefore, the passivation layer PAS2 is in contact with the passivation layer PAS1 and the passivation layer PAS3. The wiring W3 is disposed between the passivation layer PAS1 and the passivation layer PAS2, and the connection electrode ZTCO is disposed between the passivation layer PAS2 and the passivation layer PAS3. This improves the adhesion of the passivation layers PAS1 to PAS3. In addition, the passivation layers PAS1 to PAS3 are deposited at a low temperature of 150°C or more and 250°C or less. As a result, the hydrogen contained in the source gas and the hydrogen contained in the silicon nitride layer can be prevented from diffusing due to the heat applied during the deposition of the passivation layers PAS1 to PAS3.Furthermore, since no silicon oxide is used for the passivation layers PAS1 to PAS3, it is possible to suppress dust formation during deposition. [6. Crystal structure of the oxide semiconductor layer]

[0128] The oxide semiconductor layer POS described in the present embodiment contains the poly-OS. A particle diameter of a crystal grain contained in the poly-OS, observed from the upper surface of the oxide semiconductor layer POS (or the thickness direction of the oxide semiconductor layer POS), is 0.1 μm or more, preferably 0.3 μm or more, and more preferably 0.5 μm or more. For example, the particle diameter of the crystal grain can be determined using cross-sectional SEM observation, cross-sectional TEM observation, or an electron backscatter diffraction (EBSD) method.

[0129] In the poly-OS method, the multiple crystal grains can have one or more types of crystal structures. The crystal structure of the poly-OS can be identified using an electron diffraction method, an XRD method, or the like. That is, the crystal structure of the oxide semiconductor layer POS can be identified using the electron diffraction method, the XRD method, or the like.

[0130] The crystal structure of the oxide semiconductor layer POS is preferably cubic. The cubic crystal exhibits a high degree of symmetry of the crystal structure, and even if oxygen deficiency occurs in the oxide semiconductor layer POS, structural relaxation is unlikely and the crystal structure is stable. As described above, by increasing the indium content, the crystal structure of each of the plurality of crystal grains is controlled, and the oxide semiconductor layer POS with a cubic crystal structure can be formed.

[0131] In the transistor Tr1 including the oxide semiconductor layer POS formed by the above manufacturing methods, good transistor characteristics can be achieved even when the channel length L of the channel region OS1 is 0.5 µm or more and 2.0 µm or less. Since a miniaturized transistor can be formed, the pixel circuit can also be miniaturized. This makes it possible to provide the high-resolution display device 10.

[0132] In the transistor Tr containing the oxide semiconductor layer POS and manufactured by the manufacturing method described above, it is possible to obtain an electrical property with a mobility of 50 cm 2 / Vs or more, 55 cm 2 / Vs or more or 60 cm 2 / Vs or more in a region where the channel length L of the channel region OS1 is 0.5 μm or more and 2 μm or less, and the channel width of the channel region OS1 is 1 μm or more and 25 μm or less. The mobility in the present embodiment is the field effect mobility in a saturated region of the transistor, and means the largest value of the field effect mobility in a region where a potential difference (Vd) between the source electrode and the drain electrode is larger than the transistor (Vg - Vth), which is obtained by subtracting a threshold voltage (Vth) from a voltage (Vg) applied to the gate electrode. [7. First Modification]

[0133] Next, a first modification of the display device 10 will be described with reference to Fig. 18 to Fig. 21. In the present embodiment, a configuration was described in which only a silicon nitride layer is used as passivation layers PAS1 to PAS3, and no silicon oxide is used. In the present modification, a silicon oxide layer SO is formed on the passivation layer PAS1.

[0134] Fig. 18 is a cross-sectional view showing an outline of a display device 10A according to an embodiment of the present invention. Fig. The display device 10A shown in Figure 18 differs from the configuration of the Fig. 4 in that the silicon oxide layer SO is arranged between the passivation layer PAS1 and the wiring W3.

[0135] Fig. Fig. 19 is a sequence diagram illustrating a method for manufacturing the display device 10A according to an embodiment of the present invention. In the present modification, steps S1027 and S1016, which are different from the steps shown in Fig. 7 and Fig. 8 shown sequence diagrams, are described in more detail.

[0136] The silicon oxide layer SO is formed on the passivation layer PAS1 (see step S1027 in Fig. 19 and see Fig. 20). As described above, since dust is generated during the deposition of the silicon oxide film, the thickness T1 of the silicon oxide film SO is preferably smaller than the thickness of the passivation layers PAS1 to PAS3, and is preferably formed to a thickness of 10 nm to 50 nm or 10 nm to 30 nm. This can suppress dust generation during deposition. In addition, the temperature at which the silicon oxide film SO is formed is set to 150°C or more and 250°C or less, so that it is possible to suppress the diffusion of hydrogen contained in the passivation layer PAS1.

[0137] Next, the opening part SCON1 is formed in the passivation layer PAS1, which reaches the low-resistance region OS2. After that, the wiring W3 is formed on the passivation layer PAS1, and the wiring W3 is connected to the low-resistance region OS2 via the opening part SCON1 (see step S1016 in Fig. 8 and see Fig. 21). The deposition method of the wiring W3 and the conductive material can be found in the description of the light-shielding layer LS. The wiring W3 can be formed by processing the conductive film, but the passivation layer PAS1 can also be etched during the processing of the conductive film. By forming a thin silicon oxide layer SO on the passivation layer PAS1, the silicon oxide layer SO can act as an etch stopper.

[0138] In the present modification, the entire silicon oxide layer SO exposed from the wiring W3 is removed by etching. Therefore, as shown in Fig. 21, the silicon oxide layer SO is arranged between the passivation layer PAS1 and the wiring W3. Since the silicon oxide layer SO is masked by the wiring W3, it remains as thick as it was deposited. Therefore, the thickness T1 of the Fig. 21 shown silicon oxide layer SO is 10 nm or more and 50 nm or less, or 10 nm or more and 30 nm or less. Subsequently, a silicon nitride layer is deposited on the passivation layer PAS1 as a passivation layer PAS2, thereby improving the adhesion between the passivation layer PAS1 and the passivation layer PAS2. Therefore, in the present modification, one of the advantages of the manufacturing processes of Fig. 7 to Fig. The advantages described in Figure 8 are that it is possible to prevent more etching of the passivation layer PAS1 than necessary when processing the wiring W3. [8. Second Modification]

[0139] Next, the second modification of the display device 10 will be described with reference to Fig. 22 and Fig. 23. In the first modification, the case was described in which the silicon oxide layer SO is formed on the passivation layer PAS1, and the entire silicon oxide layer SO exposed from the wiring W3 is removed when the wiring W3 is formed. In the present modification, the case is described in which the wiring W3 is processed so that the silicon oxide layer SO remains. Therefore, the sequence diagram illustrating a manufacturing method for a display device 10B is substantially the same as that of Fig. 19.

[0140] Fig. 22 is a cross-sectional view showing an outline of the display device 10B according to an embodiment of the present invention. In the present modification, the silicon oxide layer SO is disposed between the passivation layer PAS1 and the passivation layer PAS2. In the silicon oxide layer SO, a thickness T1 of a first region overlapping the wiring W3 is greater than a thickness T2 of a second region not overlapping the wiring W3.

[0141] In the present modification, step S1016 differs in Fig. 19 is different from that in the first modification. Since the silicon oxide layer SO is formed to a thickness of 10 nm or more and 50 nm or less, preferably 10 nm or more and 30 nm or less, the thickness T1 is a thickness including the formed silicon oxide layer SO. On the other hand, since the area exposed from the wiring W3 is removed by etching, the thickness T2 is smaller than the thickness T1. The thickness T2 may be greater than 0 nm and smaller than 10 nm. To form the wiring W3, the conductive film is etched so that the silicon oxide layer SO remains.

[0142] A thin silicon oxide layer SO is arranged between the passivation layer PAS1 and the passivation layer PAS2, so that the diffusion of hydrogen contained in the layer above the passivation layer PAS2 can be suppressed. Furthermore, since the thickness of the silicon oxide layer SO is thinner than the thickness of the passivation layers PAS1 to PAS3, the influence of dust during deposition can also be reduced. [9. Third Modification]

[0143] Next, a third modification of the display device 10 will be described with reference to Fig. 24 and Fig. 25. In the present modification, a manufacturing method that is partially different from the manufacturing method of the display device 10 is described.

[0144] Fig. 24 is a cross-sectional view showing an outline of a display device 10C according to an embodiment of the present invention. As shown in Fig. 24, the configuration of the transistor Tr1 differs from the configuration of the transistor Tr1 shown in Fig. 4 is shown. In Fig. 24, the metal oxide layer MO1 formed under the oxide semiconductor layer POS is omitted.

[0145] Fig. 25 is a sequence diagram illustrating a method for manufacturing the display device 10C according to an embodiment of the present invention. Fig. The sequence diagram shown in Figure 25 differs partly from the one shown in Fig. 7 shown sequence diagram. As in Fig. 25, the process for forming the metal oxide layer MO1 formed on the second insulating layer IL2 (step S1004 shown in Fig. 7), and the process for structuring the metal oxide layer MO1 (step S1008, shown in Fig. 7) is omitted. In addition, since the process according to the Fig. 25 is the same as the step S1014 shown in Fig. 8, a detailed explanation will be omitted. Although the metal oxide layer MO1 is omitted in the present modification, the first gate insulating layer GI1 is covered by the metal oxide layer MO2. Since the oxygen released from the second insulating layer IL2 and the first gate insulating layer GI1 is covered by the metal oxide layer MO2 by the subsequent oxidation annealing, it is supplied to the upper surface and the lower surface of the oxide semiconductor layer POS, thereby repairing the oxygen deficiencies. Therefore, it is possible to efficiently supply oxygen to the oxygen deficiencies of the oxide semiconductor layer POS. [10. Fourth Modification]

[0146] Next, a fourth modification of the display device 10 will be described with reference to Fig. 26. In the present modification, a manufacturing method is described that is partially different from the manufacturing method of the display device 10. In addition, since a cross-sectional structure of the display device according to the present modification is the same as the cross-sectional structure of the display device 10C shown in Fig. 24, their illustration is omitted.

[0147] Fig. 26 is a diagram illustrating a method for manufacturing the display device according to an embodiment of the present invention. Fig. The sequence diagram shown in Figure 26 differs partially from the one shown in Fig. 7 shown sequence diagram. As in Fig. 26, the process for forming the metal oxide layer MO2 formed on the first gate insulating layer GI1 (step S1010 shown in Fig. 7), and the process for removing the metal oxide layer MO2 (step S1012 shown in Fig. 7) is omitted. In addition, since the process according to the Fig. 26 is the same as the step S1014 shown in Fig.8, a detailed explanation is omitted. In the present modification, the metal oxide layer MO2 is omitted, but the bottom surface of the oxide semiconductor layer POS is covered by the metal oxide layer MO1. This results in the oxygen released from the second insulating layer IL2 being supplied to the top and bottom surfaces of the oxide semiconductor layer POS by the subsequent oxidation annealing, thereby repairing the oxygen deficiencies. In addition, since the oxygen released from the second insulating layer IL2 is blocked by the metal oxide layer MO1 and prevented from reaching the bottom surface of the oxide semiconductor layer POS in large quantities, the formation of a defect layer can be suppressed. Therefore, it is possible to efficiently supply oxygen to the oxygen deficiencies of the oxide semiconductor layer POS.

[0148] As described in the third modification and the fourth modification, the annealing is performed in a state where the metal oxide layer MO1 or the metal oxide layer MO2 is formed on at least one of the lower surface and the upper surface of the oxide semiconductor layer POS, so that oxygen can be supplied to the oxygen deficiencies of the oxide semiconductor layer POS.

[0149] Furthermore, in the method for manufacturing the display device 10 according to the third modification and the fourth modification, good transistor characteristics can be achieved for the transistor Tr1 including the oxide semiconductor layer POS even when the channel length L of the channel region OS1 is 0.5 μm or more and 2 μm or less. Since a miniaturized transistor can be formed, the pixel circuit can also be miniaturized. This makes it possible to provide the display device 10 with high resolution.

[0150] In the method for manufacturing the display device 10C according to the third modification and the fourth modification, it is also possible to form the oxide semiconductor layer POS with a good polycrystalline structure. In the transistor Tr including the oxide semiconductor layer POS manufactured in the third modification and the fourth modification, it is possible to obtain an electrical property with a mobility of 30 cm 2 / Vs or more, 35 cm 2 / Vs or more or 40 cm 2 / Vs or more in a region where the channel length L of the channel region OS1 is 0.5 µm or more and 2 µm or less and the channel width of the channel region OS1 is 1 µm or more and 25 µm or less.

[0151] Each of the embodiments described above as an embodiment of the present invention can be combined and implemented accordingly, as long as no contradiction arises. Furthermore, the addition, removal, or modification of component configurations by those skilled in the art based on the semiconductor device and display device of the respective embodiments are also included within the scope of the present disclosure, as long as they conform to the gist of the present invention.

[0152] Furthermore, it is understood that even if the effect differs from that of the embodiments described above, the effect apparent from the description in the specification or easily foreseeable by those skilled in the art is obviously derived from the present invention. LIST OF REFERENCE SYMBOLS 10, 10a to 10C display device, 100 array substrate, 110 first driver circuit, 111 multiplexer circuit, 112 analog switches, 115 wiring part, 116 Data signal source line, 120 second driver circuit, 121 peripheral area, 122 display area, 124 sealing area, 126 exposed area, 129 scan signal line, 131 data signal line, 141 connecting wiring, 143 connecting section, 145 common wiring, 146 common electrode, 150 FPC connector, 160 transistors, 161 first gate electrode, 163 first source electrode, 164 first drain electrode, 168 capacity element, 170 liquid crystal element, 180 pixels, 182 pixel circuit, 190 counter substrate, 192 shielding part, 200 sealing part, 300 flexible circuit boards, 400 IC chips, AOS oxide semiconductor layer, B subpixels, BM black matrix, CF color filter, CMTL common auxiliary electrode, CON1 contact area, CTCO common electrode, G subpixels, GI1 first gate insulating layer, GI2 second gate insulating layer, GL1 Gate wiring, GL2 gate wiring, IL1 first insulation layer, IL2 second insulation layer, IL3 third insulation layer, MO1, MO2 metal oxide layer, OC coating layer, OF1, OF2 alignment film, OS1 channel range, OS2 area with low resistance, PAS1 to PAS3 passivation layer, PCON opening part, POS oxide semiconductor layer, PTCO pixel electrode, R pixels, S semiconductor layer, S1 semiconductor layer, S2 semiconductor layer, S3 semiconductor layer, SCON1 opening part, SCON2 opening part, SO silicon oxide layer, SP spacers, SUB1 substrate, SUB2 counter substrate, Tr, Tr1, Tr2, Tr2-1, Tr2-2 transistor, W wiring group, W1 to W3 wiring, WC1, WC2 Open, ZCON opening part, ZTCO connection electrode QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2014-146819

[0003] JP 2015-159315

[0003]

Claims

[1] A display device comprising: an oxide semiconductor layer having a polycrystalline structure; a gate insulating layer provided on the oxide semiconductor layer; a gate electrode opposite the oxide semiconductor layer on the gate insulating layer; a first silicon nitride layer provided in contact with the gate electrode; a source wiring provided in contact with the first silicon nitride layer and electrically connected to the oxide semiconductor layer; a second silicon nitride layer provided in contact with the source wiring and the first silicon nitride layer; a first transparent conductive layer provided in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer; and a third silicon nitride layer provided in contact with the first transparent conductive layer and the second silicon nitride layer, wherein a channel length of the gate electrode is 2.0 µm or less. [2] The display device according to claim 1, further comprising: a silicon oxide layer between the source wiring and the first silicon nitride layer. [3] The display device according to claim 2, wherein the thickness of the silicon oxide layer is 10 nm or more and 50 nm or less. [4] The display device according to claim 1, further comprising: an aluminum oxide layer between the gate insulating layer and the oxide semiconductor layer. [5] The display device according to claim 1, wherein the oxide semiconductor layer contains two or more metal elements including indium, and the proportion of indium in the two or more metal elements is 50% or more. [6] A display device comprising: an oxide semiconductor layer having a polycrystalline structure; a gate insulating layer provided on the oxide semiconductor layer; a gate electrode opposite the oxide semiconductor layer on the gate insulating layer; a first silicon nitride layer provided in contact with the gate electrode; a silicon oxide layer provided in contact with the first silicon nitride layer; a source wiring provided in contact with the silicon oxide layer and electrically connected to the oxide semiconductor layer; and a second silicon nitride layer provided in contact with the source wiring and the first silicon nitride layer; a first transparent conductive layer provided in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer; and a third silicon nitride layer provided in contact with the first transparent conductive layer and the second silicon nitride layer, where a channel length of the gate electrode is less than 2.0 µm and a thickness of the silicon oxide layer is smaller than a thickness of the first silicon nitride layer, a thickness of the second silicon nitride layer and a thickness of the third silicon nitride layer. [7] The display device according to claim 6, wherein a thickness of the first region overlapping the source wiring is greater than a thickness of the second region in the silicon oxide layer not overlapping the source wiring. [8] The display device according to claim 7, wherein a thickness of the first region of the silicon oxide layer is 10 nm or more and 50 nm or less. [9] The display device according to claim 7, wherein a thickness of the second region of the silicon oxide layer is greater than 0 nm and less than 10 nm. [10] The display device according to claim 6, further comprising: an aluminum oxide layer between the gate insulating layer and the oxide semiconductor layer. [11] The display device according to claim 6, wherein the oxide semiconductor layer contains two or more metal elements including indium, and a ratio of indium to the two or more metal elements is 50% or more. [12] A method of manufacturing a display device, the method comprising the steps of: Forming an oxide semiconductor layer having a polycrystalline structure; Depositing a gate insulating layer on the oxide semiconductor layer; Forming a gate electrode opposite the oxide semiconductor layer on the gate insulating layer; depositing a first silicon nitride layer in contact with the gate electrode; Forming a source wiring in contact with the first silicon nitride layer and electrically connected to the oxide semiconductor layer; Forming a second silicon nitride layer in contact with the source wiring and the first silicon nitride layer; Forming a first transparent conductive layer in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer; and Depositing a third silicon nitride layer in contact with the first transparent conductive layer and the second silicon nitride layer, where a channel length of a channel region in the oxide semiconductor layer overlapping the gate electrode is 2.0 µm or less, and a deposition temperature of the first silicon nitride layer, the second silicon nitride layer and the third silicon nitride layer is 150 °C or more and 250 °C or less, respectively.

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