DEVICE FOR PROTECTION AGAINST ELECTROSTATIC DISCHARGE

Abstract

An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes an n-type trough layer with a first positive n-type diffusion region coupled to an anode terminal; a p-type trough layer with a second positive n-type diffusion region coupled to a cathode terminal; a substrate layer; a buried n-type layer provided between the p-type trough layer and the substrate layer; and a dielectric layer coupled to a gate terminal. The buried n-type layer has a third n+ diffusion region coupled to a buried layer terminal. The n-type trough layer is provided above the p-type trough layer. A parasitic circuit is activated within the n-type trough layer and the p-type trough layer when the anode terminal receives a voltage equal to or greater than a first threshold value.

Description

TECHNICAL AREA

[0001] The present disclosure relates to a device for protection against electrostatic discharge (ESD) and in particular to a controlled rectifier with low leakage current, such as a semiconductor-controlled rectifier or a silicon-controlled rectifier (SCR). BACKGROUND

[0002] Solid-state current control devices can be used to deal with electrostatic discharge (ESD) problems.

[0003] Several ESD protection devices have been reported. US2016099241 describes an n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge. Another structure is presented in P. Mahajan, S. Suresh, XME Low, KJ Hwang, and R. Gauthier, “A Robust Scalable ESD Protection Device integrating Drain-side Floating P+ Diffusion with tunable ESD Design Window and effective Latch-up immunity for High-Voltage Power Clamp applications,” 2022 44th Annual EOS / ESD Symposium (EOS / ESD), Reno, NV, USA, 2022, pp. 1–8, doi: 10.23919 / EOS / ESD54763.2022.9928482.

[0004] These devices are limited by a significant leakage current, especially when the temperature rises above a certain level.

[0005] It is a task of revelation to address one or more of the above-mentioned limitations. SUMMARY

[0006] According to one aspect of the disclosure, a device for protection against electrostatic discharge is provided, comprising: an n-type trough layer (110) with a first positive n-type diffusion region (115) coupled to an anode terminal; a p-type trough layer (120) with a second positive n-type diffusion region (125) coupled to a cathode terminal; a substrate layer (140); a buried n-type layer (130) provided between the p-type trough layer (120) and the substrate layer (140), the buried n-type layer (130) having a third n+ diffusion region (135) coupled to a buried layer terminal; and a dielectric layer (150) coupled to a gate terminal. wherein the n-type trough layer (110) is provided above the p-type trough layer (120);and wherein a parasitic circuit within the n-type trough layer (110) and the p-type trough layer (120) is activated when the anode terminal receives a voltage equal to or greater than a first threshold value (Vt1).

[0007] For example, the substrate layer can be a p-type substrate layer or an insulator layer.

[0008] For example, the first threshold can be called the trigger voltage.

[0009] Optionally, the first threshold can be adjusted by applying a prestress to the buried layer connection. For example, the first threshold increases if the prestress increases.

[0010] Optionally, the n-type trough layer (110) has a first positive p-type diffusion area (116) coupled to a potential-free terminal; and the p-type trough layer (120) has a second positive p-type diffusion area (126) coupled to a bulk terminal.

[0011] Optionally, the device also includes a bias resistor (Rnbl) that couples the buried layer connection to the bulk connection.

[0012] Optionally, the dielectric layer is a gate oxide layer (GOX) or a high-k metal gate (HKMG) layer coupled to the gate terminal.

[0013] Optionally, if a positive voltage above the first threshold is applied to the anode terminal, a current flows from the first positive n-type diffusion region (115) to the second positive n-type diffusion region (125) via the parasitic circuit.

[0014] Optionally, the parasitic circuit includes a first parasitic transistor (111) coupled to a second parasitic transistor (112).

[0015] Optionally, the first parasitic transistor (111) is coupled to the bulk terminal via a first parasitic resistor (Rp), and the second parasitic transistor (112) is coupled to the anode terminal via a second parasitic resistor (Rn).

[0016] Optionally, the first parasitic transistor (111) has an emitter coupled to the second positive n-type diffusion region (125) and a base coupled to the second positive p-type diffusion region (126) via the first parasitic resistor (Rp).

[0017] Optionally, the second parasitic transistor (112) has an emitter coupled to the first positive p-type diffusion region (116) and a base coupled to the first positive n-type diffusion region (115) via the second parasitic resistor (Rn).

[0018] Optionally, the n-type trough layer (110) extends between a first end provided at an edge of the device and a second end located below the first positive p-type diffusion region (116).

[0019] Optionally, the first positive p-type diffusion region (116) extends along a depth axis (z) and wherein the first positive p-type diffusion region (116) is segmented along the depth axis to form a segmented region that has a variety of diffusion regions alternating between positive p-type and positive n-type.

[0020] Optionally, the n-type trough layer (110) extends between a first end provided at an edge of the device and a second end located below the gate layer (150).

[0021] Optionally, the first positive p-type diffusion region (116) extends along a depth axis (z) and wherein the first positive p-type diffusion region (116) is segmented along the depth axis to form a segmented region having a plurality of diffusion regions alternating between positive p-type and positive n-type, and wherein the segmented region is placed adjacent to a non-segmented positive p-type region.

[0022] Optionally, the device further comprises at least one gate resistor (Rg) that couples the gate terminal to the cathode terminal and a gate capacitor (Cg) that couples the gate terminal to the anode terminal.

[0023] For example, the gate resistor Rg and the gate capacitor can form an RC trigger circuit.

[0024] Optionally, the device further comprises a barrier layer (160) that at least partially covers an upper surface of the n-type trough layer (110).

[0025] Optionally, the barrier layer (160) is a silicide blocking layer (SBLK) or a resist protective oxide (RPO).

[0026] Optionally, the first threshold is a function of the overlap (Lov) between the n-type layer (110) and the gate layer (150). For example, the first voltage decreases as the overlap increases.

[0027] Optionally, the device has a holding voltage (Vh), and the holding voltage is a function of a diffusion length (Lfp) of the first positive p-type diffusion region (116). For example, the holding voltage increases as the diffusion length (Lfp) increases. DESCRIPTION OF THE DRAWINGS

[0028] The revelation is described in more detail below with reference to examples and the accompanying drawings, whereby: Fig. 1A is a cross-sectional view of a device for protection against electrostatic discharge (ESD) according to the disclosure; Fig. 1B a close-up view of the device of Fig. Figure 1 shows the parasitic circuit; Fig. 2A is a perspective three-dimensional view of the P+ diffusion area in the NW layer when the NW layer extends to a region below the GOX layer; and Fig. 2B is a perspective three-dimensional view of the P+ diffusion region in the NW layer when the NW layer extends to a region below the P+ diffusion region. DESCRIPTION

[0029] Fig. Figure 1A is a cross-sectional view of a device for protection against electrostatic discharge (ESD) according to the disclosure. Circuit 100 includes an embedded parasitic circuit, shown in bold lines. Fig. 1B is a close-up view of the device of Fig. Figure 1, which shows the parasitic circuit in more detail.

[0030] The circuit 100 can be used as a device for protection against electrostatic discharge (ESD) and can also be referred to as a semiconductor-controlled rectifier (SCR) or, in particular, as a silicon-controlled low trigger voltage / high holding voltage rectifier (LVT / HHVSCR).

[0031] The device 100 comprises an n-trough layer (NW) 110, a p-trough layer (p-BODY) 120, an n-buried layer (NBL) 130, and a p-substrate layer (p-SUB) 140. Layers 120, 130, and 140 have a horizontal and a vertical section forming an L-shaped cross-section. The NBL layer 130 is positioned between the p-SUB layer 140 and the p-BODY layer 120 to provide vertical isolation between these layers. In particular, it isolates the SCR circuitry from the substrate (p-SUB), thereby reducing the possibility of substrate noise coupling and leakage current. The NBL layer can be implemented as a deep n-type trough implant. The n-trough layer 110 has a rectangular cross-section and is located on top of the p-BODY layer 120. Layers 110 to 140 are nested to form an upper surface 101.

[0032] The upper section of the vertical area of ​​layer 140 has a p+ diffusion area 146 connected to a substrate terminal. The upper section of the vertical area of ​​layer 130 has an n+ diffusion area 135 connected to an NBL terminal. The upper section of the vertical area of ​​layer 120 has an n+ diffusion area 125 connected to a cathode or source terminal and a p+ diffusion area 126 connected to a bulk terminal. The cathode is coupled to ground. The upper section of layer 110 has an n+ diffusion area 115 connected to a drain or anode terminal and a p+ diffusion area 116 connected to a floating terminal. For ESD-SCR operation, the floating terminal should be connected to the drain terminal.For example, the potential-free connection and the drain connection can be shortened by backend-of-the-line BEOL wiring.

[0033] The n+ and p+ diffusion zones 125 and 126 are separated by a lateral isolation zone 127, also known as STI (Shallow Trench Isolation). The n+ and p+ diffusion zones 135 and 126 are separated by a lateral isolation zone 137. The n+ and p+ diffusion zones 135 and 146 are separated by a lateral isolation zone 147.

[0034] A dielectric layer 150, such as a gate oxide layer GOX or a high-k metal gate layer HKMG, is provided on a region of the upper surface 101 between the n+ region 125 and the p+ region 116. The dielectric layer 150 can be coated with a polysilicon layer or with a metal layer.

[0035] The dielectric layer 150 is connected to a gate terminal.

[0036] A barrier layer (160), also referred to as a dummy gate, may be provided on the top surface of the NW layer 110 to reduce leakage current due to surface conditions / drops. The layer 160 covers at least part of the top surface of the n-type trough layer (110). In this example, the barrier layer 160 also covers part of the gate layer 150. The barrier layer may be a silicide block layer (SBLK) or a resist protective oxide (RPO).

[0037] The length of the n-type layer 110 can vary. In a first example, the n-type layer 110 extends between a first end at an edge of the device and a second end (NWB') located below the positive p-type diffusion region 116.

[0038] In a second example, the NW layer 110 extends between a first end at an edge of the device and a second end (NWB) that is located below the GOX layer 150.

[0039] The overlap between the n-type layer 110 and the GOX layer 150 is shown by the NW-GOX length overlap (Lov). If the NW layer 110 extends to the boundary NWB, the gate length (Lg) extends between the n+ diffusion region 125 and the boundary NWB. If the NW layer extends to the boundary NWB', the gate length Lg is the length of the dielectric layer 150.

[0040] The p+ region 116 has a pseudo-floating p+ diffusion length (Lfp). The distance between the n+ region 115 and the p+ region 116 defines the pseudo-floating p+ diffusion-to-drain n+ diffusion distance (Lpn). The distance between the p+ region 116 and the GOX layer 150 defines the gate-to-pseudo-floating p+ diffusion distance (Lpg).

[0041] The bulk terminal and the source terminal can be connected to form a bulk / source terminal. The bulk / source terminal and the p-SUB terminal can be connected to ground.

[0042] Optionally, a resistor Rnbl can be provided between the NBL terminal and the bulk / source terminal. The resistor Rnbl can be tuned to bias the NBL layer 130 to a positive potential (above GND). This NBL bias can be used to regulate the potential of the p-BODY layer 120, thereby modulating the NPN base current ib1 and thus the parasitic NPN(& SCR) turn-on process.

[0043] A gate-to-source resistor (Rg) can also be provided between the source and gate terminals. A gate-to-drain capacitor (Cg) can be provided between the gate and drain terminals. When both Rg and Cg are provided, they form an RC trigger circuit that supplies a gate voltage (Vg) at the gate terminal. Alternatively, the gate voltage (Vg) can be provided using either Rg alone or Cg alone. If only Rg is provided, there is no connection (short circuit) between the gate and drain terminals. If only Cg is provided, the gate terminal is connected to the cathode terminal, for example, by backend-of-the-line (BEOL) wiring.

[0044] The parasitic circuit, also known as a parasitic SCR circuit, is shown in bold lines in the Fig. 1A and Fig. 1B shown. It includes a horizontal parasitic NPN structure (parasitic transistor 111) coupled to a vertical parasitic PNP structure (parasitic transistor 112), and two parasitic resistors R. P and R N .

[0045] The emitter of transistor 111 is connected to the n+ area 125, while the emitter of transistor 112 is connected to the p+ area 116. The collector of transistor 111 is connected to the base of transistor 112, and the collector of transistor 112 is connected to the base of transistor 111. The first parasitic resistance R P connects the base of 111 with the p+ area 126. The second parasitic resistance R N connects the base of 112 with the n+ range 115.

[0046] The parasitic circuit is activated when an ESD pulse voltage applied to the anode / drain terminal reaches a threshold value known as the trigger voltage (Vt1). This can occur during an ESD event that applies a voltage load pulse to the anode / drain terminal.

[0047] The device 100 can be tested using a transmission line pulse (TLP) which has voltage pulses with increasing amplitudes.

[0048] When a positive voltage pulse is applied to the anode terminal connected to the n+ diffusion area 115, the junction at the NW-bound NWB breaks down. If the voltage pulse is relatively low (low load pulse voltage), the ESD device does not activate, and a leakage current can flow directly between the n+ area 115 at the anode and the n+ area 125 at the cathode at a shallow depth within layers 110 and 120. As the amplitude of the voltage pulse increases, the ESD device activates, and an ESD current flows from the anode to the cathode via the parasitic SCR circuit. The amplitude of the voltage pulse can be gradually increased until the SCR circuits activate.

[0049] When the junction at the NWB breaks down, a collector current is supplied to the collector of the NPN transistor 111, which then turns on. A base current ib2 flows to the second transistor 112, which also turns on. When both parasitic transistors are turned on, a current path is created between the anode and cathode terminals via a deeper trajectory within the p-body layer 120. This allows more ESD current to flow through the device 100 without significant leakage current. The preferred ESD current path is through the parasitic horizontal NPN and vertical PNP transistors 111 and 112. Thus, the device 100 can be described as a self-starting device or a self-starting SCR device.

[0050] The current-voltage characteristics of ESD devices can be described using various key parameters, including the clamping voltage Vcl, the holding voltage Vh, and the trigger voltage Vt1. These parameters have been described in various publications; see, for example, Fig. 1 (showing the transmission line pulse (TLP) current versus the TLP voltage) of the publication by P. Mahajan, R. Kumar, R. Gauthier and KJ Hwang, “Optimization of GGNMOS Devices for High-Voltage ESD Protection in BCDLite Technology”, 2020 International EOS / ESD Symposium on Design and System (IEDS), CHENGDU, China, 2021, pp. 1-6, doi: 10.23919 / IEDS48938.2021.9468827.

[0051] Circuit 100 can operate to provide a so-called snapback protection. The snapback effect reduces the clamping voltage Vcl after the protection has been triggered. The trigger voltage Vt1 is the maximum voltage before the device switches on and snaps back to the holding voltage Vh. The holding voltage is the lowest voltage when the snapback protection has been activated. The lower the holding voltage, the better the clamping voltage Vcl. However, if the holding voltage is too low, this can lead to a potential latch-up problem. For this reason, the holding voltage Vh must always be a certain margin (e.g., 10%) above the supply voltage (Vdd).

[0052] The N-buried layer (NBL) 130 can be prestressed by applying a bias voltage Vbias to the NBL terminal. Alternatively, no bias voltage can be applied.

[0053] When a bias voltage Vbias is applied, the NBL terminal and the bulk terminal should be connected together. For example, the NBL terminal and the bulk terminal can be shortened by backend-of-the-line (BEOL) wiring. This can be used to tune the trigger voltage Vt1. Applying a positive bias voltage to the NBL terminal increases the trigger voltage Vt1. More generally, the trigger voltage Vt1 increases as the bias voltage increases. The resistor R NBL It can also be used to regulate the bias voltage applied to the NBL terminal. Alternatively, the resistor R can be used. NBL can be used without applying an additional bias voltage Vbias to the NBL connector.

[0054] The trigger voltage Vt1 can also be changed via Rg and / or Cg. When Rg increases, the base current ib1 of the NPN transistor 111 increases, and Vt1 decreases. Increasing the base current ib1 also makes it easier to turn on transistor 111. Similarly, Vt1 also decreases when Cg increases.

[0055] Additionally, the trigger voltage Vt1 could be modulated by varying the Lov parameter (overlap of the n-type layer 110 with the gate layer 150). The Lov parameter can also be tuned to regulate the turn-on of the parasitic transistor (NPN) 111. As the Lov parameter increases, the effective base width of the parasitic transistor (NPN) 111 decreases. Thus, Vt1 and Vh are expected to decrease because the parasitic bipolar current gain (β) is high. The effective Lg would also decrease as Lov increases. This could lead to channel leakage. Therefore, a balance should be struck. For example, Lov can be designed to vary between 0.33x and 0.5x of Lg.

[0056] As mentioned above, the length of the n-type layer 110 can vary along the x-axis. In one example, the n-type layer extends to a region below the p+ diffusion region 116 (n-type boundary NWB'). In a second example, the n-type layer extends to a region below the GOX layer 150 (NW boundary NWB).

[0057] Fig. Figure 2A is a perspective three-dimensional view of the p+ diffusion region 116 of the NW layer 110, where the NW layer extends to a region below the GOX layer 150. Thus, in this example, the n-trough boundary NWB is located below the gate. This implementation allows for a better formation of a parasitic SCR circuit.

[0058] The p+ diffusion region 116 extends along a depth axis (z). Region 116 is segmented along the depth axis (z) to form a segmented region exhibiting a multitude of diffusion regions alternating between positive p-type and positive n-type: P+ / N+ / P+ / N+, etc. In this example, region 116 is described as fully segmented and has N segments. The segments are separated by a barrier layer, such as SBLK or RPO. Such segmentation allows the holding voltage Vh to be designed to a desired value. Alternatively, the diffusion region 116 could be... Fig. 2A must be continuous and consist of a single p+ region.

[0059] Fig. Figure 2B is a perspective three-dimensional view of the p+ diffusion region 116 of the NW layer 110, as the NW layer extends to a region below the p+ diffusion region (NWB'). Thus, in this example, the n-trough boundary NWB' is located below the pseudo-floating p+ diffusion. Region 116 is only partially segmented due to the presence of the floating p+ region alongside the segmented region of N segments alternating P+ / N+ / P+ / N+, etc.

[0060] The p+ diffusion region (116) extends along the longitudinal axis (x) and has a length Lfp. Compared to Fig. In 2A, the length Lfp has now increased by the length D. As Lfp increases, the holding voltage Vh also increases, thus providing better latch-up immunity. However, this also increases the footprint of the device.

[0061] The holding voltage Vh can be adjusted by varying the Lfp parameter (anode / drain-side pseudo-floating p+ diffusion length) or by varying the ratio of p+ diffusion contacts to adjacent n+ diffusion contacts (along the z-direction) or by varying the Lpg parameter (gate edge to anode / drain-side pseudo-floating p+ diffusion distance) in the case of a non-self-aligned structure (when Lpg is zero, the gate layer 150 and the p+ area 116 are self-aligned).

[0062] The trigger voltage Vt1 and the holding voltage Vh can be adjusted simultaneously by varying the Lpn parameter (anode / drain-side pseudo-floating p+ diffusion to drain-side n+ diffusion distance).

[0063] Therefore, there is a trade-off between size and holding voltage value. Depending on the application, an implementation according to Fig. 2A or Fig. 3B is preferred.

[0064] Circuit 100 of the disclosure provides an efficient ESD clamp with a reduced footprint and low standby leakage current. Additionally, the trigger voltage Vt1 is relatively low and tunable. The trigger voltage can be adjusted by design as described above or by applying a bias voltage to the NBL terminal.

[0065] The holding voltage Vh is high and can be adjusted through design.

[0066] For example, the circuit of Fig. 1. It should be designed to achieve the following structures: (i) LVTSCR-based low-leakage ESD structures for 1.1 V I / O and supply pins (ii) LVTSCR-based low-leakage ESD structures for 1.8 V to 3.3 V IO pins (iii) Low-leakage HHVSCR-based ESD structures for 5 V + IO and supply pins

[0067] The ESD protection device described in the disclosure can be implemented using bulk technology or SOI technology. For SOI technology, the substrate can change from bulk (p-SUB) to SOI (insulator).

[0068] A person skilled in the art will recognize that variations of the disclosed arrangements are possible without deviating from the disclosure. Accordingly, the above description of the specific embodiments is given only as an example and not for the purpose of limitation. It will be clear to the person skilled in the art that minor modifications can be made without significant changes to the described operation. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 2016099241

[0003] Cited non-patent literature

[0000] P. Mahajan, S. Suresh, doi: 10.23919 / EOS / ESD54763.2022.9928482

[0003] P. Mahajan, R. Kumar, R. Gauthier und K. J. Hwang, „Optimization of GGNMOS Devices for High-Voltage ESD Protection in BCDLite Technology“, 2020 International EOS / ESD Symposium on Design and System (IEDS), CHENGDU, China, 2021, S. 1-6, doi: 10.23919 / IEDS48938.2021.9468827

[0050]

Claims

[1] Device for protection against electrostatic discharge, comprising: an n-type trough layer (110) with a first positive n-type diffusion region (115) coupled to an anode terminal, a p-type trough layer (120) with a second positive n-type diffusion region (125) coupled to a cathode terminal, a substrate layer (140); a buried n-type layer (130) provided between the p-type trough layer (120) and the substrate layer (140), wherein the buried n-type layer (130) has a third n+ diffusion area (135) coupled to a buried layer connection; and a dielectric layer (150) coupled to a gate terminal; wherein the n-type trough layer (110) is provided above the p-type trough layer (120); and wherein a parasitic circuit within the n-type trough layer (110) and the p-type trough layer (120) is activated when the anode terminal receives a voltage equal to or greater than a first threshold value. [2] Device according to claim 1, wherein the first threshold value is adjustable by applying a preload to the buried layer connection. [3] Device according to claim 1 or 2, wherein the n-type trough layer (110) has a first positive p-type diffusion area (116) coupled to a potential-free terminal; and wherein the p-type trough layer (120) has a second positive p-type diffusion area (126) coupled to a bulk terminal. [4] Device according to claim 3, further comprising a bias resistor coupling the buried layer connection to the bulk connection. [5] Device according to any of the preceding claims, wherein the dielectric layer (150) is a gate oxide layer or a high-k metal gate layer coupled to the gate terminal. [6] Device according to one of the preceding claims, wherein when a positive voltage is applied to the anode terminal above the first threshold value, a current flows from the first positive n-type diffusion region (115) to the second positive n-type diffusion region (125) via the parasitic circuit. [7] Device according to any one of claims 3 to 6, wherein the parasitic circuit comprises a first parasitic transistor (111) coupled to a second parasitic transistor (112). [8] Device according to claim 7, wherein the first parasitic transistor (111) is coupled to the bulk terminal via a first parasitic resistor and wherein the second parasitic transistor (112) is coupled to the anode terminal via a second parasitic resistor. [9] Device according to claim 8, wherein the first parasitic transistor (111) has an emitter coupled to the second positive n-type diffusion region (125) and a base coupled to the second positive p-type diffusion region (126) via the first parasitic resistor. [10] Device according to claim 9, wherein the second parasitic transistor (112) has an emitter coupled to the first positive p-type diffusion region (116) and a base coupled to the first positive n-type diffusion region (115) via the second parasitic resistor. [11] Device according to one of the preceding claims, wherein the n-type trough layer (110) extends between a first end provided at an edge of the device and a second end extending below the first positive p-type diffusion area (116). [12] Device according to claim 11, wherein the first positive p-type diffusion region (116) extends along a depth axis and wherein the first positive p-type diffusion region (116) is segmented along the depth axis to form a segmented region having a plurality of diffusion regions alternating between positive p-type and positive n-type. [13] Device according to one of the preceding claims, wherein the n-type trough layer (110) extends between a first end provided at an edge of the device and a second end located below the gate layer (150). [14] Device according to claim 13, wherein the first positive p-type diffusion region (116) extends along a depth axis and wherein the first positive p-type diffusion region (116) is segmented along the depth axis to form a segmented region having a plurality of diffusion regions alternating between positive p-type and positive n-type, and wherein the segmented region is placed adjacent to a non-segmented positive p-type region. [15] Device according to one of the preceding claims, further comprising at least one of a gate resistor coupling the gate terminal to the cathode terminal and a gate capacitor coupling the gate terminal to the anode terminal. [16] Device according to one of the preceding claims, further comprising a barrier layer (160) which at least partially covers an upper surface of the n-type trough layer (110). [17] Device according to claim 16, wherein the barrier layer (160) is a silicide block layer or a resist protective oxide. [18] Device according to one of the preceding claims, wherein the first threshold is a function of an overlap between the n-type trough layer (110) and the gate layer (150). [19] Device according to one of the preceding claims, wherein the device has a holding voltage and wherein the holding voltage is a function of a diffusion length of the first positive p-type diffusion region (116).

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