Circuit layout and microcontroller

Abstract

Circuit arrangement in combination with a microcontroller, wherein the circuit arrangement comprises a first transistor and a second transistor, both arranged in series and having a signal I / O between them; wherein the first transistor is configured to output a first state to the signal I / O depending on a first (sensor) signal; wherein the second transistor is configured to output a second state to the signal I / O depending on a second signal; wherein the signal I / O is configured to provide a third state when the first and second transistors are disabled.

Description

[0001] Exemplary embodiments of the present invention relate to a circuit arrangement, and in particular a sensor circuit arrangement, in combination with a microcontroller. Further exemplary embodiments relate to a method for operating a circuit arrangement, a method for operating a microcontroller, and a corresponding computer program. Some sensors, such as magnetic switches, are frequently used in combination with or integrated into sensor circuit arrangements.

[0002] These sensor circuit arrangements enable chip-to-chip communication. One example is a magnetic switch used in a three-pin assembly. This three-pin assembly performs chip-to-chip communication with a microcontroller, which, for example, collects the sensor signals and determines or monitors a failure status. This can be achieved by using an additional pin, but this incurs additional costs. Other examples use so-called live ticks. These operate with a timing scheme, which requires significant effort on the microcontroller side to continuously measure time. EP 2 546 984 A1 discloses a sensor with simultaneous automatic detection of the output mode and manual selection. EP 3 451 537 A1 describes a high-voltage output driver for a sensor device with reverse current blocking.Therefore, there is a need for an improved approach.

[0003] Exemplary embodiments of the present invention provide a (sensor) circuit arrangement in combination with a microcontroller. The circuit arrangement comprises a first transistor and a second transistor, both arranged in series, with a signal I / O of the circuit arrangement between them; the first transistor is configured to output a first state to the signal I / O of the circuit arrangement depending on a first signal, the second transistor is configured to output a second state to the signal I / O of the circuit arrangement depending on a second signal; the signal I / O of the circuit arrangement is configured to provide a third state when the first and second transistors are deactivated.The microcontroller has a signal I / O and a third transistor; the signal I / O has an input configured to distinguish between the first state and the second or third state provided by the circuit arrangement via a signal line; here, the third transistor is coupled to the signal line via the signal I / O of the microcontroller, with the signal I / O of the microcontroller being configured to distinguish between the second state and the third state by using the third transistor.

[0004] Another embodiment provides a method for operating a circuit arrangement in combination with a microcontroller. The circuit arrangement comprises a first transistor and a second transistor, both arranged in series and having a signal I / O of the circuit arrangement between them; the microcontroller has a signal I / O of the microcontroller and a third transistor, the signal I / O of the microcontroller having an input, the third transistor being coupled to the signal line via the signal I / O of the microcontroller, wherein the circuit arrangement comprises the following steps: - Outputting a first state to the signal I / O of the circuit arrangement depending on a first signal by using the first transistor; - Outputting a second state to the signal I / O of the circuit arrangement depending on a second signal by using the second transistor; - Providing a third state when the first and second transistors are deactivated; AND - Distinguishing between the first state and the second state or the third state, which is provided by the circuit arrangement via a signal line; - Differentiating between the second state and the third state by using the third transistor.

[0005] Another embodiment provides a computer program for carrying out the procedure defined above when a computer is running.

[0006] Further training is defined by the subject matter of the dependent claims.

[0007] Exemplary embodiments of the present invention are explained below with reference to the accompanying figures, wherein: Fig. Figure 1 shows an example of a conventional combination of a sensor circuit arrangement and a microcontroller to illustrate the basic principle; Fig. 2 shows a schematic block diagram of a basic implementation of a sensor circuit arrangement in combination with a microcontroller according to exemplary embodiments; Fig. 3a shows a schematic block diagram of an improved sensor circuit arrangement according to exemplary embodiments; Fig. 3b shows a schematic block diagram of a microcontroller according to exemplary embodiments; Fig. 4 the combination of the sensor circuit arrangement and the microcontroller according to Fig. 3a and Fig. 3b shows; Fig. 5a shows a schematic block diagram of the combination of a sensor circuit arrangement and a microcontroller, illustrating exemplary failures to explain embodiments; and Fig. 5b shows a schematic matrix illustrating how the failures that occur in Fig. 5a illustrates how they can be captured, according to the examples of implementation.

[0008] Exemplary embodiments of the present invention are explained below with reference to the accompanying figures, whereby identical reference numerals are provided for objects with identical or similar functions, so that their descriptions are mutually applicable and interchangeable.

[0009] Fig. Figure 1 shows the combination of a sensor circuit arrangement 10 with a microcontroller 20. The sensor circuit arrangement is a so-called three-pin circuit arrangement 10, which may include an integrated sensor 5, such as a magnetic switch. Here, it is assumed that the sensor 5 is integrated into the sensor circuit arrangement 10. A sensor circuit arrangement is coupled to GND via a first contact pin 17 and to VDD via a second contact pin 18, and has a third contact pin 19, which forms the signal I / O (signal input / output) 16.

[0010] The microcontroller 20 is also supplied with power from GND (see pin 28) and VDD (see pin 27), and via a third pin 29 connected to pin 19 (see signal line 9). The microcontroller has a universal input / output 22. This can, for example, include a comparator to distinguish between GND (low) and VDD (high).

[0011] The signal line 9 is connected via a so-called pull-up resistor 7 (R pu ) coupled with VDD.

[0012] Regarding sensor circuit 10, it should be noted that it includes a transistor 12, e.g., an open-drain transistor (S1). For example, the emitter or drain is coupled to 17, with the collector being coupled to 19 or the signal input / output. The control contact, such as the base or gate, is coupled to sensor 5.

[0013] After the structure of the sensor circuit 10 and the microcontroller 12 has been explained, the functionality will now be explained.

[0014] For example, if sensor 5, such as the magnetic switch, is closed and / or conducting, transistor 12 can be closed, with signal input / output 16 configured to send sensor data from sensor 5. In this example, sensor 5 provides microcontroller 20 with data about the open-drain (S1) state of transistor 12 and the external pull-up resistor 7. The signal or state applied to contact pin 19 is also referred to as the first state, indicating a closed transistor 12. Of course, transistor 12 can be closed due to the presence of a signal, i.e., when sensor 5 / the magnetic switch is activated. According to other implementations, this can be reversed, so that transistor 12 is closed when sensor 5 is deactivated. This depends on the specific implementation of sensor 5 and transistor 12, e.g., here as an open-drain transistor.

[0015] The microcontroller 20 has GPIO 22, which is configured as an input. It determines the initial state, e.g., through a low signal (lower than a threshold), current flow, or a short circuit.

[0016] As stated above, the first state at pin 19 can be, for example, a ground signal applied to pin 19, while another signal, also referred to as the third state, can be configured as an unstable VDD potential. Such an unstable VDD potential, also referred to as a high potential, can be set to low or ground. For example, the GPIO 22 comparator described above determines a low signal (first state) when the signal at pin 19 is below a threshold, or a high signal (hereafter referred to as the third signal) when the signal is above the threshold.For example, the low signal (resulting from a closed transistor 12 setting the potential of 9 to GND) indicates the first state, while the high signal (resulting from an open transistor 12, i.e., the pull-up resistor 7 defining the potential at signal line 9 as high) indicates a third state. In other words, the third state is the signal, which is provided externally (i.e., by an external component (external with respect to the sensor circuit 10), here the pull-up resistor 7 coupled between VDD and signal line 9). According to one implementation, the comparator may exhibit hysteresis.

[0017] It is often a problem that on the microcontroller side it is impossible to determine whether the first state results from sensor 5 applying GND to 19, or whether a failure, e.g. a damaged cable, causes this first state signal.

[0018] Conversely, it is often difficult to distinguish between the third state, caused by the switching state of transistor 12, and an open circuit at contact pin 19. To address this, sensor 10 often incorporates some type of microcontroller or diagnostic controller configured to send so-called live ticks. Here, a timing scheme is applied according to the same different states; for example, the first or third state is applied to contact pin 19. However, implementing such timing schemes places a significant burden on the microcontroller side to continuously measure time and / or to synchronize the sensor circuitry 10 and the microcontroller 20.

[0019] Based on this, the sensor circuit arrangement 10 – according to exemplary embodiments – is adapted to provide a different state, e.g., to be used as a status for sending diagnostic information, such as status information or failure information. This state is referred to as the second state.

[0020] Fig. Figure 2 shows a sensor circuit arrangement 10', which is comparable to sensor circuit arrangement 10, but improved as follows. In addition to the first transistor 12, sensor circuit arrangement 10' has a second transistor 14, wherein the first and second transistors 12 and 14 are coupled in series and have the signal I / O 16 between them. The second transistor 14 is configured to provide the second state.

[0021] This sensor circuit arrangement 10' is read by a microcontroller 20'. The microcontroller 20' is essentially the same as the microcontroller of 20, but also includes a third transistor 25. The transistor 25 is coupled between the signal I / O 22' of the microcontroller 20' and a first contact pin 28 with GND (signal of the first state). The transistor 25, in conjunction with the signal I / O 22', makes it possible to distinguish between a second and third state, which are provided by the sensor circuit arrangement 10'. Comparable to Fig. 1. The signal line 9 can be coupled with a pull-up resistor 7.

[0022] The structure and functionality of the sensor circuit arrangement 10' are explained below. The collector contact of transistor 14 is coupled to contact pin 18, while the emitter contact of transistor 12 is coupled to contact pin 17. The emitter contact of 14 is coupled to the collector contact of transistor 12, and both are coupled to the signal I / O 16. Again, the sensor signal from sensor 5 can be received using the control or base contact of transistor 12, here designated by reference numeral 12g. Transistor 14 receives a diagnostic signal, in particular a failure signal or a status signal, via its control or base contact 14g.

[0023] Transistor 12 is a pull-low resistor configured to communicate normal data using its first state (e.g., when it is closed). In this case, the first state can be GND. Thus, the signal I / O is configured to provide a GND potential (low) in the first state. The second transistor, 14, is a push-up transistor configured to provide the second state, e.g., push-up VDD, stable VDD, or stable high. Both the first and second states are activated depending on the signal applied to their respective control contacts, 12g and 14g.

[0024] If no signal is supplied to 12g and 14g, a third status is provided to signal I / O 16, for example, a pull-up VDD, unstable VDD, or unstable high. This is comparable to the description of circuit arrangement 10 of Fig. 1. This third state signal depends on the external component, namely the resistor 7. For this purpose, the pull-up resistor 7, which is in Fig. 1 and Fig. Figure 2 illustrates the use of contact pin 19. It should be noted that GND (generally low) and VDD (generally high) are only examples and are interchangeable.

[0025] In other words, the circuit arrangement 10' uses a push / pull stage to provide the three states.

[0026] The following section describes the microcontroller 20'. In its basic implementation, it features the signal I / O 22' (comparable to the signal I / O 22 of Fig. 1) and transistor 25. As already mentioned in connection with Fig. As explained in Figure 1, signal I / O 22' is configured to distinguish between the first state (low) and the third / second state (high), for example, using the comparator. Transistor 25 can be used or controlled by signal I / O 22' to distinguish between the second state (push-up VDD) and the third state (pull-up VDD).

[0027] The difference between the push-up VDD and the pull-up VDD is that the second state is a so-called stable state, while the third state is a so-called unstable state. For example, the second state could be a high signal, the first state a low signal, and the third state an unstable high signal. The unstable high signal can be brought to a low level if it is coupled to a low level, for example, via the third transistor 25. For the stable high, this coupling to a low level would result in a short circuit, which can be detected on the microcontroller side, or in a low signal, which is detected by the comparator of 22'. In this way, stable high (second state) and unstable high (third state) can be distinguished from one another. The signal I / O 22' can thus determine the second state if the signal is high when transistor 25 is off.If transistor 25 is open, it is possible to determine the first or third state (see above).

[0028] According to exemplary embodiments, the circuit arrangement 10' comprises two transistors 12 and 14, both connected in series to form a common node, which is connected to a signal I / O 16 between transistors 12 and 14. The signal I / O 16 allows output of a first state, a second state, and a third state. The first state is output via the signal I / O using the first transistor 12, and depending on the first signal, e.g., from sensor 5, the second state is provided via the signal I / O 16 using a second transistor 14, depending on a second signal. The third state is provided via the signal I / O 16 when the first and second transistors 12 and 14 are on / off. In the exemplary embodiment described above, it is assumed that 17 is coupled to low, e.g., ground, while 18 is coupled to high, e.g., B. VDD, coupled.Of course, this could be reversed, so that 17 is coupled to high / VDD and 18 is coupled to low / GND. Regardless of whether 7 is coupled to low (GND) or high (VDD), the first and second states are stable states, while the third state, according to the embodiments, is an unstable state.

[0029] In other words, GPIO 22' uses a push / pull stage to read the three states.

[0030] When the circuit arrangement 10' is used to send a signal, e.g., a sensor signal from sensor 5, the first and third signals represent the two different states of sensor 5. According to exemplary embodiments, it is of course possible to send a different (data) signal instead of a sensor signal. The second signal, generated using transistor 14, is, according to exemplary embodiments, a status signal, in particular a diagnostic signal or a failure signal. However, according to further exemplary embodiments, it is also possible to send a different sensor signal using the second status. According to further exemplary embodiments, it is also possible to transmit signals other than sensor signals as a first signal or a second signal.

[0031] In other words, embodiments of the present invention are based on the principle that a combination of open-drain and push-pull communication is used on the sensor circuit to transmit at least two independent signals. This is achieved by implementing a high-side switch 14 on the sensor side to shorten the external pull-up resistor 7 used for open-drain communication. On the microcontroller side, the pull-down transistor of a GPIO can determine whether this high-side switch 14 is ON or OFF. This can be used for failure status communication or to send another signal. Advantageously, this option can be used to obtain additional information without using an additional microcontroller pin.

[0032] According to further embodiments, the output of the signal I / O 16 of the circuit arrangement 10', 10" has a third contact pin 19, which is coupled to VDD via a pull-up resistor 7. The resistor 7 advantageously defines the signal that corresponds to the third state.

[0033] According to the implementation examples, the following operating modes are used: Mode 1 - Data transmission from the sensor circuit arrangement 10' to the microcontroller 20'. In this mode, the second transistor 14 (S2) is OFF, i.e., inactive, so that the first transistor 12 (S1) can be used to transmit the data from the sensor circuit arrangement 10' to the microcontroller 20', as described in the following. Fig. 1 explained. Mode 2 - If a fault occurs in the sensor circuit arrangement 10', the first transistor 12 (S1) is switched OFF and the second transistor 14 (S2) is switched ON. The microcontroller 20' can detect this fault condition (second state) in the sensor circuit arrangement 10' by switching on the third transistor 25 (T1) (T1 = ON): i. if the signal on line 9 is (still) high => error ii. if the signal on line 9 is low => no error

[0034] It should be noted that all related to Fig. The details explained in section 1, according to the exemplary embodiments, can be applied to the circuit arrangement 10' and the microcontroller 20'. The following sections refer to... Fig. 3a and Fig. 3b explains optional features and further details for the circuit arrangement 10' and the microcontroller 20'.

[0035] Fig. Figure 3a shows an improved embodiment, in particular an improvement with regard to Fig. 2. Here, the sensor circuit 10" with the three pins is present, with 17 being coupled to GND, 18 to VDD, and 19 to the signal line 9. The sensor circuit 10" includes the two transistors 14 and 12 with the control contacts 14g and 12g. Both transistors 14 and 12 are arranged in series and have the signal I / O 16 between them. In this embodiment, an additional resistor 12r (R1) is provided between the node and the collector of transistor 12 at the junction where the emitter of 14 and the collector of 12 are coupled to form the signal I / O.

[0036] Analogous to the example of Fig. 1 is a pull-up resistor 7 (R) on the signal output line 9. pu ) provided, which is coupled between 9 and VDD. In other words, the embodiment of Fig. 3a can be described as follows: A row for the first and second transistors 12 and 14 is arranged between a first contact pin 17 for applying GND or low and the second contact pin 19 for applying VDD or high. The signal I / O 16 has a third contact pin, which is 19 and is coupled to a VDD via a pull-up resistor 7. It is noted that according to exemplary embodiments, R1 of the resistor 12r is smaller than R PU of resistance 7 is.

[0037] Transistor 14 (S2) is configured to provide additional information about the third contact pin 19 by shortening the pull-up resistor 7 (R). pu) to provide. Thus, the signal S2 can be output via contact pin 19. As a result, 16 can send the first signal S1 as a first state, the second signal S2 as a second state, and another signal S3, which is the counterpart of S1, as a third state. According to exemplary embodiments, the signal I / O 16 is configured to provide a ground (GND) or low potential in the first state. According to further exemplary embodiments, the signal I / O 16 is configured to provide a stable VDD potential or stable high potential in the second state. It is noted that the stable VDD potential can be characterized by the fact that the stable VDD potential cannot be brought to a low level.According to further embodiments, a signal I / O 16 is configured to provide an unstable VDD potential in a third state, or is configured to provide an unstable VDD potential or unstable high in a third state, wherein the unstable VDD potential is characterized in that the unstable VDD (unstable third state in general) can be brought low because the potential is provided by the pull-up resistor 7, which is not bypassed by the second transistor 14.

[0038] In other words, this means that, according to exemplary embodiments, the input of the signal I / O 22' has or is coupled to a first transistor 25, the same being coupled between the signal I / O 22' and a first contact pin 28, which is in the first state and configured to be closed to determine a current flow, or in the second or third state.According to further embodiments, the input of the signal I / O 22' has or is coupled to a first transistor 25, wherein the same is coupled between the signal I / O 22' and a first contact pin 28, which has the first state and is configured to be closed in order to determine a current flow in the second or third state and to distinguish between the second and third states, depending on the situation that the third state can be brought into the first state and / or the second state causes a short circuit.

[0039] According to exemplary embodiments, unit 10" can include a type of controller that performs a diagnostic check to determine the status or failure of unit 10". This status can be output as signal S2 via transistor 14. For example, in the event of a failure, S2 is generated to provide a signal corresponding to the second state. Preferably, transistor 12 is open in this situation. According to exemplary embodiments, the controller 11 can be triggered by a received trigger signal to perform a diagnostic check. According to exemplary embodiments, the controller 11 can output a status signal, such as a simple acknowledgment signal, in response to the trigger. For example, if the first stage is activated, the controller 11 is configured to output a signal, different from the first state, as an acknowledgment via the second state.If the second or third state is activated, the controller can output the signal of the second state as an acknowledgment. For example, the signal's duration can be limited, e.g., 100 ms or less. Thus, according to the exemplary embodiments, the trigger signal can be configured to trigger the controller 11 for an internal process. Here, the internal process can be defined, for example, by... - Deactivating or briefly deactivating the first state, e.g., when the first state is active; - Activating or briefly activating the second state, e.g., when the first state is active; - Activating or briefly activating the first state, e.g., when the third state is active.

[0040] This principle is advantageous because it avoids the need for a time-controlled live ticker, as the microcontroller can check the live status on request / trigger.

[0041] In exemplary embodiments, the trigger signal on the circuit assembly side is received via signal I / O 16. For this purpose, signal I / O 16 has an input 16i, e.g., a GPIO, configured to receive the trigger signal via signal line 9 and contact pin 19. Input 69 of signal I / O 16 can be connected to the controller 11. In exemplary embodiments, 16i is configured to detect the error check of the microcontroller 20", e.g., via a trigger such as current flow in transistor 14 (S2). When the sensor circuit assembly 10' detects the error check, it can be used to initiate additional processes in the sensor (e.g., output an acknowledgment pulse). Additionally or alternatively, the sensor circuit assembly 10' can be configured to detect a trigger from T2, i.e., when the fourth transistor 23 (T2) is switched ON.This can be done, for example, via the current flow in the sensor through transistor 12 (S1), e.g. to check the connecting line 9 between the sensor circuit arrangement 10' and the microcontroller 20".

[0042] Fig. Figure 3b shows the microcontroller 20" as an improvement on the microcontroller 20'. It has three contact pins 27, 28, and 29, where, for example, 27 is coupled to VDD or high, and 28 is coupled to GND or low. Of course, this can be reversed according to embodiments. Contact pin 29 is coupled to signal line 9 and configured to receive a status signal, such as the first status signal, the status signal, or the third status signal. This status signal can be determined using GPIO 22' in combination with two transistors 23 and 25. Transistor 23 (third transistor) and transistor 25 (fourth transistor) are arranged in series between contact pins 27 and 28, with the signal I / O 22' positioned between them. This means that, according to embodiments, the control contact of 23 is coupled to 27, with the collector of 25 coupled to 28. is coupled.The emitter of 23 is coupled to the collector of 25 and, via a common node, to the signal I / O 22'. By switching the two channels 23 (T2) and 25 (T1), or in particular channel 25, it is possible to read out the three difference states received via signal line 9.

[0043] For example, signal acquisition can be as follows. The second transistor S2 (see...) Fig. 3a), which provides the second state, can provide the additional information via the output contact pin by shortening the pull-up resistor 7. By switching transistor 25 (T1), it is possible to detect whether S2 is on, i.e., to detect the second state, if a short circuit occurs or if the signal is still high when T1 is closed. The short circuit indicates a stable high signal. This means that transistor 25, which is used to read the second state provided by transistor 14, could, according to exemplary embodiments, have direct coupling with different potentials (high / low). Transistor 25 can be controlled by 22'. Advantageously, a failure state S2 can be provided by the sensor circuit 10" to the microcontroller 20" via the output contact pin. This will be very useful in products such as magnetic switches, e.g.The failure status can be provided without an additional contact pin.

[0044] For the sake of completeness, it should be noted that transistor 23 (T2) can be used to read the first state, i.e., when a current flows from 17 through 12 via 12r, 16, 19, 9 to 29 via 23 to 27. This current flow can be determined using 22'. It is noted that the above discussion assumes that S2 provides a stable high signal as the second state. If 14 is connected to low, it could provide a stable low signal. In this case, 25 could be connected to high to read the stable low signal.

[0045] According to exemplary embodiments, a distinction between stable high (second state) and high (third state) can be made using transistor 25 and signal I / O 22'. A short circuit is detected. In the case of a short circuit, stable high is present, so the second state is active. If there could be a current flow through 22', but the signal can be pulled low, unstable high, i.e., the third state, is present. Thus, a distinction is made between a stable high and a high state that can be pulled low by the microcontroller 20". In other words, this means that if the sensor output is high, there will always be a current flow as soon as the microcontroller 20 attempts to pull; either through the pull-up resistor 7 or the push-up transistor 14, a large current will flow.Consequently, the three signals high, pull up and low can be transferred from the circuit arrangement 10" to 20" according to the second state, the third state and the first state, and can be determined in different ways by the microcontroller 20".

[0046] According to further embodiments, wherein the third transistor 25 is configured to be closed in order to pull a signal from the signal line 9 into the first state when the signal from the signal line 9 is in the third state, the input of the signal I / O 22' of the microcontroller 20' is additionally or alternatively configured to determine the second state when the third transistor 25, which is coupled between the signal I / O 22' of the microcontroller 20' and a first contact pin 28 which is in the first state and is to be closed, does not pull a signal from the signal line 9 into the first state when the signal from the signal line 9 is in the second state.

[0047] According to further embodiments, the output of 22' is configured to output a trigger signal to the circuit arrangement 10' or 10" to initiate an internal process, or is configured to read the circuit arrangement 10', 10" particularly with regard to activating the second state.

[0048] According to exemplary embodiments, a signal, e.g., the initial status, may be continuously provided. In this case, it is advantageous if the controller 20" is enabled to initiate or trigger an internal process, such as a diagnostic process. According to exemplary embodiments, the signal I / O is configured to provide a trigger signal to the circuit arrangement 10" via contact pin 29. A constant high signal can be provided using transistor 23. Alternatively, a constant low signal can be applied using transistor 25.

[0049] As discussed above, this serves the purpose of initiating an internal process, such as a diagnostic process, or reacting to a live signal, for example, by briefly disabling the first state and switching to a third or second state, or by briefly activating the second state. If the third or second state is activated, the same could be triggered to briefly activate the first state in response. When the microcontroller 20" stops detecting a sensor fault, it no longer needs to monitor the sensor signal over time, thus reducing the demands on the microcontroller. Consequently, the microcontroller remains in charge at all times.

[0050] According to further embodiments, the output of the signal I / O 22' includes a third transistor 25, which is coupled between the signal I / O 22' and a first contact pin 28 with a first state, or is coupled to the same state, wherein the trigger is the output of the first state via the signal I / O 22' using the third transistor 25. According to further embodiments, the output of the signal I / O 22' includes a fourth transistor 23, which is coupled between the signal I / O 22' and a second contact pin 27 with a second state, or is coupled to the same state, wherein the trigger is the output of the second state via the signal I / O 22' using the second transistor 23.

[0051] According to the exemplary embodiments, the signal I / O 22' is configured to receive feedback on the first, or preferably the second or third, state in response to an internal process. This means that the sensor 10" responds to the analysis of the microcontroller 10' with a predefined response to confirm the analysis request (to perform a diagnosis, such as fault detection or acquisition).

[0052] According to further embodiments, the input of the signal I / O 22' has a fourth transistor 23 and is coupled to it, the latter being coupled between the signal I / O 22' and a second contact pin 27 with the second state and configured to be closed to determine the first state when a short circuit occurs. It should be noted that the signal I / O 22' is configured to receive and send signals via 19, i.e., it has an input and an output. The input and the output are both connected to the signal I / O contact pin 19.

[0053] Fig. Figure 4 shows the combination of 10" and 20". As can be seen, the signal line 9 connects the contact pins 19 and 29. The signal I / O of 10" is located in contact pin 19, while the signal I / O of 20" is located at contact pin 29.

[0054] It should be noted that on both the circuit side of the circuit 10" and the microcontroller side of the microcontroller 20" the signal I / O has one input and one output, both of which are coupled to the single contact pin 19 and 29 respectively.

[0055] As seen here in Fig. As illustrated in Figure 4, another embodiment provides a system that includes the circuit 10" and 20".

[0056] As described above, the dimensions of R1 and R PU preferably chosen such that R1 is smaller or significantly smaller than R PU Regarding transistors 14 and the opposite transistor 25, it should be noted that 14 is "stronger" than transistor 25.

[0057] The above embodiments have the advantage that additional information, such as diagnostic information, can be sent, with both the microcontroller 20" and the circuit arrangement 10" being based on existing standards.

[0058] Likewise, the emitter and collector contacts for circuits 10', 10", and 20" were clearly explained in the above embodiments. For example, bipolar NPN transistors are used in the described embodiment. Alternatively, different transistors such as PNP transistors can be used. It should be noted that the emitter and collector connections could be different in this case, e.g., reversed. Preferably, the control contacts, also referred to as base contacts, 12g and 14g are connected to the sensors or configured to receive the signal S1 and S2 to be transmitted. According to alternative embodiments, different transistors such as FETs with a source contact instead of a collector, a gate contact instead of a base (general control contact), and a drain contact instead of an emitter can be used.

[0059] With reference to Fig. 5 and Fig. Section 5b explains seven different phases. Fig. 5a shows the system of Fig. Figure 4 illustrates failures F1 to F7. According to failure 1, the line for pull-up resistor 7 is open. According to failure F2, signal line 9 is connected to VDD. According to failure F3, signal line 9 is set to GND. According to F4, signal line 9 is open. According to F5, the signal line next to contact pin 19 is open. According to F6, the FDD line on the sensor side is open at contact pin 18. According to failure F7, the GND line is open at contact pin 17. Fig. Figure 5 shows the possible combination of situations for capturing F1 to F7.

[0060] The following explains possible triggers depending on the open / closed state of S1 and S2. With S1 closed and S2 open, a closed pulse T2 can be sent, creating state 1, also known as the first state. If functioning correctly, some current, limited by R1, will be received at input 20". With S1 open and S2 closed, a closed pulse T1 could be sent, creating state 2. If functioning correctly, a high current could be detected at input 20", potentially activating the internal short-circuit protection. With S1 and S2 open, a closed pulse T1 could be sent, creating state 3, also known as the third state. A low current at input 20 indicates correct operation.All these three different triggers and expected responses make it possible to determine some of the failures mentioned above. In particular, failures F1, F2, F5, F6, and F7 can be identified as a function of state S1, S2, as shown by the matrix of . Fig. Figure 5 illustrates this. The light, hatched areas indicate that in such cases it is always mistakenly assumed that the tones without hatching indicate that failure detection is not possible.

[0061] For example, if F1 fails, no pull-up signal line can be floating. While some states might theoretically function correctly, the sensor detects the missing pull-up and can switch to failure state 2. To determine this failure, a differentiation between various states is performed. With S1 closed and S2 open, the current flowing to input 22' of microcontroller 20" is limited by R1. With S1 open and S2 closed, the current flowing to input 22' of microcontroller 20" is high, potentially activating internal short-circuit protection. With S1 and S2 open, a floating state at microcontroller 20" is possible if no transistor is closed.

[0062] In the event of a F2 failure, reliable detection is possible if S1 is open and S2 is closed. In this case, the second state can be determined if the microcontroller 20" defines a second state at its input 22', independent of the sensor signal.

[0063] Although some aspects have been described in relation to a device, it is understood that these aspects also constitute a description of the corresponding method, where a block or component corresponds to a method step or a feature of a method step. Similarly, aspects described in relation to a method step also constitute a description of a corresponding block, element, or feature of a corresponding device. Some or all of the method steps may be performed by (or using) a hardware device, such as a microprocessor, a programmable computer, or an electronic circuit. In some embodiments, some or several of the key method steps may be performed by such a device.

[0064] Depending on specific implementation requirements, embodiments of the invention can be implemented in hardware or in software. The implementation can be carried out using a digital storage medium, such as a floppy disk, DVD, Blu-ray disc, CD, ROM, PROM, EPROM, EEPROM, or FLASH memory, which contains electronically readable control signals that interact (or can interact) with a programmable computer system to execute the respective method. Therefore, the digital storage medium can be computer-readable.

[0065] Some embodiments according to the invention include a data carrier which has electronically readable control signals which can interact with a programmable computer system in such a way that one of the methods described herein is carried out.

[0066] In general, embodiments of the present invention can be implemented as a computer program product with program code, wherein the program code is effective in carrying out one of the methods when the computer program product is running on a computer. The program code can, for example, be stored on a machine-readable medium.

[0067] Other embodiments include the computer program for carrying out one of the procedures described herein, which is stored on a machine-readable medium.

[0068] In other words, an embodiment of the method according to the invention is therefore a computer program with program code for carrying out one of the methods described herein when the computer program is running on a computer.

[0069] Another embodiment of the methods according to the invention is therefore a data carrier (or a digital storage medium or a computer-readable medium) that contains the computer program for carrying out one of the methods described herein, which is recorded on the same. The data carrier, the digital storage medium, or the recorded medium is typically tangible and / or non-volatile.

[0070] Another embodiment of the method according to the invention is therefore a data stream or a sequence of signals that represents the computer program for carrying out one of the methods described herein. The data stream or sequence of signals can, for example, be configured to be transmitted via a data communication connection, such as the Internet.

[0071] Another embodiment includes a processing device, for example a computer, or a programmable logic module, which is configured or adapted to perform one of the methods described herein.

[0072] Another embodiment includes a computer on which the computer program for performing one of the procedures described herein is installed.

[0073] Another embodiment according to the invention comprises a device or system configured to transmit a computer program for performing one of the methods described herein (for example, electronically or optically) to a receiver. The receiver may be, for example, a computer, a mobile device, a memory component, or the like. The device or system may, for example, include a file server for transmitting the computer program to the receiver.

[0074] In some embodiments, a programmable logic device (for example, a freely programmable logic assembly) can be used to perform some or all of the functionalities of the methods described herein. In some embodiments, a freely programmable logic assembly can interact with a microprocessor to perform one of the methods described herein. Generally, the methods are preferably performed by any hardware device.

[0075] The embodiments described above are merely illustrative of the principles of the present invention. It should be noted that modifications and variations of the arrangements and details described herein will be obvious to other people skilled in the art. It is therefore intended that the present invention is limited only by the scope of protection of the pending claims and not by the specific details presented herein in the description and explanation of the embodiments.

Claims

[1] Circuit arrangement (10', 10") in combination with a microcontroller (20'), wherein the circuit arrangement (10', 10") comprises a first transistor (12) and a second transistor (14), both arranged in series and having a signal I / O (16) of the circuit arrangement (10', 10") between them; wherein the first transistor (12) is configured to output a first state to the signal I / O (16) of the circuit arrangement (10', 10") depending on a first signal; wherein the second transistor (14) is configured to output a second state to the signal I / O (16) of the circuit arrangement (10', 10") depending on a second signal; wherein the signal I / O (16) of the circuit arrangement (10', 10") is configured to provide a third state when the first and second transistors (14) are disabled; wherein the microcontroller (20') has a signal I / O (22') of the microcontroller (20') and a third transistor (25), the signal I / O (22') of the microcontroller (20') having an input configured to distinguish between the first state and the second state or the third state provided by the circuit arrangement via a signal line (9); wherein the third transistor (25) is coupled to the signal line (9) via the signal I / O (22') of the microcontroller (20'), wherein the signal I / O (22') of the microcontroller (20') is configured to distinguish between the second state and the third state by using the third transistor (25). [2] Circuit (10', 10") according to claim 1, wherein the second signal comprises a status signal, in particular a diagnostic signal or a failure signal. [3] Circuit arrangement (10', 10") according to one of the preceding claims, wherein the first signal comprises a sensor signal, in particular a magnetic sensor signal. [4] Circuit arrangement (10', 10") according to one of the preceding claims, wherein the signal I / O (16) of the circuit arrangement (10', 10") has a third contact pin (19) which is coupled to VDD via a pull-up resistor (7). [5] Circuit arrangement (10', 10") according to one of the preceding claims, wherein the third transistor (25) is coupled between the signal I / O (22') of the microcontroller (20') and a first contact pin (28) which has the first state and is configured to be closed in order to pull a signal from the signal line (9) into the first state when the signal from the signal line (9) is in the third state; and / or wherein the input of the signal I / O (22') of the microcontroller (20') is configured to determine the second state when the third transistor (25), which is coupled between the signal I / O (22') of the microcontroller (20') and a first contact pin (28) which has the first state and is configured to be closed, does not pull a signal from the signal line (9) into the first state when the signal from the signal line (9) is in the second state. [6] Circuit arrangement (10', 10") according to one of the preceding claims, wherein the signal I / O (16) of the circuit arrangement (10', 10") is configured to provide a stable VDD potential in the second state, wherein the stable VDD potential characterized by is that the stable VDD potential cannot be brought low by the third transistor (25); and / or wherein the signal I / O (16) of the circuit arrangement (10', 10") is configured to provide an unstable VDD potential in the third state, wherein the unstable VDD potential characterized by is that the unstable VDD potential is provided by a pull-up resistor (7) which is not bypassed by the second transistor (14) or can be brought low by the third transistor (25). [7] Circuit arrangement (10', 10") according to one of the preceding claims, wherein the array of the first transistor (12) and the second transistor (14) is arranged between a first contact pin (17) for applying GND and the second contact pin (18) for applying VDD. [8] Circuit arrangement (10', 10") according to one of the preceding claims, wherein the second signal and / or the first signal is applied to a control contact (12g, 14g) of the respective first and / or second transistor. [9] Circuit arrangement (10', 10") according to one of the preceding claims, wherein a drain or emitter contact of the first transistor (12) is coupled to a first contact pin (17); and / or wherein a source or collector contact of the second transistor (14) is coupled to a second contact pin (18); and / or wherein a source or collector contact of the first transistor (12) is coupled to a drain or emitter contact of the first contact pin (17). [10] Circuit arrangement (10', 10") according to one of the preceding claims, further comprising a controller (11) configured to determine a status, in particular a diagnostic status or a failure status, and / or connected to the second transistor (14) and configured to provide the second signal. [11] Circuit arrangement (10', 10") according to one of the preceding claims, wherein the signal I / O (16) of the circuit arrangement (10', 10") is configured to receive a trigger signal, in particular via a third contact pin (19); wherein the trigger signal is configured to trigger the control (11) for an internal process. [12] Circuit arrangement (10', 10") according to claim 11, wherein the internal process is one of the following: - Disabling or briefly disabling the first state (if the first state is active); - Activating or briefly activating the second state (when the first state is active); - Activating or briefly activating the first state (when the third state is active). [13] Circuit arrangement (10', 10") according to one of the preceding claims, wherein the signal I / O (22') of the microcontroller (20') has an output configured to output a trigger signal to the circuit arrangement to initiate an internal process, or configured to read the circuit arrangement (10', 10"), in particular with respect to the second state. [14] Circuit arrangement (10', 10") according to claim 13, wherein the output of the signal I / O (22') of the microcontroller (20') is coupled to a fourth transistor (23) which is coupled between the signal I / O (22') of the microcontroller (20') and a second contact pin (29) with a second state, wherein the trigger comprises the output of the second state by using the second transistor (23) via the signal I / O (22') of the microcontroller (20'); or wherein the output of the signal I / O (22') of the microcontroller (20') is coupled to a third transistor (25) which is coupled between the signal I / O (22') of the microcontroller (20') and a first contact pin (28) with a first state, wherein the trigger comprises the output of the first state by using the first transistor (25) via the signal I / O (22') of the microcontroller (20'). [15] Circuit arrangement (10', 10") according to any one of claims 11 to 14, wherein the circuit arrangement (10', 10") is configured to receive feedback on the first or preferably second or third state in response to the trigger or the internal process. [16] Method for operating a circuit arrangement (10', 10") in combination with a microcontroller (20'), wherein the circuit arrangement (10', 10") comprises a first transistor (12) and a second transistor (14) which are both arranged in series and have a signal I / O (16) of the circuit arrangement (10', 10") between them; the microcontroller (20') has a signal I / O (22') of the microcontroller (20') and a third transistor (25), the signal I / O (22') of the microcontroller (20') has an input, wherein the third transistor (25) is coupled to the signal line (9) via the signal I / O (22') of the microcontroller (20'), wherein the method comprises the following steps: Output of a first state to the signal I / O (16) of the circuit arrangement (10', 10") depending on a first signal by using the first transistor (12); Output of a second state to the signal I / O (16) of the circuit arrangement (10', 10") depending on a second signal by using the second transistor (14); Providing a third state when the first and second transistors (14) are deactivated; Distinguishing between the first state and the second state or the third state, which is provided by the circuit arrangement via a signal line (9); and Distinguishing between the second state and the third state by using the third transistor (25). [17] Computer program for carrying out the method according to claim 16 when the same is running on a computer.

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