Pulse width modulation signal generator and method

Abstract

A semiconductor device for generating PWM modulation signals, for example an optimized pulse pattern (OPP), is provided. An ADC 42 outputs the motor angle and is connected to a coprocessor 52, for example a digital signal processor (DSP). The coprocessor 52 has an observer 44 connected to the angle inputs for generating a motor angle, and a lookup table 48 for generating a PWM signal as a direct function of the generated motor angle. A processing unit 46 has an input connected to the coprocessor 52, and the processing unit is configured to select a lookup table based on the generated motor angle and to store the selected lookup table as the lookup table 48.

Description

Field of invention

[0001] The invention relates to a method for generating a pulse width modulation signal and a semiconductor device for generating the signal, in particular for use in driving a motor. Background of the invention

[0002] There is a need for the efficient driving of electric motors. For example, in the powertrain of an electric or hybrid vehicle, the electric motor is driven by a battery through a number of drivers. Typically, six power transistors arranged as three half-bridges are used to drive a three-phase electric motor.

[0003] The power transistors are driven by signals, typically pulse-width modulation signals; that is, the transistors are either off or on. The power transistors are driven by a driver, which is controlled by a control unit, such as a microcontroller, that generates the signals.

[0004] One approach is known as space vector pulse-width modulation, or PWM. When this approach is used, a higher switching frequency allows the generation of a PWM signal with reduced ripple and lower harmonic distortion, resulting in lower losses in the motor.

[0005] There is a general need for approaches that avoid excessive losses in engines. Brief description of the invention

[0006] According to a first example, a semiconductor device for generating a pulse pattern signal is provided, comprising: an analog-to-digital converter (ADC) for connection to a motor, which has an output to display the angle of the motor, a coprocessor comprising an angle input connected to the output of the ADC, an observer connected to the angle input for determining a motor angle, a coprocessor lookup table for generating a PWM pulse pattern signal as a direct function of the determined motor angle, and a pulse pattern signal output for outputting the pulse pattern signal, and a computing unit having an input connected to the coprocessor, wherein the computing unit is configured to select a lookup table from a variety of lookup tables based on specific motor conditions, such as acceleration and torque, and to store the selected lookup table as the coprocessor lookup table in the coprocessor.

[0007] By using a lookup table in the coprocessor, the example provides a first loop that is directly driven by the angle measurement; this can provide a fast loop without requiring complex structures in the semiconductor device.

[0008] By generating the pulse pattern signal directly from the analog-to-digital converter (ADC), the pulse pattern signal can be delivered as quickly as the ADC can output a signal. Thus, the ADC and the DSP provide a fast loop; the updating of the lookup table by the computational unit constitutes a second, slower outer loop. For example, the fast loop can operate on a timescale of less than 10 µs, such as less than 2 µs, while the outer loop, including the computational unit, can operate on a timescale of more than 20 µs, such as more than 40 µs. This, in turn, allows the use of a conventional general-purpose microcontroller core to perform the calculations in the outer loop; alternative implementations can use alternative hardware, such as an alternative core, for example, in a parallel processing unit. Brief description of the drawings

[0009] Examples of the invention will now be described purely by way of example with reference to the accompanying drawings, in which: Fig. Figure 1 illustrates an optimized pulse pattern (A) and a regular pulse pattern (B). Fig. 2 Control signals for a driver illustrated together with a driver; Fig. 3 illustrates an exemplary arrangement; Fig. 4 illustrates another exemplary arrangement; Fig. 5 PWM signals illustrated; Fig. 6 control signals illustrated; Fig. 7 illustrates another exemplary arrangement; and Fig. 8 signals illustrate the arrangement of Fig. 7 correspond. Detailed description

[0010] An example of the invention is presented purely as an illustration.

[0011] Fig. Figure 1 shows an example of an optimized pulse pattern used to drive a motor (A) and a conventional regular pulse pattern (B). The regular pulse pattern (B) starts pulses at a regular interval and adjusts the pulse length to provide pulse width modulation (PWM).

[0012] Optimized pulse patterns (OPP) can be used to deliver a signal with lower total harmonic distortion (THD) than a space vector pulse-width modulation. In such optimized patterns, switching is not restricted to regular intervals, but rather occurs at times selected for lower THD and losses.

[0013] For example, an OPP using a switching frequency of 9 kHz can deliver a THD of 2.3%. In contrast, a SVPWM approach using the same 9 kHz switching frequency can deliver a current signal with a THD of 5.7%. For the SVPWM approach to achieve a similar THD of 2.35%, the switching frequency must be increased to 20 kHz. This higher switching frequency means that the transistors in the half-bridge driving the motor switch more frequently, resulting in higher switching losses. Thus, using an OPP can significantly increase efficiency and reduce losses, which in turn leads to less heat generation, making it easier to keep the semiconductors and motor within a proper operating temperature range.

[0014] Such OPPs should be generated synchronously with the angular position of the engine. Furthermore, the OPP requires multiple shifts, at least 8 times per revolution. Fig. Figure 2 shows the control signals for a high-side and a low-side driver as a function of the angle. The angle is indicated on line 20, the high-side signal on line 22, and the low-side signal on line 24. The signals are fed into a high-side driver 26 and a low-side driver 27, which in turn feed a high-side transistor 28 and a low-side transistor 29, which are connected to Fig. Figure 2 illustrates this. It should be noted that the high-side and low-side signals are not simply inverted: In this example, a certain dead time is introduced to ensure that the high-side driver 26 and the low-side driver 27 are not both switched on simultaneously. As shown in Fig. As illustrated in point 2, the switching times are not periodic.

[0015] Calculating OPP signals requires significant computational resources. To avoid the need for excessively powerful computing hardware to perform OPP calculations in software, some hardware functionality can be integrated into the microcontroller to obtain the pulse patterns. It may not be possible to execute all the processing at a sufficient speed using software running on a conventional core when using a reasonably priced microcontroller.

[0016] There is a need for a product that can be used for this application without being complex and expensive, particularly to avoid, for example, the need for features such as a field-programmable gate array and the need for large amounts of high-speed memory and thus chip area. Accordingly, there is a need for a hardware device and a method for generating a pulse pattern signal using a hardware device that does not require such complex elements.

[0017] Fig. Figure 3 illustrates an example. A motor 30 is mechanically connected to the inductive sensor 36, the magnetic sensor 38, and the coil 34. When in use, the coil 34 is energized by a current in the carrier connection 58, and the inductive fields picked up by the inductive sensors 36 and 38 are used to generate a sine signal on the sine connection 54 and a cosine signal on the cosine connection 56. It should be noted that, although the sensors shown are inductive sensors, other sensors, such as magnetic sensors or alternative sensors, can be used.

[0018] A microcontroller 40 is provided, comprising an input ADC 42, an observer 44, a computation unit 46, a lookup table (LUT) 48, and a timer unit 50. The observer 44 and the lookup table 48 are contained in a coprocessor, in this example a digital signal processor (DSP) 52. The ADC is connected to the sensors 36 and 38 using the sine wave connection 54 and the cosine wave connection 56.

[0019] The output of the ADC is connected to the observer 44 in the DSP 52. A carrier generator 43 is provided to supply a carrier signal.

[0020] The observer 44 is an angle and speed observer that generates a measure of the angle and a measure of the rotor's speed as output from the digitized sine and cosine signals. The observer can be of any type capable of outputting angle and speed signals. Alternatively, the observer can generate only the angle signal, in which case the speed signal is calculated elsewhere, for example, in the processing unit 46.

[0021] The angle output of the observer 44 is connected to the lookup table 48, which is a lookup table of the angle relative to the pulse output (see e.g. Fig. 5 below) and outputs a pulse pattern signal, in this example a PWM signal, which is simply looked up in the lookup table based on the angle.

[0022] The timer output unit 50 is set up to display the actual high-side and low-side signals (see, for example, Fig. 6 discussed below) to generate from the digital hardware signal, taking into account the required dead time.

[0023] The computing unit 46 is connected to the output of the observer 44. A direct memory access unit 60 is also provided between the computing unit 46 and the lookup table 48, as shown below.

[0024] When in use, the ADC 42 receives the sine and cosine signals from the inductive sensors 36 and 38 along the sine connection 54 and the cosine connection 56, respectively, and digitizes them. The digital sine and cosine signals are then used in the angle observer 44 to generate an angle measurement, which is in turn passed to the lookup table 48 to generate the pulse pattern signal. This is then processed by the timer unit 50 to generate the high-side and low-side driver signals.

[0025] The ADC module 42 can acquire a sine and cosine signal relatively frequently, for example, every 1 µs, every 2 µs, or every 0.2 to 10 µs. The lookup table 48 can generate the required output at a first rate, which can simply be the rate at which the sine and cosine signals are acquired. This is possible because a lookup table can generate an output quickly without requiring complex internal hardware structures.

[0026] It should be noted that if load conditions or the required drive of motor 30 change, different lookup table patterns are required. Therefore, lookup table 48 must be updated regularly. The computation unit 46 is configured to use the angle and rotational speed measurements derived from the output of observer 44 to select the best pattern for transmission. The DMA unit 60 is then instructed to automatically transfer the selected pattern to lookup table 48.

[0027] In this way, the lookup table can be corrected regularly, although not as quickly as the ADC module's control loop. The lookup table can be updated at a second rate, for example, every 20 µs, or every 50 µs, or every 100 µs, at least five times slower than the first rate. This approach can provide a high-speed pulse pattern signal, in a specific example an OPP, without requiring expensive hardware, including, in particular, avoiding the need for high-speed, high-capacity memory.

[0028] Fig. Figure 4 illustrates an example that uses a motor driven by three-phase currents, which is driven by a pulse pattern signal, which in this example is a PWM signal, for example an OPP.

[0029] In this example, three half-bridges 74 are provided in parallel, each with a high-side transistor 28 and a low-side transistor 29. These drive three respective power lines 80, 82, 84, which are connected to and drive the motor 30.

[0030] Three current ADCs 90, 92, 94 are connected to respective current lines 80, 82, 84 to output a digital measure of the current. Each digital output is connected to an integrator 78, which provides a measure of smoothing.

[0031] The outputs of the integrators 78 are connected to the calculation unit 46.

[0032] The sine connection 54 connects the sensor 36 and the ADC 100; the cosine connection 56 connects the sensor 38 and the ADC 102.

[0033] In this case, three parallel lookup tables 48 and one observer 44 are provided in the DSP 52. The LUTs 48 each represent the PWM signal as a function of the angle input for each of the three half-bridges 74. Each LUT is connected via a respective PWM output 126 to a respective PWM output line 120, 122, 124, which is connected to the timer unit 50.

[0034] The timer unit 50 includes a sampling unit 130, which is connected to the PWM output lines 120, 122, and 124 and also has its own outputs. The timer unit 50 also includes a timer 134. The output of timer 134 is used within the timer unit 50 and is also output to the ADCs 90, 92, 94, 100, and 102, as well as the integrators 78, to maintain timing accuracy.

[0035] A dead-time and inversion unit 132 has sampling inputs connected to the sampling unit 130, in this embodiment one for each of the three respective PWM output lines, and is provided with six outputs, each connected to the six transistors of the half-bridges 74, with one output connected to each transistor. For each half-bridge, an output pair is provided, comprising a negative-side output 51, connected to drive the low-side transistor 29, and a positive-side output 53, connected to drive the high-side transistor 28. In operation, the dead-time and inversion unit 132 calculates the required output signals from the respective PWM signals received at the respective sampling inputs.

[0036] It should be noted that in Fig. Figure 4 shows the half-bridges schematically connected directly to the positive-side outputs 53 and the negative-side outputs 51 of the timer unit 50. In examples, a driver circuit with a plurality of drivers (not shown) can be provided between the outputs 51, 53 and the half-bridges 74, for example, where the transistors of the half-bridges require different drive characteristics than those available at the loop outputs 51.

[0037] In use, the lookup table enables the rapid generation of PWM signals without the need to include the calculation unit 46.

[0038] A number of lookup tables 142 are stored in memory 140.

[0039] The processing unit 46 takes as inputs the outputs of the integrators 78, which represent the current values ​​measured by the ADCs 90, 92, 94, as well as the outputs of the ADCs 104, 102, which represent the sine and cosine signals, together with the outputs of the observer 44, which represent the angle and speed of the motor 30. The processing unit can be, for example, a central processing unit, a parallel processing unit, or another unit with a core capable of executing instructions.

[0040] Using this information, the computation unit 46 identifies which of the pre-stored lookup tables 142 should be used at a given time and outputs a signal to the DMA 60, which downloads the identified lookup table from the lookup tables 48 stored in the DSPs.

[0041] Pattern identification and acceptance by the main computational unit is primarily defined by rotational speed and acceleration, but environmental measurements such as the system temperature can also lead to a recalculation or acceptance of the pattern based on the approach used for optimizing the engine performance metrics.

[0042] By using this approach, OPP operation can be achieved without using high-cost components, while still maintaining a very fast and accurate angle-to-pattern relationship.

[0043] With reference to Fig. In section 5, each of the three graphs represents the PWM signal as a function of the angle. This is the data stored in the lookup table. Each graph corresponds to one of the half-bridges 74.

[0044] After processing in the timing unit, these three graphs yield six control signals for the six transistors: the high-side and low-side transistors of a first half-bridge (PWM 4 and PWM 5), the high-side and low-side transistors of a second half-bridge (PWM 2 and PWM 3), and the high-side and low-side transistors of a third half-bridge (PWM 0 and PWM 1). These are based on the respective PWM signal, but a small amount of dead time is introduced.

[0045] The proposed method is not limited to a bridge structure containing only 6 power transistors, known as "B6" structures; the proposed method can be used for any inverter structure, such as a multi-stage inverter with other numbers of power transistors, for example, more than 6 power transistors. The number of hardware lines from the DSP(s) 48 to the timer must correspond to the independent number of power switches.

[0046] In the example of Fig. In section 4, three separate PWM output lines 120, 122, and 124 are used, along with three separate lookup tables 48. In an alternative example, a single PWM output line 120 is used to transmit multiple PWM signals. An example using this alternative is now described.

[0047] With reference to Fig. 7. A sampling time service request link 200 is provided in parallel to the PWM output line 120 between the DSP 48 and the timer unit 50. Additionally, a synchronization service request link 202 is provided from the ADC 42 back to the timer unit 50.

[0048] With reference to Fig. 8. The ADC 42 signals a service request (ADCSR) on the Sync Service Request Link 202 to indicate that a new digital signal has been acquired.

[0049] Shortly thereafter, the DSP evaluates the required outputs using lookup tables 48. The DSP sets the output on the PWM output line 120 to correspond to the output for the first half-bridge 01 and then triggers a service request on the DSPSR to signal that the timer unit should acquire the signal on the PWM output line 120. The PWM output line 120 is then set to the level for the second half-bridge B, and a second service request (DSPSR) is signaled on the sampling time service request link 200 to indicate that the timer unit 50 should acquire the signal on the PWM output line 120, which now corresponds to the PWM signal for the second half-bridge 23.This is then repeated once more, with the signal on the PWM output line 120 being set to the level for the third half-bridge C and a third service request (DSPSR) being sent on the sampling time service request link 200 to indicate that the timer should capture the third PWM value for half-bridge 45.

[0050] In the example of Fig. In the first cycle, the PWM value is high for the first half-bridge (01) and low for the second and third half-bridges (23 and 45).

[0051] The next cycle begins when ADC 42 detects a new digital signal and signals this via a new service request ADCSR on the sync service request link 202. Again, the three PWM levels are sent down to the single PWM output line 120 using the sync signal DSPSR on the sync service line 200 to indicate the signal timings for the three half-bridges 01, 23, and 45.

[0052] In the illustrated example, half-bridge 01 has a low value in this case, and half-bridges 23 and 45 have a high value.

[0053] These are sampled by sampling units 130, which correspond to each half-bridge, and then the dead-time and inversion units 132 generate the individual signals PWM0 and PWM1 for the first half-bridge, PWM2 and PWM3 for the second half-bridge and PWM4 and PWM5 for the third half-bridge.

[0054] By using the sync service request ADCSR from the ADC 42 to define the new transition period, and the service request DSPSR from the DSP 48 to signal to the timer unit that the current output value of the hardware line 120 is now valid for the corresponding output transmission of three PWM signals for the respective half-bridges 74, it is possible to use only one line 120.

[0055] Furthermore, it should be noted that although the service requests ADCSR and DSPSR are illustrated as running on dedicated hardware lines 200 and 202, it is possible to send such signals via existing buses or lines.

[0056] It should be noted that, although the embodiments of Fig. 4 to Fig. 7 described with reference to PWM signals, the method is generally applicable to the generation of pulse patterns, including optimized pulse patterns in certain examples.

[0057] In one example, a semiconductor device for generating a pulse pattern signal is provided, comprising: an analog-to-digital converter (ADC) for connection to a motor, which has an output to display the angle of the motor, a coprocessor comprising an angle input connected to the output of the ADC, an observer connected to the angle input for determining a motor angle, a coprocessor lookup table for generating a PWM pulse pattern signal as a direct function of the determined motor angle, and a pulse pattern signal output for outputting the pulse pattern signal, and a computing unit having an input connected to the coprocessor, wherein the computing unit is configured to select a lookup table from a variety of lookup tables based on specific engine conditions, such as acceleration and torque, and the selected

[0058] The lookup table is stored as the coprocessor lookup table in the coprocessor.

[0059] The example may also include: a memory that stores the multitude of lookup tables, and A Direct Memory Access Device (DMA) for loading a lookup table selected by the computing unit directly into the coprocessor as the coprocessor lookup table.

[0060] In this example, the observer can include a loop output that is connected to and configured with the computing unit: to further determine an engine speed; to output the specified motor speed and motor angle to the processing unit via the loop output; and to output the angle to the reference table; where the calculation unit can be set up to select the lookup table based on the specified motor angle and motor speed.

[0061] The lookup table can be set up to generate the pulse pattern signal at a first rate, and The processing unit can be configured to select the pulse pattern signal at a second rate, where the second rate is at least five times slower than the first rate.

[0062] The example may also include: a timing unit connected to the pulse pattern signal output of the coprocessor, wherein the timing unit comprises: an input connected to the pulse pattern signal output of the coprocessor, and a positive-side output and a negative-side output for outputting high-side and low-side pulse pattern signals to control a half-bridge.

[0063] The example can be used to control an inverter for a three-phase motor, wherein the inverter has three half-bridges, wherein the timer unit comprises three output pairs for controlling respective half-bridges, each output pair comprising a positive-side output and a negative-side output.

[0064] The semiconductor device may include: three parallel lookup tables, each lookup table serving to generate a respective PWM signal as a direct function of the generated motor angle, and Three parallel pulse pattern signal outputs for outputting the pulse pattern signal to a respective timer unit.

[0065] The semiconductor device may further include: a sampling time service request link from the coprocessor to the timing unit; the coprocessor can be configured to generate a multitude of pulse pattern signals, to output the multitude of pulse pattern signals sequentially on the pulse pattern signal output, and to output a signal on the sampling time service request link to the timer unit when a pulse pattern output signal is available on the pulse pattern signal output.

[0066] The timer unit may contain: a sampling unit having an input connected to the pulse pattern output of the coprocessor to sample the pulse pattern signal on the pulse pattern signal output when it is displayed on the sample time service request link, and a dead-time and inversion unit comprising a sampling input connected to the output of the sampling unit, further comprising the positive-side output unit and the negative-side output unit for each output pair, wherein the dead-time and inversion unit is configured to generate the high-side and low-side pulse pattern signals on the positive-side output unit and the negative-side output unit, respectively, from the signal on the sampling signal input.

[0067] The example can further include a sync service request link from the ADC to the timer unit to signal the presence of new digitized data being captured by the ADC.

[0068] In one example, a system is provided comprising a semiconductor device according to one of the preceding examples and at least one half-bridge, each containing a high-side transistor connected to a positive-side output of the semiconductor device and a low-side transistor connected to a negative-side output of the semiconductor device.

[0069] In another example, a method for generating a pulse pattern signal is provided, comprising: Digitizing a signal representing the angle of a motor, Determining a motor angle from the digitized signal using an observer;

[0070] Using a lookup table to generate a pulse pattern signal as a direct function of the generated motor angle and outputting the pulse pattern signal, and Selecting a lookup table in a calculation unit based on specific engine conditions, such as acceleration and torque, and saving the selected lookup table as the lookup table.

[0071] The procedure can further include generating a motor speed using the observer and outputting the motor speed to the computing unit.

[0072] The method can further include generating a high-side signal and a low-side signal to drive a half-bridge with the pulse pattern signal and driving the half-bridge with the high-side signal and the low-side signal.

[0073] The method can involve controlling an inverter for a three-phase motor, wherein the inverter has three half-bridges, and the method includes: Using three lookup tables to generate three respective pulse pattern signals, each as a direct function of the generated motor angle, and outputting the pulse pattern signals.

[0074] The method may further include outputting the multitude of pulse pattern signals sequentially on a pulse pattern signal output and outputting a signal on a sampling time service request link to a signal when a pulse output signal is available on the pulse pattern signal output.

[0075] The process may include: Generating the pulse pattern signal at a first rate, and Selecting the pulse pattern signal with a second rate, where the second rate is at least five times slower than the first rate.

[0076] Although specific embodiments / examples / aspects have been illustrated and described herein, it is obvious to the person skilled in the art that a multitude of alternative and / or equivalent implementations can replace the specific examples shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, it is intended that this invention is limited only by the claims and their equivalents.

[0077] It should be noted that the examples set forth in this document may be used alone or in combination with the other methods and systems disclosed herein. Furthermore, features described in connection with a device are also applicable to a corresponding method, and vice versa. Moreover, all aspects of the methods and devices described in this document may be combined in any way. In particular, the features of the claims may be combined with one another in any manner.

[0078] It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. A person skilled in the art will be able to implement various arrangements which, although not explicitly described or shown herein, embody the principles of the invention and are included in its meaning and scope. Furthermore, all examples and embodiments set forth in this document are expressly intended primarily for illustrative purposes only, to assist the reader in understanding the principles of the proposed methods and systems. Moreover, all statements herein that provide principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to include equivalents thereof.

Claims

[1] Semiconductor device for generating a pulse pattern signal, comprising: an analog-to-digital converter (ADC) for connection to a motor, which has an output to display the angle of the motor, a coprocessor comprising an angle input connected to the output of the ADC, an observer connected to the angle input for determining a motor angle, a coprocessor lookup table for generating a pulse pattern signal as a direct function of the determined motor angle, and a pulse pattern signal output for outputting the pulse pattern signal, and a computing unit having an input connected to the coprocessor, wherein the computing unit is configured to select a lookup table from a variety of lookup tables based on specific motor conditions, such as acceleration and torque, and to store the selected lookup table as the coprocessor lookup table in the coprocessor. [2] Semiconductor device according to claim 1, further comprising a memory that stores the multitude of lookup tables, and A Direct Memory Access Device (DMA) for loading a lookup table selected by the computing unit directly into the coprocessor as the coprocessor lookup table. [3] Semiconductor device according to claim 1 or 2, wherein the observer comprises a loop output connected to the computation unit and is configured as follows: to further determine an engine speed; to output the specified motor speed and motor angle to the processing unit via the loop output; and to output the angle to the reference table; the calculation unit is set up to select the lookup table based on the specified motor angle and motor speed. [4] Semiconductor device according to any one of the preceding claims, wherein the lookup table is set up to generate the pulse pattern signal at a first rate, and The computing unit is set up to select the pulse pattern signal at a second rate, where the second rate is at least five times slower than the first rate. [5] Semiconductor device according to any one of the preceding claims, further comprising: a timing unit connected to the pulse pattern signal output of the coprocessor, wherein the timing unit comprises: an input connected to the pulse pattern signal output of the coprocessor, and a positive-side output and a negative-side output for outputting high-side and low-side pulse pattern signals to control a half-bridge. [6] Semiconductor device according to claim 5 for controlling an inverter for a three-phase motor, wherein the inverter has three half-bridges, wherein the timer unit comprises three output pairs for controlling respective half-bridges, each output pair comprising a positive-side output and a negative-side output. [7] Semiconductor device according to claim 5, comprising: three parallel lookup tables, each lookup table serving to generate a respective PWM signal as a direct function of the generated motor angle, and Three parallel pulse pattern signal outputs for outputting the pulse pattern signal to a respective timer unit. [8] Semiconductor device according to claim 6 or 7, wherein the semiconductor device further comprises: a sampling time service request link from the coprocessor to the timing unit; wherein the coprocessor is configured to generate a multitude of pulse pattern signals, to output the multitude of pulse pattern signals sequentially on the pulse pattern signal output, and to output a signal on the sampling time service request link to the timer unit when a pulse pattern output signal is available on the pulse pattern signal output. [9] Semiconductor device according to claim 8, wherein the timer unit comprises: a sampling unit having an input connected to the pulse pattern output of the coprocessor to sample the pulse pattern signal on the pulse pattern signal output when it is displayed on the sample time service request link, and a dead-time and inversion unit comprising a sampling input connected to the output of the sampling unit, further comprising the positive-side output unit and the negative-side output unit for each output pair, wherein the dead-time and inversion unit is configured to generate the high-side and low-side pulse pattern signals on the positive-side output unit and the negative-side output unit, respectively, from the signal on the sampling signal input. [10] Semiconductor device according to claim 8 or 9, further comprising a sync service request link from the ADC to the timer unit for signaling the presence of new digitized data acquired by the ADC. [11] System, encompassing: a semiconductor device according to any one of the preceding claims; and at least one half-bridge comprising a high-side transistor connected to a positive-side output of the semiconductor device and a low-side transistor connected to a negative-side output of the semiconductor device. [12] Method for generating a pulse pattern signal, comprising: Digitizing a signal representing the angle of a motor, Determining a motor angle from the digitized signal using an observer; Using a lookup table to generate a pulse pattern signal as a direct function of the generated motor angle and outputting the pulse pattern signal, and Selecting a lookup table in a calculation unit based on specific engine conditions, such as acceleration and torque, and saving the selected lookup table as the lookup table. [13] Method according to claim 12, further comprising generating a motor speed using the observer and outputting the motor speed to the computing unit. [14] Method according to claim 12 or 13, further comprising: Generating a high-side signal and a low-side signal to control a half-bridge with the pulse pattern signal and controlling the half-bridge with the high-side signal and the low-side signal. [15] Method according to claim 12, 13 or 14 for controlling an inverter for a three-phase motor, wherein the inverter has three half-bridges, the method comprising: Using three lookup tables to generate three respective pulse pattern signals, each as a direct function of the generated motor angle, and outputting the pulse pattern signals. [16] Method according to claim 15, further comprising outputting the plurality of PWM signals sequentially on a pulse pattern signal output and outputting a signal on a sampling time service request link to a signal when a pulse pattern output signal is available on the pulse pattern signal output. [17] Method according to any one of claims 12 to 16, comprising Generating the pulse pattern signal at a first rate, and Selecting the pulse pattern signal with a second rate, where the second rate is at least five times slower than the first rate.

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