Method for determining the energy loss of at least one transistor

Abstract

The invention relates to a method (100) for determining the energy loss of at least one transistor (2), comprising: - Providing (101) a circuit model for modeling a switching behavior of the at least one transistor (2), - Modeling (102) the switching behavior of the at least one transistor (2) using the circuit model, wherein a gate resistance and a gate capacitance of the at least one transistor (2) is represented on the basis of a defined number of series-connected RC elements (3) in order to simulate a delay of voltage transients along individual gate fingers (4) of the at least one transistor (2) by means of the RC elements (3), - Determining (103) the loss energy based on a result of modeling (102). Furthermore, the invention relates to a computer program, a device and a storage medium for this purpose.

Description

[0001] The invention relates to a method for determining the energy loss of at least one transistor. Furthermore, the invention relates to a computer program, a device, and a storage medium for this purpose. State of the art

[0002] Transistors are crucial components in modern electronic circuits and systems. They are used in a wide variety of applications, including power electronics, digital circuits, and signal processing. However, the power efficiency of a MOSFET is significantly affected by the energy loss that occurs during its operation. This energy loss directly impacts its temperature and, consequently, the transistor's reliability and lifespan.

[0003] However, determining the energy loss, especially for fast-switching MOSFETs, is currently not possible with sufficient precision because the internal structures of the MOSFETs are not differentiated and accounted for in this calculation. Particularly in transistor types where the switching signal is distributed across the semiconductor chip by poorly conductive polysilicon, this can lead to distributed switching of the transistor. This means, for example, that the outer regions of the chip switch first, and only later do the inner regions of the semiconductor chip, connected via the gate fingers with higher resistance, switch. This distributed switching of the semiconductor causes additional losses that cannot be replicated by state-of-the-art simulations.Accurate knowledge of the switching losses of the transistor is advantageous in the design of power electronic circuits, as this allows the losses to be known early on and avoids design iterations due to incorrectly assumed losses. Disclosure of the invention

[0004] The invention relates to a method with the features of claim 1, a computer program with the features of claim 9, a device with the features of claim 10, and a A computer-readable storage medium with the features of claim 11. Further features and details of the invention will become apparent from the respective dependent claims, the description, and the drawings. Features and details described in connection with the method according to the invention naturally also apply in connection with the computer program, the device, and the computer-readable storage medium according to the invention, and vice versa, so that a reciprocal reference is always possible with regard to the disclosure of the invention.

[0005] The invention relates in particular to a method for determining the energy loss of at least one transistor, comprising the following steps: - Providing a circuit model for modeling the switching behavior of at least one transistor, in particular a metal-oxide-semiconductor field-effect transistor (MOSFET), - Modeling the switching behavior of the at least one transistor using the circuit model, wherein a gate resistance and a gate capacitance of the at least one transistor are represented on the basis of a defined number of RC elements connected in series, in order to simulate a delay of voltage transients along individual gate fingers, in particular all gate fingers, of the at least one transistor by means of the RC elements, - Determining the energy loss based on a modeling result.

[0006] The use of a circuit model that simulates gate resistance and capacitance using RC circuits allows for a realistic representation of the delay of voltage transients along individual gate fingers. This method thus offers the possibility of determining the energy loss efficiently and accurately.

[0007] The gate fingers are, in particular, fine, elongated extensions of a gate contact of the transistor, which are distributed over a surface of a semiconductor material and distribute the gate control signal in the area of ​​the semiconductor.

[0008] The at least one transistor is preferably a silicon or silicon carbide metal oxide semiconductor field-effect transistor. In general, the method can be used with any type of transistor (e.g., bipolar transistors, IGBTs, HEMTs, etc.). In particular, the method according to the invention can be advantageous for transistors in which the gate signal is distributed by a poorly conductive material such as polysilicon. Examples include silicon or silicon carbide MOSFETs and IGBTs. In these types of transistors, the gate fingers typically consist of polysilicon, which is poorly conductive. Therefore, the distributed switching effect can be particularly pronounced in these transistor types.

[0009] The circuit model is, for example, a SPICE-based simulation method or a state-space simulation. This has the advantage that the switching behavior of the transistor can be modeled accurately and efficiently. SPICE-based simulations, in particular, enable a detailed analysis of interactions between different components of the circuit, while state-space simulation methods can efficiently represent complex dynamics. This allows for the determination of energy loss with high accuracy.

[0010] The defined number of cascaded RC elements is, for example, greater than ten, preferably greater than 20, more preferably greater than 50, or also in a range between 20 and 50. The defined number of RC elements is preferably chosen to be so high that a further increase does not lead to a significant improvement in the accuracy of the predicted switching energy. This allows for a more detailed simulation of the transistor's switching behavior. This, in turn, enables a more accurate determination of the energy loss.

[0011] It is also advantageous if the at least one transistor is part of a power electronic switching cell comprising at least two transistors in a half-bridge configuration and at least one gate driver. The circuit model simulates the switching behavior of the at least two transistors, such that, during the modeling process, the gate resistance and gate capacitance of the at least two transistors are simulated based on the defined number of cascaded RC circuits. Furthermore, the power dissipation of the at least two transistors is determined. The at least one gate driver supplies voltage to a gate of one or more of the at least two transistors to control the current flow through the power electronic switching cell. This allows the power dissipation of multiple transistors within a half-bridge configuration to be simulated and determined.This allows for a more precise analysis of the switching losses in these circuits, which can be important in the development of efficient power electronics.

[0012] Furthermore, within the scope of the invention, it is conceivable that the method also includes: - Determining the efficiency and / or at least one thermal parameter of the at least one transistor.

[0013] The efficiency indirectly indicates the power loss. This is needed, for example, for designing the cooling path. At least one thermal parameter can be a junction temperature, a thermal resistance, or a case temperature. This information can be valuable for the thermal design of the power electronic product in which the transistor is used.

[0014] It is also conceivable that the procedure may further include: Determining the dimensions for a heat sink for at least one transistor based on the determined energy dissipation and preferably also based on the determined efficiency and / or the determined at least one thermal parameter. This has the advantage that the cooling of the transistor can be optimally designed. By calculating the energy dissipation, appropriate dimensions of the heat sink can be ensured. This minimizes the heating of the transistor and extends its service life.

[0015] It is also advantageous if the sum of individual capacitances of the defined number of RC elements connected in series corresponds to the gate capacitance of the transistor, and if the sum of individual resistances of the defined number of RC elements connected in series corresponds to a defined multiple, in particular a triple, of the gate resistance of the transistor.

[0016] Furthermore, the procedure may include the following step: - Providing measurement data, wherein the measurement data results from a measurement on the at least one transistor, where the modeling of the switching behavior and / or the determination of the energy loss is carried out based on the provided measurement data.

[0017] The invention also relates to a computer program, in particular a computer program product, comprising instructions which, when executed by a computer, cause the computer to execute the method according to the invention. Thus, the computer program according to the invention offers the same advantages as those described in detail with reference to a method according to the invention.

[0018] The invention also relates to a data processing device configured to execute the method according to the invention. The device can, for example, be a computer that executes the computer program according to the invention. The computer can have at least one processor for executing the computer program. Alternatively, a non-volatile data storage device can be provided in which the computer program is stored and from which the computer program can be read by the processor for execution.

[0019] The invention may also relate to a computer-readable storage medium which contains the computer program according to the invention and / or includes instructions which, when executed by a computer, cause the computer to execute the method according to the invention. The storage medium is, for example, designed as a data storage device such as a hard drive and / or non-volatile memory and / or a memory card. The storage medium can, for example, be integrated into the computer.

[0020] Furthermore, the method according to the invention can also be implemented as a computer-implemented method. Alternatively or additionally, at least one of the disclosed method steps can be computer-implemented and / or carried out automatically.

[0021] Further advantages, features, and details of the invention will become apparent from the following description, in which exemplary embodiments of the invention are described in detail with reference to the drawings. The features mentioned in the claims and in the description can each be essential to the invention individually or in any combination. The drawings show: Fig. 1 a schematic visualization of a method, a device, a storage medium and a computer program according to exemplary embodiments of the invention, Fig. 2 a schematic representation of a power electronic switching cell according to exemplary embodiments of the invention, Fig. 3 a schematic representation of a circuit model for simulating a power electronic switching cell according to embodiments of the invention, Fig. 4 a schematic representation of a transistor according to exemplary embodiments of the invention, Fig. 5 a schematic representation of a generic transistor model according to exemplary embodiments of the invention, Fig. 6 a schematic representation of a model of a capacitive current divider according to exemplary embodiments of the invention, Fig. 7 a schematic representation of a detailed model of a gate of a MOSFET, which takes into account the conduction mechanism of the gate fingers according to embodiments of the invention, Fig. 8 a further schematic representation of a detailed model of a gate of a MOSFET, which takes into account the conduction mechanism of the gate fingers according to embodiments of the invention.

[0022] In Fig. Figure 1 shows a method 100, a device 10, a storage medium 15 and a computer program 20 according to exemplary embodiments of the invention.

[0023] Fig. Figure 1 shows in particular an embodiment of a method 100 for determining the energy loss of at least one transistor 2. In a first step 101, a circuit model is provided for modeling the switching behavior of the at least one transistor 2. In a second step, the switching behavior of the at least one transistor 2 is modeled using the circuit model, wherein a gate resistance and a gate capacitance of the at least one transistor 2 are represented on the basis of a defined number of cascaded RC elements 3 in order to simulate a delay of voltage transients along individual gate fingers 4 of the at least one transistor 2 by means of the RC elements 3. In a third step 103, the energy loss is determined based on a result of the modeling 102.

[0024] Fig. Figure 2 shows a schematic representation of a power electronic switching cell 1 according to exemplary embodiments of the invention. This cell comprises two transistors 2, in particular metal-oxide-semiconductor field-effect transistors (MOSFETs), each of which in turn has several gate fingers 4. Furthermore, the power electronic switching cell 1 comprises a gate driver 5 and a heat sink 6.

[0025] The invention relates in particular to a method for the electrical simulation of the switching behavior of power transistors, especially MOSFETs, in power electronic switching cells. The method allows, for example, improved gate modeling of MOSFETs to more precisely replicate fast switching processes and to better predict the resulting losses.

[0026] An example model of a power electronic switching cell 1 with one upper and one lower MOSFET 2 is shown in Fig. 3 shown. Fig. Figure 4 shows a schematic representation of a transistor 2 according to exemplary embodiments of the invention and Fig. Figure 5 shows a schematic representation of a generic transistor model according to exemplary embodiments of the invention. The power switches, which in the context of the present invention are, for example, SiC MOSFETs 2, are represented in particular by means of voltage-controlled current sources and nonlinear capacitors. The currents and capacitances result, for example, as a function of the voltages u gs , and u ds , and the barrier temperature T j The inductances L x The switching cell can be assumed to be constant.

[0027] This switching cell can be modeled, for example, using a SPICE-based simulation method or in state space. The following section considers state-space simulation as an example. Within the framework of the method described in the exemplary implementations, a state-space model of the... Fig. 3 shown switching cell 1 in which the coupling of the energy-carrying quantities, e.g. u ds = u gs + u m or i e + i d * =i d , can be resolved by decoupling. In this way, the illustrated switching cell 1 can be modeled. The model of the MOSFET is given, for example, by the following functions: a nonlinear capacitance characteristic of the component (C) gs (U ds ), C ds (U ds ) & C m (U ds )), a channel model i ch = f(u gs ,u ds ,T j) (e.g. parameterized output characteristic), a body diode i d = f(u ds ,u gs ,T j ), an internal gate resistor R gint (this is preferably used for the simulation as R) gext R adds g = R gint + R gext )

[0028] To model the transistor behavior, the three capacitor voltages can be determined using any explicit numerical integration methods, provided a model for the capacitor currents is available, which will be derived below.

[0029] The following example describes a current divider based on Fig. 6 set up. Based on the circuit in Fig. 6. In particular, the following three equations can be derived: um+ugs=udsdumdt+dugsdt=dudsdtCm−1im+Cgs−1igs=Cds−1ids id−ich+ir=im+ids igs=im+ig

[0030] The first of equations #1 describes in particular the capacitive state coupling, which states that the voltage of the gate capacitance C gs and the voltage of the Miller capacitance C m always equal to the voltage of the output capacitance C ds must be. By differentiating and using the component equation, an equation for the three currents in the capacitors can be obtained. Together with the node equations #2 and #3, the three capacitor currents i c to be determined: im=Cds−1(id−i+ir)−Cgs−1igCm−1+Cgs−1+Cds−1 igs=im+ig ids=id−ich+ir−im

[0031] This approach can be used for all power transistors in more complex power electronic switching cells. Determining the capacitor currents allows, in particular, explicit numerical integration and thus the determination of a dynamic curve of the transistor's capacitance voltages, which in turn directly defines the channel and diode currents, as well as the capacitance values.

[0032] A model of the inductance currents can also be created using decoupling. However, this preferably requires setting up a DC system that includes all loops of switching cell 1 and all current couplings. To solve this, the current equations must preferably be derived and the respective inductance equations substituted.

[0033] These equations are below for the in Fig. 3 examples shown are listed: uds=uds*+uLd*+uLcs*+uds+uLd+uLcs+id*⋅Rc*+id⋅Rc ug*=uLg*+uLcs*+ugs*+ig*⋅Rg* ug=uLg+uLcs+ugs+ig⋅Rg ue=uLe+id⋅Rc+Re*ie+uds+uLd+uLcs ics=ig+id→uLcs⋅Lcs−1=uLg⋅Lg−1+uLd⋅Ld−1 ics*=ig*+id*→uLcs*⋅Lcs*−1=uLg*⋅Lg*−1+uLd*⋅Ld*−1 id=id*+ie→uLd⋅Ld−1=uLd*⋅Ld*−1+uLe⋅Le−1

[0034] A matrix equation can be determined to solve this system of equations, which acts as a voltage divider to express the inductance voltages u. Ld , u Ld* , u Lg , u Lg* , u Lcs , u Lcs* and u Le as a function of the gate voltage excitations u g , u g* as well as the intermediate circuit voltage u dc and the load voltage u e determined. The transistor models for the upper and lower transistors, or MOSFET 2, and the inductance current model together form, in particular, a state-space model of the in Fig. 3 shown switching cell 1.

[0035] The method outlined above specifically models the gate of MOSFET 2, as shown in Fig. 5 shown, through the internal gate resistor R gint , which is determined, for example, by small-signal excitation at a frequency around 1 MHz, and the capacitance of gate C gs , which are called C iss = C gs + C m also by small-signal excitation at a frequency around 1 MHz and subsequent subtraction by C m can be determined.

[0036] This simplified model of the gate, however, is particularly incapable of accurately predicting fast switching operations. One reason for this is, for example, that a simple RC circuit does not correctly represent the delay of voltage transients along a gate finger 4. A detailed model of a gate according to exemplary embodiments of the invention is described in Fig. Figure 7 shows that it uses many cascaded RC circuits 3 to represent the gate fingers 4. For simplicity, the Miller capacitances Cm,x, which are also assumed to be distributed, are not shown in this figure (but are shown in Figure 7). Fig. 8).

[0037] In order for the model, i.e., the circuit model, to replicate an experimentally determined curve of an impedance or resistance, the capacitances C must be x The sum of the RC elements 3 preferably corresponds to the gate capacitance C gs correspond to the sum of the gate resistances R. x must preferably correspond to a multiple, in particular a triple, of a gate resistance determined at 6 MHz.

[0038] This gate resistance becomes particularly noticeable and detrimental in the described circuit model, especially in the frequency range below 10 MHz. It follows, in particular, that the simple use of a gate model encompassing an internal gate resistance R is not feasible. ginttogether with the gate capacitance C gs is unable to correctly represent the dynamics of the gate with the gate fingers 4.

[0039] The invention, according to exemplary embodiments, describes in particular a method for modeling or simulating the gate behavior, which models the gate via RC elements 3 of a defined number N. The individual capacitances of the chain conductor are preferably determined by means of C x = C gs / N and the resistors R x as R gint *a / N is set. The value R gintThe gate impedance can be determined according to state-of-the-art methods, e.g., by small-signal identification at 1 MHz. The factor a can be, for example, three, but is preferably always greater than one. The defined number of RC elements 3 is preferably chosen to be so high that a further increase in N no longer leads to a change in the gate impedance. For this purpose, in the case of SiC MOSFETs 2, for example, N = 20-50 RC elements 3 are required.

[0040] A possible integration of this gate model into switching cell 1 is described below by way of example. The exemplary integrated gate model is in Fig. Figure 8 is shown as an example with three RC elements 3. The small number N = 3 was chosen primarily for the sake of clarity.

[0041] The in Fig.Model 8 shown can be represented in the state-space model. The state equations of MOSFET 2 can be determined directly from the equations of the simple gate model and are calculated below as an example. Based on the gate voltages u gs1 , u gs2 and u gs3 and the current in the gate inductance i g The effective currents flowing into the gate nodes can be calculated: ig1Σ=ig−(ugs1−ugs2) / Rx ig2Σ=(ugs1−ugs2) / Rx−(ugs2−ugs3) / Rx ig3Σ=(ugs2−ugs3) / Rx

[0042] Here, R x in particular the partial resistances and C x the partial capacities of the RC elements 3.

[0043] Based on the determined currents, the sum of the channel currents i ch ∑ and the sum of the diode currents i dThe currents of the Miller capacitances can be determined analogously to the simple transistor model described, using the ∑ and the capacitances of MOSFET 2: im1=(Cds−1*(id−ichΣ+irΣ)−Cgs−1*ig1Σ) / (Cm−1+Cgs−1+Cds−1) im2=(Cds−1*(id−ichΣ+irΣ)−Cgs−1*ig2Σ) / (Cm−1+Cgs−1+Cds−1) im3=(Cds−1*(id−ichΣ+irΣ)−Cgs−1*ig3Σ) / (Cm−1+Cgs−1+Cds−1)

[0044] From this, the capacitance currents of the other transistor capacitances (i) can be directly derived: igs=im+ig ids=(id−ichΣ+irΣ)−im

[0045] By numerically integrating the currents of all transistor capacitances, the dynamic behavior of the voltages of MOSFET 2 can be calculated, and based on this, the energy loss can be determined.

[0046] The preceding explanation of the embodiments describes the present invention solely by way of examples. Naturally, individual features of the embodiments can be freely combined with one another, provided this is technically feasible, without departing from the scope of the present invention.

Claims

[1] Method (100) for determining the energy loss of at least one transistor (2), comprising: - Providing (101) a circuit model for modeling a switching behavior of the at least one transistor (2), - Modeling (102) the switching behavior of the at least one transistor (2) using the circuit model, wherein a gate resistance and a gate capacitance of the at least one transistor (2) are represented on the basis of a defined number of series-connected RC elements (3) in order to simulate a delay of voltage transients along individual gate fingers (4) of the at least one transistor (2) by means of the RC elements (3), - Determining (103) the loss energy based on a result of modeling (102). [2] Method (100) according to claim 1, characterized by, that the at least one transistor (2) is part of a power electronic switching cell (1) which has at least two transistors (2) in a half-bridge circuit and at least one gate driver (5), wherein the circuit model models the switching behavior of the at least two transistors (2) (102), such that in the context of the modeling (102) the gate resistance and the gate capacitance of the at least two transistors (2) are each replicated on the basis of the defined number of RC elements (3) connected in series and in the context of the determination (103) the energy loss of the at least two transistors (2) is determined. [3] Method (100) according to any one of the preceding claims, characterized by , that the procedure (100) further includes: - Determining an efficiency and / or at least one thermal parameter of the at least one transistor (2). [4] Method (100) according to any one of the preceding claims, characterized by, that the procedure (100) further includes: - Determining a dimension for a heat sink (6) for the at least one transistor (2) based on the determined energy loss. [5] Method (100) according to any one of the preceding claims, characterized by , that a sum of individual capacitances of the defined number of RC elements connected in series (3) corresponds to the gate capacitance of the transistor (2) and a sum of individual resistances of the defined number of RC elements connected in series (3) corresponds to a defined multiple, in particular a triple, of a gate resistance of the transistor (2). [6] Method (100) according to any one of the preceding claims, characterized by that the circuit model is a SPICE-based simulation method or a state-space simulation. [7] Method (100) according to any one of the preceding claims, characterized bythat the transistor (2) is a silicon or silicon carbide metal oxide semiconductor field-effect transistor and / or the defined number of series-connected RC elements (3) is greater than ten, preferably greater than 20, more preferably greater than 50. [8] Method (100) according to any one of the preceding claims, characterized by , that the procedure (100) further comprises the following step: - Providing measurement data, wherein the measurement data result from a measurement on the at least one transistor (2), wherein the modeling (102) of the switching behavior and / or the determination (103) of the energy loss is carried out on the basis of the provided measurement data. [9] Computer program (20) comprising instructions which, when the computer program (20) is executed by a computer (10), cause it to execute the method (100) according to any of the preceding claims. [10] Device (10) for data processing which is configured to carry out the method (100) according to any one of claims 1 to 8. [11] Computer-readable storage medium (15) comprising instructions which, when executed by a computer (10), cause it to perform the steps of the method (100) according to any one of claims 1 to 8.

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