Method for determining the extraction sequence of chips from a wafer

Abstract

The invention relates to a method (100) for determining a removal sequence of chips (2) from a wafer (1), comprising the following steps: - Providing (101) position data regarding the individual chips (2) of the wafer (1), wherein the position data specify an arrangement of the chips (2) on the wafer (1), - Determine (102) at least one electrical parameter of the individual chips (2) of the wafer (1), - Determining (103) the sampling sequence based on a correlation between the provided position data and the determined at least one electrical parameter. Furthermore, the invention relates to a computer program, a device and a storage medium for this purpose.

Description

[0001] The invention relates to a method for determining the extraction sequence of chips from a wafer. Furthermore, the invention relates to a computer program, a device, and a storage medium for this purpose. State of the art

[0002] In power electronics, there is a need for parallel chips in modules, especially in power modules, as a smaller chip size is generally advantageous. Manufacturers strive to produce smaller chips because the manufacturing process allows for higher yields. However, when chips are connected in parallel within a power module, the problem of uneven current distribution and unbalanced power dissipation can arise between the parallel-connected chips, as they are not identical.

[0003] Manufacturing processes, in particular, lead to tolerances in the electrical parameters of the chips, which limit the performance of the power modules. Examples of these electrical parameters include drain-source on-resistance, gate-drain charge, gate-source charge, and threshold voltage. To ensure that the power modules meet performance requirements, modules that violate certain limits must be rejected during testing. High chip variability on modules can significantly reduce the yield, which is why the order in which chips are removed from the wafer is crucial. Disclosure of the invention

[0004] The invention relates to a method with the features of claim 1, a computer program with the features of claim 9, a device with the features of claim 10, and a computer-readable storage medium with the features of claim 11. Further features and details of the invention will become apparent from the respective dependent claims, the description, and the drawings. Features and details described in connection with the method according to the invention naturally also apply in connection with the computer program, the device, and the computer-readable storage medium according to the invention, and vice versa, so that mutual reference is always possible with regard to the disclosure of the invention.

[0005] The invention relates in particular to a method for determining a picking sequence of chips from a wafer, comprising: - Providing positional data regarding the individual chips of the wafer, wherein the positional data specifies an arrangement of the chips on the wafer, i.e., in other words, the positional data indicates, for example by coordinates in a coordinate system, where each individual chip is located on the wafer. - Determining at least one electrical parameter of the individual chips of the wafer, in particular within the framework of a wafer test, wherein the wafer test can also be referred to and understood as a wafer-level test (WLT) procedure, wherein the wafer test is in particular a testing process in semiconductor manufacturing in which the individual chips are tested directly on the wafer before the wafer is cut into individual chips and further processed, wherein in particular a functionality, electrical properties and / or a performance of each chip is tested in order to identify defects or quality deficiencies at an early stage, - Determining the sampling sequence based on a correlation between the provided position data and the determined at least one electrical parameter.

[0006] The method according to the invention advantageously increases the yield of functional modules by improving the chip removal sequence. The removal sequence specifies, in particular, the order in which the individual chips are removed from the wafer.

[0007] Determining the sampling sequence can be carried out using a machine learning model, where the machine learning model can be a trained machine learning model that has learned the correlation in a training based on reference data.

[0008] Training the machine learning model can, for example, include the following steps: - Providing reference data, wherein the reference data includes an assignment of respective position data of individual chips on the wafer and at least one electrical parameter of the individual chips to a performance of a respective module in an operation of the respective module, wherein the respective module comprises a defined number of chips, - Determining the correlation based on the reference data between the respective position data of the individual chips on the wafer and at least one electrical parameter of the individual chips with respect to The performance of the respective module during its operation. The reference data can therefore be structured such that it maps the resulting performance to the respective positions of the individual chips and the at least one electrical parameter of each chip. For example, the reference data can also include ground truth data representing an optimal extraction sequence for a given combination of the respective positions of the individual chips and the at least one electrical parameter of each chip. In this way, the machine learning model can learn to determine an optimal extraction sequence during training, minimizing any error in the machine learning model's output (i.e., an extraction sequence proposed by the machine learning model) relative to the optimal extraction sequence, e.g., the ground truth data.

[0009] Another possibility is that the procedure may also include: - Initiating the insertion of the defined number of extracted chips, for example two or four, into a respective module, in particular a power module.

[0010] In this way, the chip removal sequence, optimized by the machine learning model, can be directly integrated into the module insertion process. This enables, in particular, efficient and automated production of modules, especially power modules, with increased yield.

[0011] Furthermore, the invention may provide that the method also includes: - Determining the resulting power output of the respective modules or initiating a determination of the resulting power output of the respective modules, for example by initiating a corresponding electrical test, - Storing the determined resulting power in a context with at least one electrical parameter of the individual chips of the wafer, for example in a database, - Adjusting the correlation or machine learning model based on the stored determined performance, which allows the machine learning model to be advantageously continuously optimized.

[0012] In this way, the machine learning model can become increasingly precise over time through continuous adaptation. The stored data can also be used to identify new correlations between at least one electrical parameter and the resulting performance of the respective modules, thereby further optimizing the machine learning model.

[0013] It is also possible that the procedure may include the following: - Predicting a temperature difference between chips used in the respective module during operation of the module in order to characterize the respective module and / or to test the functionality of the respective module.

[0014] The method according to the invention particularly enables a more precise estimation of the module performance and a more precise identification of potential temperature fluctuations within a module. This allows, for example, better characterization of the modules and improves the reliability of testing their functionality.

[0015] Advantageously, the invention provides that the chips are MOSFETs (short for "metal oxide semiconductor field-effect transistor"), in particular silicon carbide (short: "SiC") MOSFETs, and that at least one parameter is selected from a drain-source-on resistance, a gate-drain charge, a gate-source charge, and / or a threshold voltage of the MOSFETs. This allows the extraction sequence to be optimized by taking into account specific electrical parameters of the MOSFETs. By considering these parameters, precise correlations can be established between the chip position, these electrical parameters, and the resulting performance of the module. Furthermore, the use of silicon carbide MOSFETs enables high power efficiency and resistance to high temperatures, which can increase the service life of the modules.

[0016] It may optionally be possible for the procedure to further include: - Providing data regarding the process homogeneity of a wafer manufacturing process, The determination of the removal sequence is further carried out based on the provided data regarding process homogeneity. The inclusion of the process homogeneity data enables the machine learning model, for example, to consider the influence of fluctuations in the manufacturing process on at least one electrical parameter and / or the performance of the modules, thus providing an optimized removal sequence.

[0017] It is also possible that the procedure may include the following: - Define at least one constraint, for example for the machine learning model, where the at least one constraint specifies at least a time limit for a removal process and / or a maximum temperature in an operation for the chips, The determination of the sampling sequence is further carried out based on at least one defined constraint. Thus, the procedure can additionally take at least one constraint into account to increase the efficiency and safety of the sampling process. By integrating time constraints and / or temperature restrictions, more realistic scenarios can be considered, and the sampling sequence can be determined more precisely, thereby also being aligned with the process conditions of actual production.

[0018] The invention also relates to a computer program, in particular a computer program product, comprising instructions which, when executed by a computer, cause the computer to execute the method according to the invention. Thus, the computer program according to the invention offers the same advantages as those described in detail with reference to a method according to the invention.

[0019] The invention also relates to a data processing device configured to execute the method according to the invention. The device can, for example, be a computer that executes the computer program according to the invention. The computer can have at least one processor for executing the computer program. Alternatively, a non-volatile data storage device can be provided in which the computer program is stored and from which the computer program can be read by the processor for execution.

[0020] The invention may also relate to a computer-readable storage medium which contains the computer program according to the invention and / or includes instructions which, when executed by a computer, cause the computer to execute the method according to the invention. The storage medium is, for example, designed as a data storage device such as a hard drive and / or non-volatile memory and / or a memory card. The storage medium can, for example, be integrated into the computer.

[0021] Furthermore, the method according to the invention can also be implemented as a computer-implemented method. Alternatively or additionally, at least one of the disclosed method steps can be computer-implemented and / or carried out automatically.

[0022] Further advantages, features, and details of the invention will become apparent from the following description, in which exemplary embodiments of the invention are described in detail with reference to the drawings. The features mentioned in the claims and in the description can each be essential to the invention individually or in any combination. The drawings show: Fig. 1 a schematic visualization of a method, a machine learning model, a device, a storage medium and a computer program according to exemplary embodiments of the invention, Fig. 2 a schematic representation of a module according to exemplary embodiments of the invention, Fig. 3 a schematic representation of a wafer according to exemplary embodiments of the invention, Fig. 4 a schematic representation of a method according to exemplary embodiments of the invention.

[0023] In Fig. Figure 1 shows a method 100, a machine learning model 50, a device 10, a storage medium 15 and a computer program 20 according to exemplary embodiments of the invention.

[0024] Fig. Figure 1 shows in particular an embodiment of a method 100 for determining a removal sequence of chips 2 from a wafer 1. In a first step 101, position data for the individual chips 2 of the wafer 1 are provided, wherein the position data specify an arrangement of the chips 2 on the wafer 1. In a second step 102, at least one electrical parameter of the individual chips 2 of the wafer 1 is determined. In a third step 103, the removal sequence is determined based on a correlation between the provided position data and the determined at least one electrical parameter.

[0025] Fig. Figure 2 shows a schematic representation of a module 3 according to exemplary embodiments of the invention, which comprises several chips 2. The chips 2 are, for example, MOSFETs, in particular SiC MOSFETs.

[0026] Fig. Figure 3 shows a schematic representation of a wafer 1 according to embodiments of the invention, which comprises a plurality of chips 2.

[0027] Fig. Figure 4 shows a schematic representation of a method 200 according to exemplary embodiments of the invention. The at least one electrical parameter within the scope of the wafer test 201, at least one technical model 202, and at least one constraint 203 are inputs for an optimization algorithm 204, for example, a machine learning model 50. Based on the inputs, the optimization algorithm 204 determines a map for the wafer 1 that represents the removal sequence.

[0028] Within the scope of the present invention, in particular yield losses in the context of a manufacturing process of modules 3, especially power modules, are to be minimized.

[0029] Based on wafer-level test data, so-called wafer tests, and available data on process homogeneity, a correlation of various electrical parameters of individual chips 2 with respect to the position of the individual chips 2 on the wafer 1, and specifications and models for the removal process, such as time constraints for movement and other limitations, a removal sequence for each wafer 1 can be calculated and stored, for example, in a corresponding file. Machine learning can be used, for example, to continuously optimize the removal sequence, thus minimizing the yield at the module level.

[0030] In simplified terms, the machine learning model 50 models, in particular, which combination of the electrical parameters of the individual chips 2 at the respective positions is most likely to lead to functioning modules 3 in a specific extraction sequence. For this purpose, for example, a database can be created and used that maps certain values ​​of the electrical parameters to a resulting performance of modules 3.

[0031] The method described in the exemplary embodiments can provide, for example, the following advantages: It allows for flexibility in adapting the machine learning model 50 due to changes in process, design, or requirements. Furthermore, it enables better prediction of key performance indicators (KPIs) of the manufacturing process, such as the temperature of the chips 2 during operation. Continuous improvement is also possible using the machine learning model 50, for example, through online adjustment of a wafer map, where the wafer map can represent, for instance, individual chips 2, or the presence or absence of individual chips 2, in a wafer 1. When switching from wafer to wafer, the wafer map can thus be advantageously adjusted based on the remaining chips in the last wafer.

[0032] The preceding explanation of the embodiments describes the present invention solely by way of examples. Naturally, individual features of the embodiments can be freely combined with one another, provided this is technically feasible, without departing from the scope of the present invention.

Claims

[1] Method (100) for determining a removal sequence of chips (2) from a wafer (1), comprising the following steps: - Providing (101) position data regarding the individual chips (2) of the wafer (1), wherein the position data specify an arrangement of the chips (2) on the wafer (1), - Determine (102) at least one electrical parameter of the individual chips (2) of the wafer (1), - Determining (103) the sampling sequence based on a correlation between the provided position data and the determined at least one electrical parameter. [2] Method (100) according to claim 1, characterized by , that the determination (103) of the picking sequence is carried out using a machine learning model (50), wherein training of the machine learning model (50) comprises the following steps: - Providing reference data, wherein the reference data comprise an assignment of respective position data of individual chips (2) on the wafer (1) and at least one electrical parameter of the individual chips (2) to a power of a respective module (3) in an operation of the respective module (3), wherein the respective module (3) comprises a defined number of chips (2), - Determining the correlation based on the reference data between the respective position data of the individual chips (2) on the wafer (1) and the at least one electrical parameter of the individual chips (2) with respect to the performance of the respective module (3) in the operation of the respective module (3). [3] Method (100) according to claim 1 or 2, characterized by , that the procedure (100) further includes: - Initiating the insertion of the defined number of extracted chips (2) into a respective module (3), in particular a power module. [4] Method (100) according to claim 2, characterized by , that the procedure (100) further includes: - Determining the resulting output of each module (3), - Storing the determined resulting power in a relationship with at least one electrical parameter of the individual chips (2) of the wafer (1), - Adjusting the correlation based on the stored, determined performance. [5] Method (100) according to any one of the preceding claims, characterized by , that the procedure (100) further includes: - Predicting a temperature difference between installed chips (2) in the respective module (3) during operation of the module (3) in order to characterize the respective module (3) and / or to test a functionality of the respective module (3). [6] Method (100) according to any one of the preceding claims, characterized by, that the chips (2) are MOSFETs, in particular silicon carbide MOSFETs, and that at least one parameter is selected from a drain-source-on resistance, a gate-drain charge, a gate-source charge and / or a threshold voltage of the MOSFETs. [7] Method (100) according to any one of the preceding claims, characterized by , that the procedure (100) further includes: - Providing data regarding process homogeneity of a wafer manufacturing process (1), where the determination (103) of the sampling sequence is further carried out on the basis of the data provided regarding process homogeneity. [8] Method (100) according to any one of the preceding claims, characterized by , that the procedure (100) further includes: - Define at least one constraint, wherein the at least one constraint specifies at least a time requirement for a withdrawal process and / or a maximum temperature in an operation for the chips (2), where the determination (103) of the sampling sequence is further carried out on the basis of the defined at least one restriction. [9] Computer program (20) comprising instructions which, when the computer program (20) is executed by a computer (10), cause it to execute the method (100) according to any of the preceding claims. [10] Device (10) for data processing which is configured to carry out the method (100) according to any one of claims 1 to 8. [11] Computer-readable storage medium (15) comprising instructions which, when executed by a computer (10), cause it to perform the steps of the method (100) according to any one of claims 1 to 8.

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