Semiconductor package, power electronics system and method for coupling a semiconductor package to a heat sink

Abstract

A semiconductor package comprises: a molded body comprising a first side and an opposite second side, at least one semiconductor chip encapsulated by the molded body, and a chip carrier comprising a first side and an opposite second side, wherein the at least one semiconductor chip is disposed over the first side of the chip carrier, and wherein the second side of the chip carrier is at least partially exposed from the second side of the molded body, thereby forming at least one exposed portion of the chip carrier, wherein the first side of the molded body comprises a first portion and a second portion, wherein the first portion protrudes from the second portion in a vertical direction, thereby forming a planar surface, wherein the vertical direction is perpendicular to the first side, wherein the second portion extends entirely along at least one edge of the first side,and wherein a center point of the first portion is in vertical alignment with a center point of the exposed portion.,

Description

TECHNICAL FIELD

[0001] The present disclosure generally relates to a semiconductor package, in particular to a semiconductor package wherein a first portion of a first side of a molded body protrudes vertically from a second portion, as well as to a power electronics system comprising a semiconductor package and a heat sink, and to a method for coupling a semiconductor package to a heat sink. BACKGROUND

[0002] A semiconductor package may comprise one or more semiconductor dies and a molded body configured to protect the one or more semiconductor dies from environmental influences, as described, for example, in JP 2011 - 187 819 A. Such a semiconductor package may be configured to be coupled to a heat sink configured to dissipate heat generated by the one or more semiconductor dies during operation. Such coupling may be achieved, for example, by sintering, soldering, clamping, or screwing the semiconductor package to the heat sink, as described, for example, in JP 2014 - 120 727 A for screwing. However, manufacturing tolerances may cause the semiconductor package to be tilted with respect to the heat sink during the coupling process, which could lead to unsatisfactory thermal and / or mechanical properties of the coupling.Furthermore, pressure exerted on the semiconductor package during the coupling process can cause damage if too much pressure is applied to certain parts of the semiconductor package, for example, to an edge region of the semiconductor package, as discussed in US 2023 / 0 170 287 A1. Improved semiconductor packages, improved power electronics systems including a semiconductor package, and improved methods for coupling a semiconductor package to a heat sink can help solve these and other problems. SUMMARY

[0003] Various aspects relate to a semiconductor package comprising: a molded body comprising a first side and an opposite second side, at least one semiconductor chip encapsulated by the molded body, and a chip carrier comprising a first side and an opposite second side, wherein the at least one semiconductor chip is disposed over the first side of the chip carrier, and wherein the second side of the chip carrier is at least partially exposed from the second side of the molded body, thereby forming at least one exposed portion of the chip carrier, wherein the first side of the molded body comprises a first portion and a second portion, wherein the first portion protrudes from the second portion in a vertical direction, thereby forming a planar surface, wherein the vertical direction is perpendicular to the first side,wherein the second portion extends entirely along at least one edge of the first side, and wherein a center point of the first portion is in vertical alignment with a center point of the exposed portion, wherein the first portion is disposed within a perimeter of the at least one exposed portion of the chip carrier, and wherein at least 50% of the second portion is disposed outside the perimeter.

[0004] Various aspects relate to a power electronics system comprising: a semiconductor package as described above and a heat sink, wherein the semiconductor package is mechanically coupled to the heat sink such that the second side of the semiconductor package faces the heat sink.

[0005] Various aspects relate to a method for mechanically coupling a semiconductor package to a heat sink, the method comprising: providing a semiconductor package comprising: a molded body comprising a first side and an opposite second side, at least one semiconductor chip encapsulated by the molded body, and a chip carrier comprising a first side and an opposite second side, wherein the at least one semiconductor chip is disposed over the first side of the chip carrier, and wherein the second side of the chip carrier is at least partially exposed from the second side of the molded body, thereby forming at least one exposed portion of the chip carrier, wherein the first side of the molded body comprises a first portion and a second portion, wherein the first portion protrudes from the second portion in a vertical direction, thereby forming a planar surface,wherein the vertical direction is perpendicular to the first side, wherein the second portion extends entirely along at least one edge of the first side, and wherein a center point of the first portion is in vertical alignment with a center point of the exposed portion; disposing the semiconductor package over a heat sink such that the second side of the semiconductor package faces the heat sink; and applying pressure to the first portion, but not to the second portion of the first side of the molded body, to mechanically and thermally couple the semiconductor package to the heat sink.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals refer to similar or identical elements. The elements of the drawings are not necessarily to scale relative to one another. The features of the various illustrated examples may be combined, provided they are not mutually exclusive. Fig. 1 illustrates a sectional view of a semiconductor package, wherein a first side of a molded body includes a first portion that protrudes vertically from a second portion of the first side. Fig. 2 illustrates a sectional view of the semiconductor package of Fig. 1, which is coupled to a heat sink using a press. The press exerts pressure on the first section of the first side of the molded body, but not on the second section. Fig. 3A to Fig. 3C show another exemplary semiconductor package including a molded body having the first portion and the second portion. Fig. 4A to Fig. 4D show a power electronics system comprising a semiconductor package connected via terminals ( Fig. 4A and Fig. 4B), via screws ( Fig. 4C) and a sintered layer ( Fig. 4D) is coupled to a substrate. Fig. 5 is a flow diagram of an exemplary method for coupling a semiconductor package to a heat sink. Fig. 6 shows another exemplary semiconductor package including a molded body having a first portion including separate islands. Fig. Figure 7 illustrates a sectional view of the semiconductor package of Fig. 6, which is coupled to a heat sink using a press. The press exerts different pressures on the islands of the first section. DETAILED DESCRIPTION

[0008] In the following detailed description, well-known structures and elements are shown in schematic form to facilitate describing one or more aspects of the disclosure. In this regard, directional terminology such as "top," "bottom," "left," "right," "upper," "lower," etc., is used with reference to the orientation of the described figure(s). Because components of the disclosure can be positioned in a number of different orientations, the directional terminology is used for illustrative purposes only. It is understood that other examples may be used and structural or logical changes may be made.

[0009] Furthermore, although a particular feature or aspect of an example may be disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for a given or particular application, unless expressly stated otherwise or technically limited. Furthermore, to the extent that the terms "comprising," "having," "with," or other variations thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising." The terms "coupled" and "connected" may be used together with derivatives thereof.It is understood that these terms can be used to indicate that two elements cooperate or interact, whether in direct physical or electrical contact or not; intervening elements or layers can be provided between the "bonded," "attached," or "connected" elements. However, it is also possible for the "bonded," "attached," or "connected" elements to be in direct contact with each other. Furthermore, the term "exemplary" is intended merely as an example and not as the best or optimal.

[0010] In several examples, layers or layer stacks are applied to one another, or materials are applied or deposited onto layers. It is understood that any such terms such as "applied" or "deposited" are intended to cover literally all types and techniques of applying layers to one another. In particular, they are intended to cover techniques in which layers are applied all at once, such as lamination techniques, as well as techniques in which layers are deposited in a sequential manner, such as sputtering, plating, molding, CVD, etc.

[0011] An efficient semiconductor package, an efficient power electronics system, and an efficient method for coupling a semiconductor package to a substrate such as a heat sink can, for example, reduce material consumption, ohmic losses, chemical waste, etc., and can thus enable energy and / or resource savings. Improved semiconductor packages, improved power electronics systems, and improved methods for coupling a semiconductor package to a substrate such as a heat sink, as specified in this description, can thus at least indirectly contribute to green technology solutions, i.e., climate-friendly solutions that provide a reduction in energy and / or resource use.

[0012] Fig. 1 shows a cross-sectional view of a semiconductor package 100 comprising a molded body 110, at least one semiconductor chip 120, and a chip carrier 130. The semiconductor package 100 may, for example, be a power semiconductor package configured to operate with a high voltage, e.g., a voltage of 100 V or more, or 200 V or more, or 500 V or more, or 1 kV or more, and / or a high electrical current, e.g., a current of 1 A or more, or 10 A or more, or 100 A or more. The semiconductor package 100 may be configured to be used in any suitable application, e.g., automotive applications, industrial applications, household applications, etc.

[0013] The semiconductor package 100 may include any suitable electrical circuit, or the semiconductor package 100 may be configured to be part of any suitable electrical circuit. For example, the semiconductor package 100 may include a half-bridge circuit, a full-bridge circuit, a converter circuit, an inverter circuit, etc.

[0014] The molded body 110 includes a first side 111 and an opposite second side 112. The molded body 110 may further include lateral sides 113 connecting the first and second sides 111, 112. The molded body 110 may have any suitable shape and dimensions. For example, the molded body 110 may have a substantially rectangular or square shape when viewed from above the first side 111. According to one example, the first and second sides 111, 112 may have identical or substantially identical shapes and / or sizes. The first and second sides 111, 112 may be those sides of the molded body 110 that have the largest surface area of ​​any of the sides of the molded body 110.

[0015] The molded body 110 may be manufactured using any suitable manufacturing process, for example, compression molding, injection molding, or transfer molding. The molded body 110 may comprise or consist of any suitable molding material. According to one example, the molded body 110 may also comprise inorganic filler particles configured to reduce the thermal resistance of the molded body 110.

[0016] The at least one semiconductor chip 120 is encapsulated by the molded body 110. The molded body 110 can be configured to protect the at least one semiconductor chip 120 from environmental influences. The at least one semiconductor chip 120 can be any suitable type of semiconductor chip, for example, a power semiconductor chip. The at least one semiconductor chip 120 can, for example, comprise a vertical transistor structure or a lateral transistor structure.

[0017] In the Fig. 1, the semiconductor package 100 comprises two semiconductor dies 120. However, the semiconductor package 100 may comprise any suitable number of semiconductor dies 120, for example, one, two, four, six, etc. Furthermore, the more than one semiconductor die 120 may all be the same type of chip or different types of chips. It should be noted that for the sake of simplicity, Fig. 1 no internal electrical connections of the semiconductor package 100 are shown.

[0018] The chip carrier 130 includes a first side 131 and an opposite second side 132. The at least one semiconductor die 120 is arranged over the first side 131 of the chip carrier 130. Furthermore, the second side 132 of the chip carrier 130 is at least partially exposed from the second side 112 of the molded body 110. In other words, the chip carrier 130 may include at least one exposed portion that is not covered by the molded body 110.

[0019] The at least one exposed portion of the chip carrier 130 may be configured to be mechanically and thermally connected to a heat sink and / or a base plate. Such a connection may include, for example, sintering, soldering, screwing, or clamping the semiconductor package 100 to the heat sink and / or to the base plate.

[0020] In the Fig. In the example shown in Figure 1, the chip carrier 130 includes a single exposed portion. However, the chip carrier 130 may include any suitable number of exposed portions, for example, one, two, three, four, etc. The exposed portions may be arranged, for example, in a line, in a matrix, etc., on the second side 112 of the mold body 110.

[0021] Chip carrier 130 may be any suitable type of chip carrier, for example, a direct copper interconnect (DCB), a direct aluminum interconnect (DAB), an active metal solder (AMB), an insulated metal substrate (IMS), a printed circuit board (PCB), a lead frame, etc. Chip carrier 130 may, for example, be a power electronics substrate. Chip carrier 130 may, for example, comprise two electrically conductive layers 133, 134 separated from each other by an electrically insulating layer 135.

[0022] As in Fig. As shown in Figure 1, the first side 111 of the molded body 110 comprises a first portion 114 and a second portion 115. The first portion 114 protrudes from the second portion 115 in a vertical direction, wherein the vertical direction is perpendicular to the first side 111. Furthermore, the first portion 114 forms a planar surface. The planar surface may be parallel to the second side 132 of the chip carrier 130, in particular parallel to the exposed portion of the chip carrier 130.

[0023] In the Fig. In the example shown in Figure 1, the first side 111 comprises an inclination between the flat surface of the first portion 114 and the second portion 115. This inclination may, for example, be arranged at an angle in the range of approximately 30° to slightly less than 90° with respect to the flat surface. However, it is also possible for the first side 111 to comprise a vertical step between the first portion 114 and the second portion 115.

[0024] The semiconductor package 100 may include external contacts, for example, from one or more of the lateral sides 113 and / or the first side 111 of the mold body 110 (in Fig. 1 not shown). The external contacts can be, for example, power contacts, e.g., DC contacts and one or more phase current contacts, as well as control contacts, measuring contacts, etc. The power contacts can be, for example, exposed from one or more of the lateral sides 113, and the control or measuring contacts can be, for example, exposed from the first side 111, in particular the first region 114 and / or the second region 115. Power contacts can, for example, comprise or consist of metal clips. Control or measuring contacts can, for example, comprise or consist of pins.

[0025] The semiconductor package 100 may have any suitable dimensions and any suitable shape. For example, the semiconductor package may have a substantially square or rectangular shape when viewed from above the first side 111. For example, the semiconductor package 100 may have edge lengths, when viewed from above the first side 111, in the range of about 5 mm to about 10 cm. The first portion 114 may, for example, comprise about 30% or more, or about 50% or more, or about 70% or more, or about 90% or more of the surface area of ​​the first side 111.

[0026] The second section 115 extends completely along at least one edge of the first side 111 (or in other words, along one of the lateral sides 113 of the molded body 110). The second section 115 can also extend completely along two edges of the first side 111 (e.g., along two opposite edges), or along three edges, or along all four edges of the first side 111. In other words, it is possible for the first section 114 to be completely surrounded by the second section 115.

[0027] Furthermore, a center point of the first portion 114 is in vertical alignment with a center point of the exposed portion of the chip carrier 130. This is in Fig. 1 by the vertical line z. In the case where the exposed portion of the chip carrier 130 is the center of the chip carrier 130, the center point of the first portion 114 is in vertical alignment with a center point of the chip carrier 130 as a whole. In this regard, the "center point" is the center of the surface of the first portion 114 or the exposed portion when viewed from above the first portion 114 or from below the exposed portion of the chip carrier 130, respectively.

[0028] According to the Fig. 1, the first portion 114 is arranged within a perimeter of the at least one exposed portion of the chip carrier 130, and the second portion 115 is arranged at least partially outside the perimeter of the exposed portion. This is shown in Fig. 1 by the two dashed lines between the first portion 114 and the second portion 115. According to one example, as claimed, at least 50% of the second portion 115 is located outside the perimeter of the exposed portion of the chip carrier 130.

[0029] In the Fig. 1, the perimeter of the exposed portion of the chip carrier 130 and a perimeter of the first portion 114 of the first side 111 of the mold body 110 are substantially in perfect alignment. According to another example, the exposed portion of the chip carrier 130 may be smaller than the first portion 114, such that the perimeter of the exposed portion is laterally disposed within the perimeter of the first portion 114. According to yet another example, it is the other way around. In both cases, however, the centers of the first portion 114 and the exposed portion of the chip carrier 130 are in vertical alignment along line z.

[0030] The above-described arrangement of the first portion 114 and the exposed portion of the chip carrier 130 relative to each other may have the following advantages: As mentioned above, the semiconductor package 100 may be configured to be connected to a substrate such as a heat sink and / or a base plate such that the second side 112 of the molded body 110 faces the substrate. Connecting the semiconductor package 100 to the substrate may include exerting pressure on the first side 111 of the molded body 110 and on the substrate (and thereby on the exposed portion of the chip carrier 130). An example of such a connection process is described in Fig. 2, wherein the semiconductor package 100 and a substrate 210 are arranged in a press 200. As in Fig. 2, pressure is applied to the first portion 114, but not to the second portion 115, of the first side 111 of the mold body 110. Since the first portion 114 is in vertical alignment with the exposed portion of the chip carrier 130, as described above, pressure may be evenly distributed across the exposed portion of the chip carrier 130. For this reason, it may be possible to fabricate a bond (e.g., a sintered bond) of homogeneous thickness between the semiconductor package 100 and the substrate 210.

[0031] If the first portion 114 were missing, i.e., if the first side 111 of the mold body 110 was flat, a higher pressure could be exerted on one edge region of the first side 111 than on an opposite second edge region due to alignment tolerances between the semiconductor package 100 and the substrate 210, on the one hand, and the press 200, on the other hand. This could, for example, create a tilted connection between the semiconductor package 100 and the substrate 210 and / or this could lead to the production of a defective connection. In other words, the protruding first portion 114, which is aligned with the exposed portion of the chip carrier 130, can assist in producing a connection of uniform thickness. This can, for example, improve the thermal and / or mechanical properties of such a connection.

[0032] The above-described alignment between the first portion 114 and the exposed portion of the chip carrier 130 may have another advantage: As in the example of Fig. As shown in Figure 1, the chip carrier 130 may include the insulating layer 135, which may protrude laterally beyond the conductive layers 133, 134. The insulating layer 135 may, for example, comprise or consist of a ceramic layer and may be relatively brittle. If the press 200 were to exert pressure on the second region 115, the insulating layer 135 could crack if this pressure becomes too high. However, the configuration of the semiconductor package 100 with the first portion 114 and the second portion 115, as described above, may prevent such cracks from occurring.

[0033] The first portion 114 may protrude from the second portion 115 by any suitable height as long as the above-mentioned effects are obtained. For example, the first portion 114 may protrude by about 50 µm or more, or about 100 µm or more, or about 150 µm or more, or about 300 µm or more, or about 500 µm or more.

[0034] Fig. 3A shows a perspective view of a semiconductor package 300, which may be similar or identical to the semiconductor package 100, except for the differences described below. It should be noted that in Fig. 3A, the semiconductor package 300 is shown with the second side 112 of the molded body 110 facing upward and the first side 111 facing downward.

[0035] The semiconductor package 300 may, for example, be configured to be connected to a substrate such as a heat sink or a base plate via a sintered connection. To fabricate such a connection, sintering material 310 is deposited over the exposed portion of the chip carrier(s) 130 exposed from the second side 112 of the mold body 110. It should be noted that in the Fig. 3A, the semiconductor package 300 comprises four exposed portions of the chip carrier(s) 130 arranged in a matrix. The four in Fig. The exposed portions shown in Figure 3A have the same shapes and sizes. However, it is also possible for the exposed portions to have different shapes and / or different sizes.

[0036] The semiconductor housing 300 may comprise an external contact 320 arranged on one of the lateral sides 113 of the molded body 110. The semiconductor housing 300 may comprise further external contacts 320, which may be arranged, for example, on the same lateral side 113 as the external contact 320 and / or on the opposite lateral side 113. The further external contacts 320 may, for example, be exposed from the second portion 115 of the first side 111 (cf. Fig. 3B and Fig. 3C).

[0037] The semiconductor package 300 may have an asymmetric configuration when viewed from above the second side 112 of the mold body 110. This may mean that the exposed portions of the chip carrier(s) 130 and therefore the deposits of sintering material 310 are not centered on the second side 112 (in Fig. 3A, the exposed portions and therefore the deposits of sintering material 310 are located closer to the left edge than to the right edge of the second side 112. For this reason, if the first side 111 did not include a protruding first portion 114 aligned with the deposits of sintering material 310, the press 200 could exert pressure on the entire first side 111 during a sintering process (compare Fig. 2). In this case, the sintered material 310 would be pressed downwards more strongly at one edge of the first side 111 than at the opposite edge of the first side 111.

[0038] Fig. 3B shows a sectional view of the semiconductor package 300. As in Fig. 3B, the first portion 114 of the first side 111 is in vertical alignment with the exposed portions of the chip carriers 130 and therefore also with the deposits of sintering material 310. This may mean that a center point of the first side 111 and a common center point of the exposed portions of the chip carriers 130 are both arranged along the vertical line z. Furthermore, the exposed portions of the chip carriers 130 may be arranged, for example, within a perimeter of the first portion 114 (compare Fig. 3B). According to another example, the opposite is true.

[0039] Fig. 3C shows a sectional view of the semiconductor package 300 according to another example, which is similar or identical to that shown in Fig. 3B, except for the differences described below. In particular, in the example shown in Fig. 3C, the first side 111 includes a plurality of first portions 114 that are in vertical alignment with the plurality of exposed portions of the chip carriers 130. For example, there may be a first portion 114 aligned with each individual exposed portion of the chip carriers 130, or two or more of the exposed portions may be aligned with a common first portion 114.

[0040] Since the second portion 115 and not the first portion 114 is arranged vertically above the specific part of the second side 112 that does not include exposed portions of the chip carriers 130, the semiconductor package 300 is not tilted by the press 200 and sintered joints of homogeneous thickness can be manufactured.

[0041] Fig. 4A shows a cross-sectional view of a power electronics system 400. The power electronics system 400 includes a semiconductor package 410 mounted on a substrate 420. The semiconductor package 410 may be similar or identical to the semiconductor package 100 or 300. The substrate 420 may be, for example, a heat sink and / or a base plate. The semiconductor package 410 is arranged over the substrate 420 such that the second side 112 of the molded body 110 faces the substrate 420. In the Fig. In the example shown in Figure 4A, the first side 111 of the molded body 110 comprises a plurality of first sections 114. However, the first side 111 may of course also comprise only a single first section 114.

[0042] The semiconductor package 410 is mechanically coupled to the substrate 420 by clamps 430 that apply pressure to the first portion(s) 114 of the first side 111 of the mold body 110. The clamps 430 may be metal clamps, for example, and may be arranged on opposite lateral sides of the semiconductor package 410. Because the semiconductor package 410 is mechanically attached to the substrate 420 by the clamps, it may not be necessary to also solder or sinter the semiconductor package 410 to the substrate 410.

[0043] According to one example, the power electronics system 400 includes a rigid plate 440 connected between the clamps 430 and the semiconductor package 410. The rigid plate 440 may be configured to distribute the mechanical force exerted by the clamps 430 on the semiconductor package 410 across the first portion(s) 114 of the first side 111 of the molded body 110. The rigid plate 440 may be a metal plate, for example.

[0044] According to one example, the power electronics system 400 further comprises an elastic layer 450 disposed between the rigid plate 440 and the first portion(s) 114 of the first side 111 of the molded body 110. The elastic layer 450 may be configured to homogeneously distribute pressure across the first portion(s) 114 and / or to compensate for height tolerances. The elastic layer 450 may comprise or consist of any suitable elastic material and may, for example, comprise or consist of a rubber mat. According to another example, the power electronics system 400 does not comprise the elastic layer 450, which means that the rigid plate 440 directly contacts the first portion(s) 114.

[0045] The power electronics system 400 may further include an electrically insulating layer 460 disposed between the semiconductor package 410 and the substrate 420 and configured to electrically isolate the semiconductor package 410 from the substrate 420.

[0046] Fig. 4B shows a plan view of the power electronics system 400 from above the rigid plate 440. As in Fig. For example, as shown in Figure 4B, the terminals 430 may be arranged on two opposite lateral sides of the semiconductor package 410, and the remaining two lateral sides of the semiconductor package 410 may include external contacts 470.

[0047] For example, the first section(s) 114 of the first side 111 of the molded body 110 may be arranged at a non-zero distance from the edges of the first side 111. The reason for such an arrangement may be that exerting pressure on the edges could lead to severe warpage of the semiconductor package 410, and such warpage could potentially damage the semiconductor package 410. The first section(s) 114 may therefore be arranged on the first side 111 in positions such that severe warpage of the semiconductor package 410 can be avoided.

[0048] Fig. 4C shows the power electronics system 400 according to another example. In particular, in the Fig. 4C, the terminals 430 are replaced by screws 480. In the example shown in Fig. In the example shown in Figure 4C, a spring element 490 is disposed between the screws 480 and the rigid plate 440, wherein the spring element 490 is configured to exert pressure on the rigid plate 440. According to another example, the screws 480 are directly connected to the rigid plate 440.

[0049] Fig. 4D shows the power electronics system 400 according to yet another example. In Fig. 4A-4C, the semiconductor package 410 is reversibly coupled to the substrate 420 using clamps or screws. In the Fig. 4D, the semiconductor package 410 is sintered onto the substrate 420 via a sintered layer 492. As shown in Fig. As shown in Figure 4D, the sintered layer 492 may be disposed within a perimeter of the first portion 114. Furthermore, a space between the semiconductor package 410 and the substrate 420 below the second portion 115 may be free of the sintered layer 492.

[0050] Fig. 5 is a flowchart of an exemplary method 500 for mechanically coupling a semiconductor package to a heat sink. For example, method 500 may be used to couple one of semiconductor packages 100, 300, and 400 to substrate 200 or 420.

[0051] The method 500 includes, at 501, a process for providing a semiconductor package, comprising: a molded body comprising a first side and an opposite second side, at least one semiconductor chip encapsulated by the molded body, and a chip carrier comprising a first side and an opposite second side, wherein the at least one semiconductor chip is disposed over the first side of the chip carrier, and wherein the second side of the chip carrier is at least partially exposed from the second side of the molded body, thereby forming at least one exposed portion of the chip carrier, wherein the first side of the molded body comprises a first portion and a second portion, wherein the first portion protrudes from the second portion in a vertical direction, thereby forming a planar surface, wherein the vertical direction is perpendicular to the first side,wherein the second portion extends entirely along at least one edge of the first side, and wherein a center point of the first portion is in vertical alignment with a center point of the exposed portion. The method 500 includes, at 502, a process of disposing the semiconductor package over a heat sink such that the second side of the semiconductor package faces the heat sink, and, at 503, a process of applying pressure to the first portion, but not to the second portion, of the first side of the mold body to mechanically and thermally couple the semiconductor package to the heat sink.

[0052] According to one example of method 500, coupling the semiconductor package to the heat sink includes a sintering process. According to another example, coupling the semiconductor package to the heat sink includes a clamping process or a screwing process.

[0053] Fig. 6 shows a cross-sectional view of a semiconductor package 600, which may be similar or identical to the semiconductor package 100, 300, 410, except for the differences described below. The semiconductor package 600 is shown with a recess 608 in the first portion 114 of the mold body 110. The first portion 114 has two separate islands, e.g., a first island 604 and a second island 606, separated from each other by the recess 608. The recess 608 may be formed by a protrusion in the mold or by dicing, e.g., laser dicing, etching. As an example, the semiconductor package 600, as shown in Fig. 6, two islands separated by a recess. However, the semiconductor package 600 may have more than two islands and more than one recess. The semiconductor package may also have an external contact, such as, but not limited to, a press-fit pin 610 protruding from the recess 608. The contact may be electrically coupled to the semiconductor chip 120 either directly or via the chip carrier 130, e.g., an upper conductive layer 133.

[0054] When mounting a semiconductor package 600 on the substrate 420 using a sintering press, it may be desirable to apply different pressures to different portions of the semiconductor package. For example, areas of the semiconductor package with a significant amount of rigid material, semiconductor die, or metal contacts such as press-fit pins may transmit pressure to the sintering press that differs from the surrounding molding compound. The total maximum pressure exerted by the sintering press may thus be limited by specific portions of the semiconductor package. The recesses in the mold package may spare some areas from being applied if the total pressure limitation were still present. Fig. 7 shows another example of the bonding process of the semiconductor package 600 to the substrate 420, in which the pressure of a sintering press 702 can be further optimized. The semiconductor package 600 and the substrate 420, e.g., a base plate or a cooler, are arranged in the sintering press 702. The sintering layer 491, e.g., a sintering paste, is arranged between the exposed portion of the chip carrier 130 and the substrate 420. The sintering press 702 has an upper portion 702a facing the first portion 114 and a lower portion 702b facing the substrate 420. The upper portion 702a has a first independent segment 704 and a second independent segment 706 mounted on a head 708. The independent segments 704, 706 are separated from each other by a gap 710.The upper portion 702a is arranged such that the first independent segment 704 faces the first island 604, the second independent segment 706 faces the second island 606, and the gap 710 faces the recess 608 of the first portion 114. The islands 604 and 606 can now be pressed with different forces, each exerted by the upper portion 702a of the sintering press 702. An O-ring 712 comprising an elastic material can be arranged between the head 708 and the first independent segment 704, as shown in FIG. Fig. 7. When the upper portion 702a presses the first portion 114, the O-ring 712 is deformed and reduces the force exerted on the first island 604 compared to the second island 606. In particular, the first independent segment 704 is configured to press the first island 604 with a first force, and the second independent segment 706 is configured to press the second island 606 with a second force, which may be different from the first force. Due to the O-ring 712 in the sintering press 702, the first force is less than the second force. Therefore, pressure is unevenly distributed across the exposed portion of the chip carrier 130. Consequently, the sintered layer 491 also experiences the uneven pressure. The sintered layer 491 may have a thickness in a range of 15 to 500 µm, in particular 30 to 300 µm, measured vertically between the exposed portion of the chip carrier 130 and the substrate 420.Due to the thickness of the sintered layer 491 of a few µm, the uneven pressure leads to different porosities in the final sintered layer 492. In particular, since a first portion 493 of the sintered layer 491 under the first island 604 experiences less pressure than a second portion 494 of the sintered layer 491 under the second island 606, the joint formed in the first portion 493 of the sintered layer 492 will have a higher porosity than the joint formed in the second portion 494 of the sintered layer 492. A higher porosity implies that particles, e.g., silver particles, in the first portion 493 of the joint are separated by a greater distance compared to particles in the second portion 494 of the joint. The first portion 493 may have more voids compared to the second portion 494.The difference in porosity depends on the difference in pressure and can range from 2% to 50%, especially 5% to 30%. The uneven porosity of the joint increases the flexibility of the joint without changing its mechanical strength.

[0055] Pressing the first section 114 can be achieved by different methods. For example, the upper section 702a can be a chamber containing a gas, e.g., nitrogen, for pressing. The gas can be distributed within the upper section 702a so that the upper section 702a presses the first island 604 with the first force and the second island 606 with the second force.

[0056] As described hereinabove, the gap 710 of the sintering press 702 overlaps with the recess 608 of the first portion 114 and therefore the sintering press 702 does not exert any force on the recess 608. If a contact, such as a press-fit pin, is inserted into the recess, as in Fig. 6, the semiconductor package 600 can be pressed onto the substrate 420 without damaging the press-fit pin 610 or the underlying chip carrier 130. EXAMPLES

[0057] In the following, the semiconductor package, the power electronics system and the method for mechanically coupling a semiconductor package to a heat sink are further explained using specific examples.

[0058] Example 1 is a semiconductor package comprising: a molded body comprising a first side and an opposite second side, at least one semiconductor chip encapsulated by the molded body, and a chip carrier comprising a first side and an opposite second side, wherein the at least one semiconductor chip is disposed over the first side of the chip carrier, and wherein the second side of the chip carrier is at least partially exposed from the second side of the molded body, thereby forming at least one exposed portion of the chip carrier, wherein the first side of the molded body comprises a first portion and a second portion, wherein the first portion protrudes from the second portion in a vertical direction, thereby forming a planar surface, wherein the vertical direction is perpendicular to the first side, wherein the second portion extends entirely along at least one edge of the first side,and wherein a center point of the first portion is in vertical alignment with a center point of the exposed portion, wherein the first portion is disposed within a perimeter of the at least one exposed portion of the chip carrier and wherein at least 50% of the second portion is disposed outside the perimeter.

[0059] Example 2 is the semiconductor package of Example 1, wherein the second portion extends entirely along at least two opposite edges of the first side.

[0060] Example 3 is the semiconductor package of Example 1, wherein the second portion extends completely along all four edges of the first side.

[0061] Example 4 is the semiconductor package according to any one of the preceding examples, wherein the first section comprises a plurality of islands separated from each other by the second section.

[0062] Example 5 is the semiconductor package according to Examples 1 to 3, wherein the first portion has a recess.

[0063] Example 6 is the semiconductor package of Example 5, further comprising a press-fit pin protruding from the recess.

[0064] Example 7 is the semiconductor package according to any one of the preceding examples, further comprising: power contacts electrically connected to power terminals of the at least one power semiconductor chip, wherein the power contacts are exposed from the second portion of the first side of the molded body.

[0065] Example 8 is the semiconductor package according to any one of the preceding examples, wherein the chip carrier comprises or consists of a lead frame or a substrate comprising two electrically conductive layers separated by an electrically insulating layer.

[0066] Example 9 is the semiconductor package according to example according to any one of the preceding examples, wherein the chip carrier comprises two metal layers separated by a ceramic layer, wherein a protrusion portion of the ceramic layer protrudes laterally beyond the metal layers, wherein the lateral direction is parallel to the first and second sides of the chip carrier, and wherein a part of the first side of the molded body vertically above the protrusion portion consists of the second portion.

[0067] Example 10 is a power electronics system comprising: a semiconductor package according to any one of the preceding claims and a heat sink, wherein the semiconductor package is mechanically coupled to the heat sink such that the second side of the semiconductor package faces the heat sink.

[0068] Example 11 is the power electronics system of Example 10, wherein the second side of the chip carrier is connected to the heat sink by a sintered layer.

[0069] Example 12 is the power electronics system of Example 11, wherein the sintered layer is disposed within a perimeter of the first portion.

[0070] Example 13 is the power electronics system of example 11 or 12, wherein a space vertically below the second portion is free of the sintered layer.

[0071] Example 14 is the power electronics system of Example 10, wherein the semiconductor package is mechanically coupled to the heat sink by clamps or screws that apply pressure to the first portion of the first side of the molded body.

[0072] Example 15 is the power electronics system of Example 14, further comprising: a rigid plate connected between the clamps or screws and the semiconductor package, and an elastic layer disposed between the rigid plate and the first portion of the first side of the mold body and configured to homogeneously distribute pressure along the first portion.

[0073] Example 16 is a method for mechanically coupling a semiconductor package to a heat sink, the method comprising: providing a semiconductor package comprising: a molded body comprising a first side and an opposite second side, at least one semiconductor chip encapsulated by the molded body, and a chip carrier comprising a first side and an opposite second side, wherein the at least one semiconductor chip is disposed over the first side of the chip carrier, and wherein the second side of the chip carrier is at least partially exposed from the second side of the molded body, thereby forming at least one exposed portion of the chip carrier, wherein the first side of the molded body comprises a first portion and a second portion, wherein the first portion protrudes from the second portion in a vertical direction, thereby forming a planar surface,wherein the vertical direction is perpendicular to the first side, wherein the second portion extends entirely along at least one edge of the first side, and wherein a center point of the first portion is in vertical alignment with a center point of the exposed portion; disposing the semiconductor package over a heat sink such that the second side of the semiconductor package faces the heat sink; and applying pressure to the first portion, but not to the second portion of the first side of the molded body, to mechanically and thermally couple the semiconductor package to the heat sink.

[0074] Example 17 is the method of Example 16, wherein coupling the semiconductor package to the heat sink comprises a sintering process.

[0075] Example 18 is the method of Example 17, further comprising: forming a recess in the first portion defining first and second islands that are separated from each other, and wherein applying pressure to the first portion comprises pressing the first portion through a press comprising two independent segments, a first independent segment of the press pressing onto the first island of the first portion with a first force and a second independent segment of the press pressing onto the second island of the first portion with a second force.

[0076] Example 19 is the method of Example 20, wherein the first force is different from the second force.

[0077] Example 20 is the method of Example 18, wherein coupling the semiconductor package to the heat sink comprises a clamping process or a screwing process.

[0078] Although specific examples have been illustrated and described herein, those skilled in the art will recognize that a variety of alternative and / or equivalent implementations may be substituted for the specific examples shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific examples discussed herein.

Claims

[1] Semiconductor package (100) comprising: a shaped body (110) comprising a first side (111) and an opposite second side (112), at least one semiconductor chip (120) encapsulated by the molded body (110), and a chip carrier (130) comprising a first side (131) and an opposite second side (132), wherein the at least one semiconductor chip (120) is arranged over the first side (131) of the chip carrier (130) and wherein the second side (132) of the chip carrier (130) is at least partially exposed from the second side (112) of the molded body (110), thereby forming at least one exposed portion of the chip carrier (130), wherein the first side (111) of the molded body (110) comprises a first portion (114) and a second portion (115), wherein the first portion (114) protrudes from the second portion (115) in a vertical direction, thereby forming a flat surface, wherein the vertical direction is perpendicular to the first side (111), wherein the second portion (115) extends completely along at least one edge of the first side (111), and wherein a center point of the first portion (114) is in vertical alignment with a center point of the exposed portion, wherein the first portion (114) is disposed within a perimeter of the at least one exposed portion of the chip carrier (130) and wherein at least 50% of the second portion (115) is disposed outside the perimeter. [2] The semiconductor package (100) of claim 1, wherein the second portion (115) extends entirely along at least two opposite edges of the first side (111). [3] The semiconductor package (100) of claim 1, wherein the second portion (115) extends completely along all four edges of the first side (111). [4] A semiconductor package (100) according to any one of the preceding claims, wherein the first portion (114) comprises a plurality of islands separated from each other by the second portion (115). [5] Semiconductor package (100) according to claims 1 to 3, wherein the first portion (114) has a recess. [6] The semiconductor package of claim 5, further comprising a press-fit pin protruding from the recess. [7] Semiconductor package (300) according to one of the preceding claims, further comprising: Power contacts (320) electrically connected to power terminals of the at least one power semiconductor chip (120), wherein the power contacts (320) are exposed from the second portion (115) of the first side (111) of the molded body (110). [8] Semiconductor package (100) according to one of the preceding claims, wherein the chip carrier (130) comprises or consists of a lead frame or a substrate comprising two electrically conductive layers (133, 134) separated by an electrically insulating layer (135). [9] Semiconductor package (100) according to one of the preceding claims, wherein the chip carrier (130) comprises two metal layers separated by a ceramic layer, wherein a projection portion of the ceramic layer projects laterally beyond the metal layers, wherein the lateral direction is parallel to the first and second sides (131, 132) of the chip carrier (130), and wherein a part of the first side (111) of the molded body (110) consists of the second portion (115) vertically above the projection portion. [10] Power electronics system (400), comprising: a semiconductor package (410) according to one of the preceding claims, and a heat sink (420), wherein the semiconductor package (410) is mechanically coupled to the heat sink (420) such that the second side of the semiconductor package (410) faces the heat sink (420). [11] The power electronics system (400) of claim 10, wherein the second side (132) of the chip carrier (130) is connected to the heat sink (420) by a sintered layer (492). [12] The power electronics system (400) of claim 11, wherein the sintered layer (492) is disposed within a perimeter of the first portion (114). [13] The power electronics system (400) of claim 11 or 12, wherein a space vertically below the second portion (115) is free of the sintered layer (492). [14] The power electronics system (400) of claim 10, wherein the semiconductor package (410) is mechanically coupled to the heat sink (420) by clamps (430) or screws (480) that apply pressure to the first portion (114) of the first side (111) of the molded body (110). [15] The power electronics system (400) of claim 14, further comprising: a rigid plate (440) connected between the terminals (430) or screws (480) and the semiconductor housing (410), and an elastic layer (450) disposed between the rigid plate (440) and the first portion (114) of the first side (111) of the molded body (110) and configured to homogeneously distribute pressure along the first portion (114). [16] A method (500) for mechanically coupling a semiconductor package to a heat sink, the method (500) comprising: Providing (501) a semiconductor package comprising: a shaped body comprising a first side and an opposite second side, at least one semiconductor chip encapsulated by the molded body, and a chip carrier comprising a first side and an opposite second side, wherein the at least one semiconductor chip is arranged over the first side of the chip carrier and wherein the second side of the chip carrier is at least partially exposed from the second side of the molded body, thereby forming at least one exposed portion of the chip carrier, wherein the first side of the molded body comprises a first portion and a second portion, the first portion protruding from the second portion in a vertical direction, thereby forming a flat surface, the vertical direction being perpendicular to the first side, wherein the second portion extends entirely along at least one edge of the first side, and wherein a center point of the first portion is in vertical alignment with a center point of the exposed portion; Arranging (502) the semiconductor package over a heat sink such that the second side of the semiconductor package faces the heat sink; and Applying (503) pressure to the first portion, but not to the second portion, of the first side of the mold body to mechanically and thermally couple the semiconductor package to the heat sink. [17] The method (500) of claim 16, wherein coupling the semiconductor package to the heat sink comprises a sintering process. [18] The method of claim 17, further comprising Forming a recess in the first section forming a first and a second island separated from each other; and wherein applying (503) pressure to the first section comprises pressing the first section by a press comprising two independent segments, wherein a first independent segment of the press is pressed onto the first island of the first section with a first force and a second independent segment of the press is pressed onto the second island of the first section with a second force. [19] The method of claim 18, wherein the first force is different from the second force. [20] The method (500) of claim 16, wherein coupling the semiconductor package to the heat sink comprises a clamping process or a screwing process.

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