INTEGRATED ANTENNA IC PACKAGE AND MANUFACTURING METHOD

Abstract

An IC package includes: a transmitter and / or a receiver disposed in a semiconductor die and having a signal terminal; a pad disposed on a first surface of the semiconductor die, the pad electrically connected to the signal terminal; a passivation layer disposed on the first surface and having a first opening aligned with the pad; a first post-passivation interconnect (PPI) layer having a conductive path electrically connected to the pad; a second PPI layer having an antenna structure electrically connected to the conductive path; and a substrate disposed on a second surface of the semiconductor die opposite the passivation layer, the substrate having a plurality of substrate vias (TSVs) electrically connected to the transmitter and / or the receiver.

Description

Priority claim

[0001] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 633,222, filed April 12, 2024, which is incorporated by reference into this application. background

[0002] In some applications, integrated circuits (ICs) contain transmitters and / or receivers configured to perform telecommunications operations, for example, as part of cellular or other radio networks or in radar applications. Advances in telecommunications technology often aim to perform these operations using radio-frequency signals that support bandwidths greater than those of lower frequencies. In some cases, signals correspond to radio frequency (RF) bands from 30 kHz to 300 GHz. Short description of the drawings

[0003] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Rather, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 is a cross-sectional view of an IC package according to some embodiments. The Fig. 2A to 2C are plan views of antenna structures according to some embodiments. Fig. 3 is a schematic diagram of a transceiver circuit according to some embodiments. Fig. 4 is a flow diagram of a method of manufacturing an IC package according to some embodiments. The Fig. 5A to 5P are cross-sectional views of an IC package at various stages of manufacturing according to some embodiments. Fig. 6 is a flow diagram of a method of operating an IC package according to some embodiments. Fig. 7 is a block diagram of an IC manufacturing facility and an associated IC manufacturing flow according to some embodiments. Detailed description

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like are also contemplated. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact.Furthermore, reference numbers and / or letters may be repeated throughout the various examples in the present disclosure. This repetition is for convenience and clarity and does not, in itself, dictate any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structural element to one or more other elements or structural elements illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90° or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0006] In various embodiments, an integrated circuit (IC) package, e.g., a wafer-level chip-scale package (WLCSP), comprises: a semiconductor die with a transmitter and / or a receiver, e.g., a transceiver; a pad electrically connected to the transmitter / receiver; a passivation layer; a first post-passivation interconnect (PPI) layer with a conductive path electrically connected to the pad; a second PPI layer with an antenna structure electrically connected to the conductive path; and a substrate opposite the passivation layer containing substrate vias (TSVs) electrically connected to the transmitter / receiver.The IC package thus contains a transmitter / receiver that is configured to transmit and / or receive signals via an antenna or antenna array on a front side of the die, while being powered and controlled from a back side of the die via the TSVs.

[0007] This allows transceiver operations to be performed using a package that is lower cost and has a smaller form factor than other approaches, such as approaches where antenna, power, and control connections are on the same side of a die; approaches where a transceiver and antenna are integrated into a single die; and / or approaches that use a flip-chip or waveguide antenna.

[0008] According to various embodiments, Fig. 1 a sectional view of an IC package 100; the Fig. 2A to 2C are plan views of antenna structures 200A to 200C; Fig. 3 is a schematic diagram of a transceiver circuit 300; Fig. 4 is a flow diagram of a method 400 for manufacturing an IC package, e.g., the IC package 100; the Fig. 5A to 5P are cross-sectional views of the IC package 100 at various stages of manufacture; Fig. 6 is a flow diagram of a method 600 for operating an IC package; and Fig. 7 is a block diagram of an IC manufacturing system 700 and an associated IC manufacturing process.

[0009] The figures shown here, e.g. Fig. 1 to 2C and 5A to 5P, are each simplified for explanation. The figures are representations of IC structures, devices, and packages, with various elements included and omitted to facilitate the discussion below. In various embodiments, an IC structure, an IC device, and / or an IC package includes one or more elements corresponding to power distribution structures, metal interconnects, contacts, vias, gate structures, source / drain (S / D) structures, bulk interconnects, or other transistor elements; isolation structures, or the like, in addition to the elements shown in the Fig. 1 to 2C and 5A to 5P.

[0010] The relative sizes, shapes and dimensions of the various elements used in the Fig. 1 to 2C and 5A to 5P are non-limiting examples for illustrative purposes. Elements having different relative sizes, shapes and dimensions than those shown in the Fig. 1 to 2C and 5A to 5P are also within the scope of the present disclosure.

[0011] Fig. 1 shows a cross-sectional view of an IC package 100 and an x- and z-direction, according to some embodiments. A y-direction (not shown), which is perpendicular to the x- and z-directions, extends into the illustrated cross-section.

[0012] The IC package 100 includes: a printed circuit board (PCB) P1 bonded to a substrate SUB; a semiconductor die D1 containing the substrate SUB; one or more pads PD; a passivation layer PS; and antenna layers ANL disposed on the pads PD and the passivation layer PS. In some embodiments, the IC package 100 does not include the PCB P1.

[0013] The Fig. 1 is simplified for illustrative purposes to show limited instances of various elements. In some embodiments, IC package 100 includes additional instances of some or all of the elements shown in Fig. 1, e.g. TSVs V1 and / or a pad PD.

[0014] At the Fig. In the embodiment shown in Figure 1, the IC package 100 is configured as a WLCSP, and in some embodiments, it is also referred to as a WLCSP 100. An IC package 100 configured as a different package type, e.g., as a 3DIC package, is also within the scope of the present disclosure.

[0015] The PCB P1 is a rigid board containing one or more insulating materials, e.g., a glass-fiber-reinforced epoxy material such as FR-4, and several metals, e.g., copper, and having conductive traces (not shown) arranged on a surface S1 (the surface S1 is also referred to as a surface S1 of the substrate SUB and corresponds to an interface, e.g., a bonding surface between the PCB P1 and the substrate SUB). In some embodiments, the PCB P1 includes a plurality of PCB pads (not shown) arranged on the surface S1 and electrically connected to or contained within the conductive traces, and the interface is a solder joint including solder balls (not shown) attached to some or all of the PCB pads.

[0016] The substrate SUB is a structure containing one or more semiconductor materials, e.g., silicon, and having a plurality of TSVs V1 containing one or more conductive materials, e.g., a metal such as copper and / or aluminum, and extending between the surface S1 and a surface S2, which is also referred to as a surface S2 of a CMOS layer (CMOS: complementary metal oxide semiconductor). In some embodiments, e.g., as described in Fig. 1, the substrate SUB is also referred to as a CMOS substrate SUB.

[0017] The die D1 is a semiconductor die that includes one or more layers of combinations of semiconducting, conductive, and insulating materials and is configured as a CMOS device that includes one or more transmitters and / or receivers 100TR, e.g., one or more transceivers (transceivers), such as a transceiver 300, which will be described later with reference to Fig. 3 and is arranged on the substrate SUB.

[0018] In some embodiments, the die D1 and the substrate SUB are the same bulk substrate, and the area S2 corresponds to a position of active areas of CMOS transistors included in the one or more transmitters and / or receivers 100TR.

[0019] In some embodiments, for example in Fig. 1, the substrate SUB is a semiconductor substrate; the surface S2 comprises one or more layers of insulating materials, e.g., silicon dioxide (SiO2); the die D1 contains an epitaxial layer of silicon; and the die D1 with the epitaxial layer, the substrate SUB, and the surface S2 is collectively referred to as a silicon-on-insulator (SOI) structure.

[0020] The one or more transmitters and / or receivers 100TR are ICs each configured to receive one or more transmission signals at one or more signal terminals (in Fig. 1 not shown) based on received data and / or generate data from one or more transmission signals received at one and the same or one or more additional signal terminals. In some embodiments, the die D1 includes one or more additional ICs, e.g., logic, processing, memory ICs, or the like, and the one or more transmitters and / or receivers 100TR are configured to receive and / or generate some or all of the data from the additional ICs.

[0021] In various embodiments, the one or more transmitters and / or receivers 100TR are configured to generate and / or receive the one or more transmission signals at a single signal terminal corresponding to a signal path, at a pair of signal terminals corresponding to different signal paths, or at two or more signal terminals corresponding to one or more signal paths and a ground path.

[0022] The one or more transmission signals have a corresponding equal number of one or more frequencies or a smaller number of one or more frequencies. As a given frequency of the one or more frequencies increases, a corresponding bandwidth also increases, thereby increasing the amount of data that can be transmitted in a given period of time.

[0023] In some embodiments, the one or more transmitters and / or receivers 100TR are configured to generate and / or receive one or more transmission signals having one or more frequencies corresponding to a radio frequency (RF) ranging from 30 kHz to 300 GHz, e.g., an RF band.

[0024] In some embodiments, the one or more transmitters and / or receivers 100TR are configured to generate and / or receive one or more transmission signals having one or more frequencies in a D-band ranging from 130 GHz to 174.8 GHz and corresponding to wavelengths from 1.7 mm to 2.3 mm. In some embodiments, the one or more transmitters and / or receivers 100TR are configured to generate and / or receive one or more transmission signals having a frequency equal to 140 GHz.

[0025] In some embodiments, the one or more transmitters and / or receivers 100TR are configured to generate and / or receive one or more transmission signals using frequency division multiplexing (FDM) and / or time division multiplexing (TDM) techniques, such as a time division duplexing (TDD) technique, as described later with reference to Fig. 3 is discussed in more detail.

[0026] The one or more transmitters and / or receivers 100TR, and in some embodiments, other ICs, include terminals (not shown) connected to some or all of the TSVs V1 and are thereby configured, in operation, to receive at least one of a supply voltage, a reference voltage, e.g., ground, and one or more control, data, or other signals via the TSVs V1 and, in response thereto, to perform the corresponding signal transmitting and / or receiving operations.

[0027] It is assumed that two or more circuit elements are connected based on one or more direct electrical connections and / or one or more indirect electrical connections comprising one or more switches or logic devices, e.g., an inverter or logic gate, between the two or more circuit elements. In some embodiments, electrical or signal transmissions between the two or more connected circuit elements may be modified, e.g., inverted or made dependent, by means of the one or more switches or the one or more logic devices.

[0028] In some embodiments where the IC package 100 includes the PCB P1, some or all of the TSVs V1 are bonded and electrically connected to the PCB pads on the PCB P1 by appropriate solder balls, and thereby the one or more transmitters and / or receivers 100TR are configured to receive, in operation, the at least one supply voltage, the reference voltage, and the one or more control, data, or other signals via the PCB P1.

[0029] Some or all of the TSVs V1, and in some embodiments, the PCB P1, are thereby configured to distribute the at least one supply voltage, the reference voltage, and the one or more control, data, or other signals to the one or more transmitters and / or receivers 100TR.

[0030] The one or more pads PD are arranged on a surface S3 of the die D1 and are electrically connected to one or more corresponding signal terminals of the one or more transmitters and / or receivers 100TR. The one or more pads PD and the corresponding electrical connections contain one or more conductive materials, e.g., one or more metals such as copper and / or aluminum.

[0031] The corresponding electrical connections include one or more metallic interconnect layers between the one or more transmitters and / or receivers 100TR and the one or more pads PD. In some embodiments, the corresponding electrical connections include a redistribution layer (RDL) in addition to the metallic interconnect layers.

[0032] The area S3 and the one or more pads PD correspond to a top metal layer of the metal interconnect layers of the die D1 and, in some embodiments, the RDL. In some embodiments, the area S3 is referred to as a first side or front side of the die D1, and the area S1 is referred to as a second side or back side of the die D1.

[0033] The passivation layer PS contains one or more insulating materials, e.g., SiO2, undoped silicate glass (USG), silicon nitride, and / or silicon oxynitride. It is arranged on the surface S3 and has one or more openings corresponding to the one or more pads PD.

[0034] Antenna layers ANL are arranged on the passivation layer PS and the one or more pads PD. These layers comprise insulating layers INS1 to INS3 and PPI (Post-Passivation Interconnect) layers PPI1 and PPI2. The insulating layers INS1 to INS3 each contain one or more layers of insulating materials, e.g., polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), other suitable polymer-based dielectric materials, SiO2, silicon nitride, and / or silicon oxynitride. The PPI layers PPI1 and PPI2 each contain one or more conductive materials, e.g., one or more metals such as copper and / or aluminum.

[0035] At the Fig. In the embodiment shown in Figure 1, the insulating layers INS1 to INS3 contain PBO and are referred to as insulating layers PBO1 to PBO3, and the PPI layers PPI1 and PPI2 contain copper and are referred to as PPI layers Cu-PPI1 and Cu-PPI2. Other combinations of materials are also within the scope of the present disclosure.

[0036] The insulating layer INS1 is arranged over the passivation layer PS and the one or more pads PD and is arranged, for example, on and in direct contact with the passivation layer PS and the one or more pads PD, and it has one or more openings aligned with the one or more pads PD in the z-direction.

[0037] The PPI layer PPI1 includes one or more parts arranged above the insulating layer INS1 and one or more parts PM1 extending into the one or more openings of the insulating layer INS1 that are aligned with the one or more pads PD. The one or more parts PM1 are electrically connected to the corresponding one or more pads PD, e.g., in direct contact with them.

[0038] The insulating layer INS2 is disposed over the insulating layer INS1 and the PPI layer PPI1 and is adjacent to the one or more parts of the PPI layer PPI1 disposed over the insulating layer INS1, and has one or more openings aligned in the z-direction with the one or more parts of the PPI layer PPI1 located over the insulating layer INS1.

[0039] The PPI layer PPI2 includes one or more parts arranged above the insulating layer INS2 and one or more parts PM2 extending into the one or more openings of the insulating layer INS2 corresponding to the one or more parts of the PPI layer PPI1 arranged above the insulating layer INS1. The one or more parts PM2 are electrically connected to the corresponding one or more parts of the PPI layer PPI1, e.g., in direct contact with them.

[0040] The insulating layer INS3 is disposed over the insulating layer INS2 and the PPI layer PPI2 and is adjacent to the one or more parts of the PPI layer PPI2 disposed over the insulating layer INS2, and it has one or more openings INS3O aligned in the z-direction with the one or more parts of the PPI layer PPI2 located over the insulating layer INS2.

[0041] At least one of the one or more parts of the PPI layer PPI2 arranged above the insulating layer INS2 contains one or more antenna structures AS, and at least one of the one or more openings INS3O is aligned with the corresponding at least one antenna structure AS, as described later with reference to the Fig. 2A to 2C. In some embodiments, at least one of the one or more portions of the PPI layer PPI1 disposed above the passivation layer PS comprises one or more regions corresponding to a ground plane aligned in the z-direction with at least one of the one or more antenna structures AS.

[0042] In various embodiments, one or more of the PPI layers PPI1 and PPI2 or the insulating layers INS1 to INS3 are collectively referred to as an antenna.

[0043] The section view of Fig. The arrangement of the PPI layers PPI1 and PPI2 shown in Figure 1 is a non-limiting example for illustrative purposes. PPI layers PPI1 and PPI2 with arrangements other than that shown in Fig. 1, e.g., with parts extending in the y-direction, are also within the scope of the present disclosure.

[0044] A given instance of a pad PD that is electrically connected to a signal terminal of a corresponding instance of the transmitter and / or receiver 100TR is thereby also electrically connected to the higher-level part PM1 and one or more corresponding parts of the PPI layer PPI1 located above the insulating layer INS1. In various embodiments, a given higher-level part PM1 is electrically connected to only a part of the PPI layer PPI1 above the insulating layer INS1 or to multiple parts of the PPI layer PPI1 above the insulating layer INS1.

[0045] A given instance of a portion of the PPI layer PPI1 above the insulating layer INS1 is thereby also electrically connected to the higher-level portion PM2 and one or more corresponding portions of the PPI layer PPI2 located above the insulating layer INS2. In various embodiments, a given higher-level portion PM2 is electrically connected to only a portion of the PPI layer PPI2 above the insulating layer INS2 or to multiple portions of the PPI layer PPI2 above the insulating layer INS2.

[0046] Thereby, at least one signal terminal of a given instance of the transmitter and / or receiver 100TR is electrically connected to at least one antenna structure AS through the corresponding higher-lying part PM1 and at least a part of the PPI layer PPI1 above the insulating layer INS1 and through the corresponding higher-lying part(s) PM2 and one or more parts of the PPI layer PPI2 arranged above the insulating layer INS2 and electrically connected to the lower-lying at least a part of the PPI layer PPI1.

[0047] In some embodiments, e.g., those in which only one signal terminal is electrically connected to a single antenna structure AS, an entire given portion PM1 and an entire corresponding portion of the PPI layer PPI1 above the insulating layer INS1, or a portion thereof, are referred to as a conductive path.

[0048] In some embodiments, e.g., those in which multiple signal terminals are electrically connected to multiple antenna structures AS, the PPI layer PPI1 is referred to as a network or an antenna network, and all or a part of a given part PM1 and one or more corresponding parts of the PPI layer PPI1 above the insulating layer INS1 are referred to as a conductive path, a network path, or an antenna network path.

[0049] In some embodiments, a plurality of signal terminals are electrically connected to two or more antenna structures AS configured as an antenna array, which may be described, for example, later with reference to Fig. 2C. In various embodiments, a given signal terminal is electrically connected to only one antenna structure AS of the array or to multiple antenna structures AS of the array, e.g., to an entire row or column of the array or to a portion thereof.

[0050] In some embodiments, a plurality of transmitters and / or receivers of the one or more transmitters and / or receivers 100TR are configured to, in operation, perform a beamforming operation on the transmitted signal or a direction-based operation on the received signal using the antenna array, as also described with reference to Fig. 2C is discussed.

[0051] In the beamforming operation, the multiple transmitters generate multiple transmit signals having the same frequency and phase shifts corresponding to rows or columns of the array, combining multiple transmit signals into a wavefront forming an angle with respect to the xy plane (the x and y directions correspond to those of Fig. 1) which is based on the frequency, phase shifts and a spacing of the rows or columns.

[0052] In a direction-based operation, the received signal has phase shifts based on the row or column pitch, the signal frequency, and the angle relative to the xy plane. In various embodiments, the direction-based operation includes targeting or detecting the angle relative to the xy plane.

[0053] The IC package 100 is thereby configured to include a die D1 containing the one or more transmitters and / or receivers 100TR; a pad PD electrically connected to the corresponding signal terminal; a passivation layer PS; a PPI layer PPI1 having a conductive path electrically connected to the pad PD; a PPI layer PPI2 having an antenna structure AS electrically connected to the conductive path; and a substrate SUB opposite the passivation layer PS, containing TSVs V1 electrically connected to the one or more transmitters and / or receivers 100TR. The IC package 100 thereby includes one or more transmitters and / or receivers 100TR configured to transmit and / or receive signals via an antenna or antenna array on a front side of the die while being powered and controlled from a back side of the die via the TSVs V1.

[0054] This allows operations of the one or more transmitters and / or receivers 100TR to be performed using an IC package 100 that is lower cost and has a smaller form factor than other approaches, such as approaches in which antenna, power, and control connections are on the same side of a die; approaches in which a transmitter / receiver and an antenna are integrated into a single die; and / or approaches in which a flip-chip or waveguide antenna is used.

[0055] The Fig. 2A to 2C are top views of antenna structures 200A to 200C according to some embodiments. Each of the antenna structures 200A to 200C is a non-limiting example of an antenna structure usable as one or more instances of the antenna structure AS described above with reference to Fig. 1 has been discussed.

[0056] The Fig. 2A to 2C show the x- and y-directions and the corresponding one of the antenna structures 200A to 200C, respectively, comprising one or more instances of the PPI layer PPI2 with the antenna structure AS, the insulating layer INS3 or the opening INS30 aligned with a corresponding antenna structure AS in the z-direction, all elements being described above with reference to Fig. 1 have been discussed.

[0057] As in Fig. As shown in Figure 2A, the antenna structure 200A corresponds to a patch antenna with a rectangular shape corresponding to a single portion of the PPI layer PPI2 aligned with a single opening INS30. In some embodiments, the portion of the PPI layer PPI2 aligned with the opening INS30 has a shape other than a rectangle, for example, the shape of a circle, a triangle, or another polygon.

[0058] In some embodiments, the antenna structure 200A corresponds to a patch antenna that includes more than one portion (not shown) of the PPI layer PPI2, each aligned with corresponding openings INS3O. In some embodiments, the antenna structure 200A includes a portion of the PPI layer PPI1 configured as a ground plane (not shown) aligned with one or more portions of the PPI layer PPI2 and one or more corresponding openings INS3O.

[0059] In some embodiments, a total length in the x- and / or y-direction of the one or more parts of the PPI layer PPI2 corresponds to half a wavelength of a transmission signal of the one or more transmitters and / or receivers 100TR described above with reference to Fig. 1, and the total length is, for example, 0.85 mm to 1.15 mm, which corresponds to the frequency range of the D-band.

[0060] As in Fig. As shown in Figure 2B, the antenna structure 200B corresponds to a dipole antenna having two elongated segments aligned in the x-direction, corresponding to portions of the PPI layer PPI2 aligned with a rectangular opening INS3O. In some embodiments, the portions of the PPI layer PPI2 aligned with the opening INS3O correspond to separate signal paths of a differential signal. In some embodiments, the portions of the PPI layer PPI2 aligned with the opening INS3O correspond to segments aligned in the y-direction and / or comprise more than two aligned segments, e.g., four segments.

[0061] In some embodiments, a total length of the dipole segments corresponds to half a wavelength of a transmission signal of the one or more transmitters and / or receivers 100TR described above with reference to Fig. 1, and the total length is, for example, 0.85 mm to 1.15 mm, which corresponds to the frequency range of the D-band.

[0062] As in Fig. As shown in Figure 2C, the antenna structure 200C corresponds to an antenna array including rows and columns of portions of the PPI layer PPI2 and the aligned openings INS30 configured as plates, e.g., square or rectangular segments. In various embodiments, a given signal path corresponds to a single plate, an entire or partial row of plates, or an entire or partial column of plates.

[0063] At the Fig. In the embodiment shown in Figure 2C, the antenna structure 200C includes a total of four rows and four columns. In various embodiments, the antenna structure 200C includes a total of fewer or more than four rows and / or fewer or more than four columns, e.g., two rows and two columns, four rows and eight columns, eight rows and eight columns, or sixteen rows and sixteen columns.

[0064] As the number of rows and / or columns increases, the antenna footprint increases, and beamforming and direction-based operations are improved for transmission signals transmitted by or received with the antenna structure 200C.

[0065] At the Fig. In the embodiment shown in Figure 2C, the antenna structure 200C has a phased array architecture with columns spaced at a pitch D. In some embodiments, the antenna structure 200C has a phased array architecture with rows spaced at the pitch D.

[0066] In some embodiments, the pitch D corresponds to half a wavelength of a transmission signal of the one or more transmitters and / or receivers 100TR described above with reference to Fig. 1, e.g. a pitch of 0.85 mm to 1.15 mm, which corresponds to the frequency range of the D-band.

[0067] By means of the configurations discussed above, the IC package 100 with the antenna structures 200A to 200C as one or more instances of the antenna structure AS can realize the advantages set forth above for the IC package 100.

[0068] Fig. 3 is a schematic diagram of a transceiver circuit (transceiver circuit) 300 according to some embodiments. The transceiver circuit 300 is usable as some or all of the one or more transmitters and / or receivers 100TR described above with reference to Fig. 1 have been discussed.

[0069] The transceiver circuit 300 is a CMOS circuit with a total number N of transceivers 300-1 to 300-N. Each transceiver 300-1 to 300-N includes a transmitter Tx, a receiver Rx, and a switch SW, each connected between the transmitter Tx and the receiver Rx and a corresponding signal terminal T1 to TN.

[0070] At the Fig. In the embodiment shown in Figure 3, the transmitter Tx, the receiver Rx, and the corresponding signal terminals T1 through TN each correspond to a single signal path. In some embodiments, the transmitter Tx, the receiver Rx, and the corresponding signal terminals T1 through TN each correspond to more than one signal path, e.g., a pair of signal paths corresponding to differential signals or including a ground reference.

[0071] The transmitter Tx has an input terminal (not labeled) connected to an amplifier, e.g., a power amplifier, which is arranged to output, in operation, a transmission signal to the switch SW based on a data signal received at the input terminal.

[0072] The receiver Rx has an output terminal (not labeled) connected to an amplifier, e.g., a low-noise amplifier, which is arranged, in operation, to output a data signal at the output terminal based on a transmission signal it receives from the switch SW.

[0073] The switch SW contains one or more switching elements, e.g., transistors and / or transmission gates, which are arranged to connect, in operation, the transmitter Tx or the receiver Rx to the corresponding signal terminal T1 to TN in response to one or more control signals.

[0074] In some embodiments, one or more of the transceivers 300-1 to 300-N are thereby configured to perform a TDM operation, e.g., a TDD operation, based on the switch SW alternately connecting the transmitter Tx or the receiver Rx to the corresponding signal terminal T1 to TN.

[0075] In some embodiments described above with reference to Fig. 1, the transceivers 300-1 through 300-N are configured to perform a beamforming operation using the transmitters Tx and / or to perform a direction-based operation using the receivers Rx. In some embodiments, one or more of the transceivers 300-1 through 300-N include or are coupled to one or more phase-shifting elements, e.g., delay elements (not shown).

[0076] In some embodiments, the total number N of transceivers is equal to one, and the transceiver circuit 300 corresponds to a single transceiver. In some embodiments, the transceiver circuit 300 includes a total number N that is equal to a number of rows or columns of an antenna array, e.g., the antenna structure 200C described above with reference to Fig. 2C has been discussed.

[0077] In some embodiments, the transceiver circuit 300 includes a total number N of 2 to 32. In some embodiments, the transceiver circuit 300 includes a total number N of 4 to 8. As the total number N increases, the circuit space requirement increases, and beamforming and direction-based operations are improved for transmit signals transmitted by or received with the transceiver circuit 300.

[0078] In some embodiments, the transceiver circuit 300 is configured to operate at an RF frequency, as described above with reference to Fig. 1. In some embodiments, transceiver circuitry 300 is configured to operate at a frequency of 130 GHz to 174.8 GHz. In some embodiments, transceiver circuitry 300 is configured to operate at a frequency equal to 140 GHz.

[0079] By means of the configurations discussed above, the IC package 100 with the transceiver circuit 300 as some or all of the one or more transmitters and / or receivers 100TR is capable of realizing the benefits set forth above for the IC package 100.

[0080] Fig. 4 is a flow diagram of a method 400 for manufacturing an IC package according to some embodiments. The method 400 may be performed, for example, according to a manufacturing flow described below with reference to Fig. 7 for manufacturing the IC package 100 described above with reference to the Fig. 1 to 3 have been discussed.

[0081] The Fig. 5A to 5P are cross-sectional views of the IC package 100 at various stages of manufacture corresponding to the method 400, according to some embodiments. Each of the Fig. 5A to 5P corresponds to a subset of the Fig. 1, where the x- and y-directions and some of the reference symbols are omitted for clarity.

[0082] In some embodiments, the operations of method 400 are performed in the manner described in Fig. 4. In some embodiments, the operations of method 400 are performed in a different order than that of Fig. 4. In some embodiments, one or more additional operations are performed before, during, between, and / or after the operations of method 400.

[0083] In some embodiments, one or more of the operations of method 400 are a subset of operations of a method for manufacturing a WLCSP.

[0084] In an operation 410, in some embodiments, a plurality of TSVs are fabricated in a substrate. Fabricating the plurality of TSVs includes fabricating a plurality of TSVs extending through the substrate. In some embodiments, fabricating the plurality of TSVs in the substrate includes fabricating TSVs V1 in a substrate SUB, which are described above with reference to Fig. 1 has been discussed.

[0085] In some embodiments, forming the plurality of TSVs in the substrate comprises forming the plurality of TSVs as part of an SOI process.

[0086] Fig. 5A shows an IC package 100 with a substrate SUB before fabricating the plurality of TSVs, and Fig. 5B shows an IC package 100 with the substrate SUB after fabricating the plurality of TSVs (V1).

[0087] The Fig. 5C to 5L each show a substrate SUB including the plurality of TSVs in embodiments where operation 410 is performed. In embodiments where operation 470, discussed later, is performed instead of operation 410, the substrate SUB does not include the Fig. 5C to 5L shows the majority of TSVs.

[0088] Fabricating the plurality of TSVs includes performing a plurality of fabrication operations, e.g., a lithography, etching, deposition, and / or other operation suitable for performing a suitable patterning process corresponding to the plurality of TSVs.

[0089] In an operation 420, a CMOS layer containing one or more transmitters and / or receivers is formed on the substrate, wherein the one or more transmitters and / or receivers have one or more corresponding signal terminals. In some embodiments, forming the CMOS layer includes forming a CMOS layer in the die D1 containing the substrate SUB and the one or more transmitters and / or receivers 100TR described above with reference to Fig. 1 have been discussed.

[0090] In some embodiments, fabricating the CMOS layer containing the one or more transmitters and / or receivers having one or more corresponding signal terminals comprises fabricating a transceiver circuit 300 having one or more signal terminals T1 to TN described above with reference to Fig. 3 have been discussed.

[0091] In some embodiments, forming the CMOS layer includes forming a CMOS layer that includes one or more circuits in addition to the one or more transmitters and / or receivers, e.g., one or more logic, processing, or memory ICs, or the like.

[0092] Forming the CMOS layer includes forming a metallic interconnect structure that includes one or more electrical connections from each of the one or more signal terminals to a top metal layer of the metallic interconnect structure.

[0093] In some embodiments, forming the CMOS layer on the substrate comprises forming an insulating layer and forming the CMOS layer on the insulating layer as part of an SOI process, which includes, for example, depositing an epitaxial layer of silicon on the insulating layer. In some embodiments, forming the CMOS layer on the substrate comprises forming a CMOS layer concurrently with the substrate.

[0094] In embodiments where operation 410 is performed, forming the CMOS layer also includes forming electrical connections from the one or more transmitters and / or receivers to the plurality of TSVs. In embodiments where operation 470 is performed instead of operation 410, forming the CMOS layer includes forming one or more transmitters and / or receivers configured to be electrically connected to a plurality of TSVs after forming the CMOS layer.

[0095] Fig. 5C shows an IC package 100 with the CMOS layer fabricated on the substrate SUB in the die D1.

[0096] Fabricating the CMOS layer containing the one or more transmitters and / or receivers includes fabricating one or more structures and / or devices, e.g., transistor elements, including S / D structures in active areas of the semiconductor die, gate structures on and / or in the active areas, and electrical connections between the devices according to an IC design.

[0097] Fabricating the CMOS layer containing the one or more transmitters and / or receivers thereby comprises performing a plurality of fabrication operations, e.g., a lithography, diffusion, deposition, etching, planarization, and / or other operation suitable for fabricating the CMOS transistor elements.

[0098] In some embodiments, fabricating the CMOS layer containing the one or more transmitters and / or receivers includes performing one or more FEOL and / or BEOL (Front End of Line; BEOL: Back End of Line) operations.

[0099] In an operation 430, at least one pad and a passivation layer are formed on the CMOS layer. Forming the at least one pad includes forming at least one electrical connection to the upper metal layer of the metallic interconnect structure, thereby electrically connecting each pad of the at least one pad to a corresponding signal terminal of the one or more transmitters and / or receivers.

[0100] Forming the passivation layer comprises forming one or more portions of the passivation layer disposed over the at least one pad and having one or more openings aligned with each pad of the at least one pad in the z-direction.

[0101] In some embodiments, forming the at least one pad and the passivation layer comprises forming at least one instance of the pad PD and the passivation layer PS on the CMOS layer, as described above with reference to Fig. 1 has been explained.

[0102] Fig. 5D shows an IC package 100 containing the at least one pad on the CMOS layer, and Fig. 5E shows an IC package 100 that includes the passivation layer on the CMOS layer and over which at least one pad is disposed.

[0103] Forming the at least one pad and the passivation layer on the CMOS layer includes performing a plurality of manufacturing operations, e.g., a lithography, etching, deposition, spin coating, and / or other operation suitable for performing a suitable patterning and manufacturing process corresponding to the at least one pad and the passivation layer having one or more openings aligned with each pad of the at least one pad.

[0104] In an operation 440, a first insulating layer and a first metal layer are formed on the passivation layer, wherein the first metal layer includes at least one conductive path electrically connected to the at least one pad.

[0105] Forming the first insulating layer comprises forming, over the at least one pad, one or more portions of the first insulating layer having one or more openings aligned with each pad of the at least one pad in the z-direction.

[0106] In some embodiments, forming the first insulating layer and the first metal layer comprises forming a PPI layer PPI1 and an insulating layer INS1, wherein the PPI layer PPI1 includes each conductive path of the at least one conductive path electrically connected to a corresponding pad PD of the at least one pad PD on the CMOS layer, as described above with reference to Fig. 1 has been explained.

[0107] Fig. 5F shows an IC package 100 having a first insulating layer INS1 on an instance of a pad PD and the passivation layer; Fig. 5G shows an IC package 100 having an opening in the insulating layer INS1 aligned with the instance of the pad PD in the z-direction; and Fig. 5H shows an IC package 100 having a PPI layer PPI1 electrically connected to the pad instance PD.

[0108] Forming the first insulating layer and the first metal layer includes performing a plurality of manufacturing operations, e.g., a lithography, etching, deposition, spin coating, and / or other operation suitable for performing a suitable patterning and manufacturing process corresponding to the first metal layer and the first insulating layer having one or more openings aligned with each pad of the at least one pad.

[0109] In an operation 450, a second insulating layer and a second metal layer are formed on the first metal layer, wherein the second metal layer includes at least one antenna structure electrically connected to the at least one conductive path.

[0110] Forming the second insulating layer comprises forming one or more portions of the second insulating layer disposed over the at least one conductive path and having one or more openings aligned with each conductive path of the at least one conductive path in the z-direction.

[0111] In some embodiments, forming the second insulating layer and the second metal layer comprises forming a PPI layer PPI2 and an insulating layer INS2, wherein the PPI layer PPI2 includes each antenna structure AS of the at least one antenna structure AS electrically connected to a corresponding conductive path of the at least one conductive path in the PPI layer PPI1, as described above with reference to Fig. 1 has been explained.

[0112] In some embodiments, forming the second metal layer including at least one antenna structure electrically connected to the at least one conductive path comprises forming one or more antenna structures 200A to 200C described above with reference to the Fig. 2A to 2C have been discussed.

[0113] Fig. 5I shows an IC package 100 having a second insulating layer INS2 on the PPI layer PPI1 and the first insulating layer INS1; Fig. 5J shows an IC package 100 having an opening in the insulating layer INS2 aligned with a conductive path of the PPI layer PPI1 in the z-direction; and Fig. 5K shows an IC package 100 having a PPI layer PPI2 electrically connected to the conductive path of PPI layer PPI1.

[0114] Forming the second insulating layer and the second metal layer comprises performing a plurality of manufacturing operations, e.g., a lithography, etching, deposition, spin coating, and / or other operation suitable for performing a suitable patterning and manufacturing process corresponding to the second metal layer having one or more antenna structures and the second insulating layer having one or more openings aligned with each conductive path of the at least one conductive path.

[0115] In an operation 460, a third insulating layer is formed on the second metal layer, the third insulating layer having one or more openings aligned with the at least one antenna structure in the z-direction.

[0116] In some embodiments, forming the third insulating layer comprises forming an insulating layer INS3 having one or more openings aligned with each of the at least one antenna structure AS in the PPI layer PPI2, as described above with reference to Fig. 1 has been explained.

[0117] In some embodiments, creating the one or more openings in the third insulating layer comprises creating one or more openings aligned with one or more of the antenna structures 200A to 200C described above with reference to the Fig. 2A to 2C have been discussed.

[0118] Fig. 5L shows an IC package 100 having a third insulating layer INS3 on the PPI layer PPI2 and the second insulating layer INS2; and Fig. 5M shows an IC package 100 having an opening INS3O in the insulating layer INS3 that is aligned with an antenna structure AS of the PPI layer PPI2 in the z-direction.

[0119] Forming the third insulating layer comprises performing a plurality of manufacturing operations, e.g., a lithography, etching, deposition, spin coating, and / or other operation suitable for performing a suitable patterning and manufacturing process corresponding to the third insulating layer having one or more openings aligned with each of the at least one antenna structure.

[0120] In an operation 470, in some embodiments, a plurality of TSVs are formed in the substrate. Forming the plurality of TSVs comprises forming a plurality of TSVs extending through the substrate. In some embodiments, forming the plurality of TSVs in the substrate comprises forming TSVs V1 in the substrate SUB, which were described above with reference to Fig. 1 have been discussed.

[0121] In various embodiments, forming the plurality of TSVs in the substrate includes forming one or more TSVs instead of or in addition to forming one or more TSVs as part of performing operation 410 discussed above.

[0122] In some embodiments, forming the plurality of TSVs in the substrate comprises forming a plurality of TSVs in a backside of a semiconductor die, e.g., die D1.

[0123] Fig. 50 shows an IC package 100 with the substrate SUB prior to the fabrication of the plurality of TSVs; and Fig. 5P shows an IC package 100 with the substrate SUB after the fabrication of the majority of TSVs (V1).

[0124] Fabricating the plurality of TSVs includes performing a plurality of fabrication operations, e.g., a lithography, etching, deposition, spin coating, and / or other operation suitable for performing a suitable patterning process corresponding to the plurality of TSVs.

[0125] In an operation 480, the substrate is bonded to a PCB. Bonding the substrate to the PCB includes establishing mechanical and electrical connections between the substrate and the PCB. In some embodiments, bonding the substrate to the PCB includes bonding the substrate SUB to the PCB P1 at the surface S1, as described above with reference to Fig. 1 has been discussed.

[0126] In some embodiments, bonding the substrate to the PCB comprises electrically connecting the plurality of TSVs of the substrate to a plurality of conductive traces, including, for example, solder or other bond pads, on a surface of the PCB.

[0127] In some embodiments, bonding the substrate to the PCB includes attaching solder balls to the plurality of TSVs and / or the PCB.

[0128] In some embodiments, bonding the substrate to the PCB includes performing one or more die dicing operations, e.g., cutting operations, before or after attaching solder balls to the TSVs, e.g., as part of a WLCSP process.

[0129] In some embodiments, bonding the substrate to the PCB includes performing one or more soldering operations, e.g., a reflow operation.

[0130] Fig. 5N shows an IC package 100 having a substrate SUB attached to the PCB, e.g., as an entire WLCSP or as a part thereof.

[0131] By performing some or all of the operations of method 400, an IC package is fabricated that includes one or more transmitters and / or receivers configured to transmit and / or receive signals via an antenna or antenna array on a front side of a die while being powered and controlled from a back side of the die via a plurality of TSVs, thereby enabling the benefits discussed above for IC package 100.

[0132] Fig. 6 is a flow diagram of a method 600 for operating an IC package according to some embodiments. The method 600 is usable with an IC package, e.g., the IC package 100 described above with reference to FIG. Fig. 1 to 5P has been discussed.

[0133] The order in which the operations of method 600 are performed in Fig. 6 is for illustrative purposes only, and the operations of method 600 may be performed in orders other than that of Fig. 6. In some embodiments, operations in addition to those in Fig. 6 operations before, between, during and / or after the operations referred to in Fig. 6 are performed. In some embodiments, the operations of method 600 are a subset of a method for operating a telecommunications device, a radar device, or the like.

[0134] In an operation 610, a supply voltage, a reference voltage, and one or more control and / or data signals are received at a plurality of TSVs in a substrate disposed on a first side of a die.

[0135] Receiving the supply voltage, the reference voltage and the one or more control and / or data signals comprises receiving a supply voltage, a reference voltage and one or more control and / or data signals at a surface S1 of the substrate SUB located on the back side of the die D1, which was described above with reference to the Fig. 1 to 5P has been discussed.

[0136] In an operation 620, a transmitter and / or a receiver on the die are used to output and / or receive a transmission signal at a signal terminal in response to the supply voltage, the reference voltage, and the one or more control and / or data signals.

[0137] Using the transmitter and / or the receiver to output and / or receive the transmission signal in response to the supply voltage, the reference voltage and the one or more control and / or data signals comprises using one or more transmitters and / or receivers 100TR described above with reference to the Fig. 1 to 3 have been discussed.

[0138] In some embodiments, using the transmitter and / or the receiver to output and / or receive the transmission signal at the signal terminal in response to the supply voltage, the reference voltage, and the one or more control and / or data signals comprises using the transceiver 300 described above with reference to Fig. 3 has been discussed.

[0139] In various embodiments, using the transmitter and / or the receiver to output and / or receive the transmit signal at the signal terminal in response to the supply voltage, the reference voltage, and the one or more control and / or data signals comprises performing an FDM, a TDM, a TDD, a beamforming, and / or a direction-based operation.

[0140] In an operation 630, the transmit signal is received and / or transmitted from the signal terminal to an antenna structure in a PPI layer arranged on a second side of the die opposite the first side of the die.

[0141] Receiving and / or transmitting the transmission signal at the antenna structure in the PPI layer arranged on the second side of the die opposite the first side of the die comprises receiving and / or transmitting a transmission signal at an antenna structure AS in a PPI layer PPI2 arranged on the front side of the die D1, as described above with reference to the Fig. 1 to 3.

[0142] In some embodiments, receiving and / or transmitting the transmission signal at the antenna structure comprises receiving and / or transmitting the transmission signal at one or more of the antenna structures 200A to 200C described above with reference to the Fig. 2A to 2C have been discussed.

[0143] In various embodiments, receiving and / or transmitting the transmission signal from / to the signal terminal on the antenna structure in the PPI layer arranged on the second side of the die opposite the first side of the die comprises performing an FDM, a TDM, a TDD, a beamforming, and / or a direction-based operation.

[0144] By performing some or all of the operations of method 600, operations are performed using an IC package including one or more transmitters and / or receivers configured to transmit and / or receive signals via an antenna or antenna array on a front side of a die while being powered and controlled from a back side of the die via a plurality of TSVs, thereby enabling the benefits discussed above for IC package 100.

[0145] Fig. 7 is a block diagram of an IC manufacturing tool 700 and an associated IC manufacturing process, according to some embodiments. In some embodiments, based on an IC layout diagram, (A) one or more semiconductor masks and / or (B) at least one component in a layer of a semiconductor integrated circuit are manufactured using the manufacturing tool 700. The manufacturing tool 700 and the associated manufacturing process may be used to perform all or part of the method 400 described above with reference to Fig. 4 to 5P has been discussed.

[0146] In Fig. 7, the IC manufacturing facility 700 includes multiple units, such as a design house 720, a mask house 730, and an IC manufacturer ("microchip fab") 750, that interact with each other in the design, development, and manufacturing cycles and / or services associated with the manufacture of an IC device 760. The units in the facility 700 are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network includes many different networks, such as an intranet and the Internet. The communications network includes wired and / or wireless communications channels. Each unit interacts with one or more of the other units and provides and / or receives services to one or more of the other units.In some embodiments, two or more of the design house 720, mask house 730, and IC factory 750 units are owned by a single larger company. In some embodiments, two or more of the design house 720, mask house 730, and IC factory 750 units coexist in a common facility and share common resources.

[0147] The design house (or design team) 720 generates an IC design layout diagram 722. The IC design layout diagram 722 contains various geometric structures. The geometric structures correspond to structures of metal, oxide, or semiconductor layers that form the various components of the IC device 760 to be manufactured. The various layers together form various IC structural elements. For example, a portion of the IC design layout diagram 722 includes various IC structural elements, such as an active area, a gate electrode, a source and drain, metal lines or vias, an interlayer interconnect, and openings for bond pads to be manufactured in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design house 720 implements an appropriate design method for generating the IC design layout diagram 722.The design process includes a logic design, a physical design, or placement and routing. The IC design layout diagram 722 is represented in one or more data files containing information about the geometric structures. The IC design layout diagram 722 is represented, for example, in a GDSII file format or a DFII file format.

[0148] In the mask house 730, data preparation 732 and mask fabrication 744 are performed. The mask house 730 uses the IC design layout diagram 722 to create one or more masks 745 to be used for fabricating the various layers of the IC device 760 according to the IC design layout diagram 722. The mask house 730 performs data preparation 732, in which the IC design layout diagram 722 is translated into a representative data file (RDF). During mask data preparation 732, the RDF is provided for mask fabrication 744. A mask writer is used during mask fabrication 744. A mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 745 or a semiconductor wafer 753.The design layout diagram 722 is manipulated by the mask data preparation 732 to conform to certain characteristics of the mask writer and / or to meet requirements of the IC factory 750. In . Fig. 7, mask data preparation 732 and mask fabrication 744 are depicted as separate elements. In some embodiments, mask data preparation 732 and mask fabrication 744 may be collectively referred to as mask data preparation.

[0149] In some embodiments, mask data preparation 732 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image defects, such as those that may arise from diffraction, interference, other process effects, and the like. OPC adjusts IC design layout diagram 722. In some embodiments, mask data preparation 732 includes further resolution enhancement techniques (RETs), such as off-axis exposure, partial resolution assist elements, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0150] In some embodiments, during mask data preparation 732, a mask rule checker (MRC) checks the IC design layout diagram 722, which has undergone processes in the OPC, against a set of mask generation rules that include certain geometric and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes and the like. To comply with the mask generation rules, in some embodiments, the MRC modifies the IC design layout diagram 722 to compensate for constraints during mask fabrication 744 that may undo some of the modifications performed by the OPC.

[0151] In some embodiments, mask data preparation 732 includes a lithography process (LPC) test that simulates the processing implemented by IC fabrication shop 750 to fabricate IC device 760. In LPC, this processing is simulated based on IC design layout diagram 722 to produce a simulated fabricated device, such as IC device 760. The processing parameters in LPC simulation may include: parameters associated with various processes of the IC manufacturing cycle; parameters associated with tools used to manufacture ICs; and / or other aspects of the manufacturing process. LPC considers various factors, such as inter-image contrast, depth of field (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof.In some embodiments, if after fabricating a simulated fabricated device by LPC, the simulated device deviates too much in shape from compliance with the design rules, the OPC and / or the MRC may need to be repeated to further improve the IC design layout diagram 722.

[0152] It should be understood that the above description of mask data preparation 732 has been simplified for clarity. In some embodiments, mask data preparation 732 includes additional elements, such as a logic operation (LOP), to modify IC design layout diagram 722 according to manufacturing rules. Furthermore, the processes used on IC design layout diagram 722 during mask data preparation 732 can be performed in a variety of other orders.

[0153] After mask data preparation 732 and during mask fabrication 744, a mask 745 or a group of masks 745 is fabricated based on the modified IC design layout diagram 722. In some embodiments, mask fabrication 744 includes performing one or more lithographic exposures based on the IC design layout diagram 722. In some embodiments, an electron beam or a multiple electron beam mechanism is used to create a pattern on a mask (photomask or reticle) 745 based on the modified IC design layout diagram 722. The masks 745 can be fabricated using various technologies. In some embodiments, the mask 745 is fabricated using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions.A radiation beam, such as an ultraviolet (UV) or EUV beam, used to expose the photosensitive material layer (e.g., photoresist) deposited on a wafer is blocked by the opaque region and passes through the transparent regions. In one example, a binary mask variant of the mask 745 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) deposited in the opaque regions of the mask. In another example, the mask is fabricated using phase-shifting technology. In a phase-shifting mask (PSM) variant of the mask 745, various elements in the structure created on the phase-shifting mask are configured to have a phase difference suitable for improving resolution and image quality.In various examples, the phase-shift mask may be an attenuated phase-shift mask or a variable phase-shift mask. The masks produced by mask fabrication 744 are used in many different processes. Such masks are used, for example, in an ion implantation process for creating various doped regions in semiconductor wafer 753, in an etching process for creating various etch regions in semiconductor wafer 753, and / or in other suitable processes.

[0154] The IC fab 750 is an IC manufacturing company that has one or more manufacturing facilities for producing many different IC products. In some embodiments, the IC fab 750 is a semiconductor fabrication facility. For example, there may be one facility for front-end assembly (FEOL) of a plurality of IC products, a second facility may perform back-end assembly (BEOL) for interconnecting and packaging the IC products, and a third facility may provide other services for the manufacturing operation.

[0155] The IC fab 750 uses wafer fabrication tools 752 configured to perform various manufacturing operations on the semiconductor wafer 753 such that the IC device 760 is fabricated according to the one or more masks, e.g., the mask 745. In various embodiments, the fabrication tools 752 include a wafer stepper, an ion implantation tool, a photoresist coating tool, a process chamber, e.g., a CVD chamber or an LPCVD (low pressure CVD) furnace, a CMP tool, a plasma etch tool, a wafer cleaning tool, and / or other fabrication facilities capable of performing one or more suitable fabrication processes discussed herein.

[0156] The IC fabrication shop 750 uses the masks 745 manufactured by the mask house 730 to manufacture the IC device 760. Thus, the IC fabrication shop 750 at least indirectly uses the IC design layout diagram 722 to manufacture the IC device 760. In some embodiments, the semiconductor wafer 753 is manufactured by the IC fabrication shop 750 using one or more masks 745 to manufacture the IC device 760. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on the IC design layout diagram 722. The semiconductor wafer 753 comprises a silicon substrate or other suitable substrate on which material layers are fabricated. The semiconductor wafer 753 further includes one or more different doped regions, dielectric features, multilevel interconnects, and the like (which are formed in later manufacturing steps).

[0157] In some embodiments, an IC package includes: a transmitter and / or a receiver disposed in a semiconductor die and having a signal terminal; a pad disposed on a first surface of the semiconductor die, the pad electrically connected to the signal terminal; a passivation layer disposed on the first surface and having a first opening aligned with the pad; a first PPI layer having a conductive path electrically connected to the pad; a second PPI layer having an antenna structure electrically connected to the conductive path; and a substrate disposed on a second surface of the semiconductor die opposite the passivation layer, the substrate including a plurality of TSVs electrically connected to the transmitter and / or the receiver. In some embodiments, the antenna structure comprises a patch antenna or a dipole antenna.In some embodiments, the IC package further comprises: a first insulating layer disposed on the passivation layer, wherein the conductive path is disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer, wherein the antenna structure is disposed on the second insulating layer; and a third insulating layer disposed on the second insulating layer and having a second opening aligned with the antenna structure. In some embodiments, the IC package further comprises a PCB bonded to the substrate and including a plurality of conductive traces electrically connected to the plurality of TSVs. In some embodiments, the transmitter and / or the receiver are configured to receive a supply voltage and one or more control signals via the plurality of TSVs.In some embodiments, the transmitter and / or the receiver each comprise a transmitter and a receiver, and a switching device connected between the signal terminal and each of the transmitter and the receiver; and a transceiver configured to perform time division duplexing. In some embodiments, the transmitter and / or the receiver are configured to operate at a frequency of 130 GHz to 174.8 GHz. In some embodiments, the semiconductor die, the first and second PPI layers, and the substrate are configured as a WLCSP.

[0158] In some embodiments, an IC package comprises: a plurality of transceivers arranged in a semiconductor die; a plurality of pads arranged on a first surface of the semiconductor die, each pad of the plurality of pads electrically connected to a signal terminal of a corresponding one of the plurality of transceivers; a passivation layer arranged on the first surface and having a plurality of first openings aligned with corresponding pads of the plurality of pads; a first PPI layer having a plurality of network paths electrically connected to corresponding pads of the plurality of pads; a second PPI layer having an antenna array including a plurality of plates electrically connected to corresponding paths of the plurality of network paths; and a substrate,disposed on a second surface of the semiconductor die opposite the passivation layer, wherein the substrate includes a plurality of TSVs electrically connected to the plurality of transceivers. In some embodiments, the IC package further comprises: a first insulating layer disposed on the passivation layer, wherein the plurality of network paths are disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer, wherein the plurality of plates of the antenna array are disposed on the second insulating layer; and a third insulating layer disposed on the second insulating layer and having a plurality of second openings aligned with corresponding plates of the plurality of plates. In some embodiments, the plurality of plates has a phased array architecture with columns of plates,which are spaced according to a pitch of half a wavelength of a transmission signal; and the plurality of transceivers are configured to perform a beamforming operation on the transmission signal using the antenna array. In some embodiments, the plurality of transceivers are configured to output the transmission signal at a frequency of 140 GHz. In some embodiments, the IC package further comprises a PCB bonded to the substrate and including a plurality of conductive traces electrically connected to the plurality of TSVs, wherein the plurality of TSVs are configured to distribute a supply voltage and one or more control signals to the plurality of transceivers. In some embodiments, each transceiver of the plurality of transceivers includes a switching device,which is connected between the corresponding signal terminal and a transmitter and a receiver, respectively, wherein the plurality of transceivers are configured to perform time division duplex operation. In some embodiments, the semiconductor die, the first and second PPI layers, and the substrate are configured as a WLCSP.

[0159] In some embodiments, a method of manufacturing an IC package comprises: forming a CMOS layer with a transmitter and / or a receiver on a substrate, wherein the transmitter and / or the receiver have a signal terminal; forming a pad and a passivation layer on the CMOS layer, wherein forming the pad comprises establishing an electrical connection between the signal terminal and the pad; forming a first insulating layer and a first metal layer on the passivation layer, wherein the first metal layer includes a conductive path electrically connected to the pad; forming a second insulating layer and a second metal layer on the first metal layer, wherein the second metal layer includes an antenna structure electrically connected to the conductive path;Forming a third insulating layer on the second metal layer, the third insulating layer having an opening aligned with the antenna structure; and forming a TSV in the substrate, the TSV being electrically connected to the transmitter and / or the receiver. In some embodiments, forming the CMOS layer with the transmitter and / or the receiver on the substrate comprises forming a plurality of transmitters including the transmitter; the plurality of transmitters has a plurality of signal terminals including the signal terminal; forming the second metal layer comprises forming a plurality of antenna structures including the antenna structure;and each antenna structure of the plurality of antenna structures is electrically connected to a signal terminal of the plurality of signal terminals. In some embodiments, the method further comprises bonding the substrate to a PCB. In some embodiments, the TSV is formed before the CMOS layer is formed. In some embodiments, the third insulating layer is formed before the TSV is formed.

[0160] Features of various embodiments have been described above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other methods and structures for achieving the same objectives and / or obtaining the same benefits as the embodiments presented herein. Those skilled in the art will also appreciate that such equivalent interpretations do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

[1] Integrated circuit package (IC package) with: a transmitter and / or a receiver arranged in a semiconductor die and having a signal terminal; a pad disposed on a first surface of the semiconductor die, the pad being electrically connected to the signal terminal; a passivation layer disposed on the first surface and having a first opening aligned with the pad; a first post-passivation interconnect (PPI) layer having a conductive path electrically connected to the pad; a second PPI layer having an antenna structure electrically connected to the conductive path; and a substrate disposed on a second surface of the semiconductor die opposite the passivation layer, the substrate having a plurality of substrate vias (TSVs) electrically connected to the transmitter and / or the receiver. [2] The IC package of claim 1, wherein the antenna structure comprises a patch antenna or a dipole antenna. [3] The IC package of claim 1 or 2, further comprising: a first insulating layer disposed on the passivation layer, wherein the conductive path is disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer, wherein the antenna structure is disposed on the second insulating layer; and a third insulating layer disposed on the second insulating layer and having a second opening aligned with the antenna structure. [4] The IC package of any preceding claim, further comprising a printed circuit board (PCB) bonded to the substrate and including a plurality of conductive traces electrically connected to the plurality of TSVs. [5] The IC package of any preceding claim, wherein the transmitter and / or the receiver are configured to receive a supply voltage and one or more control signals via the plurality of TSVs. [6] IC package according to one of the preceding claims, wherein the transmitter and / or the receiver each comprise a transmitter and a receiver and a switching device connected between the signal terminal and each of the transmitter and the receiver, and a transceiver is configured to perform time division duplex operation. [7] IC package according to one of the preceding claims, wherein the transmitter and / or the receiver are arranged to operate at a frequency of 130 GHz to 174.8 GHz. [8] The IC package according to any one of the preceding claims, wherein the semiconductor die, the first and second PPI layers and the substrate are configured as a wafer-level chip-scale package (WLCSP). [9] Integrated circuit package (IC package) with: a plurality of transceivers arranged in a semiconductor die; a plurality of pads arranged on a first surface of the semiconductor die, each pad of the plurality of pads being electrically connected to a signal terminal of a corresponding one of the plurality of transceivers; a passivation layer disposed on the first surface and having a plurality of first openings aligned with corresponding pads of the plurality of pads; a first post-passivation interconnect (PPI) layer having a plurality of network paths electrically connected to corresponding pads of the plurality of pads; a second PPI layer having an antenna array including a plurality of plates electrically connected to corresponding paths of the plurality of network paths; and a substrate disposed on a second surface of the semiconductor die opposite the passivation layer, the substrate having a plurality of substrate vias (TSVs) electrically connected to the plurality of transceivers. [10] The IC package of claim 9, further comprising: a first insulating layer disposed on the passivation layer, wherein the plurality of network paths are disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer, wherein the plurality of plates of the antenna array are disposed on the second insulating layer; and a third insulating layer disposed on the second insulating layer and having a plurality of second openings aligned with corresponding plates of the plurality of plates. [11] IC package according to claim 9 or 10, wherein the plurality of plates has a phased array architecture with columns of plates spaced according to a pitch of half a wavelength of a transmission signal, and the plurality of transceivers are configured to perform a beamforming operation on the transmission signal using the antenna array. [12] The IC package according to any one of claims 9 to 11, wherein the plurality of transceivers are arranged to output the transmission signal at a frequency of 140 GHz. [13] The IC package of any one of claims 9 to 12, further comprising: a printed circuit board (PCB) bonded to the substrate and including a plurality of conductive traces electrically connected to the plurality of TSVs, wherein the plurality of TSVs are configured to distribute a supply voltage and one or more control signals to the plurality of transceivers. [14] IC package according to one of claims 9 to 13, wherein each transceiver of the plurality of transceivers has a switching device connected between the corresponding signal terminal and a transmitter and a receiver, respectively, and the plurality of transceivers are configured to perform time division duplex operation. [15] The IC package according to any one of claims 9 to 14, wherein the semiconductor die, the first and second PPI layers and the substrate are configured as a wafer-level chip-scale package (WLCSP). [16] A method of manufacturing an integrated circuit (IC) package, comprising: Producing a complementary metal oxide semiconductor (CMOS) layer having a transmitter and / or a receiver on a substrate, wherein the transmitter and / or the receiver have a signal terminal; Forming a pad and a passivation layer on the CMOS layer, wherein forming the pad comprises forming an electrical connection between the signal terminal and the pad; Forming a first insulating layer and a first metal layer on the passivation layer, the first metal layer including a conductive path electrically connected to the pad; forming a second insulating layer and a second metal layer on the first metal layer, the second metal layer including an antenna structure electrically connected to the conductive path; Forming a third insulating layer on the second metal layer, the third insulating layer having an opening aligned with the antenna structure; and Forming a substrate via (TSV) in the substrate, wherein the TSV is electrically connected to the transmitter and / or the receiver. [17] The method of claim 16, wherein producing the CMOS layer with the transmitter and / or the receiver on the substrate comprises producing a plurality of transmitters containing the transmitter, the plurality of transmitters has a plurality of signal terminals including the signal terminal, producing the second metal layer comprises producing a plurality of antenna structures containing the antenna structure, and each antenna structure of the plurality of antenna structures is electrically connected to a signal terminal of the plurality of signal terminals. [18] The method of claim 16 or 17, further comprising bonding the substrate to a printed circuit board (PCB). [19] The method of any one of claims 16 to 18, wherein the TSV is formed prior to the CMOS layer being formed. [20] The method of any one of claims 16 to 19, wherein the third insulating layer is formed prior to the formation of the TSV.

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