Semiconductor device and method for its manufacture

Abstract

One process involves fabricating a three-layer etch stop layer over a source / drain, for example, with the following steps: fabricating a nitrogen-free dielectric low-k layer on the source / drain; fabricating an oxygen-treated dielectric low-k layer on the nitrogen-free dielectric low-k layer; and fabricating a dielectric layer on the oxygen-treated dielectric low-k layer. The nitrogen-free dielectric low-k layer has a first dielectric constant, the oxygen-treated dielectric low-k layer has a second dielectric constant that is higher than the first dielectric constant, and the dielectric layer has a third dielectric constant that is higher than both the second and the first dielectric constants.The process may further include: producing an intermediate dielectric layer (ILD layer) over the three-layer etch stop layer; removing part of the three-layer etch stop layer and part of the ILD layer to create a source / drain contact opening that exposes the source / drain; and producing a source / drain contact structure in the source / drain contact opening.

Description

[0001] The present document is a non-provisional application relating to the provisional US patent application filed on June 3, 2024, with file number 63 / 655,198, which is incorporated by reference into the present application and whose priority the present application claims. background

[0002] The IC (integrated semiconductor circuit) industry has experienced exponential growth. Technological advances in IC materials and designs have spawned generations of ICs, each generation featuring smaller and more complex circuits than the previous one. Throughout IC evolution, feature density (i.e., the number of interconnected devices per unit area of ​​the chip) has generally increased, while feature size (i.e., the smallest component that can be produced using a manufacturing process) has decreased. This miniaturization process generally offers advantages by increasing production efficiency and reducing associated costs. However, this miniaturization has also increased the complexity of machining and manufacturing ICs, and similar advancements in IC materials and fabrication are necessary to realize these improvements. Brief description of the drawings

[0003] The present disclosure is best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not drawn to scale and are shown for illustrative purposes only. Rather, the dimensions of the various elements may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is a complete or partial flowchart of a process for producing a source / drain contact structure according to various aspects of the present disclosure. The Fig. Figures 2 to 15 are complete or partially schematic cross-sectional views of a device at various stages of the fabrication of a source / drain contact structure, such as those produced by the method of Fig. 1 are associated, according to various aspects of the present revelation. The Fig. 16A and Fig. 16B are complete or partially schematic cross-sectional views of the device of Fig. 15 according to various aspects of the present revelation. The Fig. Figures 17 to 24 are complete or partially schematic cross-sectional views of other configurations of a device 100 after fabrication of a source / drain contact structure, such as those produced by the method of Fig. 1 are associated, according to various aspects of the present revelation. Detailed description

[0004] The present disclosure relates generally to the production of source / drain contacts and in particular to etch stop layers that are implemented in the production of the source / drain contacts.

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact.Furthermore, spatially relative terms such as "lower," "upper," "horizontal," "vertical," "above," "over," "below," "under," "upward," "downward," "above," "below," etc., as well as their derivatives (e.g., the adverbs "horizontal," "downward," "upward," etc.) are used here to easily describe the relationship of one element to another in the present disclosure. These spatially relative terms are intended to cover different orientations of the device incorporating the elements. Reference numerals and / or letters may also be repeated in the various examples in the present disclosure. This repetition serves the purpose of simplicity and clarity and does not, in itself, prescribe a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, when a number or range of numbers is described using terms such as "about," "approximately," "essentially," and the like, the term shall encompass numbers that are within a reasonable range, taking into account variations that are inherent in manufacturing processes, as understood by a person skilled in the art. For example, the number or range of numbers encompasses a reasonable range containing the stated number, such as within ±10% of the stated number, and is based on known manufacturing tolerances associated with the production of an element that has a property associated with the number. For example, a material layer thickness of "about 5 nm" may encompass a dimensional range of 4.5 nm to 5.5 nm, where a person skilled in the art understands manufacturing tolerances associated with the deposition of a material layer to be ±10%.Considering the variations inherent in a manufacturing process, when device elements are described as having "essential" properties and / or characteristics, this term should encompass properties and / or characteristics that are within the tolerances of the manufacturing processes. For example, "essentially vertical" or "essentially horizontal" elements should include elements that are approximately vertical or horizontal, respectively, within given tolerances of the manufacturing processes used to produce these elements, but are not mathematically or absolutely vertical or horizontal.

[0007] Etch stop layers (ESLs), also known as contact etch stop layers (CESLs), are frequently implemented to protect underlying layers and / or structural elements during semiconductor device fabrication. Creating a source / drain contact, for example, might involve: fabricating an ESL over a source / drain; fabricating an interlayer dielectric (ILD) layer over the ESL; creating a source / drain contact opening that extends through the ILD layer and the ESL to expose the source / drain; and creating a source / drain contact within the source / drain contact opening. The ESL can protect the source / drain when the ILD layer is etched to create the source / drain contact opening. Because the ESL is often placed over the source / drain and / or between the source / drain contact and a gate structure (e.g., a gate), it is possible to create a source / drain contact within the source / drain contact opening.If the effect of the ESL on the manufactured semiconductor device (e.g., a gate stack with gate spacers arranged along its side walls) remains, then an ESL design, such as an ESL composition and an ESL fabrication, must take into account the effect of the ESL on the manufactured semiconductor device.

[0008] The present disclosure provides a three-layer ESL over a source / drain and a method for its fabrication, which minimizes and / or prevents unwanted oxidation of the source / drain during ESL fabrication and / or subsequent fabrication of a semiconductor device. The disclosed three-layer ESL and the disclosed method for its fabrication are also designed to minimize the dielectric constant of dielectric materials between electrically conductive structural elements of the semiconductor device (e.g., between a source / drain contact and a gate stack of the semiconductor device and / or between the source / drain and the gate stack), thereby reducing the parasitic capacitance between them and improving the overall device performance (e.g., device speed).Details of the proposed three-layer etch stop layer over a source / drain are described here, along with methods for its fabrication. Different embodiments may have different advantages, and no particular advantage for any one embodiment is required.

[0009] Fig. Figure 1 is a complete or partial flowchart of a process 10 for fabricating a source / drain contact structure according to various aspects of the present disclosure. In a block 15, the process 10 comprises fabricating a three-layer ESL over a source / drain. The block 15 may include: fabricating a nitrogen-free dielectric low-k layer (e.g., a silicon oxycarbide layer) on the source / drain in a block 20; fabricating an oxygen-treated dielectric low-k layer (e.g., a silicon oxycarbide layer and a silicon oxide carbonitride layer) on the nitrogen-free dielectric low-k layer in a block 25; and fabricating a dielectric layer (e.g., a silicon nitride layer) on the oxygen-treated dielectric low-k layer in a block 30.The fabrication of the nitrogen-free dielectric low-k layer, the oxygen-treated dielectric low-k layer, and the dielectric layer can be configured to provide a three-layer ESL with a dielectric constant increasing from bottom to top and a nitrogen-free portion with a low dielectric constant connected to the source / drain. To prevent source / drain oxidation, the nitrogen-free dielectric low-k layer and the oxygen-treated dielectric low-k layer are fabricated using short, low-temperature deposition processes. Fabrication of the oxygen-treated dielectric low-k layer can involve depositing a dielectric low-k layer onto the nitrogen-free dielectric low-k layer and performing an oxygen treatment of the dielectric low-k layer after deposition.To avoid source / drain oxidation, no oxygen treatment is performed between the deposition of the nitrogen-free dielectric low-k layer and the deposition of the dielectric low-k layer, and the nitrogen-free dielectric low-k layer and the dielectric low-k layer can be deposited in the same process chamber (e.g., to limit and / or prevent exposure of the nitrogen-free dielectric low-k layer to an oxygen environment prior to the deposition of the dielectric low-k layer, which can occur when an apparatus is transported between process chambers). In block 35, method 10 comprises fabricating an ILD layer over the three-layer ESL. In block 40, method 10 comprises removing a portion of the three-layer ESL and a portion of the ILD layer to create a source / drain contact opening that exposes the source / drain.In block 45, method 10 comprises fabricating a source / drain contact structure in the source / drain contact opening. Further steps may be provided before, during, and after method 10, and some of the described steps may be deferred, replaced, or omitted in further embodiments of method 10. The following discussion describes devices that have source / drain structures fabricated according to method 10.

[0010] The Fig. Figures 2 to 15 are complete or partially schematic sectional views of a device 100 at various stages of the fabrication of a source / drain contact structure (such as those produced by method 10 of Fig. 1 are associated), according to various aspects of the present revelation. The Fig. 16A and Fig. 16B are complete or partially schematic sectional views of the device 100 along a line A - A or a line B - B of Fig. 15 according to various aspects of the present revelation. The Fig. Figures 17 to 24 are complete or partially schematic sectional views of various embodiments with different configurations of the device 100 according to various aspects of the present disclosure. The device 100 may comprise at least one transistor, such as a gate-all-around transistor (GAA transistor), i.e., a transistor with a gate that at least partially encloses one or more floating channels (e.g., one or more nanowires, one or more nanosheets, one or more nanobars, or the like) and extends between source and drains. The device 100 may be contained within a microprocessor, a memory, another IC device, or combinations thereof.In some embodiments, the device 100 is part of an IC chip, a system-on-chip (SoC), or part thereof, and it may contain various passive and / or active electronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary MOS transistors (CMOS transistors) (comprising, for example, an n-type transistor and a p-type transistor), bipolar transistors (BITs), side-diffused MOS transistors (LDMOS transistors), high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. Fig. For the sake of clarity, Figures 2 to 15, 16A and 16B, and 17 to 24 have been simplified to make the inventive concepts of the present disclosure more readily understandable. Further elements can be added to the device 100, and some of the elements described below can be replaced, modified, or omitted in other embodiments of the device 100.

[0011] In Fig. 2. A device precursor for the device 100 can be manufactured and / or received, which can then be processed as described here to produce a source / drain contact structure. The device 100 can comprise: a substrate 105; a mesa 105'; a multilayer stack 110 (containing, for example, mesas 105P', sacrificial layers 115, and semiconductor layers 120) in channel regions (C) of the device 100; substrate isolation structures 125 (see, for example, the Fig. 15A and Fig. 15B); and gate structures 128. In the illustrated embodiment, gate structures each comprise a dummy gate stack 130 and gate spacers 132. The device 100 may further comprise internal spacers 145 and source / drain structures 150, which are arranged in source / drain regions (S / D regions) of the device 100. Each source / drain structure 150 may be multilayered and, for example, comprise a semiconductor layer 152, an insulating layer 154, a semiconductor layer 156, and a semiconductor layer 158.

[0012] The substrate 105 and the mesa 105' (and the mesas 105P') contain an elemental semiconductor, such as silicon and / or germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide, or combinations thereof; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof; or combinations thereof. In some embodiments, the substrate 105 is a silicon substrate. In some embodiments, the substrate 105 is a semiconductor-on-insulator substrate, such as an SOI substrate (SOI: silicon on insulator), an SGOI substrate (SGOI: silicon germanium on insulator), or a GOI substrate (GOI: germanium on insulator). The substrate 105 (and the mesa 105') can have various doped regions, such as p-doped regions (p-wells), n-doped regions (n-wells) or combinations thereof.N-doped regions contain n-doped atoms, such as phosphorus, arsenic, other n-doped atoms, or combinations thereof. P-doped regions contain p-doped atoms, such as boron, indium, gallium, other p-doped atoms, or combinations thereof. In some embodiments, the doped regions contain both p- and n-doped atoms. The doped regions can be created on and / or in the substrate 105 and / or the mesa 105', thereby providing, for example, a p-well structure, an n-well structure, a double-well structure, a raised structure, another suitable structure, or combinations thereof. In some embodiments, the substrate 105 and / or the mesa 105' and overlying semiconductor layers can have an n-well and / or a p-well. The substrate 105, the Mesa 105' and / or the Mesas 105P' can, for example, have a p-well in an n-transistor area and an n-well in a p-transistor area.

[0013] The sacrificial layers 115 and the semiconductor layers 120 are stacked vertically (e.g., along the z-direction) from a top surface of the substrate 105 in a nested and / or alternating configuration. The composition of the sacrificial layers 115 differs from that of the semiconductor layers 120 to achieve etch selectivity. For example, the sacrificial layers 115 and the semiconductor layers 120 may have different materials, constituent percentage atomic fractions, constituent percentage mass fractions, other properties, or combinations thereof to achieve etch selectivity. In some embodiments, the sacrificial layers 115 contain silicon germanium, the semiconductor layers 120 contain silicon, and for a given etchant, the etching rate of the semiconductor layers 120 differs from that of the sacrificial layers 115.In some embodiments, the sacrificial layers 115 and the semiconductor layers 120 contain the same material but different constituent percentage atomic fractions. For example, the sacrificial layers 115 and the semiconductor layers 120 may contain silicon germanium, but with different percentage germanium atom fractions. In some embodiments, the sacrificial layers 115 are dielectric layers (e.g., they may be oxide layers), and the semiconductor layers 120 are silicon layers to provide etch selectivity. The sacrificial layers 115 and the semiconductor layers 120 may contain a combination of materials that provide desired etch selectivity, desired differences in oxidation rates, desired performance characteristics, or combinations thereof (e.g., materials that maximize current flow), including, but not limited to, the materials disclosed herein.

[0014] The semiconductor layers 120, or parts thereof, can form channels for transistors of the device 100. In Fig. Figure 2 contains a multilayer stack 110 comprising three sacrificial layers 115 and three semiconductor layers 120. The multilayer stack 110 thus contains three pairs of semiconductor layers arranged over the substrate 105, each pair comprising one sacrificial layer 115 and one semiconductor layer 120. After processing the multilayer stack 110, this configuration can result in three-channel transistors. However, in some embodiments, the multilayer stack 110 contains other numbers of semiconductor layers 120, depending, for example, on the number of channels desired for transistors of the device 100 and / or on design requirements of the device 100. The multilayer stack 110 can, for example, contain two to six pairs of semiconductor layers, each pair comprising one sacrificial layer 115 and one semiconductor layer 120.

[0015] Adjacent to and around a lower part of the multilayer stack 110 (e.g., its mesas 105P'), substrate isolation structures 125 can be fabricated, and the device 100 (e.g., the multilayer stacks 110 in their channel regions and / or the source / drain structures 150 in their source / drain regions) can be separated by the substrate isolation structures 125 from other devices and / or from device regions of the substrate isolation structures 125. The substrate isolation structures 125 can electrically isolate an active device region (e.g., the mesas 105P' and / or the source / drain structures 150) from other device regions. The substrate isolation structures 125 contain silicon oxide, silicon nitride, silicon oxide nitride, other suitable insulating materials (such as silicon, oxygen, nitrogen, carbon, other suitable insulating components, or combinations thereof), or combinations thereof.The substrate insulation structures 125 can have a multilayer structure. For example, the substrate insulation structures 125 can have a solid dielectric (e.g., an oxide layer) over a dielectric coating (e.g., silicon nitride, silicon oxide, silicon nitride oxide, silicon carbonitride oxide, or combinations thereof). In another example, the substrate insulation structures 125 can have a solid dielectric over a doped coating, such as a BSG coating (BSG: borosilicate glass) and / or a PSG coating (PSG: phosphosilicate glass). The dimensions and / or properties of the substrate insulation structures 125 can be configured to provide STI structures (STI: shallow trench insulation), DTI structures (DTI: deep trench insulation), LOCOS structures (LOCOS: local oxidation of silicon), other suitable insulation structures, or combinations thereof.

[0016] Gate structures 128 can be fabricated above channel regions (C) of the device 100 (e.g., the multilayer stack 110) and between respective source / drain regions (S / D) of the device 100 (e.g., the source / drain structures 150). As described, the gate structures 128 can each contain a dummy gate stack 130 and respective gate spacers 132. The dummy gate stacks 130 extend longitudinally along a direction different from a longitudinal direction of the multilayer stack 110 (e.g., perpendicular to it). For example, the dummy gate stacks 130 extend along the y-direction, having a length along the y-direction, a width along the x-direction, and a height along the z-direction. The dummy gate stacks 130 can extend substantially parallel to each other. Fig. 2 (e.g., in the xz-plane), dummy gate stacks 130 are arranged on respective channel regions of the device 100 and between respective source / drain regions of the device 100. In a sectional view along the yz-plane, the dummy gate stacks 130 can enclose respective channel regions (e.g., be arranged over their top and side walls), and in some embodiments, they can be arranged over the top surfaces of the substrate isolation structures 125.

[0017] The dummy gate stacks 130 can include a dummy gate dielectric and a dummy gate electrode. The dummy gate dielectric contains a dielectric material, such as silicon dioxide and / or another suitable dielectric material. The dummy gate electrode contains a suitable dummy gate material, such as polysilicon. The dummy gate stacks 130 can also include a hard mask, which may be configured to protect the dummy gate dielectric and / or the dummy gate electrode during processing. The hard mask layer can, for example, contain a material resistant to an etching process, such as an etching associated with creating source / drain recesses and / or an etching associated with creating source / drain contact openings, in order to protect the dummy gate dielectric and / or the dummy gate electrode. In some embodiments, the hard mask has a multi-layer structure.The hard mask may contain a suitable hard mask material.

[0018] Gate spacers 132 are manufactured adjacent to and along the side walls of the dummy gate stacks 130. The gate spacers 132 contain a dielectric material that may include silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxide nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxide carbonitride, or combinations thereof). In some embodiments, the gate spacers 132 have a multilayer structure, such as two or more dielectric layers with different compositions. In some embodiments, the gate spacers 132 comprise more than one group of spacers, such as gasket spacers, offset spacers, sacrificial spacers, dummy spacers, main spacers, or combinations thereof.In these embodiments, the different groups of spacers can have different compositions.

[0019] Internal spacers 145 are arranged beneath the gate structures 128 (e.g., beneath their gate spacers 132) and along the sidewalls of the sacrificial layers 115. The internal spacers 145 are located between the sacrificial layers 115 and the source / drain structures 150, between adjacent semiconductor layers 120, and between the bottom semiconductor layer 120 and the mesas 105P'. The internal spacers 145 contain a dielectric material comprising silicon, oxygen, carbon, nitrogen, or combinations thereof, such as silicon oxide, silicon nitride, silicon oxide nitride, silicon carbide, silicon oxide carbonitride, etc. In some embodiments, the internal spacers 145 contain a high-k dielectric material. In some embodiments, dopants (e.g. p- and / or n-dopants) are introduced into the dielectric material, and the internal spacers 145 contain one or more doped dielectric materials.

[0020] The source / drain structures 150 contain a semiconductor material; they can be doped with n- and / or p-type dopants and can have the same or different compositions and / or materials. In some embodiments, the semiconductor materials of the source / drain structures 150 are deposited by an epitaxial process, and the source / drain structures 150 are fabricated from an epitaxially grown / deposited semiconductor material. In these embodiments, the source / drain structures 150 can be referred to as epitaxial sources / drains. In some embodiments (e.g., when fabricating parts of n-transistors), the source / drain structures 150 can contain silicon doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof. In some embodiments (e.g.,(in the fabrication of parts of p-transistors) the source / drain structures 150 may contain silicon germanium doped with boron, other p-doped elements, or combinations thereof. In some embodiments, doped regions, such as heavily doped source / drain regions (HDD regions), lightly doped source / drain regions (LDD regions), other doped regions, or combinations thereof, are arranged within the source / drain structures 150. In some embodiments, doped regions, such as LDD regions, may extend into channel regions. A source / drain region, a source / drain, a source / drain structure, an epitaxial source / drain, an epitaxial source / drain element, etc., used herein, may denote a source of the device 100, a drain of the device 100, collectively a source and a drain of the device 100, or a source and / or a drain of several devices.

[0021] Each source / drain structure 150 can contain a semiconductor layer 152, an insulating layer 154, a semiconductor layer 156, and a semiconductor layer 158. The semiconductor layers 152 are arranged on the mesas 105P' and / or the substrate 105. In the illustrated embodiment, the semiconductor layers 152 contain a dopant-free semiconductor material (i.e., a semiconductor material that is essentially free of n- and p-dopeds). For example, no intentional doping is performed during the fabrication of the semiconductor layers 152, e.g., by an epitaxial growth process. The semiconductor layers 152 can therefore provide high-resistance paths on the undersides of the source / drain structures 150, thus preventing leakage current from flowing between the source / drain structures 150 through the mesas 105P' and / or the substrate 105.In some embodiments, the undoped semiconductor layers are made of silicon, germanium, silicon germanium, other suitable semiconductor materials, or combinations thereof. The semiconductor layers 152 can, for example, be dopant-free silicon layers or dopant-free silicon germanium layers.

[0022] Insulating layers 154 are arranged on the semiconductor layers 152, and the insulating layers 154 may be arranged between the semiconductor layers 158 and the semiconductor layers 152. The insulating layers 154 contain an electrically insulating material, such as a dielectric material, which can also prevent an unwanted leakage current from flowing between the source / drain structures 150 (e.g., their semiconductor layers 158) through the mesas 105P' and / or the substrate 105. In some embodiments, the insulating layers 154 contain a silicon-containing dielectric material, such as silicon nitride, silicon oxide nitride, silicon oxide carbonitride, silicon oxycarbide, silicon carbonitride, other silicon-containing dielectric materials (which may include silicon and nitrogen, carbon, oxygen, other suitable dielectric components, or combinations thereof), or combinations thereof.In some embodiments, the insulating layers 154 contain a metal-containing dielectric material, such as a metal oxide material (e.g., aluminum oxide and / or hafnium oxide) and / or a metal nitride material. In some embodiments, the insulating layers 154 contain a doped semiconductor material containing a dopant type opposite to that of the semiconductor layers 158. For example, if the source / drain structures 150 are parts of p-transistors with p-doped semiconductor layers, the insulating layers 154 may contain an n-doped semiconductor material, such as phosphorus-doped silicon. In another example, where the source / drain structures 150 are parts of n-transistors with n-doped semiconductor layers, the insulating layers 154 may contain a p-doped semiconductor material, such as boron-doped silicon.

[0023] Semiconductor layers 156 and 158 are arranged above insulating layers 154 and are connected to semiconductor layers 120. Semiconductor layers 156 can be arranged between semiconductor layers 158 and 120. In the illustrated embodiment, semiconductor layers 156 and 158 comprise a semiconductor material (e.g., silicon, germanium, silicon germanium, other suitable semiconductor materials, or combinations thereof) doped with n- and / or p-type dopants.Semiconductor layers 156 and semiconductor layers 158 can have different compositions and / or different dimensions / configurations, whereby the different compositions can be achieved with different semiconductor materials, different dopants, different constituent percentage atomic fractions, different doping concentrations, or combinations thereof. For example, semiconductor layers 158 can be heavily doped semiconductor layers, and semiconductor layers 156 can be lightly doped semiconductor layers, with the doping concentration of the heavily doped semiconductor layers being higher than that of the lightly doped semiconductor layers.In some embodiments, the semiconductor layers 156 and 158 can contain silicon doped with varying concentrations of carbon, phosphorus, arsenic, antimony, other n-doped elements, or combinations thereof. In another example, the semiconductor layers 156 and 158 can contain silicon germanium doped with varying concentrations of boron, gallium, other p-doped elements, or combinations thereof. In some embodiments, the semiconductor layers 156 and 158 contain materials and / or dopants that provide a desired tensile and / or compressive stress in the channel regions.

[0024] Prior to the fabrication of the source / drain structures 150, the multilayer stacks 110 (e.g., their mesa 105', sacrificial layers 115, and semiconductor layers 120) can extend continuously and substantially along the x-direction, having a length along the x-direction, a width along the y-direction, and a height along the z-direction. The multilayer stack 110 can be referred to as a fin, a fin structure, a fin element, an active fin region, an active area, etc. In some embodiments, the mesa 105' is a structured, projecting portion and / or an extension of the substrate 105, and the mesa 105' can be referred to as a substrate extension, a substrate fin portion, a fin portion, an etched substrate portion, etc.During the fabrication of the source / drain structures 150, the sacrificial layers 115, the semiconductor layers 120, and the mesa 105' (in some embodiments) can be removed to create source / drain recesses in the source / drain regions of the device 100 where the source / drain structures 150 are fabricated. After the creation of the source / drain recesses, which may extend into the mesa 105', portions of the multilayer stack 110 may remain in the channel regions of the device 100, these portions being able to include the mesas 105P', the sacrificial layers 115, and the semiconductor layers 120, as shown.

[0025] In the Fig. In steps 3 to 6, a three-layer etch stop layer (ESL) 160 is fabricated over the device 100, e.g., over its source / drain structures 150. The three-layer ESL 160 is configured with a combination of dielectric layers and is fabricated in such a way as to reduce and / or prevent unwanted oxidation of the source / drain structures 150 during the fabrication of the three-layer ESL 160 and / or during subsequent processing of the device 100. Furthermore, the three-layer ESL 160 and the method for its fabrication are configured to minimize the dielectric constant of the dielectric material between a subsequently fabricated source / drain contact and gate stacks of the gate structures 128 and / or between the source / drain structures 150 and the gate stacks of the gate structures 128, thereby reducing the parasitic capacitance.As outlined here, the three-layer ESL 160 contains a nitrogen-free dielectric low-k layer 162, an oxygen-treated dielectric low-k layer 164 and a dielectric layer 166.

[0026] In Fig. 3. The nitrogen-free dielectric low-k layer (NFD layer) 162 is produced over the device 100, e.g., over the gate structures 128 and the source / drain structures 150. In the illustrated embodiment, the NFD layer 162 is produced directly on the gate structures 128 and the source / drain structures 150. The NFD layer 162 has a thickness t1. The thickness t1 is less than the space between adjacent gate structures 128 (e.g., the gap s between their gate spacers 132), so that the NFD layer 162 partially fills the space (and / or the gap s). The space (and / or the gap s) can be approximately equal to the width w1 of a top surface of a respective source / drain structure 150 between the adjacent gate structures 128. In some embodiments, the thickness t1 is approximately 0.5 nm to approximately 1.5 nm.

[0027] The NFD layer 162 is made from a dielectric low-k material that is free of nitrogen. For the purposes of this disclosure, a dielectric low-k material generally means a dielectric material with a dielectric constant lower than that of silicon dioxide (k ≈ 3.9), and the NFD layer 162 is made from a nitrogen-free dielectric material with a dielectric constant lower than about 3.9. In some embodiments, the NFD layer 162 is made from a dielectric material with a dielectric constant of at least 3.6 (i.e., 3.6 ≤ k < 3.9). In some embodiments, the NFD layer 162 contains silicon, oxygen, and carbon. For example, NFD layer 162 is a silicon oxycarbide layer (SiOC layer) with a dielectric constant of about 3.6 to about 3.7 (i.e., 3.6 ≤ k ≤ 3.7).In some embodiments, the NFD layer 162 has a silicon content (Si%) of about 25 atomic percent (at%) to about 35 at%, a carbon content (C%) of about 20 at% to about 30 at%, an oxygen content (O%) of about 40 at% to about 50 at%, and a nitrogen content (N%) of less than about 1 at%. For the purposes of this disclosure, dielectric low-k materials with a nitrogen content (N%) of less than about 1 at% are considered nitrogen-free. In other words, nitrogen is not intentionally introduced into the NFD layer 162 during its manufacture (e.g., during deposition), but trace / negligible amounts of nitrogen (i.e., N% of less than about 1 at%) may inadvertently enter and / or diffuse into the NFD layer 162 during the manufacture of the device 100.A nitrogen content of more than 1 at% can undesirably lead to an NFD layer 162 with a dielectric constant greater than or equal to 3.9, thereby undesirably increasing the effective dielectric constant of the three-layer ESL 160 and negating reductions in parasitic capacitance achieved by providing an NFD layer 162 with a dielectric constant of less than 3.9.

[0028] Since the NFD layer 162 is directly fabricated on and bonded to the source / drain structures 150, oxygen contained in the NFD layer 162 can react undesirably with the source / drain structures 150 (e.g., with silicon and / or germanium contained therein) during the fabrication of the NFD layer 162 and / or during subsequent processing of the device 100, thereby undesirably oxidizing the source / drain structures 150. It is recognized in the present disclosure that these undesired reactions and the undesired oxidation can occur more readily when higher heat budgets (i.e., temperatures of more than or equal to 600 °C) are implemented during the fabrication of an ESL over a source / drain. Accordingly, in the present disclosure, the NFD layer 162 is produced using a short-duration, low-temperature deposition process (e.g.,a process in which a deposition temperature lower than approximately 600 °C and a deposition duration shorter than approximately 1 h are implemented). For example, NFD layer 162 is produced by plasma-enhanced chemical vapor deposition (PECVD), which enables low-temperature, short-duration deposition, such as with a deposition temperature lower than approximately 600 °C and a deposition duration shorter than approximately 1 h. In some embodiments, the PECVD deposition duration is approximately 6 min (0.1 h) to approximately 1 h. Higher deposition temperatures, such as those greater than 600 °C, and / or longer deposition durations, such as those greater than 1 h, may lead to undesirable source / drain oxidation.For example, deposition temperatures above 600 °C can trigger reactions between oxygen (such as the oxygen in the NFD layer 162) and source / drain structures 150 and / or increase the reaction rate between oxygen and source / drain structures 150. Deposition durations exceeding 1 h can allow reactions between oxygen (such as that in the NFD layer 162) and source / drain structures 150 to occur, leading to undesired source / drain oxidation. The proposed short-duration, low-temperature deposition of the NFD layer 162 thus reduces reactions between oxygen and source / drain structures 150, thereby reducing source / drain oxidation. In some embodiments, the PECVD process generates a plasma containing at least silicon, oxygen, and carbon. In some embodiments, the plasma also contains hydrogen.The plasma can be generated by introducing one or more deposition precursor gases containing silicon, carbon, oxygen, or combinations thereof [e.g., trimethylsilane, methyltriethoxysilane, oxygen (O2), other precursors, or combinations thereof] and a carrier gas (e.g., an inert gas) into a process chamber and by generating a silicon-, carbon-, and oxygen-containing plasma from it using radio frequency (RF) power and / or direct current (DC) power. PECVD parameters (e.g., deposition temperature, deposition time, deposition gases, pressure, power, bias, etc.) can be adjusted to minimize source / drain oxidation, provide an NFD 162 layer with a dielectric constant of less than approximately 3.9, provide an NFD 162 layer with an oxygen content of less than approximately 50 at%, or combinations thereof.

[0029] In the Fig. 4 and Fig. 5 a dielectric low-k layer (LKD layer) 164' is produced above the NFD layer 162 ( Fig. 4), and an oxygen treatment 165 is then carried out on the LKD layer 164' ( Fig. 5), resulting in an oxygen-treated LKD layer 164. In the illustrated embodiment, the oxygen-treated LKD layer 164 is produced directly on the NFD layer 162. The LKD layer 164' and the oxygen-treated LKD layer 164 have a thickness t2. The thickness t2 is smaller than the gap between the adjacent gate structures 128, so that the oxygen-treated LKD layer 164 also partially fills the gap (and / or the gap s) between them. The sum of the thickness t2 and the thickness t1 is smaller than the gap between the adjacent gate structures 128. The thickness t2 can be equal to, greater than, or less than the thickness t1. In some embodiments, the thickness t2 is approximately 0.5 nm to approximately 1.5 nm.

[0030] The oxygen-treated LKD layer 164 is made from a dielectric low-k material, which may or may not be nitrogen-free. In the illustrated embodiment, the oxygen-treated LKD layer 164 is made from a dielectric material with a dielectric constant higher than that of the dielectric material of the NFD layer 162. In other words, the dielectric constant of the oxygen-treated LKD layer 164 is higher than that of the NFD layer 162. In some embodiments, the oxygen-treated LKD layer 164 is made from a dielectric material having a dielectric constant of less than about 3.9, such as a dielectric constant of about 3.6 to about 3.9 (i.e., 3.6 ≤ k < 3.9). In these embodiments, the oxygen-treated LKD layer 164 can be a nitrogen-free layer.The oxygen-treated LKD layer 164 contains, for example, silicon, oxygen, and carbon, and is a silicon oxycarbide layer (SiOC layer). In these embodiments, the oxygen content of the oxygen-treated LKD layer 164 is higher than the oxygen content of the NFD layer 162. In some embodiments, the carbon content of the oxygen-treated LKD layer 164 differs from (e.g., is lower than) the carbon content of the NFD layer 162. In some embodiments, the oxygen-treated LKD layer 164 has a silicon content (Si%) of about 25 at% to about 35 at%, a carbon content (C%) of about 5 at% to about 15 at%, and an oxygen content (O%) of about 55 at% to about 70 at%. In these embodiments, the oxygen-treated LKD layer 164 may have a nitrogen content lower than about 1 at%. In some embodiments, the oxygen-treated LKD layer contains 164 nitrogen (i.e.The oxygen-treated LKD layer 164 has a nitrogen content greater than 1 at%. The oxygen-treated LKD layer 164 contains, for example, silicon, nitrogen, oxygen, and carbon. In this example, the oxygen-treated LKD layer 164 can be a SiOCN layer (SiOCN: silicon dioxide carbonitride) with a dielectric constant greater than 3.9 (e.g., k ≈ 4.3).

[0031] In Fig. 4. To minimize source / drain oxidation, the LKD layer 164' is also produced using a short-duration, low-temperature deposition process (e.g., a deposition process implementing a deposition temperature of less than approximately 600 °C and a deposition duration of less than approximately 1 h). For example, the LKD layer 164' is also produced by PECVD, which enables short-duration, low-temperature deposition. In some embodiments, the PECVD deposition temperature is approximately 200 °C to approximately 600 °C. In some embodiments, the PECVD deposition duration is approximately 6 min to approximately 1 h. Higher deposition temperatures, such as those exceeding 600 °C, and / or longer deposition durations, such as those exceeding 1 h, for the LKD layer 164' may lead to undesirable source / drain oxidation.The low-temperature, short-duration deposition of the LKD layer 164' thus reduces and / or prevents reactions between oxygen and source / drain structures 150, thereby reducing and / or preventing source / drain oxidation. In some embodiments, the PECVD generates a plasma containing at least silicon, oxygen, and carbon. In some embodiments, the plasma also contains nitrogen and / or hydrogen. The plasma can be generated by introducing one or more deposition precursor gases containing silicon, carbon, oxygen, nitrogen, or combinations thereof [e.g., trimethylsilane, methyltriethoxysilane, oxygen (O2), other precursors, or combinations thereof] and a carrier gas (e.g., an inert gas) into a process chamber and by generating a silicon-, carbon-, and oxygen-containing plasma therefrom using RF power and / or DC power.Parameters of the PECVD [e.g., deposition temperature, deposition time, deposition gas(es), pressure, power, bias, etc.] can be adjusted to minimize source / drain oxidation, provide an LKD layer 164' with a dielectric constant higher than that of the NFD layer 162, provide an LKD layer 164' with a desired oxygen content, or combinations thereof. In some embodiments, the deposited LKD layer 164' has an oxygen content lower than that of the oxygen-treated LKD layer 164. In some embodiments, the oxygen content of the LKD layer 164' is lower than approximately 50 at%. In some embodiments, the LKD layer 164' has the same oxygen content as the NFD layer 162. For example, the LKD layer 164' can have an oxygen content of about 40 at% to about 50 at%.

[0032] Occasionally, exposed surfaces of the device 100 may change during processing when exposed to an external environment, such as when the device 100 is transported between process systems and / or process chambers, for example, from one process chamber to another. For instance, oxygen may diffuse into and / or react with the NFD layer 162 when exposed to the external environment, which may unintentionally increase the oxygen content of the NFD layer 162 (e.g., to more than 50 at%) in some embodiments. This can exacerbate the undesired source / drain oxidation that reduces the performance of the device 100, as described herein. Accordingly, to minimize and / or prevent oxidation of the NFD layer 162 that can lead to unwanted source / drain oxidation, the LKD layer 164' and the NFD layer 162 are deposited in the same process chamber, such as the same PECVD chamber.In other words, the LKD layer 164' and the NFD layer 162 are produced "in situ".

[0033] In Fig. 5. Oxygen can be introduced into the LKD layer 164' by oxygen treatment 165 and / or the oxygen binding of the LKD layer 164' can be improved (e.g., strengthened). The oxygen-treated LKD layer 164 thus has an oxygen content that is higher than the oxygen content of the LKD layer 164'. In some embodiments, the oxygen content of the LKD layer 164' is lower than about 50 at%, and the oxygen treatment 165 increases the oxygen content so that the oxygen-treated LKD layer 164 has an oxygen content that is higher than or equal to about 50 at%. In some embodiments, the oxygen treatment 165 increases the density of the LKD layer 164' so that the density of the oxygen-treated LKD layer 164 is higher than the density of the LKD layer 164'.In some embodiments, the oxygen treatment 165 strengthens the Si-O bond, the CO bond, the OO bond, the ON bond, other types of oxygen bonds, or combinations thereof. For example, the extent of oxygen bonding and / or the strength of oxygen binding sites in the oxygen-treated LKD layer 164 may be greater than the extent of oxygen bonding and / or the strength of oxygen binding sites in the LKD layer 164'. By increasing the density and / or strengthening the oxygen bonding in the LKD layer 164 (and thus by providing a three-layer ESL 160 with a denser oxygen-treated LKD layer 164 that has stronger oxygen bonding), undesirable outgassing of oxygen from the three-layer ESL 160 during subsequent thermal processes can be reduced.

[0034] In some embodiments, the oxygen treatment 165 is an oxygen plasma treatment, such as an O2 plasma treatment. In some embodiments, the oxygen plasma treatment comprises: introducing an oxygen-containing precursor gas (e.g., O2) and a carrier gas (e.g., He) into a process chamber; generating an oxygen-containing plasma therefrom; and bombarding the LKD layer 164' with plasma-excited oxygen-containing species (i.e., reactive species) of the oxygen-containing plasma. The reactive species may include radicals, ions, neutrons, electrons, photons, or combinations thereof. The reactive species may react with the LKD layer 164', for example, by adsorbing onto its surfaces and by initiating chemical reactions that change the composition of the LKD layer 164' (e.g., increase its oxygen content) and / or generate byproducts that desorb from the surfaces.In some embodiments, the oxygen-containing plasma contains excited neutral atoms and / or molecules (e.g., oxygen radicals such as O*, O2*, etc.), ionized atoms and / or molecules (e.g., oxygen ions such as O2). + , O2 - , O + , O -etc.), atoms and / or molecules (e.g., O2, O, etc.), or combinations thereof. The oxygen-containing gas may contain O2 and / or another suitable oxygen-containing precursor (e.g., if the plasma activation process is an O2 plasma treatment). The carrier gas may be a noble gas and / or an inert gas, such as argon, helium, xenon, neon, krypton, another suitable gas, or a combination thereof. Parameters of the oxygen treatment 165 are adjusted to enhance oxygen binding (e.g., with silicon, carbon, nitrogen, or combinations thereof) in the LKD layer 164', increase the density of the LKD layer 164', increase the oxygen content in the LKD layer 164', provide a desired oxidation of the LKD layer 164', or combinations thereof.These parameters include a flow rate and / or concentration of an oxygen-containing precursor gas, a flow rate and / or concentration of a carrier gas, a ratio of the oxygen-containing precursor gas to the carrier gas, temperature, pressure, duration, power, a bias voltage to excite and / or accelerate the plasma, an inclination angle, other suitable parameters or combinations thereof.

[0035] The present disclosure also recognizes that undesirable oxidation occurs more readily between an ESL and a source / drain when the oxygen content at an ESL-source / drain interface is higher than 50 at%, and it is further recognized that an oxygen treatment, such as the oxygen treatment 165, can improve the quality of the ESL, for example by increasing its density and / or by improving its composition (e.g. by strengthening and / or increasing the oxygen binding therein).Therefore, the three-layer ESL 160 is provided with a two-layer dielectric low-k part - an NFD layer 162 connected to source / drain structures 150, and an oxygen-treated LKD layer 164 connected to the NFD layer 162 - with no oxygen treatment being carried out on the NFD layer 162, thereby minimizing the oxygen content at the ESL source / drain interface, but an oxygen treatment 165 being carried out on the LKD layer 164', thereby improving the quality of the two-layer dielectric low-k part without significantly increasing the oxygen content at the ESL source / drain interface. In some embodiments, the oxygen treatment 165 can also increase the density of the NFD layer 162, so that the density of the NFD layer 162 after the oxygen treatment 165 is higher than that before the oxygen treatment 165.In some embodiments, the oxygen treatment 165 can also enhance the oxygen binding in the NFD layer 162, so that the oxygen binding of the NFD layer 162 is stronger after the oxygen treatment 165 than before. However, since the LKD layer 164' masks the NFD layer 162 during the oxygen treatment 165, these increases in density and / or these improvements in oxygen binding are achieved without significantly increasing the oxygen content in the NFD layer 162. For example, the oxygen content at the interface of the NFD layer 162 and the source / drain structure 150 (i.e., at the ESL source / drain interface) remains below 50 at% even after the oxygen treatment 165.

[0036] In Fig. In the illustrated embodiment, a dielectric layer 166 is produced over the oxygen-treated LKD layer 164. The dielectric layer 166 is produced directly on the oxygen-treated LKD layer 164. The dielectric layer 166 has a thickness t3 that is smaller than the gap between the adjacent gate structures 128, so that the dielectric layer 166 also partially fills the gap (and / or the gap s) between the adjacent gate structures 128. Furthermore, the thickness t4 of the three-layer ESL 160 (i.e., a sum of thickness t3, thickness t2, and thickness t1) is smaller than the gap between the adjacent gate structures 128. The thickness t3 is greater than both thickness t2 and thickness t1, and the thickness t3 can be equal to, greater than, or less than the sum of thickness t2 and thickness t1. In some embodiments, the thickness t3 is approximately 2 nm to approximately 3 nm.

[0037] The dielectric layer 166 is made from a dielectric material having a dielectric constant greater than approximately 3.9, and the dielectric constant of the dielectric layer 166 is higher than the dielectric constant of the oxygen-treated LKD layer 164. The dielectric layer 166 is also made from a dielectric material different from that of a subsequently fabricated ILD layer (e.g., a silicon oxide layer) to provide sufficient etch selectivity between the three-layer ESL 160 and the subsequently fabricated ILD layer.For example, if an etching process is performed on the subsequently fabricated ILD layer to create a source / drain contact opening within it, the etch rate of the dielectric material of the dielectric layer 166 for a given etchant in the etching process is sufficiently lower than the etch rate of the subsequently fabricated ILD layer for the given etchant, so that the dielectric layer 166 can function as an etch stop layer and protect underlying source / drain structures 150 from the etching process. Without the dielectric layer 166, sufficient etch selectivity between the ESL above the source / drain structures 150 and the subsequently fabricated ILD layer cannot be provided. For example, a given etchant may exhibit low etch selectivity between a dielectric low-k ESL, such as the two-layer dielectric low-k portion of the three-layer ESL 160 (e.g.,the oxygen-treated LKD layer 164 or the NFD layer 162), and the subsequently produced ILD layer, thereby negating the function of the ESL as an etch stop layer. In some embodiments, the dielectric layer 166 is made of a dielectric material having a dielectric constant of about 4 to about 10 (i.e., 4 ≤ k ≤ 10). The dielectric layer 166 contains, for example, silicon and nitrogen and is a silicon nitride layer. In this example, the dielectric constant of the dielectric layer 166 can be about 6.5.

[0038] The dielectric layer 166 is deposited in a different process chamber than the oxygen-treated LKD layer 164 and the NFD layer 162, and it is produced using a different type of deposition process. For example, the dielectric layer 166 is deposited by atomic layer deposition (ALD) instead of CVD, and it is produced in an ALD chamber. In some embodiments, the dielectric layer 166 is produced by CVD instead of ALD, but in a different CVD chamber than the one in which the oxygen-treated LKD layer 164 and the NFD layer 162 are produced. In some embodiments, the dielectric layer 166 is produced using another suitable process.

[0039] This results in a decrease in the dielectric constant of the three-layer ESL 160 from top (e.g., from the dielectric layer 166) to bottom (e.g., to the NFD layer 162). The dielectric constant of the three-layer ESL 160 can decrease from top to bottom, for example, from approximately 6.5 to approximately 3.6. In some embodiments, an upper part of the three-layer ESL 160 (e.g., the dielectric layer 166, which may be connected to a higher-lying ILD layer) has a dielectric constant of approximately 5 to approximately 8; a middle part of the three-layer ESL 160 (e.g., the oxygen-treated LKD layer 164, which is connected to the dielectric layer 166 and the NFD layer 162) has a dielectric constant of approximately 3.7 to approximately 4.5. and a lower part of the three-layer ESL 160 (e.g. the NFD layer 162, which is connected to the source / drain structure 150 and the gate spacers 132) has a dielectric constant of about 3.6 to about 3.7.For example, dielectric layer 166 (e.g., a SiN layer) has a dielectric constant of about 6.5; oxygen-treated LKD layer 164 (e.g., a SiOC layer) has a dielectric constant of about 3.8; and NFD layer 162 (e.g., a SiOC layer) has a dielectric constant of about 3.7. In another example, dielectric layer 166 (e.g., a SiN layer) has a dielectric constant of about 6.5; oxygen-treated LKD layer 164 (e.g., a SiOC layer) has a dielectric constant of about 4.3; and NFD layer 162 (e.g., a SiOC layer) has a dielectric constant of about 3.7. In yet another example, the dielectric layer 166 (e.g., a SiN layer) has a dielectric constant of about 6.5; the oxygen-treated LKD layer 164 (e.g., a SiOC layer) has a dielectric constant of about 3.7; and the NFD layer 162 (e.g.,a SiOC layer) has a dielectric constant of approximately 3.6. Parameters of the deposition processes, such as the PECVD processes and the ALD process, can be adjusted to provide an NFD layer 162, an oxygen-treated LKD layer 164, and a dielectric layer 166 with desired dielectric constants, and to provide the three-layer ESL 160 with a dielectric constant that decreases from top to bottom, so that the three-layer ESL 160 can provide sufficient etch selectivity and also exhibits a lower effective dielectric constant (and thus reduces the effective capacitance).

[0040] In Fig. In the embodiment shown, an ILD layer 168 is produced over the three-layer ESL 160. The ILD layer 168 is produced directly on the dielectric layer 166 of the three-layer ESL 160, and the ILD layer 168 fills a residual portion of the space (and / or gap) between the adjacent gate structures 128. The ILD layer 168 can be produced by CVD, flowable CVD (FCVD), high aspect ratio deposition (HARP), high-density plasma CVD (HDP-CVD), another suitable deposition process, or a combination thereof.

[0041] The ILD layer 168 contains a dielectric material that differs from the dielectric material of the dielectric layer 166 to enable selective etching between the two. In the illustrated embodiment, the ILD layer 168 is a dielectric layer containing silicon and oxygen. In some embodiments, the dielectric constant of the ILD layer 168 is lower than that of the dielectric layer 166. For example, the ILD layer 168 can be a silicon oxide layer (e.g., a SiO₂ layer) that may have a dielectric constant of approximately 3.9 (k ≈ 3.9). In another example, the ILD layer 168 can be a porous silicon oxide layer that may be configured to have a dielectric constant of less than approximately 2.5 (k ≈ 2.5). In yet another example, the ILD layer 168 can be a carbon-doped oxide layer (e.g.a SiOC layer) which may be configured to also have a dielectric constant of less than approximately 2.5 (k ≈ 2.5). In some embodiments, the ILD layer 168 contains silicon oxide, carbon-doped oxide, silicon nitride, TEOS oxide (TEOS: tetraethyl orthosilicate), PSG, BSG, boron phosphosilicate glass (BPSG), fluorosilicate glass (FSG), xerogel, aerogel, amorphous fluorocarbon, parylene, a BCB-based dielectric material (BCB: benzocyclobutene), or combinations thereof. In some embodiments, the ILD layer 168 has a multilayer structure.

[0042] In Fig. 8. A CMP process (CMP: chemical-mechanical polishing) and / or another planarization process is performed on the ILD layer 168 and the three-layer ESL 160. The CMP process is carried out until the gate structures 128, such as their dummy gate stack 130, are reached and exposed. The CMP process removes portions of the ILD layer 168 and portions of the three-layer ESL 160 that extend over and / or are arranged above the top surfaces of the gate structures 128. Remnants of the ILD layer 168 and the three-layer ESL 160 form a dielectric device plane layer 170 over the source / drain structures 150. The dielectric device plane layer 170 can fill gaps between adjacent gate structures 128 (e.g., between their gate spacers 132) and / or gaps between adjacent source / drain structures 150 (e.g., along the y-direction and / or in the yz-plane).In some embodiments, the dummy gate stacks 130 (e.g., their hard masks) and / or the gate spacers 132 function as a CMP stop layer. In some embodiments, the CMP process is performed for a duration sufficient to expose the dummy gate stacks 130. The CMP process can planarize a top surface of the dielectric device plane layer 170 (which can be formed by the ILD layer 168 and each layer of the three-layer ESL 160), top surfaces of the dummy gate stacks 130, and top surfaces of the gate spacers 132. After the CMP process, the planarized top surfaces can form a substantially planar surface of the device 100.

[0043] In Fig. 9 In some embodiments, a gate replacement process can be performed to replace the dummy gate stacks 130 with gate stacks 180. In some embodiments, the dummy gate stacks 130 are removed to create gate openings (e.g., between the gate spacers 132) that expose the multilayer stack 110, such as its semiconductor layers 120 and sacrificial layers 115, in the channel regions of the device 100. For example, an etching process selectively removes the dummy gate stacks 130, with the dielectric device plane layer 170, the gate spacers 132, the internal spacers 145, the sacrificial layers 115, the semiconductor layers 120, or combinations thereof, being only minimally (or not at all) removed. The etching process is dry etching, wet etching, another suitable etching, or a combination thereof.In some embodiments, a structured mask layer can be used as an etching mask for the etching process, and the structured mask layer can cover the dielectric device plane layer 170 and / or the gate spacers 132 and can have openings in it that expose the dummy gate stacks 130.

[0044] During the gate replacement process, a channel exposure process can be performed prior to the fabrication of the gate stacks 180 to create suspended channel layers. For example, sacrificial layers 115, exposed by the gate openings, are selectively removed to create gaps between the semiconductor layers 120 and gaps between the semiconductor layers 120 and the mesas 105P', thereby suspending the semiconductor layers 120 in the channel regions. In the illustrated embodiment, each channel region contains three suspended semiconductor layers 120, referred to below as channel layers 120', stacked vertically along the z-direction to provide three channels through which current can flow between respective source / drain structures 150 during operation of the transistors of the device 100.In some embodiments, the sacrificial layers 115 are selectively etched by an etching process, while the semiconductor layers 120, the mesas 105P', the gate spacers 132, the internal spacers 145, the dielectric device plane layer 170, or combinations thereof, are only minimally etched (or not at all). In some embodiments, an etchant is selected for the etching process that etches silicon germanium (e.g., the sacrificial layers 115) at a higher rate than silicon (e.g., the semiconductor layers 120 and the mesas 105P') and than dielectric materials (e.g., the gate spacers 132, the internal spacers 145, the dielectric device plane layer 170, etc.) (i.e., the etchant has high etch selectivity with respect to silicon germanium). In some embodiments, an etchant is chosen for the etching process which is a dielectric material with a first composition (e.g.The sacrificial layers 115) are etched at a higher rate than silicon (e.g., the semiconductor layers 120 and the mesas 105P') and dielectric materials with compositions different from the first composition (e.g., the gate spacers 132, the internal spacers 145, the dielectric device plane layer 170, etc.). This etching process is characterized by high etch selectivity with respect to the dielectric material with the first composition. The etching process is dry etching, wet etching, another suitable etching process, or a combination thereof. In some embodiments, the sacrificial layers 115 can be converted into silicon-germanium oxide layers by an oxidation process prior to the etching process, and the silicon-germanium oxide layers can then be removed by the etching process.In some embodiments, an etching process is carried out to modify a profile of the semiconductor layers 120 / the channel layers 120' in order to achieve target channel dimensions / channel shapes.

[0045] Then, gate stacks 180 (also referred to as high-k / metal gates) can be manufactured in the gate openings and / or the gaps. The gate stacks 180 have parts arranged between respective gate spacers 132 and parts arranged between respective internal spacers 145. The gate stacks 180 are also arranged between channel layers 120' and between channel layers 120' and mesas 105P'. In the illustrated embodiment, where the device contains 100 GAA transistors, the gate stacks 180 can, for example, surround or extend into respective channel layers 120' in the yz plane (see, e.g., Figure 1). Fig. 16A). In some embodiments, the gate stacks 180 can completely and / or partially enclose respective channel layers 120' (i.e., they are arranged on at least two sides of the channel layers 120').

[0046] Each gate stack 180 can contain a gate dielectric 182. The gate dielectrics 182 are arranged on the channel layers 120', the mesas 105P', the internal spacers 145, the gate spacers 132, or combinations thereof. The gate dielectrics 182 can have the same or different compositions and / or configurations. The gate dielectrics 182 contain at least one dielectric layer, such as an interface layer and / or a high-k dielectric layer. The interface layer contains a dielectric material, such as SiO2 or SiGeO2. xThe dielectric high-k layer contains a dielectric high-k material, which generally denotes a dielectric material with a dielectric constant higher than that of silicon dioxide, such as HfO₂, HfSiO₂, HfSiO₄, HfSiON₂, HfLaO, HfTaO, HfTiO₂, HfZrO₂, HfAlOx, ZrO₂, ZrSiO₂, AlO₂, AlSiO₂, Al₂O₃, TiO₂, TiO₂, LaO, LaSiO₂, LaO₃, La₂O₃, Ta₂O₃, Ta₂O₅, Y₂O₃, SrTiO₃, BaZrO₂, BaTiO₃ (BTO), (Ba,Sr)TiO₃ (BST), HfO₂-Al₂O₃, other dielectric high-k materials, or combinations thereof. In some embodiments, each gate dielectric 182 can contain a hafnium-based oxide layer (e.g., an HfO2 layer) and / or a zirconium-based oxide layer (e.g., a ZrO2 layer).

[0047] Each gate stack 180 can contain one gate electrode 184. The gate electrodes 184 are arranged over the gate dielectrics 182. The gate electrodes 184 can have the same or different compositions and / or configurations, and they contain at least one electrically conductive layer made of an electrically conductive material that may include Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other electrically conductive components, or combinations thereof. In some embodiments, the gate electrodes 184 include a work function layer. The work function layer is a conductive layer that is adapted to have a desired work function, such as an n-type or p-type work function.The exit work layer contains one or more exit work metals and / or alloys thereof, such as Ti, Ta, Al, Ag, Mn, Zr, W, Ru, Mo, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TiSiN, TiN, TaN, TaSN, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, TaAl, TaAlC, TaSiAlC, TiAlN, or combinations thereof. In some embodiments, the gate electrodes 184 include a solid layer above the gate dielectric 182 and / or the exit work layer. The solid layer contains Al, W, Cu, Ti, Ta, TiN, TaN, polysilicon, one or more other suitable metals and / or alloys thereof, or combinations thereof. In some embodiments, the gate electrodes 184 include a barrier layer above the exit work layer and / or the gate dielectric 182.The barrier layer contains a material that can prevent diffusion and / or reaction of components between adjacent layers and / or promote adhesion between adjacent layers, such as between the exit layer and the bulk layer. In some embodiments, the barrier layer contains a metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride, titanium silicon nitride, tantalum silicon nitride, other suitable metal nitrides, or combinations thereof.

[0048] Fabricating the gate stacks 180 can include: depositing dielectric gate materials (e.g., interface layers, dielectric high-k layers, etc.) that partially fill the gate openings; depositing gate electrode materials (e.g., exit work layers, barrier layers, solid layers, etc.) that fill the remainder of the gate openings; and performing a planarization process to remove portions of the dielectric gate materials and / or portions of the gate electrode materials above the dielectric device plane layer 170. In some embodiments, as shown, fabricating the device 100 can further include back-etching the gate stacks 180 and fabricating hard masks, e.g., self-aligned capping structures (SAC structures) 185, over the back-etched gate stacks 180. The SAC structures 185 contain a material that differs from that of the dielectric device plane layer 170 (e.g.whose ILD layer 168) and / or differs from the materials of subsequently produced dielectric layers in order to achieve etch selectivity. In some embodiments, the SAC structures 185 contain silicon and nitrogen and / or carbon, such as silicon nitride, silicon oxide nitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon oxide carbonitride, other silicon nitrides, other silicon carbides, or combinations thereof. In some embodiments, the SAC structures 185 contain a metal and oxygen and / or nitrogen, such as aluminum oxide, aluminum nitride, aluminum oxide nitride, zirconium oxide, zirconium nitride, hafnium oxide, zirconium aluminum oxide, other metal oxides, other metal nitrides, or combinations thereof.In the illustrated embodiment, the gate stacks 180 are indeed manufactured using a gate-last process, but embodiments in which the metal gate stacks of the device 100 can also be manufactured using a gate-first process or a gate-last / gate-first hybrid process are also considered in the present disclosure.

[0049] In the Fig. In steps 10 to 15, a source / drain contact is established in the dielectric device plane layer 170 with one of the source / drain structures 150. Fig. In embodiment 10, a dielectric layer 186 can be fabricated above the dielectric device plane layer 170 and the gate structures 128. In some embodiments, the dielectric layer 186 includes a contact etch stop layer (CESL) 187 and an ILD layer 188. The ILD layer 188 can be configured and / or fabricated similarly to the ILD layer 168. For example, the ILD layer 188 includes a dielectric material such as silicon dioxide, carbon-doped oxide, TEOS oxide, PSG, BSG, BPSG, FSG, xerogel, aerogel, amorphous fluorocarbon, parylene, a BCB-based dielectric material, a polyimide, other suitable dielectric materials, or combinations thereof. The dielectric material can be the same dielectric material as, or a different dielectric material than, that of the ILD layer 168.In some embodiments, the ILD layer 188 is a dielectric low-k layer, such as a silicon and oxygen-containing dielectric layer with a dielectric constant of less than about 3.9 and in some embodiments of less than about 2.5.

[0050] The CESL 187 contains a different material than the ILD layer 188 to enable etch selectivity between the two layers, such as a dielectric material different from that of the ILD layer 188. In some embodiments, the CESL 187 contains silicon and nitrogen. For example, the CESL 187 is a silicon nitride layer and / or a silicon oxide nitride layer. In the present disclosure, an ILD layer 188 and / or a CESL 187 with a multilayer structure and / or with multiple dielectric materials are considered. In some embodiments, fabricating the dielectric layer 186 comprises: depositing a CESL 187 over the dielectric device plane layer 170; depositing an ILD layer 188 over the CESL 187; and performing a CMP and / or other planarization process on the ILD layer 188.

[0051] In Fig. In step 11, a source / drain contact opening 190 is created, exposing one of the source / drain structures 150. For example, the source / drain contact opening 190 extends through the ILD layer 188, the CESL 187, the ILD layer 168, and the three-layer ESL 160 to expose one of the source / drain structures 150 located between the gate structures 128. Portions of the three-layer ESL 160 along the sidewalls of the gate spacers 132 can be removed during the creation of the source / drain contact opening 190. In the illustrated embodiment, the dielectric layer 166 along the sidewalls of the gate spacers 132 is completely removed, and the oxygen-treated LKD layer 164 is partially removed along the sidewalls of the gate spacers 132.In these embodiments, the source / drain contact opening 190 has sidewalls formed by the ILD layer 188, the CESL 187, the oxygen-treated LKD layer 164, and the NFD layer 162. Furthermore, in these embodiments, the thickness t4 of the portions of the three-layer ESL 160 along the sidewalls of the gate spacers 132 is reduced to a thickness t6. In some embodiments, the thickness t6 is approximately 0.75 nm to approximately 2.75 nm. For example, the thickness t6 can be approximately 1.5 nm to approximately 1.75 nm. Additionally, in these embodiments, the thickness t2 of the oxygen-treated LKD layer 164 can be reduced to a thickness t7. In some embodiments, the thickness t7 is less than 1 nm.

[0052] In some embodiments, depending on the cross-sectional profile and / or shape of the source / drain contact opening 190, the thickness of the oxygen-treated LKD layer 164 along the side walls of the gate spacers 132 can be substantially uniform or vary along a gate height direction (e.g., along the z-direction). In the illustrated embodiment, the source / drain contact opening 190 has a width that decreases from top to bottom (i.e., the source / drain contact opening 190 has a conical width), and the thickness of the oxygen-treated LKD layer 164 increases from top to bottom (i.e., the oxygen-treated LKD layer 164 has a conical thickness along the side walls of the gate spacers 132). For example, the thickness of the oxygen-treated LKD layer 164 increases from thickness t7 to thickness t2.In some embodiments, the oxygen-treated LKD layer 164 is partially removed from top to bottom along the side walls of the gate spacers 132, and the thickness of the oxygen-treated LKD layer 164 increases from thickness t7 to a thickness greater than thickness t7 but less than thickness t2. Various cross-sectional profiles and / or shapes for the source / drain contact opening 190 are considered in the present disclosure. For example, the source / drain contact opening 190 may have a conical width that increases from top to bottom, and in these embodiments, the thickness of the oxygen-treated LKD layer 164 may decrease from top to bottom. In another example, the source / drain contact opening 190 may have a substantially uniform width from top to bottom (i.e.,The source / drain contact opening 190 can have substantially vertical sidewalls), and in these embodiments, the thickness of the oxygen-treated LKD layer 164 can be substantially uniform from top to bottom. In these embodiments, the substantially uniform thickness of the oxygen-treated LKD layer 164 can be the thickness t2 or less, for example, if the LKD layer 164 is partially removed. The present disclosure also considers the creation of more than one source / drain contact opening 190, such as source / drain contact openings for each of the source / drain structures 150.

[0053] The dielectric device layer 170 and the dielectric layer 186 can be structured using a lithography and etching process. Creating the source / drain contact opening 190 can, for example, involve: performing a lithography process to produce a structured mask layer 191 over the ILD layer 188; and performing an etching process to transfer a structure defined by one or more openings 1910 in the structured mask layer 191 (overlapping the respective source / drain structures 150) to the ILD layer 188, the CESL 187, the ILD layer 168, and the three-layer ESL 160.The lithography process can include the following: creating a resist layer over the ILD layer 188 (for example, by spin coating), performing a pre-curing process, performing an exposure process using a mask, performing a post-curing process, and performing a development process. During the exposure process, the resist layer can be irradiated with radiation energy, such as ultraviolet (UV) light, deep UV light (DUV light), or extreme UV light (EUV light), with the mask blocking, transmitting, and / or reflecting the radiation to the resist layer, depending on the mask structure and / or type (for example, binary mask, phase-shift mask, or EUV mask), so that an image corresponding to the mask structure is projected onto the resist layer.Alternatively, the exposure process can be implemented using or replaced by other methods, such as maskless lithography, electron beam writing, ion beam writing, and / or nano-imprint lithography. Since the resist layer is sensitive to radiation energy, exposed (or unexposed) portions of the resist layer undergo chemical changes, and these exposed (or unexposed) portions are resolved during the development process depending on the properties of the resist layer and the properties of a developer solution used in the development process. After development, the structured resist layer exhibits a resist structure corresponding to the mask. In some embodiments, the structured mask layer 191 is a structured resist layer.In some embodiments, the structured resist layer is used as an etching mask for removing portions of a hard mask layer, resulting in the structured mask layer 191. In some embodiments, the structured mask layer 191 comprises a structured resist layer and a structured hard mask layer, with the structured resist layer positioned above the structured hard mask layer. In the illustrated embodiment, the structured mask layer 191 is fabricated directly on the dielectric layer 186 (e.g., on its ILD layer 188). In some embodiments, the dielectric layer 186 is omitted, and the structured mask layer 191 is fabricated directly on the dielectric device-level layer 170 and the gate structures 128.

[0054] In the Fig. 12 and Fig. 13. Contact spacers 192S are manufactured in the source / drain contact opening 190 such that they partially fill the source / drain contact opening 190. The contact spacers 192S are manufactured along the side walls of the source / drain contact opening 190, and they cover these side walls. In Fig. 12 After removal of the structured mask layer 191, a dielectric contact coating 192 can be deposited over the dielectric layer 186 using a suitable process, partially filling the source / drain contact opening 190. The dielectric contact coating 192 is produced on a top surface of the ILD layer 188 and on side walls and a bottom surface of the source / drain contact opening 190. For example, the dielectric contact coating 192 covers side walls of the source / drain contact opening 190 formed by the ILD layer 188, the CESL 187, the oxygen-treated LKD layer 164, and the NFD layer 162. The dielectric contact coating 192 also covers a bottom surface of the source / drain contact opening 190 formed by the exposed source / drain structure 150 (e.g., its semiconductor layer 158). The dielectric contact coating 192 is deposited using a suitable method.For example, the dielectric contact coating 192 is conformally deposited by ALD so that it has a thickness t8 which is essentially uniform.

[0055] The dielectric contact coating 192 contains a dielectric material that differs from the dielectric material of the ILD layer 188, the oxygen-treated LKD layer 164, and the NFD layer 162 to enable selective etching between the layers. The dielectric material can be configured to hinder and / or prevent the diffusion of metallic components from the electrically conductive part of a source / drain contact into the dielectric layer 186, the ILD layer 168, the three-layer ESL 160, or combinations thereof. In the illustrated embodiment, the dielectric contact coating 192 contains silicon and nitrogen. For example, the dielectric contact coating 192 is a silicon nitride layer. In some embodiments, the dielectric contact coating 192 is a metal oxide layer and / or a metal nitride layer.

[0056] In Fig. 13. Parts of the dielectric contact coating 192 are removed by an etching process, such as dry etching, wet etching, another suitable etching process, or a combination thereof. Remaining parts of the dielectric contact coating 192 form the contact spacers 192S, which cover the side walls of the source / drain contact opening 190. Accordingly, after the etching process, the source / drain contact opening 190 has side walls formed by the contact spacers 192S and bottom walls formed by the exposed source / drain structure 150 (e.g., its semiconductor layer 158). The contact spacers 192S extend longitudinally along the z-direction and have a thickness t9 (e.g., along the x-direction). In the illustrated embodiment, the thickness t9 is equal to the thickness t8.In some embodiments, the dielectric contact coating 192 can be thinned along the x- and / or y-direction by the etching process, such that the thickness t9 is less than the thickness t8. In some embodiments, the contact spacers 192S have substantially uniform thicknesses along their lengths. For example, the thickness t9 is substantially the same from the top end to the bottom end of the source / drain contact opening 190 (i.e., along the lengths of the contact spacers 192S). In some embodiments, the contact spacers 192S have tapered thicknesses along their lengths. For example, the thickness t9 can increase from the top end to the bottom end of the source / drain contact opening 190 (i.e., along the lengths of the contact spacers 192S). In another example, the thickness t9 can decrease from the top end to the bottom end of the source / drain contact opening 190 (i.e., along the lengths of the contact spacers 192S).

[0057] The etching process allows the dielectric contact coating 192 to be selectively etched, leaving the ILD layer 188, the CESL 187, the oxygen-treated LKD layer 164, the NFD layer 162, the semiconductor layers 158, or combinations thereof only minimally etched (or not at all). In some embodiments, an etchant is selected for the etching process that etches a dielectric material with a first composition (e.g., silicon nitride) at a higher rate than semiconductor materials (e.g., silicon and / or germanium) and than dielectric materials with compositions different from the first composition (e.g., silicon oxycarbide, silicon oxide, silicon oxide carbonitride, etc.) (i.e., the etchant has high etch selectivity with respect to the dielectric material with the first composition).In some embodiments, the etching process is an anisotropic etching process, which generally denotes an etching process with different etching rates in different directions, such that the etching process removes material in certain directions. For example, the etching may have a vertical etching rate that is higher than a horizontal etching rate (in some embodiments, the horizontal etching rate is zero). With the anisotropic etching process, material is therefore removed substantially in the vertical direction (here in the z-direction), with minimal (or no) material removal in the horizontal direction (here in the x- and / or y-direction). In these embodiments, the anisotropic etching removes portions of the dielectric contact coating 192 on the horizontally oriented surfaces of the device 100 (i.e.,, from the top of the ILD layer 188 and the top of the source / drain structure 150), while parts of the dielectric contact coating 192 on the vertically oriented surfaces (i.e., parts of the ILD layer 188, the CESL 187, the oxygen-treated LKD layer 164 and the NFD layer 162, which in the illustrated embodiment form the side walls of the source / drain contact opening 190) are not removed at all or only minimally.

[0058] In the Fig. 14 and Fig. 15. A source / drain contact 194 can be produced as follows: Deposition of an electrically conductive contact material 194' over the dielectric layer 186 and the contact spacers 192S ( Fig. 14) and performing a planarization process (e.g. a CMP process) to remove excess electrically conductive contact material 194', which is located, for example, above the top of the dielectric layer 186 ( Fig. 15) A residue of the electrically conductive contact material 194' forms the source / drain contact 194. The planarization process can be carried out until the dielectric layer 186 is reached and exposed. In some embodiments, the ILD layer 188 can be a CMP stop layer, and the CMP process can be used to planarize a top surface of the device 100 (e.g., a top surface of the source / drain contact 194, a top surface of the ILD layer 188, and top surfaces of the contact spacers 192S).

[0059] The electrically conductive contact material 194' contains tungsten, ruthenium, cobalt, molybdenum, copper, aluminum, titanium, tantalum, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, or combinations thereof. In some embodiments, the production of the electrically conductive contact material 194' includes depositing a solid metallic material, such as tungsten, cobalt, or ruthenium, over the device 100. In these embodiments, the source / drain contact 194 may comprise a tungsten, cobalt, or ruthenium pin. The solid metallic material may have a multilayer structure, such as a solid layer arranged over a seed layer. The solid metallic material may be deposited using a protective deposition process, such as protective CVD.In some embodiments, the protective deposition process is physical vapor deposition (PVD), ALD, electroplating, electroless plating, another suitable process, or a combination thereof. In some embodiments, the solid metallic material is deposited using a bottom-up deposition process, which generally refers to a deposition process by which the source / drain contact opening 190 is filled from the bottom up. In some embodiments, the bottom-up deposition process comprises several deposition and etching cycles, each of which may include the deposition of an electrically conductive material and subsequent back-etching of the electrically conductive material.

[0060] In some embodiments, the source / drain contact 194 is barrier-free. For example, the electrically conductive material 194' comprises a solid metallic material / layer, but no barrier or coating material or barrier or coating layer. In these embodiments, a metal pin of the source / drain contact 194 (formed, for example, by the solid metallic material / layer) can directly contact an enclosing dielectric material, such as the contact spacers 192S (or the ILD layer 188, the CESL 187, and the three-layer ESL 160, as in embodiments where the contact spacers 192S are not present). In some embodiments, the source / drain contact 194 includes at least one coating / barrier layer between its metal pin and its enclosing dielectric material.In these embodiments, the deposition of the electrically conductive contact material 194' further comprises the deposition of a barrier / coating material over the dielectric layer 186 prior to the deposition of the solid metallic material. The barrier / coating material partially fills and coats the source / drain contact opening 190, and the solid metallic material is deposited over the barrier / coating material and fills the remainder of the source / drain contact opening 190. In these embodiments, a barrier layer / coating is formed between a metal pin of the source / drain contact 194 (which, for example,The barrier layer / coating separates the metal pin from the surrounding dielectric material, such as the contact spacers 192S (or the ILD layer 188, the CESL 187, and the three-layer ESL 160, as in embodiments where the contact spacers 192S are not present). The barrier / coating material can promote adhesion between the contact spacers 192S and the solid metallic material and / or prevent diffusion of metallic components from the solid metallic material into adjacent dielectric material, such as the contact spacers 192S, the ILD layer 188, the CESL 187, and the three-layer ESL 160, or combinations thereof.In some embodiments, the barrier / coating material may contain tantalum, tantalum nitride, tantalum aluminum nitride, tantalum silicon nitride, tantalum carbide, titanium, titanium nitride, titanium silicon nitride, titanium aluminum nitride, titanium carbide, tungsten, tungsten nitride, tungsten carbide, molybdenum nitride, cobalt, cobalt nitride, ruthenium, palladium or combinations thereof.

[0061] In some embodiments, a silicide structure 198 is produced over the exposed source / drain structure 150 before or after the deposition of the electrically conductive material 194'. The silicide structure 198 can be produced, for example, by depositing a metal layer over the semiconductor layer 158 and heating the device 100, such as by a tempering process, to cause components of the semiconductor layer 158 (e.g., silicon and / or germanium) to react with metallic components in the metal layer. The metal layer contains a metallic component suitable for promoting silicide formation, such as nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, zirconium, other suitable metals, or combinations thereof. The silicide structure 198 thus contains a metallic component and a component of the semiconductor layer 158 (e.g., silicon and / or germanium).In some embodiments, the metal layer is a titanium-, cobalt-, or nickel-containing layer, and the silicide structure 198 contains titanium, cobalt, or nickel and silicon and / or germanium. In these embodiments, the silicide structure 198 can be a titanium silicide, nickel silicide, or cobalt silicide layer. In some embodiments, during the silicideation process, portions of the semiconductor layer 158 are converted into the silicide structure 198. Unconverted metals, such as remaining portions of the metal layer, are selectively removed by a suitable process, such as etching. The silicide structure 198 can be considered part of the respective source / drain structure 150 or the respective source / drain contact 194.

[0062] The source / drain contact 194 is connected to the source / drain structure 150 and / or the silicide structure 198. The source / drain contact 194 is separated from and electrically insulated against the gate stacks 180 by the contact spacers 192S, the three-layer ESL 160, and the gate spacers 132. Since the source / drain contact 194 and the gate electrodes 184 of the gate structures 128 are electrically conductive materials separated by a dielectric material, e.g., the gate spacers 132 and the three-layer ESL 160 (and in some embodiments by the contact spacers 192S), parasitic capacitance can arise between them. The parasitic capacitance and / or capacitive coupling between the source / drain contact 194 and the gate electrodes 184 can reduce the device performance, for example by slowing down and / or delaying electrical signals.The disclosed three-layer ESL 160 reduces the parasitic capacitance by decreasing the dielectric constant of the dielectric material between the source / drain contact 194 and the gate electrodes 184. Since, for example, the capacitance is directly proportional to the dielectric constant of a dielectric material between two electrically conductive plates (e.g., the source / drain contact 194 and the gate electrodes 184), the capacitance decreases with decreasing dielectric constant of the dielectric material. In the illustrated embodiment, the three-layer ESL 160 is configured with a two-layer dielectric low-k layer (e.g., the NFD layer 162 and the oxygen-treated LKD layer 164) and the dielectric layer 166, thus providing the desired etch selectivity between the three-layer ESL 160 and the dielectric material. B. the upper dielectric layer 166 (e.g.a SiN layer), and the ILD layer 168, exhibiting a lower effective capacitance than an ESL containing only nitride, thus imparting a lower effective capacitance to the dielectric material between the source / drain contact 194 and the gate electrodes 184. In particular, by reducing the nitrogen content of an ESL fabricated over the gate structures 128 and the source / drain structures 150 [e.g., by setting up the three-layer ESL 160 with the NFD layer 162 (e.g., a SiOC layer) and, in some embodiments, with a nitrogen-free oxygen-treated LKD layer 164 (e.g., a SiOC layer with a higher oxygen content)], a dielectric constant for the ESL can be provided that is lower than 3.9.Lowering the effective capacitance improves electrical signal transmission, thereby increasing device speed and / or overall device performance. Furthermore, since the three-layer ESL 160 has a dielectric constant that decreases from top to bottom, even if some of the three-layer ESL 160 is removed during source / drain contact fabrication and / or during further fabrication of the device 100, the dielectric constant of the remaining three-layer ESL 160 between the source / drain contact 194 and the gate electrodes 184 is lower than that of silicon oxide.

[0063] In the present disclosure, various configurations of the three-layer ESL 160 and / or the source / drain contact 194 are considered, which may result from process variations, such as the configurations described in the Fig. Figures 17 to 23 are shown. In some embodiments, at least a portion of the oxygen-treated LKD layer 164 is completely removed from the side walls of the gate spacers 132, as shown in Fig. Figure 17 shows that in these embodiments, the NFD layer 162 of the three-layer ESL 160 is located between a first part of a source / drain contact 190 and first parts of the gate stacks 180 (e.g., their upper parts), while the NFD layer 162 and the oxygen-treated LKD layer 164 of the three-layer ESL 160 are located between a second part of the source / drain contact 190 and second parts of the gate stacks 180 (e.g., their lower parts). In some embodiments, the dielectric layer 166 is partially removed along the side walls of the gate spacers 132, as shown in Figure 17. Fig. Figure 18 shows that in these embodiments, the NFD layer 162 and the oxygen-treated LKD layer 164 of the three-layer ESL 160 are located between the first part of a source / drain contact 190 and the first parts of the gate stacks 180 (e.g., their upper parts), while the NFD layer 162, the oxygen-treated LKD layer 164, and the dielectric layer 166 of the three-layer ESL 160 are located between the second part of the source / drain contact 190 and the second parts of the gate stacks 180 (e.g., their lower parts). In some embodiments, no contact spacers 192S are used in the source / drain contact structure of the device 100, so that the source / drain contact 194 directly contacts the three-layer ESL 160, as shown in the Fig. Figures 19 to 21 are shown. In these embodiments, the source / drain contact 194 can be the oxygen-treated LKD layer 164 ( Fig. 19), the NFD layer 162 and the oxygen-treated LKD layer 164 ( Fig. 20) or the oxygen-treated LKD layer 164 and the dielectric layer 166 ( Fig. 21) contact directly. In some embodiments, the source / drain contact 194 or the contact spacers 192S contact the NFD layer 162 directly, but not the LKD layer 164 and the dielectric layer 166, e.g., when these layers are completely removed when creating the source / drain contact opening 190. In some embodiments, which are described in Fig. As shown in Figure 22, a depression (dishing) D can occur if the ILD layer 168 and / or the three-layer ESL 160 are planarized, as is the case, for example, with reference to Fig. 8 has been described. Fig. 22 By planarization, an upper part of the dielectric layer 166 can be completely removed, and an upper part of the oxygen-treated LKD layer 164 can be partially removed. In these embodiments, the CESL 187 (e.g., a silicon nitride layer) can fill the well D, as shown in Fig. 23, and the CESL 187 can also be located between the gate stacks 180 (e.g. their upper parts) and the source / drain contact 194 (and, in some embodiments, the contact spacers 192S), as shown in Fig. Figure 24 shows that in these embodiments the CESL 187 can be located between an upper part of the three-layer ESL 160 and the source / drain contact 194 (and, in some embodiments, the contact spacers 192S), as shown in Fig. 24 is shown.

[0064] Numerous different embodiments are provided in the present disclosure. One exemplary process comprises the fabrication of a three-layer etch stop layer over a source / drain by the following steps: fabricating a nitrogen-free dielectric low-k layer on the source / drain; fabricating an oxygen-treated dielectric low-k layer on the nitrogen-free dielectric low-k layer; and fabricating a dielectric layer on the oxygen-treated dielectric low-k layer. The nitrogen-free dielectric low-k layer has a first dielectric constant, the oxygen-treated dielectric low-k layer has a second dielectric constant that is higher than the first dielectric constant, and the dielectric layer has a third dielectric constant that is higher than both the second and the first dielectric constants.In some embodiments, the nitrogen-free dielectric low-k layer is produced with a first thickness, the oxygen-treated dielectric low-k layer is produced with a second thickness, and the dielectric layer is produced with a third thickness. The third thickness is greater than the first and second thicknesses.

[0065] In some embodiments, the method further comprises fabricating an intermediate dielectric layer (ILD layer) over the three-layer etch stop layer. In some embodiments, the method further comprises removing a portion of the three-layer etch stop layer and a portion of the ILD layer to create a source / drain contact opening that exposes the source / drain; and fabricating a source / drain contact structure within the source / drain contact opening. In some embodiments, fabricating the dielectric layer includes performing an atomic layer deposition process.

[0066] In some embodiments, the nitrogen-free dielectric low-k layer and the oxygen-treated dielectric low-k layer are each made from an oxygen-containing dielectric material, wherein a first oxygen content of the oxygen-containing dielectric material of the nitrogen-free dielectric low-k layer is lower than a second oxygen content of the oxygen-containing dielectric material of the oxygen-treated dielectric low-k layer. In some embodiments, the first oxygen content is lower than about 50 atomic percent (at%), and the second oxygen content is higher than 50 at%.

[0067] In some embodiments, producing the nitrogen-free dielectric low-k layer includes depositing a first silicon oxycarbide layer (SiOC layer); and producing the oxygen-treated dielectric low-k layer includes depositing a second SiOC layer and performing an oxygen treatment on the second SiOC layer. In some embodiments, producing the dielectric layer includes producing a silicon nitride layer (SiN layer).

[0068] In some embodiments, the production of the nitrogen-free dielectric low-k layer comprises performing a first plasma-enhanced chemical vapor deposition (PECVD) process; and the production of the oxygen-treated dielectric low-k layer comprises performing a second PECVD process and performing an oxygen treatment after the second PECVD process. In some embodiments, no oxygen treatment is performed between the first and second PECVD processes. In some embodiments, a deposition temperature of approximately 200 °C to approximately 600 °C and a deposition time of approximately 6 minutes to approximately 1 hour are implemented for the first PECVD process.In some embodiments, a deposition temperature of approximately 200 °C to approximately 600 °C and a deposition duration of approximately 6 minutes to approximately 1 hour are also implemented for the second PECVD process. In some embodiments, a dielectric low-k layer is deposited over the nitrogen-free dielectric low-k layer in the second PECVD process, and during the oxygen treatment, the dielectric low-k layer is exposed to an O2 plasma.

[0069] Another exemplary method comprises the fabrication of a contact etch stop layer over a source / drain by the following steps: depositing a first silicon oxycarbide (SiOC) layer on the source / drain; depositing a second SiOC layer on the first SiOC layer; performing an oxygen treatment on the second SiOC layer; and depositing a silicon nitride (SiN) layer on the oxygen-treated second SiOC layer. The method further comprises the fabrication of an interlayer dielectric (ILD) layer on the contact etch stop layer and the fabrication of a source / drain contact with the source / drain. The source / drain contact is formed in the contact etch stop layer and the ILD layer. In some embodiments, no oxygen treatment is performed between the deposition of the first SiOC layer and the deposition of the second SiOC layer.In some embodiments, the first and second SiOC layers are deposited in the same deposition process chamber. In some embodiments, the first SiOC layer is deposited by a first plasma-enhanced chemical vapor deposition (PECVD), and the second SiOC layer is deposited by a second PECVD. In some embodiments, the SiN layer is deposited by atomic layer deposition. In some embodiments, the deposition temperature for the first SiOC layer is lower than approximately 600 °C. In some embodiments, the deposition temperature for the second SiOC layer is also lower than approximately 600 °C. In some embodiments, the deposition time for the first SiOC layer is shorter than approximately 1 hour. In some embodiments, the deposition time for the second SiOC layer is also shorter than approximately 1 hour.In some embodiments, establishing the source / drain contact with the source / drain involves completely removing part of the SiN layer and partially removing part of the second SiOC layer along a side wall of a gate spacer.

[0070] An exemplary device structure comprises: a gate stack; a gate spacer arranged along a side wall of the gate stack; a source / drain located adjacent to the gate spacer; a source / drain contact structure arranged on the source / drain; and a contact etch stop layer located between the gate spacer and the source / drain contact structure. The contact etch stop layer has a nitrogen-free portion connected to the source / drain and the gate spacer. In some embodiments, the dielectric constant of the nitrogen-free portion connected to the source / drain and the gate spacer is approximately 3.6 to approximately 3.7.In some embodiments, the nitrogen-free portion is a first silicon oxycarbide portion with a first oxygen content, and the contact etch stop layer further comprises a second silicon oxycarbide portion arranged above the first silicon oxycarbide portion. The second silicon oxycarbide portion has a second oxygen content that is higher than the first oxygen content. In some embodiments, the first silicon oxycarbide portion has a first carbon content, and the second silicon oxycarbide portion has a second carbon content. The second carbon content is different from the first carbon content (e.g., lower than the first carbon content in some embodiments).

[0071] Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present disclosure. It should be clear to those skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other methods and structures to achieve the same objectives and / or to obtain the same advantages as in the embodiments presented here. Those skilled in the art should also recognize that such equivalent interpretations do not deviate from the fundamental concept and scope of protection of the present disclosure and that they can make various changes, substitutions, and modifications without deviating from the fundamental concept and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 655,198

[0001]

Claims

[1] Procedure, encompassing: Producing a three-layer etch stop layer over a source / drain using the following steps: Fabricating a nitrogen-free dielectric low-k layer on the source / drain, wherein the nitrogen-free dielectric layer has a first dielectric constant, Producing an oxygen-treated dielectric low-k layer on the nitrogen-free dielectric low-k layer, wherein the oxygen-treated dielectric low-k layer has a second dielectric constant that is higher than the first dielectric constant, and Forming a dielectric layer on the oxygen-treated dielectric low-k layer, wherein the dielectric layer has a third dielectric constant that is higher than the second dielectric constant and the first dielectric constant; Creating an intermediate dielectric layer (ILD layer) over the three-layer etch stop layer; Removing part of the three-layer etch stop layer and part of the ILD layer to create a source / drain contact opening that exposes the source / drain; and Establishing a source / drain contact structure in the source / drain contact opening. [2] Method according to claim 1, wherein: The production of the nitrogen-free dielectric low-k layer includes the deposition of a first silicon oxycarbide layer (SiOC layer), and The production of the oxygen-treated dielectric low-k layer includes the deposition of a second SiOC layer and the performance of an oxygen treatment on the second SiOC layer, and The production of the dielectric layer includes the production of a silicon nitride layer (SiN layer). [3] Method according to claim 1 or 2, wherein: The production of the nitrogen-free dielectric low-k layer includes performing an initial plasma-enhanced chemical vapor deposition (PECVD) process. The production of the oxygen-treated dielectric low-k layer includes performing a second PECVD process and performing an oxygen treatment after performing the second PECVD process, and The production of the dielectric layer involves carrying out an atomic layer deposition process. [4] Method according to claim 3, wherein no oxygen treatment is carried out between performing the first PECVD process and performing the second PECVD process. [5] Method according to claim 3 or 4, wherein for the first PECVD process and the second PECVD process, a deposition temperature of about 200 °C to about 600 °C and a deposition time of about 6 min to about 1 h are implemented. [6] Method according to claim 3, 4 or 5, wherein: In the second PECVD process, a dielectric low-k layer is deposited over the nitrogen-free dielectric low-k layer, and During oxygen treatment, the dielectric low-k layer is exposed to an O2 plasma. [7] Method according to any of the preceding claims, wherein the nitrogen-free dielectric low-k layer and the oxygen-treated dielectric low-k layer are each made from an oxygen-containing dielectric material, wherein a first oxygen content of the oxygen-containing dielectric material of the nitrogen-free dielectric low-k layer is lower than a second oxygen content of the oxygen-containing dielectric material of the oxygen-treated dielectric low-k layer. [8] Method according to claim 7, wherein the first oxygen content is lower than about 50 atomic % (at%) and the second oxygen content is higher than 50 at%. [9] Method according to any one of the preceding claims, wherein: the nitrogen-free dielectric low-k layer is produced with a first thickness, the oxygen-treated dielectric low-k layer is produced with a second thickness, and The dielectric layer is produced with a third thickness that is greater than the thickness and the second thickness. [10] Procedures, including: Creating a contact etch stop layer over a source / drain using the following steps: Deposition of a first silicon oxycarbide layer (SiOC layer) on the source / drain, Deposition of a second SiOC layer on the first SiOC layer, Performing an oxygen treatment on the second SiOC layer, and Deposition of a silicon nitride layer (SiN layer) on the oxygen-treated second SiOC layer; Creating an intermediate dielectric layer (ILD layer) on the contact etch stop layer; and Establishing a source / drain contact with the source / drain, wherein the source / drain contact is established in the contact etch stop layer and the ILD layer. [11] Method according to claim 10, wherein the first SiOC layer and the second SiOC layer are deposited in the same deposition process chamber. [12] Method according to claim 10, wherein: the first SiOC layer is deposited using a first plasma-enhanced chemical vapor deposition (PECVD), the second SiOC layer is deposited using a second PECVD, and The SiN layer is deposited by atomic layer deposition. [13] Method according to any one of claims 10 to 12, wherein the deposition temperature for the deposition of the first SiOC layer and for the deposition of the second SiOC layer is lower than about 600 °C. [14] Method according to any one of claims 10 to 13, wherein the deposition time for the deposition of the first SiOC layer and for the deposition of the second SiOC layer is each less than about 1 hour. [15] Method according to any one of claims 10 to 14, wherein establishing the source / drain contact with the source / drain comprises a complete removal of a part of the SiN layer and a partial removal of a part of the second SiOC layer along a side wall of a gate spacer. [16] Method according to any one of claims 10 to 15, wherein no oxygen treatment is carried out between the deposition of the first SiOC layer and the deposition of the second SiOC layer. [17] Device structure with: a gate stack; a gate spacer arranged along a side wall of the gate stack; a source / drain that is located adjacent to the gate spacer; a source / drain contact structure arranged on the source / drain; and a contact etch stop layer arranged between the gate spacer and the source / drain contact structure, wherein the contact etch stop layer has a nitrogen-free portion connected to the source / drain and the gate spacer. [18] Device structure according to claim 17, wherein: the nitrogen-free part is a first silicon oxycarbide part, wherein the first silicon oxycarbide part has a first oxygen content, and the contact etch stop layer further comprises a second silicon oxycarbide part arranged above the first silicon oxycarbide part, wherein the second silicon oxycarbide part has a second oxygen content that is higher than the first oxygen content. [19] Device structure according to claim 18, wherein: the first silicon oxycarbide part has a first carbon content, and the second silicon oxycarbide part has a second carbon content, the second carbon content being lower than the first carbon content. [20] Device structure according to one of claims 17 to 19, wherein the dielectric constant of the nitrogen-free part connected to the source / drain and the gate spacer is about 3.6 to about 3.7.

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