GATE-FREE SCRAPER CELLS AND METHOD FOR THEIR MANUFACTURE

Abstract

Embodiments of the present disclosure provide a semiconductor device with receiving components, such as sampling cells, without gate structures and methods for manufacturing the semiconductor devices.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] This application claims priority over the preliminary US patent application No. 63 / 675,310, filed on July 25, 2024, which is incorporated by reference into the present application. BACKGROUND

[0002] As the physical size of integrated circuits decreases and the number of transistors packed into a single device increases, smaller trace widths are used in integrated circuits, and the transistors are placed closer together. A latch-up is a type of short circuit that occasionally occurs in integrated circuits. Some integrated circuits incorporate tap cells to prevent such latch-ups. Because the tap cells must be placed at appropriate intervals, an integrated circuit can have many tap cells, thus increasing the overall size of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity.

[0004] Fig. Figure 1 is a graphical representation of a layout design with a sampling cell according to embodiments of the present disclosure.

[0005] Fig. Figure 2A is a graphical representation of an integrated circuit layout with tap cells according to embodiments of the present disclosure.

[0006] Fig. 2B is an enlarged partial view of the integrated circuit layout of Fig. 2A.

[0007] The Fig. 2C-2D are sectional views of the integrated circuit layout of Fig. 2A.

[0008] Fig. Figure 3A is a graphical representation of an integrated circuit layout with tap cells according to embodiments of the present disclosure.

[0009] Fig. 3B is an enlarged partial view of the integrated circuit layout of Fig. 3A.

[0010] The Fig. 3C-3D are sectional views of the integrated circuit layout of Fig. 3A.

[0011] The Fig. Figures 4A-4B, 5A-5B, 6A-6B, 7A-7B, 8A-8B, 9A-9B, 10A-10B, 11A-11B, 12, 13, 14A, 14B, 14C and 14D schematically show different stages of the fabrication of an integrated circuit with tap cells according to the present disclosure.

[0012] The Fig. Figures 15A-15B schematically show an integrated circuit structure according to embodiments of the present disclosure.

[0013] The Fig. 16A, Fig. 16B, Fig. 16C, Fig. 16D, Fig. 16E and Fig. Figure 16F schematically show exemplary sampling cells according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] The disclosure below provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the description below may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0015] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0016] The fins can be structured using any suitable method. For example, the fins can be structured using one or more photolithographic processes, such as dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithographic and self-aligning processes, enabling the creation of structures with, for example, smaller grid spacings than those achievable with a single direct photolithographic process. For instance, in one embodiment, a sacrificial layer is produced over a substrate and then structured using a photolithographic process. Spacers are produced along the structured sacrificial layer using a self-aligning process. Subsequently, the sacrificial layer is removed, and the remaining spacers can then be used to structure the fins.

[0017] Integrated circuit (IC) layout diagrams feature tap cells, also known as well tap cells, pickup tap cells, or tap structures, to improve the latch-up immunity of ICs. A tap cell can be a standard cell that defines a region within a doped well where the doped well is connected to a bias voltage, such as a power supply voltage. According to current technology, a tap cell is constructed similarly to a transistor, with active regions fabricated across the doped well and a gate structure fabricated across these active regions.

[0018] In connection with the current trend toward miniaturization of semiconductor devices, one or more considerations arise regarding the placement of sample cells in an IC layout scheme for IC fabrication, such as processing difficulties resulting from the small lithographic critical dimension (CD) and mixed channel effects. Embodiments of the present disclosure provide a sample cell without gate structures to address one or more of these considerations. In particular, a sample cell according to embodiments of the present disclosure may include a semiconductor fin structure and an epitaxial crown grown from the semiconductor fin structure.Since the tap cell has no gate structures, the design layout with such tap cells can be smaller by avoiding design rules for gate grid spacing in directions along and across the fin structures. In some embodiments, circuit layouts incorporating the tap cells according to this disclosure can reduce the circuit area by between approximately 7% and 15%. As a result, one or more effects can be achieved with the tap cells according to this disclosure, such as: easing processing constraints, increasing latch-up immunity with smaller well tap areas, reducing well tap resistance, and improving tap current collection.

[0019] Fig. Figure 1 is a schematic representation of a layout design 100 with a tap cell 102 according to embodiments of the present disclosure. The layout design 100 can be part of an integrated circuit. The layout design 100 comprises two transistors 104a, 104b. The tap cell 102 is arranged between the transistors 104a, 104b. The transistors 104a, 104b can have an active region 140 along the x-direction and gate structures 142 along the y-direction. In some embodiments, the transistors 104a, 104b can be FinFET devices, wherein the active region 140 can have one or more semiconductor fins and epitaxially grown source / drain regions. The gate structures 142 can have a dielectric gate layer and a gate electrode layer formed around the semiconductor fin.The tap cell 102 comprises an active region 120 along the same direction as the active region 140 of transistors 104a, 104b. In some embodiments, the active region 120 may have one or more semiconductor fins along the x-direction and epitaxial regions grown from the one or more semiconductor fins. The tap cell 102 does not have a gate structure across the active region 120. The active region 120 of the tap cell 102 may be connected to conductive vias and traces along the x-direction and form a conductive wall between transistors 104a, 104b. The conductive wall blocks mutual interference between transistors 104a, 104b.

[0020] The active region 120 of tap cell 102 can be connected to a power rail, thereby reducing substrate resistance and unwanted positive feedback in the integrated circuit. For example, if the active region 120 is an n-well region, it can be connected to the VDD power rails. Connecting the active region 120 to power rails applies a body bias to transistors 104a and 104b, preventing unwanted latch-up caused by parasitic bipolar transistors in integrated circuits. Through tap cell 102, n-well regions of transistors 104a and 104b are connected to VDD power rails, and p-well regions or p-substrates are connected to VSS power rails, which are the electrical ground.Connecting the basin areas and substrate areas to the VDD busbars or VSS busbars can lead to a reduction in substrate resistance and a reduction in unwanted positive feedback in the integrated circuit.

[0021] Current technologies incorporate dummy gate electrodes (dummy polysilicon conductors) in the sampling cells to achieve process uniformity. However, these dummy gate electrodes negatively increase the chip area utilization of the sampling cells. By omitting gate structures in sampling cell 102, the chip area is reduced. As shown in Fig. As shown in Figure 1, the sampling cell 102 can have a cell width Wtc along the y-direction. In some embodiments, the ratio of cell width Wtc to cell width Wsc lies in a range between approximately 0.2 and approximately 0.8.

[0022] For clarity, conductive layers and dielectric materials are not shown in layout design 100. Further details are described in the following figures.

[0023] Fig. 2A is a schematic representation of an integrated circuit layout 200 with tap cells according to embodiments of the present disclosure. Fig. 2B is an enlarged partial view of the integrated circuit layout 200 from Fig. 2A. The Fig. 2C and Fig. 2D are sectional views of the integrated circuit layout 200 along lines CC and DD respectively in Fig. 2B.

[0024] The integrated circuit layout 200 can be part of an integrated circuit, such as an image signal processor. An image signal processor can have columns of analog-to-digital converters (ADCs), logic circuits, and digital-to-analog converters (DACs). Fig. 2A features an integrated circuit design with 200 functional cells 204 arranged in rows and columns.

[0025] Each function cell 204 can be a standard cell configured to perform a specific function or part of a standard cell. In the example of the Fig. In 2A-2D, the functional cell 204 comprises two transistors 240. In some embodiments, the functional cell 204 can be a cell in an ADC circuit. The transistors 240 can be FinFET transistors, planar transistors, or GAA transistors. Fig. 2A-2D are the transistors 240 FinFET transistors fabricated on fin structures 241 along the x-direction. In some embodiments, the transistors 240 are arranged side by side along the x-direction. The transistors 240 can have an active region 242 along the x-direction and gate structures 244 along the y-direction. In some embodiments, the transistors 240 can be FinFET devices, wherein the active region 242 can have one or more semiconductor fins and epitaxially grown source / drain regions. The gate structures 244 can have a dielectric gate layer and a gate electrode layer fabricated around the semiconductor fin. Conductive structural elements, such as source / drain contacts 246, gate contacts 248, and vias 250, can be fabricated over the active regions 242 and the gate structures 244.

[0026] The transistors 240 are arranged within a cell boundary 204b, which defines a cell region. In some embodiments, the integrated circuit layout 200 has a tap region 202 around the cell boundary 204b. The tap region 202 can be a belt-shaped region along the cell boundary 204b. The tap region 202 can have horizontal segments 202h along the x-direction and vertical segments 202v along the y-direction. The horizontal segment 202h is shared by two functional cells 204 arranged in a column along the y-direction, as shown in Fig. Figure 2A shows that the vertical segment 202h is shared by two functional cells 204 arranged in a row along the x-direction (not shown here). The horizontal segment 202h of the tap area 202 can have a width W202h, and the vertical segment 202v of the tap area 202 can have a width W202v. The width W202h and the width W202v can be the same or different from each other. In some embodiments, the tap area 202 is free of gate structures. The widths W202h and W202v can be selected to be sufficient to create tap cells or tap structures without gate structures.

[0027] In some embodiments, sampling cells 220 are manufactured in the horizontal segments 202h of the sampling area 202. In some embodiments, a single sampling cell 220 is manufactured in a single horizontal segment 202h. The sampling cell 220 has a length L220 along the x-direction. In some embodiments, the length L220 can be in a range between approximately 100 nm and approximately 600,000 nm. The sampling cell 220 is configured to block noise between the functional cells 204 on opposite sides of the horizontal segment 202h of the sampling area 202. The sampling cell 220 can have a continuous conductive structure that prevents electrical signals from one side of the sampling cell 220 from passing across to the other side of the sampling cell 220. In some embodiments, the sampling cell 220 can have an active area 222 that is arranged along the x-direction.The active region 222 can extend substantially along the entire length of the tap cell 220 in the x-direction. The active region 222 can have a semiconductor fin structure extending along the x-direction and an epitaxial material grown from the semiconductor fin structure. Contact structure elements 224, 226, 228 are subsequently fabricated over the active region 222.

[0028] In some embodiments, dummy tap cells 260 are fabricated in the vertical segments 202v of the tap area 202. In some embodiments, one or more dummy tap cells 260 are fabricated in a single vertical segment 202v. The one or more dummy tap cells 260 can be arranged in a column along the y-direction. The dummy tap cells 260 can be fabricated to provide a structure density equilibrium. In other embodiments, the dummy tap cells 260 can block some of the noise between the functional cells 204 on opposite sides of the vertical segments 202v of the tap area 202. In other embodiments, the dummy tap cells 260 can be used to connect a substrate or an active area to a busbar. Each dummy tap cell 260 can have a column-like conductive structure.In some embodiments, the dummy tap cell 260 can have an active region 262 arranged along the x-direction. The active region 262 can extend substantially over the width and length of the vertical segment 202v of the tap region 202. The active region 262 can have a semiconductor fin structure extending along the x-direction and an epitaxial material grown from the semiconductor fin structure. Subsequently, conductive structural elements 264, 266, 268 are fabricated over the active region 262.

[0029] The Fig. Figures 2B-2D schematically show details of the sampling cells 220 according to some embodiments of the present disclosure. As in the Fig. 2B and Fig. As shown in Figure 2C, the transistors 240 are FinFET transistors. The active region 242 comprises several fin structures 241 and source / drain regions 243. In some embodiments, the number of fin structures 241 can range from 1 to approximately 20. The fin structures 241 are fabricated over a substrate 201 along the x-direction. An isolation region 210 is fabricated around the lower part of the fin structure 241. The gate structure 244 can have a gate length L244 along the x-direction. The gate length L244 can be selected according to the function of the transistor 240. For example, a large gate length L244 can be selected for the transistor 240 if the transistor 240 is a high-voltage transistor, while a small gate length L244 can be selected for the transistor 240 if the transistor 240 is a low-voltage transistor.In some embodiments, the gate length L244 can be in a range between approximately 16 nm and approximately 12000 nm.

[0030] The gate structure 244 is fabricated across a central portion of the multiple fin structures 241. The fin structures 241 extend beyond the gate structure 244 in the x-direction. The source / drain regions 243 are fabricated over the fin structures 241 extending from the gate structure 244. In some embodiments, dummy gate structures 244d are fabricated over the end portions of the fin structures 241. The dummy gate structures 244d provide physical boundaries for the source / drain regions 243, enabling the source / drain regions 243 to be grown with sufficient volume and desirable shapes. The dummy gate structure 244d can have a gate length L244d along the x-direction. The gate length L244d can be selected according to the design rules and the wavelengths of the structuring tool. In some embodiments, the gate length L244d can be in a range between approximately 16 nm and approximately 240 nm.In some embodiments, a source / drain length L243 is defined by a distance between the dummy gate structures L244d and the gate structure 244.

[0031] The tap cell 220 is arranged between the transistors 240 along the x-direction and forms a conductive wall between the transistors 240. As shown in the Fig. As shown in Figures 2B-2C, the active region 222 of the tap cell 220 can have one or more fin structures 221 extending along the x-direction and epitaxial crowns 223 grown from the two or more fin structures 221. The fin structures 221 are parallel to the fin structures 241 of the transistor 240. In some embodiments, the fin structures 221 and the fin structures 241 can be produced simultaneously and have the same pitch. In other embodiments, the fin structures 221 can have a smaller pitch than the fin structures 241. The fin structures 221 have a pitch P221. In some embodiments, the pitch P221 of the fin structures 221 can be in a range between about 14 nm and about 32 nm. In some embodiments, the sampling cell 220 can have several fin structures to obtain sufficient conductive volume.In some embodiments, the number of fin structures 221 can be in a range between 1 and 4, for example 3.

[0032] The epitaxial crowns 223 are grown by the fin structures 221 above the isolation area 210. In some embodiments, the epitaxial crowns 223 in the tap cells 220 and the source / drain regions 243 of the transistors 240 are produced in different epitaxial deposition processes. In some embodiments, the epitaxial crowns 223 in the tap cells 220 can be produced simultaneously with the source / drain regions 243 of the transistors 240.

[0033] Since there are no gate structures across the fin structures 221, the epitaxial crown 223 can have a smaller volume than the source / drain regions 243. In some embodiments, the source / drain region 243 can have a fused volume resulting from the epitaxial growth of the multiple fin structures 241, while the epitaxial crowns 223 grown from different fin structures 221 remain separate from each other.

[0034] In some embodiments, after the formation of the epitaxial crown 223, the fin structures 221 remain above a top surface 210t of the isolation area 210. The epitaxial crown 223 can be grown from an upper part of the fin structures 221. For example, the epitaxial crowns 223 can be grown from the top surfaces and side walls of the fin structures 221. In some embodiments, the epitaxial crowns 223 in the tap cells 220 can be higher than the source / drain areas 243 in the transistors 240.

[0035] As in Fig. As shown in Figure 2D, the fin structure 221 extends almost the entire length L202 of the sampling cell 220. The epitaxial crown 223 also extends along the length L202 of the sampling cell 220. Each fin structure 221 and the corresponding epitaxial crown 223 form a continuous conductive body. In some embodiments, the active area 222 can have two or more continuous conductive bodies separated by dielectric materials, such as a contact etch stop layer and an intermediate dielectric layer (in the Fig. 2A-2D (omitted for clarity) are separated.

[0036] In some embodiments, one or more tap contact structural elements 224 are fabricated on the active area 222. The tap contact structural elements 224 can be fabricated during the same process as the source / drain contact structural elements 246. In some embodiments, the tap contact structural elements 224, like the source / drain contact structural elements 246, can be fabricated along the y-direction. In some embodiments, the tap contact structural elements 224 extend transversely across the one or more fin structures 221 and the epitaxial crowns 223 and electrically connect the one or more fin structures 221 and the epitaxial crowns 223.

[0037] In some embodiments, two or more tap contact structural elements 224 can be distributed along the active region 222 depending on the tap cell length L202 and the structure density of the source / drain regions 243. In some embodiments, the tap contact structural elements 224 have a grid spacing P224 along the x-direction. In some embodiments, the grid spacing P224 can be selected according to the gate length L244 of the gate structures 244 in the transistors. In some embodiments, the grid spacing P224 is greater than the gate length L244. In some embodiments, the grid spacing P224 corresponds to the sum of the gate length L244 and the source / drain length L243.

[0038] In some embodiments, a tap line 226 is provided above the active area 222, which electrically connects the two or more tap contact structural elements 224. The tap line 226 extends along the entire length of the active area 222. As shown in the Fig. 2C and Fig. As shown in Figure 2D, the tap line 226 and the tap contact structural elements 224 effectively form a conductive wall with the active region 222. In some embodiments, the tap line 226 and the gate contact structural elements 248 of the transistors 240 can be structured and fabricated in the same process. In some embodiments, the gate contact structural elements 248 can be conductive lines fabricated along the x-direction.

[0039] In some embodiments, conductive vias 228 can be made above the tap line 226 to establish a connection with subsequent conductive layers, for example, an interconnect structure. In some embodiments, the conductive vias 228 can be aligned with the tap contact structural elements 224. The conductive vias 228 can be made with the conductive vias 248 above the transistors 240 during the same process.

[0040] Fig. 3A is a schematic representation of an integrated circuit layout 200a with tap cells according to embodiments of the present disclosure. Fig. 3B is an enlarged partial view of the integrated circuit layout 200a from Fig. 3A. The Fig. 3C and Fig. 3D images are sectional views of the integrated circuit layout 200a along lines CC and DD, respectively. Fig. 3B. The integrated circuit layout 200a is similar to the integrated circuit layout 200, except that the integrated circuit layout 200a has two or more tap cells 220a arranged between the two transistors 240 instead of one long continuous tap cell 220.

[0041] The sampling cells 220a resemble the sampling cell 220, except that the sampling cells 220a are shorter along the x-direction than the sampling cell 220. In some embodiments, two or more sampling cells 220a can be arranged along the x-direction with a gap G220a between adjacent sampling cells 220a. As shown in the Fig. As shown in Figure 3A, a plurality of tap cells 220a are arranged between the transistors 240, forming a substantially conductive wall between the transistors 240. As shown in the Fig. As shown in Figures 3B-3C, each tap cell 220a has an active region 222a. The active region 222a can have one or more fin structures 221a extending along the x-direction and epitaxial crowns 223a grown from the two or more fin structures 221a. The fin structures 221a are parallel to the fin structures 241 of the transistors 240. In some embodiments, the fin structures 221a and the fin structures 241 can be produced simultaneously and have the same grid spacing. In some embodiments, the tap cell 220 can have multiple fin structures to provide a sufficient conductive volume. In some embodiments, the number of fin structures 221 can be in a range between 1 and 4, for example, 3.

[0042] The epitaxial crowns 223a are grown from the fin structures 221a above the isolation region 210. In some embodiments, the epitaxial crowns 223a can be produced simultaneously with the source / drain regions 243. Without support from the gate structures across the fin structures 221a, the epitaxial crown 223a may have a smaller volume than the source / drain regions 243 produced at the same time. By keeping the fin structures 221a short along the x-direction, the epitaxial crown 223a can be grown more densely, thus increasing its volume. As shown in the Fig. 3A and Fig. As shown in the 3D figure, several tap cells 220a are distributed along the x-direction to cover the length L202 of the tap area 202. In some embodiments, each of the tap cells 220a has a cell length L220a along the x-direction. Adjacent tap cells 220a have a gap G220a. The cell length L220a and the gap G220a can be selected according to the design rules. In some embodiments, the gap G220a can be in a range between about 1 nm and about 20 nm. The cell length L220a can be in a range between about 20 nm and about 12000 nm. In some embodiments, the tap cells 220a are arranged at a cell grid spacing P220a. In some embodiments, the cell grid spacing P220a can be similar to the grid spacing of the source / drain regions 243 in the transistors 240.

[0043] The sampling cells 220a can have one or more sampling contact structural elements 224a that are fabricated on the active area 222. In some embodiments, a sampling contact structural element 224a is fabricated near a central region of the sampling cell 220a. The sampling contact structural elements 224a can be fabricated during the same process as the source / drain contact structural elements 246. In some embodiments, the sampling contact structural elements 224a, like the source / drain contact structural elements 246, can be fabricated along the y-direction. In some embodiments, the sampling contact structural elements 224a extend transversely across the one or more fin structures 221a and the epitaxial crowns 223a and electrically connect the one or more fin structures 221a and the epitaxial crowns 223a.

[0044] In some embodiments, a tap line 226a is brought into contact with the tap contact structural elements 224a above the active area 222. The tap line 226a extends along the entire length of the active area 222a. The tap line 226a and the tap contact structural element 224a effectively form a conductive wall with the active area 222a.

[0045] As discussed above, the sampling cells 220, 220a can be produced with functional cells on the same substrate. Fig. Figures 4A-4B, 5A-5B, 6A-6B, 7A-7B, 8A-8B, 9A-9B, 10A-10B, 11A-11B, 12, 13 and 14A-14D schematically show different stages of the fabrication of an integrated circuit with tap cells according to the present disclosure.

[0046] Fig. Figure 4A is a schematic perspective view of part of the integrated circuit 200 after fabrication of the fin structures 221 for the tap cell 220 and the fin structures 241 for the transistors 240. The gate structures 244 are fabricated across the fin structures 241. Fig. 4B is a schematic sectional view of the fin structures 221 for the sampling cell 220.

[0047] As in the Fig. 4A and Fig. As shown in Figure 4B, the fin structures 221 and 241 are fabricated on substrate 201. Substrate 201 can be a silicon substrate. Alternatively, substrate 201 can comprise: another elemental semiconductor, such as germanium; a compound semiconductor, such as IV-IV compound semiconductors, e.g., SiC and SiGe; a III-V compound semiconductor, e.g., GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0048] In some embodiments, the substrate 201 comprises a crystalline silicon substrate (e.g., a wafer). A p-substrate or an n-substrate can be used, and the substrate 201 can have various doped regions depending on the design requirements. In some embodiments, the doped regions can be doped with p- or n-doped elements. For example, the doped regions can be doped with p-doped elements such as boron or BF₂; n-doped elements such as phosphorus or arsenic; and / or combinations thereof. The doped regions can be configured for an n-FinFET or, alternatively, for a p-FinFET.In some alternative embodiments, the substrate 201 can be made from another suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Alternatively, the substrate can also have an epitaxial layer. For example, the substrate can have an epitaxial layer located over a bulk semiconductor. Furthermore, the substrate can be strained to improve performance. For example, the epitaxial layer can have a semiconductor material different from that of the bulk semiconductor, such as a layer of silicon germanium located over bulk silicon, or a layer of silicon located over bulk silicon germanium.Such strained substrates can be fabricated by selective epitaxial growth (SEG). Alternatively, the substrate can have a semiconductor-on-insulator (SOI) structure. It can also alternatively feature a buried dielectric layer, such as a buried oxide layer (BOX layer), which can be fabricated using methods such as separation by implantation of oxygen (SIMOX), wafer bonding, SEG, or another suitable process.

[0049] The fin structures 221, 241 are arranged above the substrate 201. The fin structures 221, 241 can be made of the same material as the substrate 201 and can extend continuously from the substrate 201. In this embodiment, the fin structures 221, 241 are made of silicon (Si). The silicon layer of the fin structures 221, 241 can be intrinsically conductive or doped with an n-type or p-type dopant. The fin structures 221, 241 can be produced by suitable structuring and etching processes.

[0050] After fabrication of the fin structures 221, 241, the insulating region 210 is produced on the substrate 201 and around the lower portions of the fin structures 221, 241. The insulating region 210 can be produced by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or another suitable deposition process followed by a etching process. In some embodiments, a dielectric material can be conformally fabricated to cover the fin structures 221, 241 using a suitable deposition process, such as atomic layer deposition (ALD). In some embodiments, the dielectric material can comprise silicon oxide, silicon nitride, silicon oxide nitride, fluorine-doped silicate glass (FSG), a low-k dielectric, or combinations thereof.The dielectric material is subjected to a recess etching process using a suitable anisotropic etching process to expose the fin structures 221, 241. As in . Fig. As shown in Figure 4A, the fin structures 221, 241 extend above a top surface 210t of the insulation area 210.

[0051] The gate structures 244 are then fabricated over the fin structures 231. In some embodiments, the gate structures 244 can be sacrificial gate structures. The gate structures 240 are fabricated over a portion of the fin structure 241, which is intended to have channel regions. In some embodiments, the gate structures 244 can comprise a dielectric sacrificial gate layer, a sacrificial gate electrode layer, a pad layer, and a mask layer.

[0052] The dielectric sacrificial gate layer can be produced by unstructured deposition over the fin structures 221, 241 and the insulating area 210. The dielectric sacrificial gate layer comprises one or more layers of insulating material, such as a silicon oxide-based material. In some embodiments, silicon oxide produced by CVD is used. In some embodiments, the dielectric sacrificial gate layer has a thickness in the range of approximately 1 nm to approximately 5 nm.

[0053] The sacrificial gate electrode layer is then deposited in an unstructured manner onto the dielectric sacrificial gate layer. The sacrificial gate electrode layer contains silicon, such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer is in the range of approximately 100 nm to approximately 200 nm. In some embodiments, the sacrificial gate electrode layer undergoes a planarization operation. The sacrificial gate electrode layer can be fabricated using CVD, such as LPCVD and PECVD, PVD, ALD, or other suitable processes.

[0054] Next, the pad layer and the mask layer are fabricated over the sacrificial gate electrode layer. The pad layer can contain silicon nitride. The mask layer can contain silicon oxide. Then, a structuring operation is performed on the mask layer, the pad layer, the sacrificial gate electrode layer, and the dielectric sacrificial gate layer to fabricate the gate structures 240.

[0055] After the gate structures 240 are fabricated, a sidewall spacer layer 245 is then produced on the sidewalls of the gate structures 244 and the fin structures 221, 241. In some embodiments, the sidewall spacer layer 245 is produced by unstructured deposition of an insulating material followed by anisotropic etching to remove the insulating material from horizontal surfaces. The sidewall spacer layer 245 can have a thickness in the range of approximately 2 nm to approximately 10 nm. The sidewall spacer layers 245 can comprise one or more silicon nitride-based materials, such as SiN, SiON, SiOCN, or SiCN, and combinations thereof.

[0056] After fabrication of the sidewall spacer layer 245, a mask layer 271 is arranged over the fin structures 241, 221 and the gate structures 240. In some embodiments, the mask layer 271 can be deposited by ALD or another suitable process. The mask layer 271 can be structured to protect selected zones during subsequent epitaxial processes. The mask layer 271 can be a low-k dielectric material, for example, a dielectric material with a k-value in the range of about 5 to about 8. In some embodiments, the mask layer 271 is SiOCN with a thickness of about 50 Å.

[0057] As in the Fig. 4A and Fig. As shown in Figure 4B, a photoresist layer 280 is deposited and structured to expose zones for the subsequent fabrication of source / drains. In the example of the Fig. 4A and Fig. 4B zones of n-devices are exposed. Other zones, such as the sampling cells 220 and the p-device zones, are covered by the photoresist layer 280.

[0058] After structuring the photoresist layer 280, the mask layer 271, which has been exposed by the photoresist layer 280, is removed, and the fin structures 241 in the n-device are exposed. A back-etching process is performed to remove the exposed fin structures 241. In some embodiments, the fin structures 241 are recessed to a height below the top surface 210t of the isolation area 210, forming source / drain recesses above this level. The photoresist layer 280 is then removed, as described in the Fig. 5A-5B is shown. Fig. 5A is a schematic perspective representation of part of the integrated circuit 200 after the etching process and removal of the photoresist layer. Fig. 5B is a sectional view of the fin structures 221 for the sampling cell 220.

[0059] As in the Fig. 5A and Fig. As shown in Figure 5B, the mask layer 271 covers the semiconductor materials in the fin structures 221 in the tap cell 220 and the fin structures 241 in the p-device zone. The source / drain regions 243 for the n-devices are grown from exposed semiconductor surfaces of the fin structures 241. As shown in Fig. As shown in Figure 6A, the epitaxial source / drain regions 243 for the n devices are fabricated. The epitaxial source / drain regions 243 for the n devices can have one or more layers of Si, SiP, SiC and SiCP with n dopants.

[0060] A mask layer 272 is then deposited over the source / drain regions 243 for the n-devices, the fin structures 241 for the p-devices, the fin structures 221 for the sampling cells 220, and the gate structures 240. In some embodiments, the mask layer 272 can be deposited using ALD or another suitable process. The mask layer 272 can be structured to protect selected zones during the subsequent epitaxial processes. The mask layer 272 can be a low-k dielectric material, for example, a dielectric material with a k-value in the range of approximately 5 to approximately 8. In some embodiments, the mask layer 272 is SiOCN with a thickness of approximately 50 Å. After this operation, the fin structures 221 in the sampling cell 220 are covered by the mask layers 271 and 272.

[0061] As in the Fig. 7A and Fig. As shown in Figure 7B, a photoresist layer 281 is deposited and structured to expose zones for subsequent source / drain fabrication. In the example of the Fig. 7A and Fig. 7B zones for p-devices are exposed. Other zones, such as the sampling cells 220 and the n-device zones, are covered by the photoresist layer 281.

[0062] After structuring the photoresist layer 281, the mask layer 272, which has been exposed by the photoresist layer 281, is removed, and the fin structures 241 in the p-device are exposed. A back-etching process is performed to remove the exposed fin structures 241. In some embodiments, the fin structures 241 are recessed to a height below the top surface 210t of the isolation area 210, forming source / drain recesses above this level. The photoresist layer 281 is then removed, as described in the Fig. 8A-8B is shown.

[0063] As in the Fig. 8A and Fig. As shown in Figure 8B, the mask layer 272 covers the semiconductor materials in the fin structures 221 in the tap cell 220 and the source / drain regions 243 in the n-device zone. The source / drain regions 243 for the p-devices are grown from the exposed semiconductor surfaces of the fin structures 241. As shown in Fig. As shown in Figure 9A, the epitaxial source / drain regions 243 for the p-devices are fabricated. In some embodiments, the epitaxial source / drain regions 243 for the p-device can have one or more layers of Si, SiGe, Ge and p-dopeds.

[0064] A mask layer 273 is then deposited over the source / drain regions 243 for the n-devices, the source / drain regions 243 for the p-devices, the fin structures 221 for the sampling cells 220, and the gate structures 240. In some embodiments, the mask layer 273 can be deposited using ALD or another suitable process. The mask layer 273 can be structured to protect selected zones during the subsequent epitaxial processes. The mask layer 273 can comprise a suitable dielectric material, for example, a silicon nitride-containing material. In some embodiments, the mask layer 273 comprises SiN with a thickness of approximately 50 Å. As shown in Fig. As shown in Figure 9B, the fin structures 221 are covered by three mask layers 271, 272, 273.

[0065] As in the Fig. 10A and Fig. As shown in Figure 10B, a photoresist layer 282 is deposited and structured to expose zones of the sampling cells 220. Other zones, such as the zones for the n-devices and p-devices, are covered by the photoresist layer 282.

[0066] After structuring the photoresist layer 282, the mask layers 273, 272, 271 exposed by the photoresist layer 282 are partially removed, and the fin structures 221 for the scanning cells 220 are exposed. In some embodiments, the fin recession process is omitted. As in Fig. As shown in Figure 10B, the upper parts of the fin structures 221 are exposed. Fig. As shown in Figure 10B, the mask layers 273, 272, 271 remain partially in the trench between the fin structures 221 and above the isolation area 210. Consequently, the mask layers 273, 272, 271 form recess structural elements 225. The recess structural elements 225 are arranged above the isolation area 210. As shown in Fig. As shown in Figure 10B, a top surface 225t of the recess structure elements 225 is located above the top surface 210t of the insulation region 210. A top surface 221t and side walls 221s of the fin structures 221 are exposed above the recess structure elements 225. The photoresist layer 282 is then removed for epitaxial deposition.

[0067] As in the Fig. 11A and Fig. As shown in Figure 11B, the mask layer 273 covers the semiconductor materials of the source / drain regions 243 in the n-device zone, and the p-device prevents further epitaxial growth on the source / drain regions 243. The epitaxial crowns 223 for the tap cells 220 are grown from exposed semiconductor surfaces of the fin structures 221. In some embodiments, the epitaxial crowns 223 are grown from the top 221t and side walls 221s of the fin structures 221. The epitaxial crowns 223 are produced over the recess structure elements 225. In some embodiments, the epitaxial crown 223 can resemble the source / drain regions of an NMOS transistor or a PMOS transistor.

[0068] In some embodiments, after fabrication of the epitaxial crowns 223, the mask layer 273 can remain on the source / drain areas 243 for the p- and n-devices. The mask layer 272 can remain on the source / drain areas 243 for the n-devices. In other words, the mask layers 272 and 273 cover the source / drain areas 243 of the n-devices. The mask layer 273 covers the source / drain areas 243 for the p-devices.

[0069] In Fig. In Figure 12, which is a cross-sectional view of the sampling cell 220, a contact etch stop layer (CESL) 274 is fabricated over the exposed surfaces. The CESL 274 is fabricated on the epitaxial source / drain regions 243, the epitaxial crowns 223, and the mask layer 273 or the recess structure elements 225. In some embodiments, the CESL 274 has a thickness in the range of approximately 1 nm to approximately 15 nm. The CESL 274 can be Si3N4, SiON, SiCN, or another suitable material and can be fabricated by CVD, PVD, or ALD.

[0070] An interlayer dielectric layer (ILD layer) 275 is fabricated over the CESL 274. The materials for the ILD layer 275 contain compounds with Si, O, C, and / or H, such as silicon dioxide, SiCOH, and SiOC. Organic materials, such as polymers, can also be used for the ILD layer 275. After fabrication of the ILD layer 275, a planarization operation, such as CMP, is performed to expose the sacrificial gate structure for a replacement process. The ILD layer 275 protects the epitaxial source / drain regions 243 and the epitaxial crowns during the gate replacement process. During the gate replacement process, the dielectric sacrificial gate layer and the sacrificial gate electrode layer are removed to expose the fin structures 241. A dielectric gate layer is then produced over the fin structures 241 using CVD, ALD or another suitable method.The dielectric gate layer comprises one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, another suitable dielectric material, and / or combinations thereof. Examples of high-k dielectric materials include HfO₂, HfSiO₂, HfSiON₄, HfTaO, HfTiO₂, HfZrO₂, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide alloy (HfO₂-Al₂O₃ alloy), other suitable high-k dielectric materials, and / or combinations thereof. A gate electrode layer is fabricated on the dielectric gate layer. The gate electrode layer has one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or combinations thereof.

[0071] Following the gate replacement process sequence, the contact structure elements 224, 226 are fabricated in the ILD layer 275. A second dielectric layer 277 can be deposited over the ILD layer 275, and the conductive vias 228 can be fabricated in the dielectric layer 277, as shown in the Fig. Figures 14A-14D show an interconnect structure comprising several dielectric layers with metal conductors and vias (not shown here) that can be fabricated on the second ILD layer 277 and electrically connected to the transistors 240 and the tap cells 220. Fig. As shown in Figure 14A, the epitaxial crowns 223 are arranged above the isolation area 210. The epitaxial source / drain areas 243 are, as shown in Fig. As shown in Figure 14D, the epitaxial crowns 223 are partially arranged below the top surface of the isolation area 210. In some embodiments, the epitaxial crowns 223 can be arranged at a greater height along the z-direction than the source / drain areas 243.

[0072] The Fig. 15A and Fig. Figure 15B schematically shows a layout 300 according to embodiments of the present disclosure. The layout 300 is similar to the design layout 100 and the circuit layout 200, except that the layout 300 has planar devices. Fig. 15A is a graphical representation of an integrated circuit layout 300 with tap cells according to embodiments of the present disclosure. Fig. Figure 15B is a sectional view of the integrated circuit layout 300 along line BB in Fig. 15A. The integrated circuit layout 300 can be part of an integrated circuit, such as an image signal processor. An image signal processor can have columns of ADCs (analog-to-digital converters), logic circuits, and DACs (digital-to-analog converters). The layout 300 can have a tap cell 320 located between two transistors 340. The transistors 340 are planar devices. The transistors 340 can have an active region 342 along the x-direction and gate structures 344 along the y-direction. Conductive structural elements, such as source / drain contacts 346, gate contacts 348, and vias 350, are fabricated over the active regions 342 and the gate structures 344.

[0073] In some embodiments, tap cells 320 are located between the transistors 340. In some embodiments, a single tap cell 320 is provided between the transistors 340. The tap cell 320 is configured to block noise between the transistors 240. The tap cell 320 may have a continuous conductive structure that prevents electrical signals from one side of the tap cell 320 from passing across to the other side. In some embodiments, the tap cell 320 may have an active region 322 arranged along the x-direction. The active region 322 may extend substantially over the entire length of the tap cell 320 along the x-direction. Conductive structural elements 324, 326, 328 are subsequently fabricated over the active region 322.

[0074] The Fig. Figures 16A-16F schematically show exemplary sampling cells according to embodiments of the present disclosure. Fig. Figure 16A shows sectional views of a source / drain region of an n-transistor and a tap cell with an active p-region. As in Fig. As shown in Figure 16A, the fin structure 241 for the n-transistor has a larger grid spacing than the fin structures 221 of the tap cell. Fig. Figure 16B shows sectional views of epitaxial crowns 223 that were fabricated from epitaxial p-material and epitaxial n-material. As in Fig. As shown in Figure 16B, the epitaxial n-crowns 223 have an essentially triangular cross-section, while the epitaxial p-crowns 223 have a rounded cross-sectional shape. Furthermore, the epitaxial crowns 223 that have grown on outer fin structures 221 are lower than the epitaxial crowns 223 that have grown on the middle fin structure 221. In the Fig. 16C and Fig. Figure 16D shows cross-sections of a sampling cell with a long active area. Fig. 16E and Fig. Figure 16F shows cross-sections of sampling cells with short active areas.

[0075] The various embodiments or examples described here offer several advantages over the prior art. Embodiments of the present disclosure provide a sampling cell without gate structures. By omitting the gate structures, the device density can be increased.

[0076] It is understood that not all advantages have necessarily been discussed here, no specific advantage is required for all embodiments or examples, and other embodiments or examples may offer other advantages.

[0077] Some embodiments of the present disclosure provide a sampling cell comprising: a first fin structure and a second fin structure produced on a substrate along a first direction; a first epitaxial crown arranged on the first fin structure; a second epitaxial crown arranged on the second fin structure; an isolation area arranged on the substrate and surrounding the lower portions of the first fin structure and the second fin structure; a recess structure element arranged on a top surface of the isolation area and between the first fin structure and the second fin structure; and a contact etch stop layer arranged on the first epitaxial crown and the second epitaxial crown and the recess structure element, wherein the first epitaxial crown and the second epitaxial crown are arranged above the recess structure element.

[0078] Some embodiments of the present disclosure provide an integrated circuit structure comprising: a cell region arranged on a substrate, wherein the cell region comprises: a first transistor having a first source / drain region and a second source / drain region arranged along a first direction; and a gate structure arranged between the first source / drain region and the second source / drain region, the gate structure being arranged along a second direction perpendicular to the first direction; and a tap region arranged on a boundary of the cell region on the substrate, wherein the tap region comprises: one or more tap cells arranged along the first direction, the one or more tap cells not having any gate structures.

[0079] Some embodiments of the present disclosure provide a method. The method comprises the following steps: fabricating two or more first fin structures in a cell region and two or more second fin structures in a tap region surrounding the cell region on a substrate; fabricating an insulating region on the substrate surrounding the first and second fin structures; depositing a dielectric gate layer and a gate electrode layer over the cell region and the tap region; removing the dielectric gate layer and the gate electrode layer from the tap region and fabricating a gate structure over the two or more first fin structures; depositing a first mask layer over the two or more first fin structures and two or more second fin structures; and structuring the first mask layer to expose the two or more first fin structures.Recessing the two or more first fin structures to form source / drain recesses; creating source / drain areas within the source / drain recesses; depositing a second mask layer over the two or more second fin structures and the source / drain areas; structuring the second mask layer to expose the two or more second fin structures; removing the first and second mask layers to expose the two or more second fin structures; and creating epitaxial crowns on the two or more second fin structures.

[0080] Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present disclosure. It should be clear to those skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other methods and structures to achieve the same objectives and / or to obtain the same advantages as in the embodiments presented here. Those skilled in the art should also recognize that such equivalent interpretations do not deviate from the fundamental concept and scope of protection of the present disclosure and that they can make various changes, substitutions, and modifications without deviating from the fundamental concept and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 675,310

[0001]

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