PACKAGE STRUCTURES AND METHODS FOR THEIR MANUFACTURING

Abstract

Embodiments of the present disclosure relate to methods for fabricating a package structure. One method comprises: depositing a first layer on a front side of a wafer and a second layer on a back side of the wafer; depositing a third layer on the first layer and a fourth layer on the second layer; depositing an etch stop layer on the third layer; depositing a fifth layer on the etch stop layer and a sixth layer on the fourth layer; removing the fifth layer by a first process; and removing the etch stop layer by a second process.

Description

Cross-reference to related registration

[0001] The present application claims priority over the preliminary US patent application filed on August 18, 2024, under file number 63 / 684.400, which is incorporated by reference into the present application. background

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers onto a semiconductor substrate. These different material layers are then patterned by lithography to create circuit components and elements on the substrate. The semiconductor devices on a substrate are grouped into individual dies to achieve specific functions. In some cases, two or more substrates with different devices can be bonded together to create a complex substrate, with each individual die comprising two or more dies.For example, a substrate with logic devices can be bonded to a substrate with image sensors, so that the logic devices are connected to the image sensors and each individual die can contain a logic chip and an image sensor chip. The individual dies are separated by sawing integrated circuits along a scoring groove. Subsequently, the individual dies are individually encapsulated, for example, in multi-chip modules or other packaging types.

[0003] The semiconductor industry is continuously improving the integration density of various electronic components by constantly reducing the smallest feature size, allowing more components to be integrated into a given area. These smaller electronic components necessitate smaller and more sophisticated encapsulation systems than previous packages in some applications. As more metal layers are used in modern BEOL (Back End of Line) processing, SoC (System on a Chip) substrate deflection becomes increasingly pronounced, significantly degrading the SoIC (System on Integrated Chip) process window and resulting in low bond yields.

[0004] Therefore, an improved package structure is needed. Brief description of the drawings

[0005] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. The Fig. Figures 1A to 1F are schematic sectional views of a package structure during manufacturing according to some embodiments. The Fig. 2A, Fig. 2B, Fig. 3A, Fig. 3B, Fig. 4A and Fig. Figure 4B shows schematic side views of two device structures to be bonded according to some embodiments. The Fig. 5A and Fig. Figure 5B shows schematic side views of a rear surface structure according to some embodiments. The Fig. 6A and Fig. Figure 6B shows schematic side views of a device structure during manufacturing according to some embodiments. The Fig. Figures 7A to 7E are schematic side views of a package structure during manufacturing according to some embodiments. The Fig. Figures 8A to 8C schematically show a deflection modulation according to some embodiments. Detailed description

[0006] The disclosure below provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the description below may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0007] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of one element or structural element to one or more other elements or structural elements depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90° or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0008] Embodiments of the present disclosure relate to methods for processing and bonding substrates to fabricate IC chips (IC: integrated circuit). The substrates have semiconductor devices fabricated on the front faces of the substrates, and these can be referred to as device substrates. In particular, embodiments of the present disclosure provide a method for depositing a back-side structure to protect devices on the substrate and / or to adapt the substrate deflection during bonding and capping. In some embodiments, the back-side structure is deposited in a batch process chamber in which the layers of the back-side structure are fabricated on both the front and back faces of the substrate. The layers fabricated on the back face of the substrate can reduce void defects.

[0009] The Fig. Figures 1A to 1F are schematic sectional views of a package structure 100 during its manufacture according to some embodiments of the present disclosure. As in Fig. As shown in Figure 1A, a front-side layer 104F and a back-side layer 104B are deposited on a front-side layer 102F and a back-side layer 102B, respectively, of a wafer 102, and a front-side layer 106F and a back-side layer 106B, respectively, are deposited on the front-side layer 104F and the back-side layer 104B. In some embodiments, the wafer 102 is an uncoated wafer made of: an elemental semiconductor, such as crystalline silicon or crystalline germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminium indium arsenide (AlInAs), aluminium gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP); combinations thereof or any other suitable material.In some embodiments, the wafer 102 has multilayer semiconductors, semiconductors on insulators (SOI), for example silicon on insulator or germanium on insulator, and / or the like.

[0010] In some embodiments, the front-side layer 104F and the back-side layer 104B are produced simultaneously and have essentially the same properties, such as composition and thickness. For example, the front-side layer 104F and the back-side layer 104B are deposited simultaneously in a process chamber in which the front-side 102F and the back-side 102B of the wafer 102 are exposed to the processing environment. The front-side and back-side layers 104F, 104B can contain a suitable dielectric material, such as an oxide, e.g., SiO₂, SiO₂, SiNO, SiONC, or the like. In some embodiments, the front-side and back-side layers 104F, 104B can contain a semiconductor, such as SiGe, SiP, or the like. In some embodiments, if the wafer 102 is a silicon wafer, the front and back layers 104F, 104B are each made of or contain silicon oxide.In some embodiments, the front and back layers 104F, 104B can be deposited using a suitable method. In some embodiments, the front and back layers 104F, 104B are produced by introducing an oxidizing precursor into the process chamber. In some embodiments, one or more purification processes can be performed to remove inherent oxides and / or impurities from the wafer 102 before the front and back layers 104F, 104B are produced.

[0011] The front-side layer 104F is sometimes referred to as a pad layer intended for use in a subsequent structuring process. In some embodiments, the front-side layer 104F and the back-side layer 104B have the same or different thicknesses T1. In some embodiments, the thickness T1 is approximately 20 Å to approximately 2000 Å, e.g., approximately 20 Å to approximately 60 Å.

[0012] In some embodiments, the front-side layer 106F and the back-side layer 106B are produced simultaneously and have essentially the same properties, such as composition and thickness. For example, the front-side layer 106F and the back-side layer 106B are deposited simultaneously in a process chamber in which the dielectric front-side layer 104F and the dielectric back-side layer 104B are exposed to the processing environment. In some embodiments, the dielectric layers 104F, 104B, 106F, and 106B are deposited in the same process chamber.

[0013] The front and back layers 106F and 106B can contain a suitable dielectric material, such as a nitride, e.g., SiN, SiNO, Si3N4, SiNC, SiONC, or the like. In some embodiments, the front and back layers 106F and 106B can contain a semiconductor, such as SiGe, SiP, or the like. The front and back layers 106F and 106B contain a material different from that of the front and back layers 104F and 104B. In some embodiments, the front layer 106F and the back layer 106B are each made of or contain a nitride, such as silicon nitride. The front and back layers 106F and 106B can be deposited using a suitable method. In some embodiments, the front and back layers 106F, 106B are produced by introducing a nitrogen-containing precursor and a semiconductor-containing precursor into the process chamber.The front-side layer 106F and the back-side layer 106B have the same or different thicknesses T2. In some embodiments, the thickness T2 is approximately 100 Å to approximately 600 Å. The front-side layer 106F can function as a hard mask layer during the subsequent structuring process. In some embodiments, the thickness T2 of the front-side layer 106F is greater than the thickness T1 of the front-side layer 104F. In some embodiments, the ratio R1 of the thickness T1 of the front-side layer 104F to the thickness T2 of the front-side layer 106F is approximately 1:1 to approximately 1:18, e.g., approximately 1:9 to approximately 1:10.

[0014] While the front-side layer 104F and the front-side layer 106F are produced to enable subsequent FEOL processes, the back-side layer 104B and the back-side layer 106B remain on the back side 102B of the wafer 102 during wafer processing and can protect the wafer 102. However, during certain processes, such as a bonding process and a wet cleaning process, the back-side layers 104B and 106B, which are produced simultaneously with the front-side layer 104F and the front-side layer 106F respectively, do not provide sufficient protection for the wafer 102, resulting in cracks and void defects in the wafer 102. Embodiments of the present disclosure provide an improved back-side structure to prevent damage to the wafer 102 during wafer processing.

[0015] As in Fig. As shown in Figure 1B, an etch stop layer 108 is deposited on the front-side layer 106F. The etch stop layer 108 can be made of (or contain) a suitable material having an etch selectivity different from that of the front-side layer 106F. In some embodiments, the etch stop layer 108 contains the same material as the front-side layer 104F. The etch stop layer 108 can have a thickness T3. In some embodiments, the thickness T3 is approximately 50 Å to approximately 1000 Å.

[0016] In some embodiments, the etch stop layer 108 is produced in a process chamber in which the back side of the package structure 100 is not exposed to the processing environment. As a result, no material is formed on the back side layer 106B during the production of the etch stop layer 108. The etch stop layer 108 can be produced using a suitable method, such as atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD).

[0017] As in Fig. As shown in Figure 1C, a front layer 110F and a back layer 110B are produced on the etch stop layer 108 and the back layer 106B, respectively. Similar to the front and back layers 104F, 104B and the front and back layers 106F, 106B, the front layer 110F and the back layer 110B are produced simultaneously and can have essentially the same properties, such as composition and thickness. The front layer 110F and the back layer 110B are produced simultaneously in a process chamber in which the etch stop layer 108 and the back layer 106B are exposed to the processing environment.

[0018] The backside layer 110B has a thickness T4. In some embodiments, the thickness T4 is approximately 100 Å to approximately 1600 Å. In some embodiments, the backside layer 110B contains the same material as the backside layer 106B, and the backside layer 110B and the dielectric backside layer 106B have a combined thickness T5. In some embodiments, the thickness T5 is approximately 200 Å to approximately 20,000 Å. The backside layers 106B and 110B with a thickness of T5 can improve void defects during the bonding process. Furthermore, in the embodiment where the backside layers 106B and 110B are made of silicon nitride, greater mechanical stresses are introduced, and the deflection of the package structure 100 is affected. In some embodiments, the ratio R2 of the thickness T1 of the back side layer 104B to the combined thickness T5 of the back side layers 106B, 110B is approximately 1 : 20 to approximately 1 : 60.The smaller ratio R2 compared to the ratio R1 (i.e., the greater thickness T5 compared to the thickness T2) can lead to improved cavity defects and a stress and deflection matching of the package structure 100.

[0019] As in Fig. As shown in Figure 1C, the backside layer 110B, the backside layer 106B, and the backside layer 104B form a backside structure 112. The backside structure 112 can remain on the wafer 102 during wafer processing to protect the backside 102B of the wafer 102. In some embodiments, the backside structure 112 can also function as a stress modulation or deflection adaptation structure to achieve a specific deflection in the package structure 100.

[0020] As in Fig. As shown in Figure 1D, the front layer 110F is removed, while the back layer 110B remains. In some embodiments, the package structure 100 is placed in a process chamber where the back layer 110B is not exposed to the processing environment. The process chamber can be a dry etching chamber, such as a plasma etching chamber. In some embodiments, the front layer 110F is removed using a plasma etching process with a plasma source and an etchant. The plasma source can be an ICP source (ICP: inductively coupled plasma), a TCP source (TCP: transformer-coupled plasma), an ECR source (ECR: electron cyclotron resonance), a CCP source (CCP: capacitively coupled plasma), or the like.In some embodiments, the etchant may contain tetrafluoromethane (CF4), difluoromethylene (CH2F2), or hexafluoroethane (C2F6), with the optional addition of oxygen and / or nitrogen to control the etching rate and selectivity. In some embodiments, the etchant exhibits high etch selectivity of the front-side layer 110F over the etch-stop layer 108. The etch-stop layer 108 allows the front-side layer 110F to be removed without damaging the front-side layer 106F.

[0021] As in Fig. As shown in Figure 1E, the etch stop layer 108 is removed. The etch stop layer 108 can be removed by a process that does not significantly affect the front-side layer 106F. In some embodiments, a wet etching process is performed to remove the etch stop layer 108, while the front-side layer 106F is not significantly affected by the wet etching process. In some embodiments, the wet etching process includes immersion in dilute HF acid.

[0022] In some embodiments, the package structure 100 comprises: the wafer 102; the front-side layers 104F and 106F, which are arranged on the front side 102F of the wafer 102; and the back-side layers 104B, 106B, and 110B, which are arranged on the back side 102B of the wafer 102. In some embodiments, the front-side layer 104F and the back-side layer 104B each contain silicon oxide, and the front-side layer 106F and the back-side layers 106B and 110B each contain silicon nitride. The front-side layers 104F and 106F can function as a mask structure during a structuring process. The backside layer 104B can function as a transition layer because the material of the backside layer 104B and the material of the wafer 102 have a better lattice match than the material of the backside layer 106B and the material of the wafer 102.The backside layers 106B and 110B can function as a protective layer to safeguard the wafer 102. Due to the properties of the backside layers 106B and 110B and their combined thickness T5, they help prevent cracks or void defects in the backside 102B of the wafer 102. If the backside layers 106B and 110B are applied directly to the backside 102B of the wafer 102 without the backside layer 104B, they can easily detach from the backside 102B of the wafer 102.

[0023] After removal of the etch stop layer 108, FEOL processes are performed on the wafer 102 to fabricate a plurality of devices (not shown), and BEOL processes (BEOL: Back End of Line) can be performed to fabricate an interconnect structure 120 over the wafer 102, as shown in Fig. Figure 1F is shown. In some embodiments, the plurality of devices comprises a plurality of ASIC devices (ASIC: application-specific integrated circuit). In some embodiments, the plurality of devices forms a logic circuit, a memory circuit, a sensor circuit, or the like. In some embodiments, the plurality of devices forms a control circuit for a sensor circuit. In some embodiments, the plurality of devices comprises transistors, capacitors, diodes, resistors, or the like. In some embodiments, the devices are transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS transistors), bipolar transistors (BJTs), high-voltage transistors, high-frequency transistors, PFETs / NFETs, or other suitable transistors.The transistors can be planar field-effect transistors (FETs), FinFETs, nanostructured transistors, or other suitable transistors. The nanostructured transistors can include nanosheet transistors, nanowire transistors, gate-all-around transistors (GAA transistors), multi-bridge-channel transistors (MBC transistors), or transistors whose gate electrode surrounds the channels.

[0024] The interconnect structure 120 can be fabricated using BEOL manufacturing processes. BEOL encompasses the fabrication and structuring of dielectric layers and conductive metal layers. The interconnect structure 120 contains a plurality of conductive structural elements 118, such as conductive traces and conductive vias, embedded in a dielectric structure 116.

[0025] As in Fig. As shown in Figure 1F, the package structure 100 further comprises a structure 150 bonded to the interconnect structure 120. In some embodiments, the structure 150 includes CIS devices (CIS: CMOS image sensor). In some embodiments, the CIS devices are back-illuminated CIS devices (BSI-CIS devices). For example, in some embodiments, the structure 150 includes an interconnect structure 151 and a wafer 158 mounted on the interconnect structure 151. The interconnect structure 151 includes dielectric layers 152 and conductive structural elements 154 embedded in the dielectric layers 152. In some embodiments, a top surface of the interconnect structure 120 is configured for bonding to a top surface of the interconnect structure 151 of the structure 150. A microlens arrangement 156 can be fabricated on wafer 158.Thus, in some embodiments, wafer 102 is a logic circuit wafer with logic circuits, and structure 150 is a sensor wafer with integrated BSI sensor circuits. The logic circuit wafer and the sensor wafer are bonded together to fabricate three-dimensional integrated circuits (3D ICs).

[0026] The logic circuit wafer and the sensor wafer are bonded together using a suitable process such as direct bonding, hybrid bonding, or the like. Pressure can be applied to the package structure 100 during the bonding process. The backside structure 112 protects the backside 102B of wafer 102 during the bonding process. Furthermore, the backside structure 112 protects wafer 102 from damage caused by the process chemicals during a wet etching process.

[0027] The Fig. Figures 2A to 4B are schematic side views of two device structures 200 and 202 that are to be bonded together according to some embodiments. As in Fig. As shown in Figure 2A, the fixture structure 200 and the fixture structure 202 are bonded together. In some embodiments, the fixture structures 200 and 202 are wafers on which fixtures and interconnect structures are fabricated. For example, the fixture structure 200 can bond the wafer 102, the plurality of fixtures, and the interconnect structure 120. Fig. 1F, and the device structure 202 can include the interconnect structure 151, the wafer 158, and the microlens arrangement 156. Fig. 1F. In some embodiments, the device structure 200 is a die, and the device structure 202 is also a die. As in Fig. As shown in Figure 2A, the device structure 200 has a bonding surface 204 which is to be bonded to a bonding surface 206 of the device structure 202. The bonding surface 204 can be a top surface of the uppermost layer of the device structure 200. For example, the bonding surface 204 can be a top surface of the interconnect structure 120 ( Fig. 1F). The bonding surface 206 can be a top surface of the uppermost layer of the device structure 202. For example, the bonding surface 206 can be a top surface of the interconnect structure 151 ( Fig. 1F). In some embodiments, the cross-sectional profile of bonding surface 204 and the cross-sectional profile of bonding surface 206 do not match. As in Fig. As shown in Figure 2A, for example, the bonding surface 204 is essentially flat, and the bonding surface 206 is curved and has, for example, a concave cross-sectional profile.

[0028] In some embodiments, to change the cross-sectional profile of the bonding surface 204, a backside structure 210 is produced on a backside surface 208 of the device structure 200, as shown in Fig. Figure 2B shows that the backside structure 210 comprises at least one protective layer 212 and at least one buffer layer 214. In some embodiments, the protective layer 212 contains the same material as the backside layer 104B, and the buffer layer 214 contains the same material as the backside layer 106B. In some embodiments, two or more of the protective layers 212 and two or more of the buffer layers 214 are stacked alternately on top of each other, as shown in Figure 2B. Fig. Figure 2B is shown. As explained above, the material of the protective layer 212 and the material of the wafer 102 have a better lattice fit compared to the material of the buffer layer 214 and the material of the wafer 102. Furthermore, the protective layer 212 tends to cause concave deflection, and the buffer layer 214 tends to cause convex deflection. Thus, in some embodiments, the thickness of the buffer layer 214 is significantly greater than the thickness of the protective layer 212 in order to cause concave deflection. As shown in Fig. As shown in Figure 2B, after the rear surface structure 210 is fabricated on the rear surface 208 of the fixture structure 200, the fixture structure 200 has a convex deflection, and the bonding surface 204 has a convex cross-sectional profile. The convex cross-sectional profile of the bonding surface 204 matches the concave cross-sectional profile of the bonding surface 206. This improves the bonding process for bonding the fixture structure 200 to the fixture structure 200.

[0029] In some embodiments, which are in Fig. As shown in Figure 3A, the device structure 200 has the bonding surface 204, which is curved and has, for example, a concave cross-sectional profile, and the device structure 202 has the bonding surface 206, which is curved and has, for example, a convex cross-sectional profile. In some embodiments, the cross-sectional profile of the bonding surface 204 is modified by producing the backside structure 210 on the backside surface 208 of the device structure 200, as shown in Figure 3A. Fig. Figure 3B is shown. As explained above, the backside structure 210 has alternating protective layers 212 and buffer layers 214. In some embodiments, the thickness of the protective layer 212 is greater than the thickness of the buffer layer 214, since the protective layer 212 tends to cause a concave deflection. Thus, with the backside structure 210 having thicker protective layers 212, the cross-sectional profile of the bonding surface 204 is changed from convex to concave, as shown in Figure 3B. Fig. Figure 3B shows that the concave profile of bonding surface 204 matches the convex profile of bonding surface 206. Fig. 3B is shown.

[0030] In some embodiments, which are in Fig. As shown in Figure 4A, the device structure 200 has a bonding surface 204 that is curved and has, for example, a concave cross-sectional profile, and the device structure 202 has a bonding surface 206 that is curved and has, for example, a convex cross-sectional profile. In some embodiments, the cross-sectional profiles of the bonding surface 204 and the bonding surface 206 are modified by producing the backside structure 210 on the backside surface 208 of the device structure 200 and on a backside surface 216 of the device structure 202, as shown in Figure 4A. Fig. Figure 4B is shown. As explained above, the backside structure 210 has alternating protective layers 212 and buffer layers 214. In some embodiments, the thickness of the protective layer 212 is greater than the thickness of the buffer layer 214, since the protective layer 212 tends to cause a concave deflection. Thus, with the backside structure 210 having thicker protective layers 212, the cross-sectional profile of the bonding surface 204 is changed from convex to concave, as shown in Figure 4B. Fig. Figure 4B shows that in some embodiments, the convex bonding surface 206 of the device structure 202 does not match the concave bonding surface 204 of the device structure 200. Therefore, the backside structure 210 is fabricated on the backside surface 216 of the device structure 200 to modify the degree of convexity of the bonding surface 206 of the device structure 200. In some embodiments, the bonding surface 206 becomes more convex with the addition of the backside structure 210, and the backside structure 210 has protective layers 212 that are thicker than the buffer layer 214. In other embodiments, the bonding surface 206 becomes less convex with the addition of the backside structure 210, and the backside structure 210 has buffer layers 214 that are thicker than the protective layer 212.By changing the cross-sectional profile of the bonding surface 204 from convex to concave and by changing the cross-sectional profile of the bonding surface 206 from convex to more or less convex, the fit between the bonding surfaces 204 and 206 is improved.

[0031] Due to the reverse side structure 210, which is in the Fig. 2B, Fig. 3B and Fig. As shown in 4B, the deflection of the device structure 200 (and the device structure 202) is shown in Fig. 4B) modified to change the cross-sectional profile of bonding surface 204 (and bonding surface 206 in Fig. 4B) to modify so that the bonding surfaces 204 and 206 align. Furthermore, the backside structure 210 protects the backside surface 208 of the fixture structure 200 (and the backside surface 216 of the fixture structure 202) during the bonding process, similar to how the backside structure 112 protects the wafer 102, as described in reference to Fig. 1F has been explained.

[0032] Device structures 200 and 202 can be any suitable structures. In some embodiments, device structure 200 is a logic wafer, device structure 202 is another logic wafer, and the bonding of device structure 200 and device structure 202 is a wafer-wafer bond. In some embodiments, device structure 200 is a die, device structure 202 is another die, and the bonding of device structure 200 and device structure 202 is a die-die bond. In some embodiments, device structure 200 is a wafer, device structure 202 is a die, and the bonding of device structure 200 and device structure 202 is a die-wafer bond.By bonding the device structures 200 and 202, further types of packages can be created, such as a chip-on-wafer-on-substrate package (CoWoS package), a system-on-integrated-chip package (SoIC package), or the like.

[0033] The Fig. 5A and Fig. Figure 5B shows schematic side views of the backside structure 210 according to some embodiments. In some embodiments, the backside structure 210 has alternating protective layers 212 and buffer layers 214, as shown in Fig. Figure 5A shows the following. The number of protective layers 212 can be from 1 to 50, and the number of buffer layers 214 can also be from 1 to 50. In some embodiments, the thickness of the protective layers 212 is essentially constant, and the thickness of the buffer layers 214 is also essentially constant. In some embodiments, the thickness of the protective layers 212 is essentially equal to the thickness of the buffer layers 214. In some embodiments, the thickness of the protective layers 212 is significantly different from the thickness of the buffer layers 214. As explained above, the thickness of the protective layers 212 is greater than the thickness of the buffer layers 214 to produce a concave deflection. In some embodiments, the thickness of the buffer layers 214 is greater than the thickness of the protective layers 212 to produce a convex deflection.

[0034] In some embodiments, the thickness of the buffer layers 214 is not constant, as shown in Fig. Figure 5B shows that, for example, the backside structure 210 has protective layers 212 and buffer layers 214a to 214c. Buffer layer 214a is the one closest to the backside of a wafer (or die) on which the backside structure 210 is fabricated, and buffer layer 214c is the one furthest from the backside of the wafer (or die). In some embodiments, the thickness of buffer layers 214a to 214c increases in one direction away from the wafer. For example, buffer layer 214a has a first thickness, buffer layer 214b has a second thickness greater than the first thickness, and buffer layer 214c has a third thickness greater than the second thickness. As explained above, due to the lattice mismatch between the buffer layer 214 and the wafer, the protective layer 212 is produced between the buffer layer 214 and the wafer.In some embodiments, the thickness of the buffer layer 214 is increased to cause convex deflection of the wafer. If the thickness of the buffer layer 214 exceeds a threshold value, the buffer layer 214 can easily detach. Therefore, to achieve a thicker buffer layer 214, additional protective layers 212 are produced in the backside structure 210 to subdivide the thick buffer layer 214 into smaller layers. As the buffer layer 214 moves further away from the wafer, the risk of detachment decreases. Thus, the buffer layer 214 can have a greater thickness as it moves further away from the wafer. Fig. Although Figure 5B shows three protective layers 212 and three buffer layers 214a to 214c, other numbers of protective layers 212 and buffer layers 214a to 214c can also be used. In some embodiments, the back-side structure 210 has alternating protective layers 212 and buffer layers 214, and the thickness of the buffer layers 214 increases in one direction away from a wafer (or die) on which the back-side structure 210 is fabricated. The thickness of the buffer layers 214 can remain essentially constant.

[0035] In some embodiments, the thickness of the protective layers 212 increases in a direction away from the wafer, while the thickness of the buffer layers 214 remains constant. In some embodiments, the buffer layers 214 provide protection for the wafer, and the protective layers 212 are softer than the buffer layers 214 and can provide cushioning when the wafer is held by a substrate holder.

[0036] The Fig. 6A and Fig. Figure 6B shows schematic side views of the device structure 200 during manufacturing according to some embodiments. In some embodiments, which are described in Fig. As shown in Figure 6A, the device structure 200 is placed in a process chamber in which the front and back of the device structure 200 are exposed to the machining environment. Then, the back structure 210 is fabricated on the back of the device structure 200, and a front structure 250 is fabricated on the front of the device structure 200. In some embodiments, the front structure 250 and the back structure 210 are fabricated simultaneously. The layers of the back structure 210 are fabricated sequentially, and the layers of the front structure 250 are fabricated sequentially and simultaneously with corresponding layers of the back structure 210.If the front structure 250 and the back structure 210 are manufactured simultaneously on the fixture structure 200, the deflection of the fixture structure 200 is not affected, since the front structure 250 and the back structure 210 are manufactured on the front and back of the fixture structure 200, respectively.

[0037] As in Fig. As shown in Figure 6B, the front-side structure 250 is then removed. The fixture structure 200, comprising the front-side structure 250 and the back-side structure 210, can be placed in an etching chamber where the back-side structure 210 is not exposed to the machining environment. The layers of the front-side structure 250 can be removed using one or more etching processes. The etching processes can be dry etching, wet etching, or a combination thereof. After the removal of the front-side structure 250, the deflection of the fixture structure 200 (or its absence) is adjusted to accommodate the deflection of another fixture structure, such as the fixture structure 202, which is to be bonded to the fixture structure 200.

[0038] In some embodiments, the device structure 200 is an uncoated wafer or an uncoated support wafer. After the components have been fabricated or bonded onto the uncoated wafer, the deflection of the uncoated wafer can be adjusted using the backside structure 210 to match the deflection of a device that is to be bonded to the components on the uncoated wafer.

[0039] In some embodiments, the back-side structure 210 is manufactured in a process chamber in which the back of the fixture structure 200 is exposed to the machining environment, while the front of the fixture structure 200 is not exposed to the machining environment. In this case, the back-side structure 210 is manufactured on the back of the fixture structure 200, but the front-side structure 250 is not manufactured on the front of the fixture structure 200.

[0040] The Fig. Figures 7A to 7E are schematic side views of the package structure 100 during manufacturing according to some embodiments. In some embodiments, which are described in Fig. As shown in Figure 7A, the package structure 100 is a CoWoS package. The package structure 100 has a carrier 302, on which an adhesive layer 304 is arranged, and a plurality of dies 308 are arranged above the adhesive layer 304. The dies 308 can be any suitable dies, such as integrated circuit dies. The dies 308 can be separated by a dielectric material 306. The dielectric material 306 can be any suitable dielectric material. In some embodiments, the dielectric material 306 is a molding material that encapsulates the dies 308. An interconnect structure 310 is arranged above the dies 308. The interconnect structure 310 has conductive structural elements 312 that are made in one or more dielectric layers. The interconnect structure 310 is bonded to an interconnect structure 314.The interconnect structure 314 can have conductive structural elements that are electrically connected to the conductive structural elements 312 of the interconnect structure 310. The interconnect structures 310 and 314 can be bonded using a suitable process, such as direct bonding or hybrid bonding. An interposer substrate 320 is arranged above the interconnect structure 314, and a plurality of vias 318 are produced in the interposer substrate 320. In some embodiments, the vias 318 are substrate vias. The interposer substrate 320 and the interconnect structure 314 can be fabricated separately from the dies 308 and the interconnect structure 310, respectively. Likewise, the dies 308 and the interconnect structures 310 can be manufactured over the carrier 302 before being bonded to the interconnect structure 314 and the interposer substrate 320.

[0041] As in Fig. As shown in Figure 7B, the interposer substrate 320 is thinned to expose the vias 318. The interposer substrate 320 can be thinned by grinding, lapping, etching, polishing, or any other suitable process, or combinations thereof. As shown in Fig. As shown in Figure 7C, the backside structure 210 is then fabricated on the interposer substrate 320. The backside structure 210 can have alternating protective layers 212 and buffer layers 214, as shown in Figure 7C. Fig. Figure 7C shows that in some embodiments, the interposer substrate 320 is a silicon substrate, and the protective layer 212 is produced on the interposer substrate 320 for better lattice matching. As explained above, the thicknesses of the buffer layers 214 can differ and, for example, increase in one direction away from the interposer substrate 320. In some embodiments, the thicknesses of the buffer layers 214 are greater than the thicknesses of the protective layers 212 to cause a convex deflection of the interposer substrate 320. In other embodiments, the thicknesses of the protective layers 212 are greater than the thicknesses of the buffer layers 214 to cause a concave deflection of the interposer substrate 320.

[0042] In some embodiments, which are in Fig. As shown in Figure 7D, the backside structure 210 is removed, while the interposer substrate 320 retains the deflection caused by the presence of the backside structure 210. In other words, if the backside structure 210 caused a deflection in the interposer substrate 320, removing the backside structure 210 does not affect the deflection. A dielectric material 322 is deposited over the interposer substrate 320, and electrical interconnects 324 are fabricated in the dielectric material 322. The dielectric material 322 can be any suitable dielectric material. In some embodiments, the dielectric material 322 contains a polymer, such as a polyimide. The electrical interconnects 324 are electrically connected vias 318.The electrical interconnects 324 can be solder balls, metal columns, C4 contact bumps (C4: Controlled Collapse Chip Interconnect), microbumps, contact bumps produced by the ENEPIG process (ENEPIG: Electroless Nickel Electroless Palladium Immersion Gold), or the like. The electrical interconnects 324 can be manufactured by commonly used processes such as vapor deposition, electroplating, printing, solder transfer, ball placement, or the like.

[0043] In some embodiments, the backside structure 210 is not removed, and the electrical interconnects 324 are manufactured within the backside structure 210. The electrical interconnects 324 extend, for example, through the protective layers 212 and the buffer layers 214 of the backside structure 210 to be electrically connected to the vias 318.

[0044] As in Fig. As shown in Figure 7E, the package structure 100 is turned over and attached to a printed circuit board (PCB) 330, and the carrier 302 is removed. The carrier 302 can be removed using a suitable method. In some embodiments, the carrier 302 is removed using a peel-off layer (not shown). In some embodiments, the adhesive layer 304 remains over the dies 308, as shown in Figure 7E. Fig. Figure 7E shows that the electrical connecting elements 324 are electrically connected to the PCB 330. In some embodiments, the interposer substrate 320 has a concave deflection due to the presence of the back surface structure 210 produced on it. The concave deflection of the interposer substrate 320 improves the contacts between the electrical connecting elements 324 and the PCB 330.

[0045] The Fig. Figures 8A to 8C schematically show a deflection modulation according to some embodiments. As in Fig. As shown in Figure 8A, first dies 402 are to be bonded to a second die 410. In some embodiments, each of the first dies 402 has circuit layers 404 that are electrically insulated by an insulating layer 406. In some embodiments, the circuit layers 404 contain a plurality of devices, such as the plurality of devices referred to in Fig. 1F have been described. The insulating layer 406 can contain a suitable dielectric material. A plurality of electrical connecting elements 408 are arranged above the circuit layers 404, as described in Fig. Figure 1F shows that an interconnect structure 409 can be arranged beneath the circuit layers 404 and the insulation layer 406. The interconnect structure 409 is placed on a carrier 411, and the backside structure 210 is fabricated on the back side of the carrier 411, as shown in Figure 1F. Fig. Figure 8A shows that the back-side structure 210 can create a deflection in the support 411 and the materials located thereon. In some embodiments, a concave deflection is created, which allows the electrical connecting elements 408 to be better connected to the second die 410.

[0046] As in Fig. As shown in Figure 8A, the second die 410 has circuit layers 412, which are electrically insulated by an insulating layer 414. An interposer substrate 416 is arranged below the circuit layers 412 and the insulating layer 414, and a plurality of vias 418 are made in the interposer substrate 416. The vias 418 can be electrically connected to corresponding circuit layers 412. The first dies 402 and the second die 410 are bonded such that the electrical connecting elements 408 are electrically connected to corresponding vias 418.

[0047] As in Fig. As shown in Figure 8B, instead of using the electrical connecting elements 408, the first dies 402 are bonded to the second dies 410 using dielectric layers 452 and 456, which contain conductive structural elements 450 and 454, respectively. In some embodiments, the dielectric layer 452 is produced on each first die 402, and the conductive structural elements 450 are produced within the dielectric layer 452. The backside structure 210 can provide the dielectric layer 452 with a domed top surface, allowing the top surface of the dielectric layer 452 to better fit a bottom surface of the dielectric layer 456. The dielectric layer 456 and the conductive structural elements 454 are arranged beneath the interposer substrate 416. In some embodiments, each via 418 is electrically connected to a corresponding conductive structural element 454, as shown in Figure 8B. Fig. 8B is shown. The backside structure 210 can be used in a similar manner to the backside structure 210 shown with reference to the Fig. 2B and Fig. 3B has been described.

[0048] In some embodiments, the cross-sectional profile of the underside of the dielectric layer 456 can be modified by means of the backside structure 210, as shown in Fig. Figure 8C shows that in some embodiments a support 460 is fabricated over the circuit layers 412 and the insulating layer 414, and the backside structure 210 is fabricated on the support 460. The backside structure 210 can modify the cross-sectional profile of the underside of the dielectric layer 456 so that the underside of the dielectric layer 456 can better match the top side of the dielectric layer 452 of the first die 402 ( Fig. 8B). After the first dies 402 have been bonded to the second die 410, the backside structure 210 and the support 460 can be removed. The backside structures 210 can be used in a similar manner to the backside structures 210 described with reference to 4B.

[0049] The in the Fig. The package shown in Figures 8A to 8C can be a SoIC package. The backside structure 210 creates a deflection in one or more dies (or it modifies the cross-sectional profile of the top and / or bottom surfaces to be bonded) to improve the bonding process and the bonding of the dies. The backside structure 210 can also be used in other types of packages.

[0050] In the present disclosure, a method for manufacturing a package structure 100 is provided in various embodiments. In some embodiments, the method includes manufacturing a back-side structure 210 on the back side of a device structure 200. The back-side structure 210 has alternating protective layers 212 and buffer layers 214. Some embodiments can achieve advantages. For example, the protective layers 212 tend to cause a concave deflection in the device structure 200, and the buffer layers 214 tend to cause a convex deflection in the device structure 200. By adapting the device structure 200, the bonding of the device structure 200 to another device structure is improved.

[0051] One embodiment relates to a method. The method comprises the following: depositing a first layer on a front side of a wafer and a second layer on a back side of the wafer; depositing a third layer on the first layer and a fourth layer on the second layer; depositing an etch stop layer on the third layer; depositing a fifth layer on the etch stop layer and a sixth layer on the fourth layer; removing the fifth layer by a first process; and removing the etch stop layer by a second process.

[0052] Another embodiment also relates to a method. The method comprises providing a first device structure, wherein the first device structure has a first surface and a second surface opposite the first surface, the second surface having a first cross-sectional profile. The method further comprises depositing a first structure onto the first surface, wherein the first structure causes the second surface to have a second cross-sectional profile that differs from the first cross-sectional profile. The method further comprises bonding the first device structure to a second device structure.

[0053] Another embodiment also relates to a method. The method comprises the following: bonding an interposer substrate to one or more dies; removing a portion of the interposer substrate to expose one or more vias; and depositing a structure on the interposer substrate and the vias. The deposition of the structure comprises the following: depositing a first protective layer on the interposer substrate and the vias; depositing a first buffer layer on the first protective layer; depositing a second protective layer on the first buffer layer; and depositing a second buffer layer on the second protective layer. The method further comprises the following: removing the structure; depositing a dielectric material on the interposer substrate and the vias; and creating one or more electrical interconnects in the dielectric material.

[0054] Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present disclosure. It should be clear to those skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other methods and structures to achieve the same objectives and / or to obtain the same advantages as in the embodiments presented here. Those skilled in the art should also recognize that such equivalent interpretations do not deviate from the fundamental concept and scope of protection of the present disclosure and that they can make various changes, substitutions, and modifications without deviating from the fundamental concept and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 684.400

[0001]

Claims

[1] Procedure, encompassing: Deposition of a first layer on a front side of a wafer and a second layer on a back side of the wafer; Depositing a third layer on the first layer and a fourth layer on the second layer; Deposition of an etch stop layer on the third layer; Deposition of a fifth layer on the etch stop layer and a sixth layer on the fourth layer; Removal of the fifth layer using a first process; and Removing the etch stop layer with a second process. [2] Method according to claim 1, wherein the first and second layers each contain an oxide, and The third and fourth layers each contain a nitride. [3] Method according to any of the preceding claims, wherein the sixth layer contains the same material as the fourth layer. [4] Method according to any one of the preceding claims, wherein the first layer has a first thickness, the second layer has a second thickness the third layer has a third thickness, and The fourth and sixth layers together have a fourth thickness. [5] Method according to claim 4, wherein the fourth thickness is greater than the second thickness. [6] Method according to claim 4 or 5, wherein a first ratio of the first thickness to the third thickness is smaller than a second ratio of the second thickness to the fourth thickness. [7] Method according to claim 6, wherein the first ratio is 1 : 1 to 1 : 18, and the second ratio is 1 : 20 to 1 :

60. [8] Method according to any of the preceding claims, wherein the first process is a dry etching process. [9] Method according to claim 8, wherein the second process is a wet etching process. [10] Procedures, including: Providing a first device structure, wherein the first device structure has a first surface and a second surface opposite the first surface, the second surface having a first cross-sectional profile; Deposition of a first structure on the first surface, wherein the first structure causes the second surface to have a second cross-sectional profile that is different from the first cross-sectional profile; and Bonding the first device structure to a second device structure. [11] Method according to claim 10, wherein the first structure has alternating protective layers and buffer layers. [12] Method according to claim 11, wherein the protective layers include oxide layers, and The buffer layers include nitride layers. [13] Method according to claim 11 or 12, wherein the thickness of the buffer layers increases in a direction away from the first surface. [14] Method according to claim 11, 12 or 13, wherein the thickness of the buffer layers is greater than the thickness of the protective layers, the first cross-sectional profile is flat, and the second cross-sectional profile is convex. [15] Method according to any one of claims 11 to 14, wherein the thickness of the buffer layers is less than the thickness of the protective layers, the first cross-sectional profile is convex, and the second cross-sectional profile is concave. [16] Method according to any one of claims 10 to 15, further comprising depositing a second structure on a surface of the second device structure opposite a bonding surface of the second device structure, wherein a cross-sectional profile of the bonding surface is modified by the second structure. [17] Procedures, including: Bonding of an interposer substrate to one or more dies; Removing part of the interposer substrate to expose one or more vias; Deposition of a structure on the interposer substrate and the vias using the following steps: Deposition of a first protective layer on the interposer substrate and the vias, Deposition of a first buffer layer on the first protective layer, Deposition of a second protective layer on the first buffer layer, and Deposition of a second buffer layer on the second protective layer; Removal of the structure; Deposition of a dielectric material on the interposer substrate and the vias; and Manufacturing one or more electrical connecting elements in the dielectric material. [18] Method according to claim 17, wherein the thickness of the first buffer layer is greater than the thickness of the first protective layer. [19] Method according to claim 17 or 18, wherein the thickness of the second buffer layer is greater than the thickness of the first buffer layer. [20] Method according to any one of claims 17 to 19, wherein the thickness of the first protective layer is equal to the thickness of the second protective layer.

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