Storage devices with a reduced number of front-facing power supply conductors and methods for their manufacture

Abstract

A storage device comprises memory cells fabricated on a first side of a substrate and powered by a supply voltage; a third metallization layer fabricated on the first side and comprising third metal conductors, wherein at least one of the third metal conductors is configured to carry only a non-power supply signal instead of the supply voltage; a fourth metallization layer fabricated on the first side and comprising fourth metal conductors, each of which is configured as only one word line; a fifth metallization layer fabricated on a second side of the substrate and comprising fifth metal conductors, each configured to carry the supply voltage or a ground voltage;and a sixth metallization layer, which is produced on the second side and has sixth metal conductor tracks, each configured to carry the supply voltage or the ground voltage.

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] This application claims priority over preliminary US patent application No. 63 / 690,012, filed on September 3, 2024, which is incorporated by reference into the present application in its entirety for all purposes. BACKGROUND

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density is largely attributable to repeated reductions in the smallest feature size, allowing more components to be integrated into a given area. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not shown to scale. In fact, the dimensions of the various elements may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows an exemplary block diagram of a storage device according to some embodiments. Fig. Figure 2 shows an exemplary circuit diagram of a memory cell of the storage device of Fig. 1 according to some embodiments. Fig. 3A and Fig. 3B jointly demonstrate an exemplary layout for manufacturing the storage device of Fig. 1 is set up according to some embodiments. Fig. 4A and Fig. 4B jointly demonstrate another exemplary layout used to manufacture the storage device of Fig. 1 is set up according to some embodiments. Fig. 5A and Fig. 5B together show another exemplary layout for manufacturing the storage device of Fig. 1 is set up according to some embodiments. Fig. Figure 6 shows an example layout of the memory cell of Fig. 2 according to some embodiments. Fig. Figure 7 shows a flowchart of an exemplary procedure for manufacturing the storage device of Fig. 1 according to some embodiments. DETAILED DESCRIPTION

[0004] The disclosure below provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the description below may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0006] Static random access memory (SRAM) is a type of volatile semiconductor storage device comprising multiple SRAM cells, each configured to store data bits using bistable circuitry without refreshing. An SRAM cell, typically referred to as a bit cell, stores one bit of information represented by the logic state of two cross-coupled inverters. Multiple bit cells are generally arranged as a memory matrix with rows and columns. Each bit cell in a memory matrix typically includes connections to a supply voltage and a reference voltage (e.g., ground). Logic signals on bit lines control reading from and writing to a bit cell, with a word line controlling connections of the bit lines to the inverters, which are otherwise floating.A word line can be connected to the bit cells in a row of a memory matrix, with different word lines being provided for different rows. A pair of bit lines can be connected to each column of bit cells.

[0007] For a read operation on a bit cell, the corresponding bit lines can be preloaded to a logical state H (e.g., a logic value '1'), and the corresponding word line can be addressed. The resulting values ​​on the bit lines can correspond to the logic value of the information bit stored on the bit cell. To write a '1' to a bit cell, one of the corresponding bit lines, which can be called BL (which can stand for "bit line"), can be set to '1', and the other bit line, which can be called BLB (which can stand for "bit line rail"), can be set to '0', and the word line can be addressed. To write a logic value L, BL and BLB can instead be set to '0' and '1', respectively, and the word line can be addressed. The pair of bit lines BL, BLB can be called a pair of complementary bit lines.It is understood, however, that the values ​​on BL and BLB do not necessarily have to be logically complementary to each other, as in the read operation described above, where both BL and BLB are set to '1'.

[0008] To improve memory access performance (e.g., write operations), dual-rail power supply methods have been proposed. In a dual-rail approach, a first supply voltage (e.g., VDD) is provided to power peripheral circuitry configured to control the bit cells, while a second supply voltage (e.g., VDDM) can be provided to power the bit cells themselves. Existing memory devices are limited in that both of these supply voltages (VDD and VDDM) must be routed through metal traces on the front face of a substrate.For example, a number of first metal traces fabricated in a first front-side metallization layer are configured to carry the first supply voltage (VDD), and a number of second metal traces fabricated in a second front-side metallization layer are configured to carry the second supply voltage (VDDM). Such a limitation adversely affects the flexibility of the front-side metal tracing while following the scaling trend of a larger number of bit cells over a given area. Consequently, it is understood that existing storage devices have not been entirely satisfactory in certain aspects.

[0009] The present disclosure provides various embodiments of a storage device with a reduced number of front-facing metal conductors, configured to carry a supply voltage or a ground voltage. In various embodiments, the storage device disclosed herein comprises a storage matrix and a peripheral circuit that are operationally interconnected. The storage matrix includes a plurality of memory cells. The peripheral circuit is configured to operate or control the storage matrix and may include various circuit components such as a driver circuit, an input / output circuit, etc. Each of the memory cells can be operationally formed by a plurality of first transistors, and the peripheral circuit can be operationally formed by a plurality of second transistors.These first / second transistors can be formed along a main area on the front face of a substrate. In some embodiments, the peripheral circuitry can be powered by a first supply voltage (sometimes referred to as VDD), and the memory cells can be powered by a second supply voltage (sometimes referred to as VDDM).

[0010] Unlike existing memory devices, the disclosed memory device can have a number of first metal conductors fabricated on the front side of the substrate and a number of second metal conductors fabricated on the back side of the substrate. By relocating some of the metal conductors configured to carry the second supply voltage VDDM from the front side to the back side, a substantial amount of space can be freed up for metal tracing on the front side of the substrate. This advantageously reduces the capacitance coupling between the front-side metal conductors configured as word lines of the memory matrix.Furthermore, a number of third metal conductor tracks, which carry the ground voltage and which in existing memory devices are restricted to placement on the front side and in the same metallization layer as the word lines, can be relocated to the rear side in the currently disclosed memory device. By relocating these metal conductor tracks to the rear side, the word lines can be manufactured with a greater width, thereby advantageously reducing their resistance. Consequently, various performance characteristics (e.g., speed, maximum frequency, etc.) of the disclosed memory device can be significantly improved.

[0011] Fig. Figure 1 shows a block diagram of a storage system, a storage circuit, or a storage device 100 according to various embodiments. The storage device 100 is implemented as an integrated circuit. As in the illustrative example in Fig. As shown in Figure 1, the storage device 100 comprises a memory control unit 105, a memory matrix 120, and optionally a voltage control circuit 116. The memory matrix 120 can have a number of memory circuits, memory cells, memory bits, or bit cells 125 arranged in two-dimensional or three-dimensional matrices. Each of the memory cells 125 can be accessed by a plurality of access lines (e.g., one or more bit lines BLs and at least one word line WL). The memory control unit 105 is operationally connected to the memory matrix 120 to control operations (e.g., read operation, write operation) of the memory matrix 120. The memory control unit 105 is sometimes referred to as a peripheral circuit with respect to the memory matrix 120.

[0012] The memory matrix 120 is a hardware component that stores data. For example, the memory matrix 120 is implemented as a semiconductor storage device. The memory matrix 120 generally comprises a plurality of memory circuits or memory cells 125, each configured to store at least one data bit. In some embodiments, the memory matrix 120 comprises word lines WL0, WL1...WL1 J , each extending in a first direction, and bit lines BL0, BL1...BL K, each extending in a second direction. The word lines WL and the bit lines BLs can each be constructed as one or more metal conductors or conductive rails. Each memory cell 125 is operationally connected to at least one corresponding word line WL and at least one pair of corresponding bit lines BLs (e.g., each memory cell 125 formed at a junction of the corresponding word line WL and the corresponding pair of bit lines BLs), and can be operated according to the voltages or currents through the corresponding word line WL and the corresponding bit lines BLs.

[0013] Each memory cell 125 can comprise a static random access memory (SRAM) cell. In one embodiment, the memory cell can be implemented as a six-transistor SRAM cell (6T-SRAM cell) or other than a single-port SRAM cell. In another embodiment, the memory cell 125 can be implemented as a seven-transistor SRAM cell (7T-SRAM cell) or other than a two-port SRAM cell. In yet another embodiment, the memory cell 125 can be implemented as an eight-transistor SRAM cell (8T-SRAM cell) or other than a three-port SRAM cell. It is understood, however, that the memory cell 125 can be implemented in various other configurations, while still remaining within the scope of protection of this disclosure.

[0014] The memory control unit 105 is a hardware component configured to control operations of the memory matrix 120. In some embodiments, the memory control unit 105 comprises at least one bit line control unit 112 and one word line control unit 114. In various embodiments of the present disclosure, each of the circuit components of the memory control unit 105 can be supplied by a first supply voltage (referred to in this description as "VDD"), and the memory matrix 120 can be supplied by a second supply voltage (referred to in this description as "VDDM"). The first supply voltage VDD can be different from the second supply voltage VDDM.

[0015] For example, the word line control unit 114 and the bit line control unit 112 can each be powered by the VDD. The word line control unit 114 can be configured to provide a voltage or current signal to one or more of the word lines WL. The bit line control unit 112 can be configured to provide a voltage or current signal to one or more of the bit lines BLs. The bit line control unit 112 can further comprise one or more input / output circuits (e.g., read amplifiers, latches, etc.) configured to sample a voltage or current signal read from the memory matrix 120 through the one or more bit lines BLs. Although not shown, it is understood that the memory control unit 105 may include other circuit components such as an address decoder, an error correction circuit, a clock generator, etc.can exhibit capabilities to perform appropriate memory operations.

[0016] The bit line control unit 112 can be connected to the bit lines BLs of the memory matrix 120, and the word line control unit 114 can be connected to the word lines WLs of the memory matrix 120. In general, the word line control unit 114 is configured to write a data bit to a memory cell 125 by applying a voltage or current signal (occasionally referred to as a WL signal) to a corresponding word line WL, and the bit line control unit 112 is configured to apply a voltage or current signal corresponding to the data bit to be stored in the memory cell 125 to one of the corresponding pair of bit lines BLs.To read the data bit from a memory cell 125, the word line control unit 114 is configured to apply a WL signal to the corresponding word line WL, and the bit line control unit 112 is configured to sample a voltage or current signal corresponding to the data bit to be stored by the memory cell 125 and present on the corresponding bit line BL. In some other embodiments, the memory control unit 105 may have more, fewer, or different components than shown. Fig. 1 are shown, but also lies within the scope of protection of the present disclosure.

[0017] The voltage control circuit 116 is a hardware component configured to control the current supplying the memory matrix 120 and the current supplying the memory control unit (or peripheral circuit) 105. In some embodiments, the voltage control circuit 116 may have a number of first headers and / or a number of first footers operationally connected to the memory control unit 105 and a number of second headers and / or a number of second footers operationally connected to the memory matrix 120. Such headers / footers are generally configured to selectively connect a supply voltage (e.g., VDD, VDDM) or a reference voltage (e.g., a ground voltage) to the memory matrix 120 or the memory control unit 105 based on a control, enable, or track signal. The headers / footers are occasionally referred to as power supply gating devices.: power gating device). In addition to the headers / footers, the voltage control circuit 116 may include various other circuit components (e.g., voltage boosters, voltage regulators, etc.) suitable for setting or otherwise controlling the supply voltage provided to the memory matrix 120 and / or the memory control unit 105.

[0018] For example, the first header (e.g., a first PMOS transistor) can receive the first supply voltage (VDD) at a source / drain terminal of the first PMOS transistor and selectively supply the memory control unit 105 with a virtual supply voltage (occasionally referred to as 'VDDHD') through the other source / drain terminal of the first PMOS transistor based on a signal input into a gate terminal of the first PMOS transistor; and the second header (e.g., a second PMOS transistor) can receive the second supply voltage (VDDM) at a source / drain terminal of the second PMOS transistor and selectively supply the memory matrix 120 with another virtual supply voltage (occasionally referred to as 'VDDAI') through the other source / drain terminal of the second PMOS transistor based on a signal input into a gate terminal of the second PMOS transistor.

[0019] In various embodiments of the present disclosure, the storage device 100 disclosed herein can be fabricated on both sides of a substrate. For example, the storage matrix 120 and the storage control unit 105 of the storage device 100 can be fabricated as multiple transistors on a front side of the substrate. On the front side, a number of front-side metallization layers, each having multiple front-side metal conductors, can be fabricated; and on the back side of the substrate, a number of back-side metallization layers, each having multiple back-side metal conductors, can be fabricated.In general, the front-side metallization layers are designated as Mo layer, M1 layer, M2 layer, M3 layer, M4 layer and so on (in order from the substrate to the topmost front-side metallization layer), and the back-side metallization layers are designated as BM0 layer, BM1 layer, BM2 layer and so on (in order from the substrate to the topmost back-side metallization layer).

[0020] To maximize routing flexibility for the front-side metal traces and / or to reduce capacitance coupling between them, some of the front-side metal traces carrying the supply voltage or ground voltage can be partially or completely removed from the front side and moved to the rear side. In one non-restrictive example, the front-side metal traces carrying the second supply voltage VDDM can be moved from the M2 layer to the BM1 and / or BM2 layers. In another non-restrictive example, the front-side metal traces carrying the virtual supply voltage VDDAI can be moved from the M2 layer to the BM1 and / or BM2 layers.In yet another non-restrictive example, the front-side metal conductor tracks, which are set up to carry the ground voltage VSS, the second supply voltage VDDM and the virtual supply voltage VDDAI, can all be moved from the M2 layer to the BM1 and / or BM2 layer.

[0021] Although in Fig. 1. Where the storage device 100 is depicted as part of a system with a dual power supply rail (e.g., with supply voltages VDD and VDDM feeding the storage control unit 105 and the storage matrix 120, respectively), it is understood that the present disclosure is not limited to a storage device with a system with a dual power supply rail. Even, for example, with a system with a single power supply rail (e.g., with a single supply voltage VDD that supplies both the storage control unit and the storage matrix of a storage device), the storage device may have some of the front-side metal conductor tracks carrying the supply voltage VDD, which are to be relocated from the M2 layer to the BM1 and / or BM2 layers, while still remaining within the scope of protection of the present disclosure.

[0022] Fig. Figure 2 shows a circuit diagram 200 of an exemplary implementation of memory cell 125, which is in Fig. Figure 1 (hereinafter referred to as "memory cell 200") shows some embodiments. In the illustrative example of Fig. In Figure 2, the memory cell 200 comprises a six-transistor (6T) SRAM cell. In some other embodiments, the memory cell 200 can be implemented as one of a variety of other SRAM cells, such as a two-transistor, two-resistor (2T-2R) SRAM cell, a four-transistor (4T) SRAM cell, an eight-transistor (8T) SRAM cell, a ten-transistor (10T) SRAM cell, etc. Although the discussion of the present disclosure is directed to an SRAM cell, it is also understood that other embodiments of the present disclosure can also be used in other memory cells, such as dynamic random access memory (DRAM) cells.

[0023] As shown, memory cell 200 has 6 transistors: M1, M2, M3, M4, M5, and M6. Transistors M1 and M2 are configured as a first inverter, and transistors M3 and M4 are configured as a second inverter, with the first and second inverters cross-coupled. For example, the first and second inverters are each coupled between a supply voltage 201 (e.g., VDDM in the dual-rail implementation) and a reference voltage 203 (e.g., VSS or ground). The first inverter (formed by transistors M1 and M2) is coupled to transistor M5, and the second inverter (formed by transistors M3 and M4) is coupled to transistor M6.In addition to coupling with the first and second inverters, transistors M6 and M5 are each coupled to a word line (WL) 205 and are coupled to a bit line (BL) 207 and a complementary bit line 209 respectively (occasionally referred to as bit line rail or BLB).

[0024] In some embodiments, transistors M1 and M3 are designated as pull-up transistors of memory cell 200 (hereinafter referred to as "pull-up transistor M1" and "pull-up transistor M3," respectively); transistors M2 and M4 are designated as pull-down transistors of memory cell 200 (hereinafter referred to as "pull-down transistor M2" and "pull-down transistor M4," respectively); and transistors M5 and M6 are designated as access transistors of memory cell 200 (hereinafter referred to as "access transistor M5" and "access transistor M6," respectively). In some embodiments, transistors M2, M4, M5, and M6 each comprise an n-metal-oxide-semiconductor transistor (NMOS transistor), and M1 and M3 each comprise a p-metal-oxide-semiconductor transistor (PMOS transistor). Although the embodiment shown of Fig. Figure 2 shows that the transistors M1-M6 are either NMOS or PMOS transistors. Any one of a variety of transistors or devices suitable for use in a storage device can be implemented as at least one of the transistors M1-M6, such as a bipolar junction transistor (BJT), a high-electron-mobility transistor (HEMT), etc.

[0025] Access transistors M5 and M6 each have a gate terminal connected to word line WL 205. The gate terminals of transistors M5 and M6 are configured to receive a pulse signal through word line WL 205 to allow or block access to memory cell 200, as discussed in detail below. Transistors M2 and M5 are connected at node 210 via the drain terminal of transistor M2 and the source terminal of transistor M5. Node 210 is further connected to a drain terminal of transistor M1 and node 212. Transistors M4 and M6 are connected at node 214 via the drain terminal of transistor M4 and the source terminal of transistor M6. Node 214 is further connected to a drain terminal of transistor M3 and node 116.

[0026] When a memory cell (e.g., memory cell 200) stores a data bit, a first node of the bit cell is configured to be in a first logical state (either a logical state 1 or a logical state 0), and a second node of the bit cell is configured to be in a second logical state (either a logical state 0 or a logical state 1). The first and second logical states are complementary to each other. In some embodiments, the first logical state at the first node can represent the logical state of the data bit stored in the memory cell. In the embodiment shown, Fig. 2. For example, if memory cell 200 stores a data bit with a logical state of 1, node 210 is configured to be in the logical state of 1, and node 214 is configured to be in the logical state of 0.

[0027] To read the logical state of the data bit stored in memory cell 200, bit line BL 207 and bit line rail BLB 209 are precharged to VDDM (e.g., a logical state H, for example, using a capacitor to hold the charge). Then, word line WL 205 is set or activated to a logical state H by a drive signal, which turns on access transistors M5 and M6. Specifically, a rising edge of the drive signal is received at the gate terminals of access transistors M5 and M6, respectively, to turn them on. Once access transistors M5 and M6 are turned on based on the logical state of the data bit, the precharged bit line BL 207 or bit line rail BLB 209 can be discharged. For example, if memory cell 200 stores a logical 0, node 214 (e.g.,Q) can have a voltage corresponding to logic 1, and node 210 (e.g., Q rail) can have a voltage corresponding to its complementary logic 0. In response to the activation of access transistors M5 and M6, a discharge path can be provided starting at the pre-charged bit line rail BLB 209, through access transistor M5 and pull-down transistor M2, and down to ground voltage 203. While the voltage level on bit line rail BLB 209 is pulled down by such a discharge path, pull-down transistor M4 can remain off. Consequently, bit line BL 207 and bit line rail BLB 209 can each have a voltage level sufficient to generate a sufficiently large voltage difference between bit line BL 207 and bit line rail BLB 209.Accordingly, a read amplifier connected to the bit line BL 207 and the bit line rail BLB 209 can determine, using the polarity of the voltage difference, whether the logical state of the data bit is a logical state 1 or a logical state 0.

[0028] To write the data bits stored in memory cell 200, the data to be written is applied to bit line BL 207 and / or bit line rail BLB 209. For example, bit line rail BLB 209 is connected / shorted to 0V, e.g., ground voltage 203, via a low-impedance connection. Then, word line WL 205 is set to a logic high (H) or activated by a drive signal, which turns on access transistors M5 and M6. Once access transistors M5 and M6 are turned on based on the logic state of bit line rail BLB 209, node 210 can begin to discharge. Before M5 and M6 are turned on, for example, bit line rail BLB 209 may have a voltage corresponding to logic state 0, and node 210 may have a voltage corresponding to its complementary logic state 1.In response to the activation of access transistors M5 and M6, a discharge path starting at node 210, through access transistor M5, to ground voltage 203 can be provided. Once the voltage level at node 210 is pulled below the threshold voltage (Vth) of pull-down transistor M4, M4 can be switched off and M3 can be switched on, thereby pulling node 214 up to the VDDM 201. Once node 214 is less than the Vth of VDD 201, M1 and M2 can be switched off, thereby pulling node 210 down to ground voltage 203. When word line WL 205 is no longer driven, the logical state that had been applied to bit line BL 207 and / or bit line rail BLB 209 has been stored in memory cell 200.

[0029] Fig. 3A and Fig. Figures 3B jointly disclose an exemplary layout 300 which can be configured to form the disclosed storage device 100, which has a reduced number of front-facing metal conductor tracks carrying the ground voltage, the supply voltage, and / or the virtual supply voltage according to some embodiments. It is understood that the [description of the] Fig. Layout 300 shown in 3A-B has been simplified, and consequently, Layout 300 can have various other components (e.g., structures for forming the respective structures), which is also within the scope of protection of the present disclosure.

[0030] In general, the layout 300 comprises a plurality of structures arranged to form respective structures such as front-side metal conductor tracks, rear-side metal conductor tracks, etc. Accordingly, such structures of the disclosed layout are referred to in this description as the structures to be formed in the following discussion. For example, Fig. 3A shows a top view of the layout 300 with a number of front-side metal conductor tracks, and Fig. 3B can show a top view of layout 300 (upside down) with a number of rear metal conductor tracks, while Fig. 3A and Fig. 3B each has the storage cells formed on the front side of a substrate.

[0031] First, with reference to Fig. 3A A number of (e.g., 16) memory cells 301 are formed or otherwise arranged in a region of a substrate. These multiple 16 memory cells 301 can at least partially form a memory matrix (e.g., 120 of Fig. 1) form a table arranged across multiple rows and multiple columns. For example, in Fig. 3A The memory cells 301 are arranged over 8 rows (extending, for example, in the y-direction) and 2 columns (extending, for example, in the x-direction). Furthermore, the memory cells 301 can each be assigned to the in Fig. The two 6T SRAM cells shown correspond to 200 and can each be implemented as a standard cell in the layout 300. In general semiconductor IC design, the standard cell methodology uses standard cells as abstract representations of specific functions to integrate millions of devices onto a single chip.

[0032] An exemplary layout of the standard cell of each of these memory cells 301 is given with reference to Fig. Section 6 discusses this in more detail. In general, when implemented as a standard cell based on a 6T SRAM cell structure, memory cell 301 can have a number of active regions extending along a first lateral direction and a number of gate structures extending along a second lateral direction. Each of these active regions can be superimposed on one or more of the gate structures to form the six transistors, M1 to M6, that operationally constitute a 6T SRAM cell. It is understood that if memory cell 301 is implemented as a different SRAM cell structure, the layout of the corresponding standard cell can vary accordingly.

[0033] Before, at the same time as, or after the transistors configured as the 301 memory cells are formed on the front side of the substrate, a plurality of other transistors can also be formed on the front side of the substrate. These transistors can form at least one memory control unit (e.g., 105 of Fig. 1) form, which is operationally connected to the memory cells 301. In some embodiments, these transistors can be physically formed around the area in which the memory cells 301 are formed and implemented as various other standard cells (e.g., an AND gate, an OR gate, an XOR gate, a NOT gate, a NAND gate, a NOR gate and an XNOR gate, as well as combinational logic circuits such as a multiplexer, a flip-flop, an adder, a counter, etc.), which are not shown for clarity.

[0034] After the transistors, which operationally serve as the memory cells and the memory control unit, have been formed, a number of front-facing metallization layers can be fabricated over these transistors. Each of these front-facing metallization layers can have a plurality of metal conductors embedded in one or more dielectric layers (made, for example, from an oxide material or a low-k dielectric material). As disclosed in this description, the lowest of the front-facing metallization layers is called the Mo layer, and the metal conductors fabricated in the Mo layer are called M0 conductors.Above the Mo layer, an M1 layer, which has a number of M1 conductors, can be produced; above the M1 layer, an M2 layer, which has a number of M2 conductors, can be produced; above the M2 layer, an M3 layer, which has a number of M3 conductors, can be produced, and so on.

[0035] Furthermore, with reference to Fig. Layout 3A comprises a number of first structures for forming the M0 traces 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, and 324. The M0 traces 310 to 324 each extend along the x-direction and are each configured to perform a specific function. For example, the M0 traces 310-311, 317, and 323-324 can each be configured to carry the ground voltage VSS; the M0 traces 322 and 318 can be configured as BL and BLB of a first column, BL[0] and BLB[0]; The M0 traces 312 and 316 can be configured as BL and BLB of a second column, BL[1] and BLB[1]; the M0 traces 313, 315, 319 and 321 can be configured to carry the second supply voltage VDDM; and the M0 traces 314 and 320 can each be configured to carry the virtual supply voltage VDDAI.Although not shown, it is understood that each of these M0 conductor tracks 310 to 324 may be electrically connected to the underlying transistors by one or more via structures (occasionally referred to as VGs or VDs) and / or one or more contact structures (occasionally referred to as MDs).

[0036] Above the M0 traces 310 to 324, layout 300 features a number of secondary structures for forming the M1 traces 330, 331, 332, 333, 334, 335, 336, and 337. The M1 traces 330 to 337 can each extend along the y-direction and each be configured to perform a specific function.For example, M1 trace 337 can be configured as the word line of a first line, WL[0]; M1 trace 336 can be configured as the word line of a second line, WL[1]; M1 trace 335 can be configured as the word line of a third line, WL[2]; M1 trace 334 can be configured as the word line of a fourth line, WL[3]; M1 trace 333 can be configured as the word line of a fifth line, WL[4]; M1 trace 332 can be configured as the word line of a sixth line, WL[5]; M1 trace 331 can be configured as the word line of a seventh line, WL[6]; and M1 trace 330 can be configured as the word line of an eighth line, WL[7].

[0037] A number of structures for forming M2 traces could be arranged above the M1 traces 330 to 337. In existing technologies, these M2 traces, each configured to carry the ground voltage VSS, the second supply voltage VDDM, or the virtual supply voltage VDDAI, are restricted to being formed on the front side. However, according to the present disclosure, these M2 traces are moved from the front side to the back side, which in Fig. 3B is discussed. By relocating these M2 traces, each carrying a supply / reference voltage, a considerable amount of space is freed up in the M2 layer, improving flexibility in the placement of other M2 traces (e.g., 339A, 339B, 339C, 339D, 339E, etc.) each configured to carry a non-power supply signal. As revealed in this description, such a non-power supply signal generally refers to a signal that is not directly related to (connected to) a supply voltage or a reference voltage and is communicated operationally in a single circuit component (e.g., an SRAM cell) or across different circuit components (e.g., adjacent SRAM cells), such as the signal present on bit line BL 207, bit line rail BLB 209, or word line WL 205.Furthermore, without the M2 conductors carrying a generated supply / reference voltage, the capacitance coupling between the word lines formed in the M1 layer and the word lines formed in the M3 layer (discussed below) can be significantly reduced.

[0038] Above the M2 layer (or the M2 traces 339A-E that are not configured to carry a supply / reference voltage), the layout 300 includes a number of third structures for forming M3 traces 340, 341, 342, 343, 344, 345, 346, and 347. The M3 traces 340 to 347 can each extend along the y-direction and each can be configured to perform a specific function.For example, M3 trace 347 can be configured as the word line of the first line, WL[0]; M3 trace 346 can be configured as the word line of the second line, WL[1]; M3 trace 345 can be configured as the word line of the third line, WL[2]; M3 trace 344 can be configured as the word line of the fourth line, WL[3]; M3 trace 343 can be configured as the word line of the fifth line, WL[4]; M3 trace 342 can be configured as the word line of the sixth line, WL[5]; M3 trace 341 can be configured as the word line of the seventh line, WL[6]; and M3 trace 340 can be configured as the word line of the eighth line, WL[7]. In some embodiments, none of these M3 conductor tracks are present. Fig. The M3 traces shown in Figure 3A are configured to carry the ground voltage VSS, which is often limited in existing technologies. Such M3 traces, which carry the ground voltage VSS and are limited in existing technologies, are moved from the front to the back, allowing each of the word lines (e.g., M3 traces 340 to 347) to be made wider (in the x-direction) or allowing the word lines to be spaced further apart. With a greater width, these word lines can advantageously have lower resistance, and with a greater spacing, capacitance coupling between adjacent word lines can be advantageously suppressed.

[0039] The following are some non-restrictive examples compared to existing storage devices. As a first non-restrictive example, with a constant spacing of approximately 30 nanometers between adjacent M3 traces, the width of each of the M3 traces 340 to 347 can be increased from approximately 56 nanometers to approximately 66 nanometers. Consequently, the width-to-spacing ratio can increase to more than 2. As a second non-restrictive example, where the spacing between adjacent M3 traces increases by approximately 33%, the width of each of the M3 traces 340 to 347 can increase by approximately 18%. As a third non-restrictive example, where the spacing between adjacent M3 traces increases by approximately 40%, the width of each of the M3 traces 340 to 347 can decrease by approximately 4%.As a fourth non-restrictive example, where the distance between adjacent M3 conductor tracks increases by about 47%, the width of each of the M3 conductor tracks 340 to 347 can decrease by about 8%.

[0040] After the front-side metal conductors have been fabricated, the substrate is flipped over, and a number of back-side metallization layers are fabricated one above the other. Each of these back-side metallization layers can have a plurality of metal conductors embedded in one or more dielectric layers (fabricated, for example, from an oxide material or a low-k dielectric material). As disclosed in this description, the bottommost of the back-side metallization layers is referred to as the BM0 layer, and the metal conductors fabricated in the BM0 layer are referred to as the BM0 conductors.Above the BM0 layer, a BM1 layer, which has a number of BM1 conductors, can be manufactured; above the BM1 layer, a BM2 layer, which has a number of BM2 conductors, can be manufactured; above the BM2 layer, a BM3 layer, which has a number of BM3 conductors, can be manufactured; and so on.

[0041] Then, with reference to Fig. In 3B, where memory cells 310 are present as a reference, layout 300 includes a number of fourth structures for creating BM0 traces 350, 351, 352, 353, 354, 355, and 356. BM0 traces 350 through 356 can each extend along the x-direction and can each be configured to perform a specific function. For example, BM0 traces 350, 353, and 356 can each be configured to carry the ground voltage VSS; BM0 traces 352 and 354 can each be configured to carry the second supply voltage VDDM; and BM0 traces 351 and 355 can each be configured to carry the virtual supply voltage VDDAI. Although not shown, it is understood that each of these BM0 conductor tracks 350 to 356 may be electrically connected to the transistors by one or more via structures (occasionally referred to as BVs).

[0042] Above the BM0 traces 350 to 356, layout 300 includes a number of fifth structures for creating BM1 traces 360, 361, 362, 363, 364, 365, 366, 367, 368, 369, 370, 371, 372, and 373. The BM1 traces 360 to 373 can each extend along the y-direction and each be configured to perform a specific function. For example, BM1 traces 361, 363-370, and 372 can each be configured to carry the ground voltage VSS; BM1 traces 360 and 373 can each be configured to carry the secondary supply voltage VDDM; and the BM1 conductor tracks 362 and 371 can each be configured to carry the virtual supply voltage VDDAI.

[0043] Above the BM1 traces 360 to 373, the layout 300 includes a number of sixth structures for creating BM2 traces 380, 381, 382, ​​and 383. The BM2 traces 380 to 383 can each extend along the x-direction and can each be configured to perform a specific function. For example, BM2 traces 380 and 382 can each be configured to carry the second supply voltage VDDM; and BM2 traces 381 and 383 can each be configured to carry the ground voltage VSS.

[0044] As indicated above, according to the exemplary layout, 300 of the Fig. With the exception of the Mo layer, none of the front-side metallization layers (e.g., M1 layer, M2 layer, M3 layer) in layers 3A-B contain a metal trace carrying a supply or reference voltage. Such metal traces configured to carry the supply / reference voltage are moved to the back side. The BM1 layer, for example, includes several metal traces (e.g., 360, 373) configured to carry the second supply voltage VDDM, several metal traces (e.g., 362, 371) configured to carry the virtual supply voltage VDDAI, and several metal traces (e.g., 361, 363-370, 372) configured to carry the reference / ground voltage VSS. In another example, the BM2 layer includes several metal conductors (e.g., 380, 382) configured to carry the second supply voltage VDDM, and several metal conductors (e.g.,381, 383), which are set up in such a way that they carry the reference / ground voltage VSS.

[0045] It goes without saying that the layout 300 of the Fig. 3A-B is merely one of several exemplary layouts that can form a storage device with a reduced number of front-side metal traces, configured to carry a supply / reference voltage. The table below summarizes some of these alternative embodiments, which also includes the arrangement of layout 300 as a reference. Each of these embodiments summarizes where the VDDM / VDDAI / VSS-carrying metal traces are manufactured. Table Layout 300 AlternativesLayout 1 AlternativesLayout 2 AlternativesLayout 3 AlternativesLayout 4 AlternativesLayout 5 M3 NA NA VDDM VSS VDDM VSS M2 NA VDDAI VDDM.VDDAI VSS, VDDAI VDDM VSS M1 NA VDDAI VDDM,VDDAI VSS, VDDAI VDDM VSS M0 VDDM,VSS,VDDAI VDDM,VSS,VDDAI VDDM,VSS, VDDAI VDDM,VSS, VDDAI VDDM,VSS, VDDAI VDDM,VSS, VDDAI BM0 VDDM,VSS,VDDAI VDDM, VSS VSS VDDM VSS, VDDAI VDDM,VDDAI BM1 VDDM,VSS,VDDAI VDDM, VSS VSS VDDM VSS, VDDAI VDDM,VDDAI BM2 VDDM,VSS VDDM, VSS VSS VDDM VSS VDDM

[0046] The Fig. 4A and Fig. Figures 4B jointly show a portion of the alternative layout 1 (hereinafter “layout 400”), which can be configured to form the disclosed storage device 100 with a reduced number of front-facing metal conductor tracks carrying the ground voltage, the supply voltage, and / or the virtual supply voltage according to some embodiments. Similar to layout 300 of Fig. 3A-B will have a memory matrix with 16 memory cells 401 in the Fig. 4A-B shown for reference.

[0047] In Fig. Layout 400 comprises an M1 layer with M1 traces 430, 431, 432, 433, 434, 435, 436, and 437, each configured as a word line, and M1 traces 429 and 438, each configured to carry VDDAI; and an M2 layer with M2 traces 439A and 439B, each configured to carry VDDAI. Although not shown, layout 400 may include a Mo layer with metal traces configured to carry VDDM, VSS, and VDDAI, and an M3 layer without a metal trace configured to carry VDDM, VDDAI, or VSS, both resembling layout 300. Fig. Layout 4B comprises a BM0 layer with BM0 traces 450, 453, and 456, each configured to carry VSS, and BM0 traces 451, 452, 454, and 455, each configured to carry VDDM; a BM1 layer with BM1 traces 463, 464, 465, 466, 467, 468, 469, and 470, each configured to carry VSS; and a BM2 layer with a BM2 trace 481 configured to carry VSS and a BM2 trace 482 configured to carry VDDM. Consequently, only metal traces carrying VDDAI can be present in the M2 layer. and in the M3 layer there can be no metal conductor tracks that are configured to carry a supply or reference voltage.

[0048] The Fig. 5A and Fig. Figures 5B jointly show a portion of the alternative layout 3 (hereinafter “layout 500”), which can be configured to form the disclosed storage device 100 with a reduced number of front-facing metal conductor tracks carrying the ground voltage, the supply voltage, and / or the virtual supply voltage according to some embodiments. Similar to layout 300 of Fig. 3A-B and the layout 400 of the Fig. 4A-B will have a memory matrix with 16 memory cells 501 in the Fig. 5A-B shown for reference.

[0049] In Fig. Layout 500 5A comprises an M1 layer with M1 traces 530, 531, 532, 533, 534, 535, 536 and 537, each configured as a word line, and M1 traces 529 and 538, each configured to carry VDDAI or VSS; and an M2 layer with M2 traces 539A, 539C, 539E, each configured to carry VSS, and M2 traces 539B and 539D, each configured to carry VDDAI. Although not shown, the Layout 400 may include: a Mo layer with metal traces configured to carry VDDM, VSS, and VDDAI (similar to Layout 300), and an M3 layer with multiple metal traces configured to carry VSS. Fig. Layout 5B includes a BM0 layer with BM0 traces 551, 552, 553 and 554, each configured to carry VDDM; a BM1 layer with BM1 traces 561, 562, 563, 564, 565, 566, 567 and 568, each configured to carry VDDM; and a BM2 layer with a BM2 trace 581, configured to carry VDDM.

[0050] In such an embodiment (the alternative layout 500), the M2 traces carrying VDDAI (e.g., 539B and 539D) and the M2 traces carrying VSS (e.g., 539A, 539C, and 539E) can be arranged alternately along the y-direction. For example, each of the memory cells 501 can have a first edge extending in the x-direction, superimposed by one of the M2 traces 539A, 539C, or 539E, and a second edge extending in the x-direction, superimposed by another of the M2 traces 539A, 539C, or 539E, with one of the M2 traces 539B or 539D crossing a central part of the memory cell 501. In other words, the distance between the M2 trace carrying VSS and the M2 trace carrying VDDAI (along the y-direction) is equal to half the cell height of memory cell 501.

[0051] Fig. Figure 6 shows an exemplary 600 layout configured to accommodate a 6T SRAM cell (e.g., 200 of Fig. 2) according to some embodiments. It is understood that the layout 600, which is in Fig. Figure 6 has been simplified, and consequently the layout can have 600 different other components (e.g. structures for forming the respective structures), while still remaining within the scope of protection of the present disclosure.

[0052] As shown, the layout 600 comprises structures for forming active regions 602, 604, 606, and 608, respectively. Each of the active regions 602 to 608 can be fabricated as a fin structure or a stacked structure (with multiple first nanostructures and second nanostructures stacked alternately on top of each other) extending along the x-direction. Active regions 602 and 608 are formed in a first conduit type (e.g., n-type), and active regions 604 and 606 are formed in a second conduit type (e.g., p-type). The layout 600 includes structures for fabricating dummy regions 610, 612, 614, 616, and 618, each of which can also extend along the same lateral direction as the active regions 602 to 608. Layout 600 includes structures for creating gate structures 620, 622, 624 and 626, each of which can extend along the y-direction.

[0053] Each of the active regions 602 to 608 is spanned (or otherwise superimposed) by one or more of the gate structures 620-626 to define the respective channels of a number of transistors. A number of source / drain structures (e.g., epitaxial structures) can be fabricated on the opposite sides of each gate structure in the active region. In some embodiments, the gate structures 620 to 626 can each be segmented into a number of sections by the dummy regions 610 to 618. Consequently, six transistors M1 to M6 of a 6T SRAM cell (e.g., 200) can be realized. For example, the access transistor M5 can be defined by the gate structure 622 and the source / drain structures fabricated in the active region 602. The pull-down transistor M2 can be defined by the gate structure 624 and the source / drain structures that have been manufactured in the active area 602;The pull-up transistor M1 can be defined by the gate structure 624 and the source / drain structures fabricated in the active region 604; the pull-up transistor M3 can be defined by the gate structure 622 and the source / drain structures fabricated in the active region 606; the access transistor M6 can be defined by the gate structure 624 and the source / drain structures fabricated in the active region 608; and the pull-down transistor M4 can be defined by the gate structure 622 and the source / drain structures fabricated in the active region 608.

[0054] Fig. Figure 7 shows a flowchart of a method 700 for manufacturing a storage device according to some embodiments. The method 700 can be part of a method for manufacturing an integrated circuit. For example, the flowchart of the method 700 for manufacturing an integrated circuit based on the one described in the Fig. The layouts shown in Figures 3A-3B may be set up accordingly. Therefore, the following discussion of Method 700 may occasionally refer to the preceding figures. It is understood that Method 700 is Fig. Paragraph 7 is merely an example and is not intended to limit the present disclosure. Consequently, it is understood that the sequence of operations in Procedure 700 may be modified and, for example, further operations may be provided before, during, and after Procedure 700, and that some operations may only be briefly described in this disclosure.

[0055] Procedure 700 can begin with Operation 710 to fabricate a memory matrix on the front side of a substrate. The memory matrix comprises a number of memory cells (e.g., 301) powered by a first supply voltage (e.g., VDDM). Procedure 700 can continue with Operation 520 to fabricate a peripheral circuit (or memory control unit) on the front side. The memory control unit is operationally connected to the memory matrix and is powered by a second supply voltage (e.g., VDD). The second supply voltage is different from the first supply voltage.

[0056] Method 700 can be continued with Operation 730 to fabricate a first metallization layer on the front side and over the memory matrix and peripheral circuitry, wherein the first metallization layer comprises a plurality of first metal conductors. In some embodiments, each of the plurality of first metal conductors (e.g., M0 conductors 310 to 324) can extend along a first lateral direction and be configured to carry the first supply voltage, a virtual supply voltage (e.g., VDDAI), or a ground voltage (e.g., VSS). Method 700 can be continued with Operation 540 to fabricate a second metallization layer on the first side and over the first metallization layer, wherein the second metallization layer comprises a plurality of second metal conductors. In some embodiments, each of the plurality of second metal conductors (e.g.,M1 conductors 330 to 337) extend along a second lateral direction perpendicular to the first lateral direction and is configured as a word line operationally connected to one or more of the plurality of memory cells. Method 700 can be continued with operation 750 to produce a third metallization layer on the first side and above the second metallization layer, the third metallization layer having a plurality of third metal conductors. In some embodiments, each of the plurality of third metal conductors (e.g., M2 conductors not in ) extends Fig.(3A shown) along the first lateral direction and is configured to carry only a non-power supply signal instead of the first supply voltage. Method 700 can be continued with operation 760 to produce a fourth metallization layer on the first side and above the third metallization layer, the fourth metallization layer having a plurality of fourth metal conductors. In some embodiments, each of the plurality of fourth metal conductors (e.g., M3 conductors 340 to 347) extends along the second lateral direction and is configured only as the word line.

[0057] Method 700 can be continued with Operation 770 to fabricate a fifth metallization layer on a second side of the substrate, wherein the fifth metallization layer comprises a plurality of fifth metal conductors. In some embodiments, each of the plurality of fifth metal conductors (e.g., BM0 conductors 350 to 356) extends along the first lateral direction and is configured to carry the first supply voltage VDDM, the virtual supply voltage VDDAI, or the ground voltage VSS. Method 700 can be continued with Operation 780 to fabricate a sixth metallization layer on the second side and above the fifth metallization layer, wherein the sixth metallization layer comprises a plurality of sixth metal conductors. In some embodiments, each of the plurality of sixth metal conductors (e.g.,BM1 traces 260 to 373) extend along the second lateral direction and are configured to carry the first supply voltage VDDM, the virtual supply voltage VDDAI, or the ground voltage VSS. Method 700 can be continued with Operation 790 to fabricate a seventh metallization layer on the second side of the substrate, the seventh metallization layer having a plurality of seventh metal traces. In some embodiments, each of the plurality of seventh metal traces (e.g., BM2 traces 380 to 383) extends along the first lateral direction and is configured to carry the first supply voltage VDDM or the ground voltage VSS.

[0058] In one aspect of the present disclosure, a storage device is disclosed. The storage device comprises a plurality of memory cells physically fabricated on a first side of a substrate; a peripheral circuit operationally connected to the plurality of memory cells and physically fabricated on the first side of the substrate; a first metallization layer physically fabricated on the first side of the substrate and comprising a plurality of first metal conductors, each of the plurality of first metal conductors extending along a first lateral direction and configured to carry a supply voltage or a ground voltage, the first supply voltage being configured to power the plurality of memory cells;a second metallization layer, physically fabricated on the first side of the substrate, comprising a plurality of second metal conductors, each of the plurality of second metal conductors extending along a second lateral direction and configured as a word line operationally connected to one or more of the plurality of memory cells; a third metallization layer, physically fabricated on the first side of the substrate, comprising a plurality of third metal conductors, each of the plurality of third metal conductors extending along the first lateral direction, with at least one of the plurality of third metal conductors configured to carry only a non-power supply signal instead of the supply voltage;a fourth metallization layer, physically fabricated on the first side of the substrate, comprising a plurality of fourth metal conductors, each of the plurality of fourth metal conductors extending along the second lateral direction and configured solely as the word conductor; a fifth metallization layer, physically fabricated on a second side of the substrate, comprising a plurality of fifth metal conductors, each of the plurality of fifth metal conductors extending along the first lateral direction and configured to carry the supply voltage or the ground voltage;and a sixth metallization layer, which is physically fabricated on the second side of the substrate and has a plurality of sixth metal conductors, each of the plurality of sixth metal conductors extending along the second lateral direction and configured to carry the supply voltage or the ground voltage.

[0059] In a further aspect of the present disclosure, a storage device is disclosed. The storage device comprises a storage cell supplied by a first supply voltage; a peripheral circuit operationally connected to the storage cell and supplied by a second supply voltage; a first metal conductor and a second metal conductor arranged in a first of a plurality of front-facing metallization layers and extending in a first lateral direction, the first metal conductor and the second metal conductor being configured to carry the first supply voltage and a ground voltage, respectively, the supply voltage being provided to power the storage cell;a third metal conductor track arranged in a second of the plurality of front-facing metallization layers and extending in a second lateral direction, wherein the third metal conductor track is configured as a word line operationally connected to the memory cell; a fourth metal conductor track and a fifth metal conductor track arranged in a third of the plurality of front-facing metallization layers and extending in the first lateral direction, wherein the fourth metal conductor track and the fifth metal conductor track are configured to carry a virtual supply voltage and the ground voltage, respectively, the virtual supply voltage being selectively provided to power the memory cell;a sixth metal conductor, arranged in a first of a plurality of backside metallization layers and extending in the first lateral direction, wherein the sixth metal conductor is configured to carry the first supply voltage; and a seventh metal conductor, arranged in a second of the plurality of backside metallization layers and extending in the second lateral direction, wherein the seventh metal conductor is configured to carry the first supply voltage.

[0060] In yet another aspect of the present disclosure, a method for manufacturing a storage device is disclosed. The method comprises manufacturing a storage matrix on a first side of a substrate, wherein the storage matrix has a plurality of storage cells which is supplied by a first supply voltage. The method also comprises manufacturing a peripheral circuit on the first side of the substrate, wherein the peripheral circuit is operationally connected to the storage matrix and is supplied by a second supply voltage which is different from the first supply voltage.The method comprises fabricating a first metallization layer on the first side and over the memory matrix and the peripheral circuitry, wherein the first metallization layer has a plurality of first metal conductors, each of the plurality of first metal conductors extending along a first lateral direction and configured to carry the first supply voltage or a ground voltage. The method comprises fabricating a second metallization layer on the first side and over the first metallization layer, wherein the second metallization layer has a plurality of second metal conductors, each of the plurality of second metal conductors extending along a second lateral direction and configured as a word line operationally connected to one or more of the plurality of memory cells.The method comprises fabricating a third metallization layer on the first side and above the second metallization layer, wherein the third metallization layer has a plurality of third metal conductors, each of the plurality of third metal conductors extending along the first lateral direction and configured to carry only a non-power supply signal instead of the first supply voltage. The method comprises fabricating a fourth metallization layer on the first side and above the third metallization layer, wherein the fourth metallization layer has a plurality of fourth metal conductors, each of the plurality of fourth metal conductors extending along the second lateral direction and configured only as the word line.The method comprises fabricating a fifth metallization layer on a second side of the substrate, wherein the fifth metallization layer has a plurality of fifth metal conductors, each of the plurality of fifth metal conductors extending along the first lateral direction and configured to carry the first supply voltage or the ground voltage. The method comprises fabricating a sixth metallization layer on the second side and above the fifth metallization layer, wherein the sixth metallization layer has a plurality of sixth metal conductors, each of the plurality of sixth metal conductors extending along the second lateral direction and configured to carry the first supply voltage or the ground voltage.

[0061] In this description, the terms "approximately" and "about" generally indicate the value of a given quantity, which may vary based on a specific technology node associated with the semiconductor device of the item. Based on this specific technology node, the term "approximately" can indicate a value of a given quantity that varies, for example, within 10–30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0062] Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present disclosure. It should be clear to those skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other methods and structures to achieve the same objectives and / or to obtain the same advantages as in the embodiments presented here. Those skilled in the art should also recognize that such equivalent interpretations do not deviate from the fundamental concept and scope of protection of the present disclosure and that they can make various changes, substitutions, and modifications without deviating from the fundamental concept and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 690,012

[0001]

Claims

[1] Storage device with: a plurality of memory cells that are physically fabricated on a first side of a substrate; a peripheral circuit that is operationally connected to the majority of memory cells and is physically fabricated on the first side of the substrate; a first metallization layer that is physically produced on the first side of the substrate and has a plurality of first metal conductors, each of the plurality of first metal conductors extending along a first lateral direction and configured to carry a supply voltage or a ground voltage, the first supply voltage being configured to feed the plurality of memory cells; a second metallization layer that is physically produced on the first side of the substrate and has a plurality of second metal conductor tracks, each of the plurality of second metal conductor tracks extending along a second lateral direction and configured as a word line that is operationally connected to one or more of the plurality of memory cells; a third metallization layer that is physically produced on the first side of the substrate and has a plurality of third metal conductors, each of the plurality of third metal conductors extending along the first lateral direction, wherein at least one of the plurality of third metal conductors is configured to carry only a non-power supply signal instead of carrying the supply voltage; a fourth metallization layer, which is physically produced on the first side of the substrate and has a plurality of fourth metal conductors, each of the plurality of fourth metal conductors extending along the second lateral direction and configured only as the word conductor; a fifth metallization layer, which is physically produced on a second side of the substrate and has a plurality of fifth metal conductors, each of the plurality of fifth metal conductors extending along the first lateral direction and configured to carry the supply voltage or the ground voltage; and a sixth metallization layer, which is physically produced on the second side of the substrate and has a plurality of sixth metal conductors, each of the plurality of sixth metal conductors extending along the second lateral direction and being arranged to carry the supply voltage or the ground voltage. [2] Storage device according to claim 1, further comprising a power supply switch configured to receive the supply voltage and selectively provide a virtual supply voltage to the plurality of memory cells. [3] Storage device according to claim 1 or 2, wherein each of the storage cells is superimposed by one of the third metal conductor tracks, which is configured to carry the virtual supply voltage. [4] Storage device according to claim 3, wherein a further of the third metal conductor tracks, which is configured to carry the ground voltage, and yet another of the third metal conductor tracks, which is configured to carry the virtual supply voltage, are spaced apart from each other along the second lateral direction. [5] Storage device according to one of the preceding claims, wherein the distance is equal to half a cell height of each of the storage cells. [6] Storage device according to one of the preceding claims, wherein no further third metal conductor track is positioned between the further third metal conductor track that is configured to carry the ground voltage and the further third metal conductor track that is configured to carry the virtual supply voltage. [7] Storage device according to one of the preceding claims, wherein each of the storage cells is free from superposition by a metal conductor track which is produced in the third metallization layer and is arranged to carry the supply voltage. [8] Storage device according to one of the preceding claims, wherein each of the plurality of storage cells comprises a static direct access storage cell. [9] Storage device according to one of the preceding claims, wherein none of the plurality of fourth metal conductor tracks is arranged to carry the ground voltage. [10] Storage device according to one of the preceding claims, wherein a ratio of a width of each of the plurality of fourth metal conductor tracks along the first lateral direction to a distance between adjacent of the plurality of fourth metal conductor tracks is equal to or greater than 2. [11] Storage device according to one of the preceding claims, wherein on the first side the fourth metallization layer is arranged above the third metallization layer, which is arranged above the second metallization layer, which is arranged above the first metallization layer, and wherein on the second side the sixth metallization layer is arranged above the fifth metallization layer. [12] Storage device with: a memory cell that is powered by an initial supply voltage; a peripheral circuit that is operationally connected to the memory cell and is powered by a second supply voltage; a first metal conductor and a second metal conductor arranged in a first plurality of front-side metallization layers and extending in a first lateral direction, wherein the first metal conductor and the second metal conductor are configured to carry the first supply voltage and a ground voltage respectively, the supply voltage being provided to power the memory cell; a third metal conductor track, which is arranged in a second of the plurality of front-side metallization layers and extends in a second lateral direction, wherein the third metal conductor track is configured as a word line which is operationally connected to the memory cell; a fourth metal conductor track and a fifth metal conductor track, which are arranged in a third of the plurality of front-side metallization layers and extend in the first lateral direction, wherein the fourth metal conductor track and the fifth metal conductor track are configured to carry a virtual supply voltage and the ground voltage respectively, wherein the virtual supply voltage is selectively provided to power the memory cell; a sixth metal conductor track, which is arranged in a first of a plurality of backside metallization layers and extends in the first lateral direction, wherein the sixth metal conductor track is configured to carry the first supply voltage; and a seventh metal conductor track, which is arranged in a second of the plurality of backside metallization layers and extends in the second lateral direction, wherein the seventh metal conductor track is configured to carry the first supply voltage. [13] Storage device according to claim 12, further comprising a power supply switch configured to receive the first supply voltage and selectively provide the virtual supply voltage to the memory cell. [14] Storage device according to claim 12 or 13, wherein the storage cell and the peripheral circuitry are manufactured along a major surface of a substrate, and wherein the plurality of front metallization layers and the plurality of back metallization layers are each manufactured on opposite sides of the substrate. [15] Storage device according to one of claims 12 to 14, wherein no further metal conductor track is positioned in the third front-side metallization layer between the fourth metal conductor track and the fifth metal conductor track. [16] Storage device according to one of claims 12 to 15, wherein the fourth metal conductor track and the fifth metal conductor track are spaced apart from each other in the second lateral direction and wherein the distance is equal to half a cell height of the storage cell. [17] Storage device according to any one of claims 12 to 16, wherein the first supply voltage and the second supply voltage are different from each other. [18] Method for manufacturing a storage device comprising the following steps: Fabricating a memory matrix on a first side of a substrate, wherein the memory matrix has a plurality of memory cells which are supplied by a first supply voltage; Establishing a peripheral circuit on the first side of the substrate, wherein the peripheral circuit is operationally connected to the memory matrix and is powered by a second supply voltage that is different from the first supply voltage; Producing a first metallization layer on the first side and over the memory matrix and peripheral circuitry, wherein the first metallization layer has a plurality of first metal conductors, each of the plurality of first metal conductors extending along a first lateral direction and being arranged to carry the first supply voltage or a ground voltage; Producing a second metallization layer on the first side and above the first metallization layer, wherein the second metallization layer has a plurality of second metal conductors, each of the plurality of second metal conductors extending along a second lateral direction and being configured as a word line operationally connected to one or more of the plurality of memory cells; Producing a third metallization layer on the first side and above the second metallization layer, wherein the third metallization layer has a plurality of third metal conductors, each of the plurality of third metal conductors extending along the first lateral direction and being arranged to carry only a non-power supply signal instead of carrying the first supply voltage; Producing a fourth metallization layer on the first side and above the third metallization layer, wherein the fourth metallization layer has a plurality of fourth metal conductors, each of the plurality of fourth metal conductors extending along the second lateral direction and being configured only as the word conductor; Producing a fifth metallization layer on a second side of the substrate, wherein the fifth metallization layer has a plurality of fifth metal conductors, each of the plurality of fifth metal conductors extending along the first lateral direction and being arranged to carry the first supply voltage or the ground voltage; and Producing a sixth metallization layer on the second side and above the fifth metallization layer, wherein the sixth metallization layer has a plurality of sixth metal conductors, each of the plurality of sixth metal conductors extending along the second lateral direction and being arranged to carry the first supply voltage or the ground voltage. [19] Method according to claim 18, wherein a ratio of a width of each of the plurality of fourth metal conductor tracks along the first lateral direction to a distance between adjacent of the plurality of fourth metal conductor tracks is equal to or greater than 2. [20] Method according to claim 18 or 19, wherein each of the plurality of memory cells comprises a static direct access memory cell.

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