ASYMMETRIC STORAGE STRUCTURES AND METHODS FOR THEIR MANUFACTURING

Abstract

Storage device (100A; 100B; 100C; 100D), comprising: a channel layer (110); a gate structure (154) on a first side of the channel layer (110), wherein the gate structure (154) has a top surface (TS154) facing the channel layer (110); a drain structure (140) on a second side of the channel layer (110) opposite the first side, wherein the drain structure (140) has a first bottom surface (BS140) in contact with the channel layer (110) and the first bottom surface (BS140) overlaps the top surface (TS154) of the gate structure (154) over a first lateral direction (X);and a source structure (142) on the second side of the channel layer (110) and adjacent to the drain structure (140) along the first lateral direction (X), wherein the source structure (142) has a second underside (BS142) facing the channel layer (110), and the second underside (BS142) overlaps the top side (TS154) of the gate structure (154) across the first lateral direction (X); wherein: the drain structure (140) has a first length along a second lateral direction (Y) perpendicular to the first lateral direction (X) in a top view of the storage device (100A; 100B; 100C; 100D); the source structure (142) has a second length along the second lateral direction (Y); and the first length is smaller than the second length.

Description

BACKGROUND The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a wide variety of electronic components (for example, transistors, diodes, resistors, capacitors, etc.). These improvements in integration density largely result from repeated reductions in the smallest possible feature size, allowing more components to be integrated into a given area. From US patent 2016 / 0240683 A1, a storage device with an asymmetric arrangement of gate, drain and source is known, wherein in one embodiment a first gate electrode overlaps in a vertical direction with a source electrode, but not with a drain electrode. US 2017 / 0271381A1, like US 2016 / 0240683A1, refers to transistors with a rear-side gate electrode. US 2023 / 0 223 066 A1 describes a different semiconductor configuration in which the source region and the drain region are integrated into a channel region 112, on the top of which the gate structure is arranged. A similar semiconductor configuration for a light-emitting display, in which the drain region has a shorter length than the source region, is known from EP 1 737 046 B1. US 2017 / 0236842A1 describes transistor devices with semiconductor barrier layers to prevent hydrogen from entering the channel area. With regard to storage devices and structures, a continuous improvement in the alternating current (AC) power of the devices is desirable. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood with reference to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be enlarged or reduced as necessary for the sake of clarity in this discussion. Fig. 1 illustrates a three-dimensional perspective view of an embodiment of a storage device according to some embodiments. Fig. 2 illustrates a cross-sectional view along line AA' of the storage device of Fig. 1 according to some embodiments. Fig. 3 illustrates a cross-sectional view along line BB' of the storage device of Fig. 1 according to some embodiments. Fig. 4 and Fig.Figures 10 and 10 each illustrate a three-dimensional perspective view of a section of the storage device shown as DETAIL A in Figure 1, according to some embodiments. Figure 5 illustrates a circuit diagram of the storage device of Figure 1 according to some embodiments. Figures 6 and 8 each illustrate a cross-sectional view of a section of the storage device shown as DETAIL B in Figure 2, according to some embodiments. Figures 7A and 7B each illustrate a planar top view over an interface of a section of the storage device, as shown in Figure 6, according to some embodiments. Figure 9 illustrates a planar top view over a section of the storage device, as shown in Figure 8, according to some embodiments. Figures 11A and 11B each illustrate a planar top view over an interface of a section of the storage device, as shown in Figure 8.Figure 10 shows, according to some embodiments. Figure 12 illustrates a three-dimensional perspective view of an embodiment of a storage device according to some embodiments. Figure 13 illustrates a cross-sectional view along line CC' of the storage device of Figure 12 according to some embodiments. Figures 14 and 16 each illustrate a cross-sectional view of a section of the storage device shown as DETAIL C in Figure 13 according to some embodiments. Figures 15A, 15B, and 15C each illustrate a planar top view of a section of the storage device as shown in Figure 14 according to some embodiments. Figure 17 illustrates a three-dimensional perspective view of a section of the storage device shown as DETAIL D in Figure 16 according to some embodiments. Figures 18 and 19Figures 20 and 20 each illustrate a three-dimensional perspective view of an embodiment of a storage device according to some embodiments. Figures 19A, 19B, and 19C each illustrate a cross-sectional view along line DD' of the storage device of Figure 18 according to some embodiments. Figures 21A and 21B each illustrate a cross-sectional view along line EE' of the storage device of Figure 20 according to some embodiments. Figure 22 illustrates a three-dimensional perspective view of an embodiment of a storage device according to some embodiments. Figure 23 illustrates a cross-sectional view along line FF' of the storage device of Figure 22 according to some embodiments. Figure 24 is an exemplary flowchart of a method for manufacturing an embodiment of a storage device according to some embodiments. Figures 25, 26, 27, 28, and 29 illustrate the manufacturing process.Figures 30, 31 and 32 illustrate perspective views of the storage device during various manufacturing stages of the method shown in Figure 24 according to some embodiments. DETAILED DESCRIPTION The invention relates to a storage device according to independent claim 1, a storage device according to independent claim 8, and a method for manufacturing a storage cell according to independent claim 14. The dependent claims relate to optional embodiments. The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to limit the scope of the disclosure. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or facilities discussed. Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," "above," "below," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly. This disclosure relates generally to back-end-of-line (BEOL) memory devices and methods for their fabrication. More specifically, this disclosure relates to BEOL memory devices that have asymmetric dimensions in drain and source structures and an overlapping arrangement between the drain and gate structures. Although existing BEOL memory devices have generally been adequate, they have not been entirely satisfactory in all aspects. For example, it remains a challenge to optimize the gate-drain capacitance of each memory cell to achieve reduced stress on the local bitline structures and an improved charge distribution ratio. According to various embodiments of the present disclosure, Fig. 1 illustrates a three-dimensional perspective view of a storage device 100A; Fig. 2 illustrates a cross-sectional view of the storage device 100A along line AA' shown in Fig. 1; Fig. 3 illustrates a cross-sectional view of the storage device 100A along line BB' shown in Fig. 1; Fig. 4 illustrates a three-dimensional perspective view of a section of the storage device 100A shown as DETAIL A in Fig. 1; and Fig. 6 illustrates a cross-sectional view of a section of the storage device 100A shown as DETAIL B in Fig. 2. The storage device 100A comprises several memory cells 104 arranged as a memory array (in the example of Fig. 1).Figure 1 shows, for example, four memory cells 104, extending along both an X-direction (alternatively referred to as a first lateral direction) and a Y-direction (alternatively referred to as a second lateral direction). It is understood that the various perspective and cross-sectional views of the memory device 100A described in this text are simplified, and therefore it is understood that any other structural elements / components may also be included in figures relating to the memory device 100A without exceeding the scope of protection of this disclosure. In an overview, each of the memory cells 104 is arranged above a front face of a base structure 102, which has a semiconductor substrate, and comprises at least one transistor 105 electrically coupled to a capacitor 200. In various embodiments, the transistor 105 comprises a channel layer 110 having a back face facing the base structure 102 and a front face opposite the back face, a pair of a drain structure 140 and a source structure 142 arranged on the front face of the channel layer 110 and spaced apart along the X direction, a gate dielectric layer 152 arranged on the back face of the channel layer 110, and a gate structure 154 (also referred to as a gate electrode 154) arranged on the gate dielectric layer 152.For the purposes of this text, the "back" of the channel layer 110 is located proximal to the base structure 102, and the "front" of the channel layer 110 is located distal to the base structure 102. In this respect, the gate structure 154 is also referred to as a back-facing gate structure 154. The memory cell 104 further comprises a source line via (SVIA) 190, which is configured to electrically couple the source structure 142 to the capacitor 200. For illustrative purposes only, a dimension P1, also referred to as a cell spacing P1, of the memory cell 104, extending along the X-direction between the centerlines of two adjacent drain structures 140, is defined. The memory device 100A comprises several word line structures (WL structures) 155, each of which is electrically coupled, for example by direct contact, to the gate structure 154 of a given memory cell 104. Each WL structure 155 is arranged between the memory cell 104 and the base structure 102 along a Z-direction (alternatively also referred to as a vertical direction). In various embodiments, the WL structure 155 is vertically aligned with the corresponding gate structure 154 along the Z-direction. The memory device 100A further comprises a bit line structure (BL structure) 180, which is electrically coupled to each drain structure 140 of the memory cell 104 via a bit line via (BVIA) structure 178. Fig. 5 illustrates a schematic circuit diagram 10, which represents an embodiment of the storage device 100A. In this respect, the gate structure 154 of each memory cell 104 is electrically coupled to a corresponding WL structure 155 (for example, WL0, WL1, WL2, etc.), the drain structure 140 of each memory cell 104 is electrically coupled to a corresponding BL structure 180 (for example, BL0, BL1, BL2, etc.), and the source structure 142 of each memory cell 104 is electrically coupled to a corresponding capacitor 200 of the same memory cell 104. With further reference to Fig. 1-4, the basic structure 102 comprises the semiconductor substrate (not shown separately) comprising an elemental semiconductor material such as silicon, germanium, diamond, another elemental semiconductor material, a composite semiconductor material such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, other composite semiconductor materials, or combinations thereof. Several active / passive device structure elements, functioning collectively or individually as a logic circuit (for example, transistors, capacitors, resistors, etc.), can be formed in or above a front face of a major surface of the semiconductor substrate. The basic structure 102 can further comprise several interconnect structures (for example, conductive traces, vias, etc.) embedded in one or more dielectric layers (for example, intermetal layers (IMD layers), etch-stop layers (ESLs)), etc., and configured to electrically connect the device structure elements formed in or above the semiconductor substrate to the memory cells 104 shown in Figs. 1-4. In some examples, each dielectric layer in which its corresponding interconnect structures are embedded can be referred to as a metallization layer. Metallization layers formed successively above the semiconductor substrate can be designated—in this order—as M0, M1, M2, etc.The device structure elements formed in or above the main surface of the semiconductor substrate are generally referred to as part of the front-end-of-line (FEOL) networking / processing, and those interconnect structures formed in the dielectric layers are generally referred to as part of the middle-end-of-line (MEOL) networking / processing and the beta-end-of-line (BEOL) networking / processing. In various embodiments, components of the storage device 100A shown in this text are formed within the BEOL networking of the storage device 100A. In some embodiments, the storage device 100A comprises a dielectric layer 103 in which the WL structures 155 are embedded or surrounded by which the WL structures 155 are surrounded, wherein the dielectric layer 103 and the WL structures 155 together form an M5 metallization layer—or the fifth metallization layer—above the semiconductor substrate. The dielectric layer 103 is configured to insulate adjacent WL structures 155 from one another and may contain any suitable dielectric material, such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), one or more dielectric materials with a low dielectric constant (low k-value), such as SiCOH, SiOCN, and / or SiOC, other suitable materials, or combinations thereof.For the purposes of this text, a “low k-value dielectric material” refers to a dielectric material with a dielectric constant of less than approximately 3.9. In some embodiments – with further reference to Figs. 1-4 – the WL structures 155 each extend (in a longitudinal direction) along the Y-direction and are spaced apart along the X-direction above the base structure 102. Each WL structure 155 has a filler layer 155b, which is arranged above or surrounded by a barrier layer 155a. The barrier layer 155a can contain any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), other suitable materials, or combinations thereof.The filler layer 155b can contain any suitable conductive material, such as copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), chromium (Cr), tungsten (W), manganese (Mn), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), aluminum (Al), TaN, TiN, TiAl, polycrystalline silicon (polysilicon), other suitable conductive materials or combinations thereof. The storage device 100A further comprises a dielectric layer 126 in which the gate structures 154 are embedded. The dielectric layer 126 can be similar to or identical with the dielectric layer 103 in structure and composition. The gate structures 154 each extend (in a longitudinal direction) parallel to the corresponding WL structure 155 along the Y-direction and are spaced apart along the X-direction via the base structure 102. In various embodiments, the gate structure 154 comprises several material layers 154a, 154b, 154c, and 154d, which are formed successively over the dielectric layer 126. The material layers 154a, 154b, and 154d can each contain a conductive material, such as TiN, TaN, WN, Cu, Co, Ru, Mo, Cr, W, Mn, Rh, Ir, Ni, Pd, Pt, Ag, Au, Al, polysilicon, other suitable conductive materials, or combinations thereof. In some embodiments, the material layers 154a, 154b, and 154d can differ in their composition. In some embodiments, the material layer 154c contains a hydrogen absorption material designed to capture and remove all hydrogen atoms released through the gate structure 154, thereby protecting the nearby channel layer 110 from unintended chemical degradation.In this respect, the material layer 154c can contain a metallic, conductive oxide such as indium oxide (In₂O₃), aluminum oxide (Al₂O₃), other suitable materials, or combinations thereof. In some embodiments, the gate structure 154 has at least one of the material layers 154a-154d. In some embodiments, one or more of the material layers 154a-154d are omitted from the gate structure 154. The storage device 100A can further comprise an absorption structure 124, which is arranged between two adjacent gate structures 154 along the X-direction and extends longitudinally along the Y-direction. The absorption structure 124 is arranged between the dielectric layer 126 and the dielectric layer 103 along the Z-direction. In some embodiments, the absorption structure 124 comprises several material layers, such as a dielectric layer 124a and an absorption layer 124b, also referred to as a hydrogen absorption layer 124b, above the dielectric layer 124a. As explained in this text, the dielectric layer 124a is in direct contact with the dielectric layer 103 and can be similar or identical in composition to the dielectric layer 103.The absorption layer 124b, on the other hand, is arranged between the dielectric layer 124a and the dielectric layer 126 and can contain a hydrogen absorption material similar in composition to that of the material layer 154c described above. For example, the absorption layer 124b can be configured to protect the channel layer 110 from reaction with hydrogen atoms released from the surrounding components. In this respect, the composition of the absorption layer 124b can be similar to or the same as that of the material layer 154c. In the embodiments shown, each side wall of the gate structure 154 is in direct contact with the absorption structure 124 (i.e., each of its material layers) and the dielectric layer 126. In this respect, the absorption structure 124 and the dielectric layer 126 are arranged between adjacent gate structures 154 along the X-direction. With further reference to Fig. 1-4, the gate dielectric layer 152 can contain any suitable dielectric material, such as silicon dioxide (SiO2), hafnium oxide (HfO2), aluminum oxide (Al2O3), silicon oxynitride (SiON), lanthanum oxide (La2O3), zirconium oxide (ZrO2), titanium oxide (TiO2), manganese oxide (MgO), tantalum oxide-silicon (Ta2O5), other suitable dielectric materials, or combinations thereof. In some embodiments, the gate dielectric layer 152 contains a dielectric material with a high k-value (for example, HfO2, Al2O3, ZrO2, TiO2, MgO, Ta2O5, etc.). For the purposes of this text, a “dielectric material with a high k-value” refers to a dielectric material with a dielectric constant generally greater than about 3.9. In the present embodiments, the gate dielectric layer 152 extends continuously along both the X-direction and the Y-direction over adjacent memory cells 104.In other words, sections of the gate dielectric layer 152 are arranged over both the gate structure 154 and the dielectric layer 126 adjacent to it. As shown in the present text, the channel layer 110 of the memory device 100A extends longitudinally along the X-direction and lies above the gate dielectric layer 152 to define a channel region for each transistor 105 in the memory cell 104. In other words, a section of the channel layer 110 extends over a distance corresponding to the cell spacing P1 within each memory cell 104. In some embodiments, sections of the channel layer 110 are arranged above the dielectric layer 126 between adjacent gate structures 154. The channel layer 110 generally contains one or more metal oxide-based semiconductor materials. In this respect, the channel layer 110 can alternatively be referred to as the semiconductor layer 110. In some embodiments, the channel layer 110 contains an N-type channel material, such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), In₂O₃, tin(IV) oxide (SnO₂), other suitable N-type channel materials, or combinations thereof. In some embodiments, the channel layer 110 comprises a P-type channel layer containing nickel oxide (NiO), copper oxide (Cu₂O), copper aluminum oxide (CuAlO₂), copper gallium oxide (CuGaO₂), copper indium oxide (CuInO₂), strontium copper oxide (SrCu₂O₂), tin(II) oxide (SnO), other suitable P-type channel materials, or combinations thereof.Other metal oxide materials, such as indium tungsten oxide (IWO), indium zinc oxide (IZO), indium tungsten tin oxide (IWZO), indium tin zinc oxide (ITZO), indium tin oxide (ITO), and / or indium gallium oxide (IGO), may also be included in the channel layer 110. In some embodiments, the channel layer 110 containing an N-type channel material makes the transistor 105 an N-type transistor, and the channel layer 110 containing a P-type channel material makes the transistor 105 a P-type transistor. In some embodiments, the oxygen concentration in the channel layer 110 can be adjusted to meet specific design requirements. In the present embodiments, the channel layer 110 is free—or substantially free—of any silicon-containing semiconductor material. With reference to Fig. 2 and Fig. 3, and further to Fig. 6, the storage device 100A comprises an absorption structure 138 arranged above the channel layer 110, and a dielectric layer 148 arranged above the absorption structure 138. In some embodiments, the absorption structure 138, as described above, is similar in structure and composition to or the same as the absorption structure 124, and the dielectric layer 148, as described above, is similar in composition to or the same as the dielectric layer 103. For example, the absorption structure 138 may have a dielectric layer 138a and an absorption layer 138b, wherein the dielectric layer 138a is in direct contact with a front face of the channel layer 110, and the absorption layer 138b is arranged between the dielectric layer 138a and the dielectric layer 148. With further reference to Fig. 1-4, the multiple drain structures 140 and source structures 142 are arranged above the channel layer 110 and are arranged alternately along the X-direction, with each memory cell 104 comprising a pair of drain structures 140 and source structures 142 arranged side by side. The drain structures 140 and source structures 142 are embedded in or surrounded by the dielectric layer 148 and the absorption structure 138, which form electrical insulation between them. In this respect, one side wall of each of the drain structures 140 and source structures 142 is in direct contact with the absorption structure 138 (i.e., each of its material layers) and the dielectric layer 148. In the embodiments shown, the gate structure 154 of each memory cell 104 extends between two adjacent drain structures 140 along the X-direction and fully engages a bottom surface BS142 of the source structure 142 located between them. In other words, two adjacent drain structures 140 are arranged on each side of the gate structure 154. In the present disclosure, the source structure 142 can alternatively be referred to as a source metal electrode 142, and the drain structure 140 can alternatively be referred to as a drain metal electrode 140. In the present embodiments, the drain structure 140 and the source structure 142 have the same structure and composition and can comprise several material layers. For example, with further reference to Fig. 1-3, each of the drain structure 140 and the source structure 142 comprises an absorption layer 130, a metal layer 132 arranged above the absorption layer 130, and a metal layer 134 arranged above the metal layer 132. In some embodiments, the absorption layer 130 has a similar or identical composition to the material layer 154c. For example, the absorption layer 130 may contain a metallic conductive oxide such as indium oxide (In₂O₃), aluminum oxide (Al₂O₃), other suitable materials, or combinations thereof. In some embodiments, the absorption layer 130 is omitted from the drain structure 140 and the source structure 142. In some embodiments, metal layer 132 and metal layer 134 each contain a conductive material, such as tungsten (W), aluminum (Al), polysilicon (Ru), cobalt (Co), copper (Cu), molybdenum (Mo), nitrocellulose (Nb), tanenium (TaN), titanium nitride (TiN), other suitable conductive materials, or combinations thereof. In some embodiments, metal layer 132 and metal layer 134 differ in their composition. In some embodiments, metal layer 134 contains a conductive material that has a lower contact resistance than metal layer 132. For example, in the embodiments shown, metal layer 132 contains titanium nitride (TiN), and metal layer 134 contains tungsten (W). In some cases, metal layer 132 can be considered a barrier layer, which may be similar or identical in composition to barrier layer 155a, and metal layer 134 can be considered a filler layer, which may be similar or identical in composition to filler layer 155b. With further reference to Figs. 1-4, the BVIA structures 178 and the BL structures 180 are embedded in or surrounded by a dielectric layer 176, while the SVIA structures 190 are embedded in or surrounded by a dielectric layer 188. The dielectric layer 176 is arranged above the dielectric layer 148 and may be similar or identical in composition to the dielectric layer 103. The dielectric layer 188 is arranged above the dielectric layer 176 and may also be similar or identical in composition to the dielectric layer 103. The BL structure 180 extends longitudinally along the X-direction and is electrically coupled to each of the drain structures 140 by a corresponding BVIA structure 178 extending vertically along the Z-direction. In some embodiments, a bottom surface of the BVIA structure 178 is in direct contact with at least a section of a top surface of the drain structure 140. For example, the bottom surface of the BVIA structure 178 is in direct contact with the metal layer 132 and the metal layer 134 of the drain structure 140. In some embodiments, a top surface of the BVIA structure 178 extends into or is embedded within the BL structure 180. Each of the SVIA structures 190 extends vertically along the Z-direction and electrically couples each of the source structures 142 to a corresponding capacitor 200. In some embodiments, a bottom surface of the SVIA structure 190 is in direct contact with at least one section of a top surface of the source structure 142. For example, the bottom surface of the SVIA structure 190 is in direct contact with the metal layer 132 and the metal layer 134 of the source structure 142. Furthermore, a top surface of the SVIA structure 190 is in direct contact with a bottom surface of the capacitor 200. The BVIA structure 178, the BL structure 180, and the SVIA structure 190 can have similar or identical compositions. In some embodiments, the BVIA structure 178, the BL structure 180, and the SVIA structure 190 each have multiple material layers. For example, the BVIA structure 178, the BL structure 180, and the SVIA structure 190 can each have the metal layer 132 over their corresponding dielectric layers (for example, the dielectric layer 176 or the dielectric layer 188) and the metal layer 134 over the metal layer 132. With further reference to Figs. 1-4, the capacitor 200 is embedded in or surrounded by a dielectric structure 192, which comprises an absorption layer 194, a dielectric layer 196 above the absorption layer 194, and a dielectric layer 198 above the dielectric layer 196. In some embodiments, the absorption layer 194 is similar in composition to or identical with the absorption layer 124b, and the dielectric layers 196 and 198 differ in composition. The dielectric layers 196 and 198 may each contain a suitable dielectric material, such as SiO₂, Si₃N₄, SiON, Al₂O₃, a dielectric material with a low k-value (for example, SiCOH, SiOCN, SiOC, etc.), other suitable materials, or combinations thereof. The dielectric structure 192 may have fewer, more, or different layers than those described herein. In various embodiments, the capacitor 200 generally has a metal-insulator-metal (MIM) structure, comprising an insulating or dielectric layer sandwiched between two conductive layers or plates. The memory cell 104, which includes the transistor 105 electrically coupled to the capacitor 200, can generally be described as having a 1-transistor-1-capacitor or 1T1C structure.Depending on the types of materials used in the capacitor 200, the memory cell 104 can be configured as a dynamic random-access memory cell (DRAM cell), a magnetoresistive random-access memory cell (MRAM cell) (also referred to as a magnetic tunnel junction cell or MTJ cell), a resistive random-access memory cell (ReRAM cell), a ferroelectric random-access memory cell (FeRAM cell), the like, or other suitable types of memory cells that have been developed in the past, are currently being developed, or will be developed in the future. In the embodiments shown, the memory cell 104 can be configured as a DRAM cell. In the embodiments shown, for example, each capacitor 200 comprises a lower plate 202 (also referred to as a lower metal layer 202), a capacitor dielectric layer 204 over the lower plate 202, and an upper plate 206 (also referred to as an upper metal layer 206) over the capacitor dielectric layer 204. Each of the lower plate 202 and the upper plate 204 can contain a conductive material, such as iron (Fe), tungsten (W), copper (Cu), cobalt (Co), rubric (Ru), aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), platinum (Pt), other suitable conductive materials, or combinations (or alloys) thereof, and the capacitor dielectric layer 204 can contain a suitable dielectric material, such as a dielectric material with a high k-value (for example, HfO2, Al2O3, ZrO2, TiO2, MgO, Ta2O5, etc.), other suitable dielectric materials, or combinations thereof. For storage devices with a 1T1C structure, such as the 100A storage device, it is generally desirable to improve the device's AC performance. This can include, for example, reducing the stress on local BL structures, improving the charge distribution ratio, and improving storage latency, which affects component read speed. In many cases, achieving these design goals has presented several challenges. One such challenge is that a transistor with a large capacitance (i.e., gate-drain capacitance or Cgd) between a drain structure and a gate structure of the transistor can lead to a longer latency and an increase in the overall capacitance Cselectorde of the 105 transistor (or selector), resulting in a greater stress on the local BL structures (i.e., a large BL capacitance or CBL).Various sources of capacitance are indicated, for example, in Fig. 2. The increased load on the local BL structures can subsequently reduce the charge distribution ratio of the storage device, leading to limited flexibility in the memory circuit design. Although existing memory circuit designs have addressed this challenge to varying degrees, they have not been entirely satisfactory in all aspects. In existing 1T1C memory devices, the source and drain structures of a given memory cell are generally arranged to have the same or substantially the same dimensions (that is, the same or substantially the same footprint) along the X and Y directions, thus positioning the drain and source structures symmetrically around a gate structure of the memory cell. Furthermore, each pair of adjacent drain structures is positioned relative to each gate structure in an overlapping manner, with an edge of a bottom surface of the drain structure and a nearby edge of a top surface of the gate structure overlapping along the X direction. In other words, an overlapping region between the drain structure and the gate structure is positive (that is, greater than zero), with the overlapping region extending along both the X and Y directions.These facilities generally allow less capability and / or flexibility for the design and manufacture of storage devices with reduced Cgd, reduced BL loading and / or improved charge distribution ratio. The present disclosure provides various features of the transistor component of 1T1C storage devices for reducing Cgd, reducing BL load, and improving the charge distribution ratio. Furthermore, these features can be fine-tuned to improve one or both of the AC and DC power (for example, the write-back current Iwb) of the storage devices. In some embodiments of the present disclosure, the tuning of the features of one or more transistor components to reduce Cgd and, consequently, BL load, includes adjusting a region of the drain structure facing the gate structure, a separation distance between the drain structure and the gate structure, or both.In some embodiments, adjusting one or both of the area of ​​the drain structure facing the gate structure and the separation distance between the drain structure and the gate structure effectively changes an overlap area between the drain structure and the gate structure. More precisely, in some examples, adjusting the area of ​​the drain structure facing the gate structure may involve adjusting a dimension of the drain structure along the X-direction relative to the source structure. Alternatively or additionally, adjusting the area of ​​the drain structure facing the gate structure may involve adjusting a dimension of the drain structure along the Y-direction relative to the source structure. In this respect, adjusting one or both dimensions of the drain structure relative to the source structure reduces the overlap area between the drain and gate structures and results in an asymmetrical setup in the transistor component.In some examples, adjusting the separation distance between the drain structure and the gate structure involves reducing the overlap distance between the drain structure and the gate structure, and consequently also the overlap area between the two, causing the drain structure and the gate structure to either underlap or not overlap. "Underlapping" or "non-overlapping" between two surfaces, as described herein, can refer to the fact that the two surfaces are separated by a distance along a lateral direction, or alternatively, have edges that are vertically aligned or coincident with each other. In this respect, an underlapping or non-overlapping arrangement corresponds to a separation distance greater than or equal to zero, while an overlapping arrangement corresponds to a separation distance less than zero. In various embodiments, an underlapping arrangement between the gate structure and the drain structure improves the AC performance of the storage device by reducing Cgd.In addition or alternatively to implementing an underlap between the drain structure and the gate structure, reducing the dimensions of the drain structure relative to those of the source structure along the X-direction reduces the resistance of the source structure and improves parameters such as the write-back current Iwb, resulting in improved DC performance of the storage device. Several non-restrictive exemplary facilities that illustrate these design concepts are described in detail below. In some embodiments – with reference to Figs. 1-4, 6, 7A, 7B – the drain structures 140 are each configured with a first width W1 along the X-direction and a first length L1 along the Y-direction, and the source structures 142 are each configured with a second width W2 along the X-direction and a second length L2 along the Y-direction, wherein the first width W1 is smaller than the second width W2 and the first length L1 is equal to or substantially equal to the second length L2. Thus, the drain structure 140 and the source structure 142 have asymmetric dimensions along the X-direction. Furthermore, a first area A1 of a bottom surface BS140 of the drain structure 140, which faces the channel layer 110, is smaller than a second area A2 of a bottom surface BS142 of the source structure 142, each of the first area A1 and the second area A2 extending along the X-direction and the Y-direction.In some cases, the drain structure 140, which has an elongated dimension similar to that of the source structure 142, can be referred to as a slot-type drain structure 140. Fig. 7A illustrates an exemplary top view of transistor 105 along an interface between the drain structure 140 (and the source structure 142) and the channel layer 110, with the gate structure 154 located below the plane of view. The first region A1 is then defined by a product of the first width W1 and the first length L1, and the second region A2 is similarly defined by a product of the second width W2 and the second length L2, which is larger than that of the first region A1.Accordingly, and in contrast to existing device designs where the first area A1 and the second area A2 are arranged to be identical (i.e., the drain structure and the source structure have symmetrical dimensions), reducing the first area A1 relative to the second area A2 effectively reduces the Cgd between the drain structure 140 and the gate structure 154, thereby reducing at least the BL load of the storage device 100A (for example, reducing the CBL of the BL structure 180). In some embodiments – with further reference to Fig. 7A – the underside BS140 of the drain structure 140 is separated or laterally offset from a topside TS154 of the gate structure 154 by an overlap region 144 (defined in the channel layer 110), which has a first distance D1 and is arranged symmetrically around the source structure 142 along the X-direction. In this respect, an edge 144a of the underside BS140 is separated from an edge 144b of the topside TS154 by the first distance D1 such that the two surfaces do not overlap but overlap, and an overlap area B1 of the overlap region 144 can be defined, for example, by a product of the first distance D1 and the first length L1. The underlap of the bottom BS140 and the top TS154 effectively increases a separation distance between the drain structure 140 and the gate structure 154, thereby reducing the Cgdder memory cell 104. In some embodiments, the first distance D1, also referred to as an overlap distance D1, is greater than 0 and less than approximately 4% of the cell spacing P1 defined herein. If the first distance D1 is too large, for example, greater than approximately 4% of the cell spacing P1, the gate control of the drain structure 140 may be impaired, thereby degrading the performance of the storage device 100A. Conversely, if the first distance D1 is too small, for example, less than 0, the effect of reducing Cgd may not be significant enough to lead to a reduced load on the BL structure 180 and, consequently, to an improved charge distribution ratio. In some embodiments—referring to Fig. 7B—the edge 144a of the bottom surface BS140 is vertically aligned with the edge 144b of the top surface TS154 such that the two surfaces do not overlap but underlap. In other words, the edge 144a and the edge 144b coincide. In the embodiment shown, the vertical alignment between the drain structure 140 and the gate structure 154 is symmetrical about the source structure 142 along the X-direction. In contrast to the embodiment shown in Fig. 7A, the vertical alignment of the bottom surface BS140 and the top surface TS154 has an underlap area that is essentially zero. In some non-restrictive examples, by configuring the drain structure 140 and the source structure 142 to have asymmetrical dimensions and by forming the underlap region 144 (defined by the first distance D1), the BL load can be reduced by approximately 10% to approximately 18%. Additionally, with reference to both Fig. 7A and 7B, the reduction of the first width W1 relative to the second width W2 can be fine-tuned to reduce the overall cell spacing P1 of the memory cell 104 and thereby improve the density of the memory cells 104 in the storage device 100A. In this respect, the first width W1 can be adjusted so that the cell spacing P1 shown in Fig. 7A can be reduced compared to that of a memory cell having symmetrical dimensions between the drain structure 140 and the source structure 142.In some examples, by vertically aligning border 144a and border 144b, a cell spacing P2 can be obtained which is smaller than the cell spacing P1 by a distance equal to twice the first distance D1. Figures 8 and 9 together illustrate an embodiment of the storage device 100A, similar to that shown in Figures 6-7B, wherein Figure 8 illustrates a cross-sectional view of a section of the storage device 100A shown as DETAIL B in Figure 2, and Figure 9 illustrates an exemplary top view of the transistor 105 along an interface between the drain structure 140 and the channel layer 110. As shown here, the drain structures 140 are each configured with a third width W3 and a first length L1, and the source structures 142 are each configured with a second length L2 and a fourth width W4, which differs from the third width W3. However, unlike the embodiment of Figure 8, the transistor 105 is configured with a third width W3 and a first length L1.6-7B - the third width W3 is larger than the fourth width W4, while the first length L1 and the second length L2 are essentially the same, as described above, resulting in asymmetric dimensions for the drain structure 140 and the source structure 142 along the X-direction. In this respect, a third region A3 of the bottom BS140 is larger than a fourth region A4 of a bottom BS142. Fig. 9 illustrates an exemplary top view of transistor 105 analogous to the representation in Fig. 7A and Fig. 7B. The third region A3 is then defined by a product of the third width W3 and the first length L1, and the fourth region A4 is similarly defined by a product of the fourth width W4 and the second length L2, which is smaller than the third region A3. Accordingly, unlike existing device designs where the third region A3 and the fourth region A4 are arranged to be equal, reducing the fourth region A4 relative to the third region A3 effectively reduces the source-gate capacitance, or Cgs, between the source structure 142 and the gate structure 154. A reduced Cgs can contribute to an improvement in other aspects of AC performance, such as a reduction in the stress on the WL structures 155. In some embodiments—with further reference to Fig. 9—the bottom surface BS140 of the drain structure 140 overlaps the top surface TS154 by an overlap region 146 (as shown located within the drain structure 140) which has a second distance D2, also referred to as an overlap distance D2, along the X-direction. In the embodiment shown, the overlap region 146 is arranged symmetrically around the source structure 142 along the X-direction. In this respect, an edge 146a of the bottom surface BS140 overlaps an edge 146b of the top surface TS154 by the second distance D2, resulting in the overlap region 146 having an overlap area C1, which is defined, for example, by a product of the second distance D2 and the first length L1. Thus, no overlapping arrangement is implemented between the drain structure 140 and the gate structure 154. Referring to embodiments of the storage device 100A shown in Fig. 10, Fig. 11A, and Fig. 11B, the drain structure 140 is configured with a third length L3, and the source structure 142 is configured with a second length L2 that is greater than the third length L3, resulting in asymmetric dimensions for the drain structure 140 and the source structure 142 along the Y-direction. In this respect, a fifth region A5 of the bottom surface BS140 is smaller than a sixth region A6 of a bottom surface BS142. In some non-restrictive examples, the first width W1 of the drain structure 140 may be the same as, or substantially the same as, the second width W2 of the source structure 142. In some cases, the drain structure 140, with a dimension shortened relative to the source structure 142, may be described as a via-plated drain structure 140. In some embodiments, shortening the drain structures 140 can cause the BL structure 180 to overlap the row of SVIA structures 190, which are electrically coupled to their corresponding source structures and arranged along the X-direction. Consequently, the positions of the BL structure and the nearby row of SVIAs 190 can be shifted along the Y-direction to avoid this overlap. In one such example—referring to Fig. 10—the BL structure 180 is positioned behind the row of SVIAs 190 to compensate for the shortening of the drain structures 140. In contrast, in Fig. 4, the BL structure 180 is positioned in front of the row of SVIAs 190. Figures 11A and 11B each illustrate an exemplary top view of transistor 105 analogous to the representation in Figures 7A and 7B, respectively. The fifth region A5 is then defined by a product of the first width W1 and the third length L3, and the sixth region A6 is similarly defined by a product of the second width W2 and the second length L2, which is larger than the fifth region A5. Accordingly, in contrast to existing device designs where the fifth region A5 and the sixth region A6 are arranged to be equal, reducing the fifth region A5 relative to the sixth region A6 effectively reduces the Cgd between the drain structure 140 and the gate structure 154, which in turn reduces at least the BL load of the storage device 100A. In some embodiments – with reference to Fig. 11A – the underside BS140 of the drain structure 140 is separated or laterally offset from a topside TS154 of the gate structure 154 by an overlap region 147 (defined in the channel layer 110) which has the first distance D1 along the X-direction. In this respect, an edge 147a of the underside BS140 is separated from an edge 147b of the topside TS154 by the first distance D1 such that the two surfaces do not overlap but overlap, and an overlap area B2 of the overlap region 144 can be defined, for example, by a product of the first distance D1 and the third length L3. In some embodiments – with reference to Fig. 11B – the edge 147a of the bottom surface BS140 is vertically aligned with the edge 147b of the top surface TS154 such that the two surfaces do not overlap but underlap. In other words, the edge 147a and the edge 147b coincide. Similar to the difference between the representations in Fig. 7A and Fig. 7B, the vertical alignment of the bottom surface BS140 and the top surface TS154 has an underlap area that is essentially zero. In some non-restrictive examples, reducing the third length L3 to approximately 50% of the fourth length L4 reduces the Cgdder of the memory cell 104, which can lead to a reduction in Cselectorum of approximately 43%, a reduction in BL load of approximately 25%, and an improvement in the charge distribution ratio of approximately 17%. However, it should be noted that if the third length L3 is too short along the Y-direction (that is, if the difference between the third length L3 and the second length L2 is too large), for example, greater than approximately 50%, the resistance of the drain structure 140 can be excessively increased, which can subsequently impair the DC performance of the 100A storage device. Furthermore, an excessive reduction of the third length L3 relative to the second length L2 can lead to poorer gate control of the drain structure 140, which can also impair the performance of the 100A storage device. According to various embodiments of the present disclosure, Fig. 12 illustrates a three-dimensional perspective view of a storage device 100B, which is similar to, but not identical with, the storage device 100A; Fig. 13 illustrates a cross-sectional view of the storage device 100B along line CC' shown in Fig. 12; and Fig. 14 illustrates a cross-sectional view of a section of the storage device 100B shown as DETAIL C in Fig. 13. Similar to the storage device 100A, the storage device 100B has several memory cells 106 arranged as a memory array (for example, six memory cells 106 are shown in the example of Fig. 12) extending in both an X-direction and a Y-direction.It is understood that the various perspective and cross-sectional views of the storage device 100B described in this text are simplified, and therefore it is understood that any other structural elements / components may also be included in figures relating to the storage device 100B without exceeding the scope of protection of this disclosure. Each storage cell 106 comprises components that are essentially similar to or identical with those of the storage cell 104 described above. Therefore, these components will be designated below with the same numbers as the components of the storage cell 104, and their descriptions will not be repeated for the sake of brevity. Similar to memory cell 104, memory cell 106 includes at least transistor 105, which is electrically coupled to capacitor 200. Transistor 105 comprises channel layer 110 and the drain structure 140 and source structure 142 pair, located on the front side of channel layer 110, and a gate dielectric layer 152 located on the back side of channel layer 110. Transistor 105 further comprises gate structure 154 on the back side of channel layer 110 and gate dielectric layer 152, located between gate structure 154 and channel layer 110. Memory cell 106 also includes SVIA 190, which is configured to electrically couple source structure 142 to capacitor 200.The storage device 100B further comprises several WL structures 155, each electrically coupled to the gate structure 154 of each memory cell 106, and the BL structure 180, which is electrically coupled to each drain structure 140 of the memory cell 106 via the BVIA structure 178. However, in contrast to memory cell 104, the drain structure 140 of each memory cell 106 is shared with an adjacent memory cell 106, such that the cell spacing P3 of memory cell 106 is smaller than the cell spacing P1 of memory cell 104, as shown at least in Fig. 2. In some embodiments, the cell spacing P1 is 1.5 times the cell spacing P3, which increases the device density for memory device 100B compared to memory device 100A. Furthermore, the arrangement of the drain structures 140 and the source structures 142 in memory cell 106 also reduces the dimension of each corresponding gate structure 154 along the X-direction.Furthermore, the channel layer 110 of the memory device 100B extends only between two adjacent source structures 142 along the X direction and thus covers only a section of the gate dielectric layer 152, which connects the gate structures 154 across two adjacent and symmetrical memory cells 106. Referring to Figures 12-14, the drain structures 140 are each configured with a fifth width W5 along the X-direction, and the source structures 142 are each configured with a sixth width W6 along the X-direction, which is essentially the same as the fifth width W5. Although not shown here, the drain structures 140 and the source structures 142 are configured with the same length along the Y-direction. In this respect, a region of the bottom surface BS140 of the drain structure 140, facing the channel layer 110, is approximately the same as a region of the bottom surface BS142 of the source structure 142, thus giving the drain structure 140 and the source structure 142 symmetrical dimensions along the X-direction and the Y-direction, respectively. Analogous to the embodiments shown in Figs. 2-4, 6, and 7A with respect to the memory device 100A, Fig. 15A illustrates an exemplary top view of the transistor 105 along an interface between the drain structure 140 (and the source structure 142) and the channel layer 110 of the section of the memory device 100B shown as DETAIL C in Fig. 13. The bottom surface BS140 of the drain structure 140 is separated or laterally offset from a top surface TS154 of the gate structure 154 by an overlap region 149 (defined in the channel layer 110), which has a third distance D3 and is arranged symmetrically around the drain structure 140 along the X-direction.In this respect, an edge 149a of the bottom BS140 is separated from an edge 149b of the top TS154 by the third distance D3 such that the two surfaces do not overlap, but underlap, and an underlap area B3 of the underlap region 149 can be defined, for example, by a product of the third distance D3 and a length of the drain structure 140 (or the source structure 142). In some embodiments—referring to Fig. 15B, which is analogous to the embodiments shown in Figs. 2-4, 6, and 7B with respect to the storage device 100A—the rim 149a is vertically aligned with the rim 149b such that the two surfaces do not overlap but underlap. In other words, the rim 149a and the rim 149b coincide. In the embodiment shown, such a vertical alignment is present on both sides and symmetrically around the drain structure 140 along the X-direction. In contrast to the embodiment shown in Fig. 15A, the vertical alignment of the bottom surface BS140 and the top surface TS154 has an underlap area that is essentially zero. In some embodiments—referring to Fig.15C - the underlap region 149 is arranged asymmetrically around the drain structure 140 such that it is only present on a first side of the drain structure 140, wherein the drain structure 140 and the gate structure 154 have vertically oriented edges on a second side of the drain structure 140 opposite the first side. Accordingly, and with common reference to Fig. 15A-15C, for the memory cell 106, which has the drain structure 140 and the source structure 142 with symmetrical dimensions, the underlap of the bottom BS140 and the top TS154 on one or both sides of the drain structure 140 effectively increases the separation distance between the drain structure 140 and the gate structure 154, thereby reducing the Cgd between the drain structure 140 and the gate structure 154 and resulting in an improvement at least in the BL load of the memory device 100B. In some embodiments—referring to Fig. 14—the distance S between two gate structures 154 (their top surfaces TS154) of two adjacent memory cells 106 is extended along the X-direction to increase the separation distance between each of the gate structures 154 and its corresponding drain structure 140. This adjustment can be implemented in addition to the underlap between the bottom surface BS140 and the top surface TS154, as shown in Figs. 15A-15C. In some non-restrictive examples, the distance S along the X-direction can be increased from about 13 nm to about 30 nm. Fig. 16 illustrates a cross-sectional view of the section of the storage device 100B shown as DETAIL C in Fig. 13, and Fig. 17 illustrates a three-dimensional perspective view of a section of the storage device 100B shown as DETAIL D in Fig. 16. In some embodiments, Figs. 16 and 17 show an embodiment of the storage device 100B similar to that shown in Figs. 12-15C. For example, the drain structures 140 are each configured with the fifth width W5 along the X-direction, and the source structures 142 are each configured with the sixth width W6 along the X-direction, which is essentially the same as the fifth width W5. However, unlike the one shown in Fig.In the embodiment shown in Figure 12-15C, the drain structure 140 is configured with a fifth length L5, and the source structure 142 is configured with a sixth length L6 that is larger than the fifth length L5, resulting in asymmetric dimensions for the drain structure 140 and the source structure 142 along the Y-direction. In this respect, a seventh region A7 of the bottom surface BS140 is smaller than an eighth region A8 of a bottom surface BS142. Accordingly, unlike existing device designs where the seventh region A7 and the eighth region A8 are configured to be equal, reducing the seventh region A7 relative to the eighth region A8 effectively reduces the Cgd between the drain structure 140 and the gate structure 154, thereby improving at least the BL load of the storage device 100B. According to various embodiments of the present disclosure, Fig. 18 illustrates a three-dimensional perspective view of a storage device 100C, which is similar to, but not identical with, the storage device 100B, and Figs. 19A, 19B, and 19C each illustrate a cross-sectional view of the storage device 100C along the line EE' shown in Fig. 18. Similar to the storage device 100B, the storage device 100C has several memory cells 108 arranged as a memory array (for example, two memory cells 108 are shown in the example in Fig. 18).It is understood that the various perspective and cross-sectional views of the storage device 100C described in this text are simplified, and therefore it is understood that any other structural elements / components may also be included in figures relating to the storage device 100C without departing from the scope of protection of this disclosure. For example, while only two adjacent transistors 105 of the memory cell 108 are illustrated in Figs. 18-19C, the memory cell 108 also includes additional components not shown, such as a capacitor electrically coupled to the transistor. Each memory cell 108 comprises components that are essentially similar to or identical with those of the memory cell 106 described above. For example, the drain structure 140 is shared between two adjacent memory cells 108 along the X-direction, effectively reducing the cell spacing of the memory cell 108 (for example, compared to the cell spacing P1 of the memory cell 104) and consequently improving the device density. Furthermore, the arrangement of the drain structures 140 and the source structures 142 in the memory cell 108 also reduces a dimension of each corresponding gate structure 154 along the X-direction. However, unlike in memory cell 106, each source structure 142 is positioned next to the SW of the gate structure 154 such that a substantial portion of the bottom surface BS142 of the source structure 142 is offset laterally from the top surface TS154 of the gate structure 154 along the X-direction. In contrast - with reference to Fig.14 - for example, one of the side walls of the source structure 142 is aligned or substantially aligned with the SW of the gate structure 154, and the top surface TS154 overlaps the entire bottom surface BS142. Structural elements labeled "D", "G", and "S" are schematic projections of the drain structure 140, the gate structure 154, and the source structure 142, respectively, to illustrate the relative positions of these components along the X-direction. In some embodiments—referring to Fig. 19A—the top surface TS154 underlaps each of the bottom surface BS140 of the drain structure 140 and the bottom surface BS142 in the memory cell 108. In some embodiments—referring to Fig. 19B—the top surface TS154 underlaps the bottom surface BS140 and overlaps the bottom surface BS142, with an overlap region being defined by a fourth distance D4. In some non-restrictive examples, the fourth distance D4, also referred to as the overlap distance D4, may be greater than 0 and less than or equal to approximately 2 nm. In some embodiments—referring to Fig. 19C—the top surface TS154 overlaps each of the bottom surface BS140 and the bottom surface BS142, with each overlap region being defined by the fourth distance D4. In the embodiments shown in Figs. 19A-19C, “lower flap” between two surfaces refers to the fact that the two surfaces are separated by a distance (for example, the fourth distance D4), similar to the embodiments shown in Figs. 15A and 15C, or alternatively, that they have edges that are vertically aligned or coincident with each other, as shown in Figs. 19A and 19B, and similar to the embodiment shown in Fig. 15B. In various embodiments of the present disclosure, an underlap between the gate structure 154 and the drain structure 140 improves the AC performance of the storage device 100A / 100B / 100C by reducing Cgd, as described in the present text, while an overlap between the gate structure 154 and the source structure 142 allows or maintains adequate DC performance (for example, a sufficient inrush current Ion) of the storage device 100A / 100B / 100C. In some embodiments – with common reference to Figs. 18-19C – the drain structure 140 and the source structure 142 have the same dimension along the Y-direction: a seventh length L7. However, in some embodiments – with common reference to Figs. 20, 21A, and 21B – the drain structure 40 has a dimension, an eighth length L8, which is shorter than the seventh length L7 of the source structure 142. In this respect, a region of the bottom surface BS140 is smaller than a region of the bottom surface BS142, thereby effectively reducing Cgd between the drain structure 140 and the gate structure 154, which in turn reduces at least the BL load of the storage device 100C. According to various embodiments of the present disclosure, Fig. 20 illustrates a three-dimensional perspective view of the storage device 100C, and Figs. 21A and 21B each illustrate a cross-sectional view of a section of the storage device 100C along the line EE' shown in Fig. 20. Similar to Figs. 19A-19C, structural elements designated “D”, “G”, and “S” are schematic projections of the drain structure 140, the gate structure 154, and the source structure 142, respectively, to illustrate the relative positions of these components along the X-direction. In some embodiments—with reference to Fig. 21A—the top TS154 underlaps the bottom BS140 and overlaps the bottom BS142, an overlap region being defined by a fifth distance D5, also referred to as an overlap distance D5.As described above, the overlap distance D5 can be greater than 0 and less than or equal to approximately 2 nm in some non-restrictive examples. In some embodiments—referring to Fig. 21B—the top surface TS154 overlaps each of the bottom surface BS140 and the bottom surface BS142, with each overlap region being defined by the fifth distance D5. Due to the reduced area of ​​the bottom surface BS140, the overlap between the gate structure 154 and the source structure 142 maintains or improves the DC performance of the storage device 100C. According to various embodiments of the present disclosure, Fig. 22 illustrates a three-dimensional perspective view of a storage device 100D, and Fig. 23 illustrates a cross-sectional view of the storage device 100D along the line FF' shown in Fig. 22. More precisely, each of Fig. 22 and Fig. 23 shows a storage cell 109 of the storage device 100D. In contrast to the embodiments of storage cells 104, 106, and 108, the drain structure 140 and the source structure 142 of the storage cell 109 are arranged along the Z-direction and separated by the gate structure 154, which has a tubular shape extending longitudinally along the Z-direction.The storage device 100D comprises a dielectric layer 220, which is arranged within and completely surrounded by the gate structure 154, wherein the dielectric layer 220 may be similar or identical in composition to the dielectric layer 103. The storage cell 109 also comprises the channel layer 110 and the gate dielectric layer 152 above the channel layer 110, wherein the channel layer 110 and the gate dielectric layer 152 are arranged between the gate structure 154 and the dielectric layer 220. In this respect, by orienting the channel layer 110 and the gate structure 154 so that they extend along the Z-direction, and the drain structure 140 so that it extends along the X-direction, the separation distance between the drain structure 140 and the gate structure 154 is increased, leading to a reduction of Cgd, as described in detail above. Figure 24 illustrates a flowchart of a method 300 for forming a storage device according to various aspects of the present disclosure. For example, at least some of the operations (or steps) of method 300 can be performed to fabricate, manufacture, or otherwise form a storage device (for example, one of the storage devices 100A, 100B, or 100C, etc.). Method 300 is merely an example and is not intended to limit the present disclosure. Accordingly, it is understood that additional operations may be performed before, during, and after the method 300 of Figure 24, and that some other operations may only be briefly described in this text. The operations of method 300 are described below in the context of forming an embodiment of the storage device 100A, which is shown in one or more of Figures 1-11B for illustrative purposes only. It is understood, however, that the operations of method 300 can also be used to form embodiments of the storage device 100B or 100C, as described in this text. In various embodiments, the operations of method 300 are linked to three-dimensional perspective views of a section of the storage device 100A at different manufacturing stages, as shown in Figures 25, 26, 27, 28, 29, 30, 31, and 32. Referring to Figures 24 and 25, the dielectric layer 103 is formed over the base structure 102 in step 302. In the present embodiments, the dielectric layer 103 is formed as an area-covering layer over the entire base structure 102 and thus extends along both the X and Y directions. In some embodiments, the base structure 102 can be provided or formed by performing a series of IC fabrication operations, such as lithography, etching, deposition, etc., resulting in various FEOL, MEOL, and BEOL network / processing components over and / or within the front face of the main area of ​​the semiconductor substrate described herein. In the present embodiments, the dielectric layer 103 is formed as part of the BEOL network / processing components, such as the dielectric layer for the M5 metallization layer.The dielectric layer 103 can be formed over the base structure by any suitable deposition method, such as chemical vapor deposition (CVD), flowable CVD (FCVD), spin coating, other suitable methods, or combinations thereof. With further reference to Figs. 24 and 25, the multiple WL structures 155 are formed in the dielectric layer 103 in operation 304. In the present embodiments, the WL structures 155 are formed in the dielectric layer 103 by first performing a structuring process to form trenches (not shown) in the dielectric layer 103, the trenches extending longitudinally along the Y-direction and separated from each other along the X-direction. In some embodiments, the WL structures 155 are each embedded in and surrounded by the dielectric layer 103. In some embodiments, the WL structures 155 do not extend through the dielectric layer 103. In some embodiments, the structuring process comprises depositing a masking layer (for example, a photoresist) over the dielectric layer 103, structuring the masking layer using a suitable lithographic process (for example, photolithography, electron beam lithography, or another suitable lithographic process) to form a structured masking layer, and subsequently performing a series of etching processes to transfer the structure on the structured masking layer to the dielectric layer, thereby forming the grooves. The etching process may include a plasma etching process, which may possess some degree of anisotropic property, a wet etching process, a reactive ion etching (RIE) process, other suitable processes, or combinations thereof.In other embodiments, a hard mask can first be structured using the masking layer, and the structure can then be transferred to the dielectric layer 103. After the trenches have been formed, the structured masking layer is removed by a suitable method, such as plasma ashing or resist peeling. The barrier layer 155a is then conformally deposited in the trenches, and the filler layer 155b is subsequently deposited over the barrier layer 155a to fill the trenches. The barrier layer 155a and the filler layer 155b are each deposited by any suitable deposition process, such as CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), plating (e.g., electroplating, electroless plating, etc.), other suitable methods, or combinations thereof. Following this, the barrier layer 155a and the filler layer 155b are planarized, for example, by a chemical-mechanical planarization / polishing (CMP) process, resulting in a substantially planar surface over the top surfaces of the dielectric layer 103 and the WL structures 155. Referring to Figures 24 and 26, the absorption structure 124 and the dielectric layer 126 are formed over the WL structures 155 in operation 306. The material layers of the absorption structure 124, including the dielectric layer 124a and the absorption layer 124b, are deposited successively as planar layers by any suitable deposition process, such as CVD, ALD, PVD, flowable CVD, other suitable methods, or combinations thereof. Subsequently, the dielectric layer 126 is deposited as a planar layer over the absorption structure 124 by any suitable method similar to those described above for forming the dielectric layer 103. With further reference to Fig. 24 and Fig. 26, the gate structures 154 in the dielectric layer 126 and the absorption structure 124 are formed in operation 308. First, trenches (not shown) are formed in the dielectric layer 126 and the absorption structure 124 by a series of photolithography and etching processes similar to those described above for forming the trenches for the WL structure 155. The trenches extend longitudinally along the Y-direction and are separated from each other along the X-direction. Each of the trenches is vertically oriented toward a corresponding WL structure 155 along the Z-direction. In the present embodiments, each of the trenches extends vertically through the dielectric layer 126 and the absorption structure 124 such that it exposes a top surface of the corresponding WL structure 155. Subsequently, various material layers of the gate structure 154, including material layers 154a, 154b, 154c, and 154d, are successively deposited in the trenches by any suitable deposition process described above with respect to the barrier layer 155a and the filler layer 155b. In some embodiments, one or more of the material layers 154a-154d are omitted from the gate structure 154. The various material layers are then planarized using one or more CMP processes to form the gate structures 154. Referring to Fig. 24 and Fig. 27, the gate dielectric layer 152 and the channel layer 110 are deposited over the gate structures 154 in operation 310. In some embodiments, the gate dielectric layer 152 and the channel layer 110 are each formed as an area-covering layer over the gate structures 154 and the dielectric layer 126, respectively, using any suitable deposition process similar to those described above with respect to the barrier layer 155a and the filler layer 155b. In some embodiments, the channel layer 110 is subsequently structured to expose certain sections of the underlying gate dielectric layer 152. In one such example—referring to Figures 1-4—the channel layer 110 can be structured to form regions separated along the Y-direction by sections of the gate dielectric layer 152. In this respect, each region of the channel layer 110 extends longitudinally along the X-direction. In another example—referring to Figures 12, 13 to 14—the channel layer 110 can be structured to form regions separated along both the X-direction and the Y-direction by sections of the gate dielectric layer 152. The channel layer 110 can be structured using a series of photolithography and etching processes similar to those described above for forming the trenches for the WL structure 155. Referring to Figures 24 and 28, the absorption structure 138 and the dielectric layer 148 are formed over the channel layer 110 in operation 312. The material layers of the absorption structure 138, including the dielectric layer 138a and the absorption layer 138b, are deposited successively as planar layers by any suitable deposition process similar to those described above with respect to the formation of the absorption structure 124. Subsequently, the dielectric layer 148 is deposited over the absorption structure 124 by any suitable method similar to the method described above with respect to the formation of the dielectric layer 103. Referring to Figs. 24 and 29, in Operation 314 a pair of drain structure 140 and source structure 142 are formed in the dielectric layer 148 corresponding to each gate structure 154. In some embodiments—referring to Figs. 1-4 and 6-11B—the drain structure 140 and the source structure 142 in each memory cell 104 are formed such that they have different widths along the X-direction or different lengths along the Y-direction. Alternatively or additionally—referring to Figs. 1-4, 6-7B, and 10-11B—the bottom surface BS140 of the drain structure 140 in each memory cell 104 is formed such that it overlaps the top surface TS154 of the gate structure 154 in the same memory cell 104. Furthermore, for example, referring to Figs. 6 and 6-11B, the bottom surface BS140 of the drain structure 140 in each memory cell 104 is formed such that it overlaps the top surface TS154 of the gate structure 154 in the same memory cell 104.8 - each Source structure 142 shall be formed such that its midline is aligned or substantially aligned with a midline CL of the Gate structure 154 which lies below the Source structure 142. To form the drain structures 140 and the source structures 142, trenches (not shown) are first formed in the dielectric layer 148 and the absorption structure 138 by a series of photolithography and etching processes similar to those described above for forming the trenches for the WL structure 155. The trenches extend longitudinally along the Y-direction and are separated from each other along the X-direction. The dimensions of the trenches and their relative positions with respect to the gate structure 154 are set up according to various embodiments described in this text with respect to the storage devices 100A, 100B, and 100C. Subsequently, various material layers of each of the drain structure 140 and the source structure 142, including the absorption layer 130, the metal layer 132, and the metal layer 134, are successively deposited in the trenches by any suitable deposition process described above with respect to the barrier layer 155a and the filler layer 155b. In some embodiments, one or more of the absorption layer 130, the metal layer 132, and the metal layer 134 are omitted from each of the drain structures 140 and the source structures 142. The various material layers are then planarized using one or more CMP processes to form the drain structures 140 and the source structures 142 in the dielectric layer 148. In some embodiments, such as those shown with respect to storage device 100B, each source structure 142 can be configured such that one of its side walls is aligned or substantially aligned with the side wall SW of the gate structure 154, and the entire bottom surface BS142 can overlap or cross the top surface TS154 along the X-direction. In some embodiments, such as those shown with respect to storage device 100C, the source structure 142 is arranged adjacent to the side wall SW of the gate structure 154, and a substantial portion of the bottom surface BS142 of the source structure 142 is laterally offset from, and does not overlap, the top surface TS154 along the X-direction. Referring to Figs. 24 and 30, the BVIA structures 178 and the BL structure 180 are formed in the dielectric layer 176 in operation 316. In some embodiments, a first section of the dielectric layer 176 is first deposited as an area-covering layer over the drain structures 140 and the source structures 142 by any suitable method similar to those described above with respect to forming the dielectric layer 103. Then, in the first section of the dielectric layer 176, trenches (not shown) are formed by a series of photolithography and etching processes similar to those described above with respect to forming the trenches for the WL dielectric layer 155. The trenches are separated from each other along the X-direction and are each vertically aligned with a corresponding drain structure 140 along the Z-direction.In the present embodiments, each of the trenches extends vertically through the first section of the dielectric layer 176 such that it exposes a top surface of the corresponding drain structure 140. Subsequently, various material layers of the BVIA structures 178, including the metal layer 132 and the metal layer 134, are successively deposited in the trenches by any suitable deposition process described above with respect to the barrier layer 155a and the filler layer 155b. Afterwards, the various material layers are planarized using one or more CMP processes to form the BVIA structures 178. Subsequently, a second section of the dielectric layer 176 is deposited as an area-covering layer over the BVIA structures 178 and the first section of the dielectric layer 176 by any suitable method similar to those described above with respect to the formation of the dielectric layer 103. Then, a trench is formed in the second section of the dielectric layer 176 by a series of photolithography and etching processes similar to those described above with respect to the formation of the trenches for the WL structure 155. The trench extends longitudinally along the X-direction to expose a top surface of each BVIA structure 178. In some embodiments, the trench also exposes a section of each side wall of the BVIA structure 178 such that a top surface of each BVIA structure 178 extends into the trench. Subsequently, various material layers of the BL structure 180, including the metal layer 132 and the metal layer 134, are successively deposited in the trench by any suitable deposition process described above with respect to the barrier layer 155a and the filler layer 155b. The various material layers are then planarized using one or more CMP processes to form the BL structure 180. In some embodiments, the upper portion of each BVIA structure 178 extends into and is embedded within the BL structure 180. The resulting BVIA structures 178 each electrically couple a corresponding drain structure 140 to the BL structure 180. Referring to Fig. 24 and Fig. 31, the SVIA structures 190 are formed in the dielectric layer 188 in operation 318. The SVIA structures 190 can be formed in a manner similar to that used for forming the BVIA structures 178. For example, the dielectric layer 188 is first deposited as an area layer over the BL structure 180 and the dielectric layer 176 by any suitable method similar to those described above for forming the dielectric layer 103. Then, trenches (not shown) are formed in the dielectric layer 176 and the dielectric layer 188 by a series of photolithography and etching processes similar to those described above for forming the trenches for the WL structure 155. The trenches are separated from each other along the X direction and are each vertically aligned with a corresponding source structure 142 along the Z direction.In the present embodiments, each of the trenches extends vertically through the dielectric layer 176 and the dielectric layer 188 such that it exposes a top surface of the corresponding source structure 142. Subsequently, various material layers of the SVIA structures 190, including the metal layer 132 and the metal layer 134, are successively deposited in the trenches by any suitable deposition process described above with respect to the barrier layer 155a and the filler layer 155b. The various material layers are then planarized using one or more CMP processes to form the SVIA structures 190. The resulting SVIA structures 190 are each electrically coupled to the corresponding source structure 142. Referring to Fig. 24 and Fig. 32, the capacitors 200 are formed in the dielectric structure 192 in operation 320. Various material layers of the dielectric structure 192, including the absorption layer 194, the dielectric layer 196, and the dielectric layer 198, are each deposited as an area-covering layer over the SVIA structures 190 and the dielectric layer 188 by any suitable method similar to those described above with respect to forming the dielectric layer 103. Then, trenches (not shown) are formed in the dielectric structure 192 by a series of photolithography and etching processes similar to those described above with respect to forming the trenches for the WL structure 155. The trenches are separated from each other along the X direction and are each vertically aligned with a corresponding SVIA structure 190 along the Z direction.In the present embodiments, each of the trenches extends vertically through the dielectric structure 192 such that it exposes a top side of the corresponding SVIA structure 190. Subsequently, various material layers of the capacitors 200, including the bottom plate 202, the capacitor dielectric layer 204, and the top plate 206, are successively deposited in the trenches by any suitable deposition process described above with respect to the junction 155a and the filler layer 155b. The various material layers are then planarized using one or more CMP processes to form the capacitors 200. The resulting capacitors 200 are electrically coupled to the corresponding source structure 142 via an SVIA structure 190. Additional operations can then be performed in Operation 322. For example, additional interconnect structural elements, such as vias and conductive traces, can be formed above the 100A storage device according to various design requirements. In one aspect of the present disclosure, a storage device is disclosed. The storage device comprises a channel layer. The storage device has a gate structure on a first side of the channel layer, the gate structure having a top surface facing the channel layer. The storage device has a drain structure on a second side of the channel layer opposite the first side, the drain structure having a first bottom surface in contact with the channel layer. The first bottom surface overlaps the top surface of the gate structure in a lateral direction. The storage device has a source structure on the second side of the channel layer and adjacent to the drain structure along the lateral direction, the source structure having a second bottom surface facing the channel layer. The second bottom surface overlaps the top surface of the gate structure in the lateral direction. In a further aspect of the present disclosure, a storage device is disclosed. The storage device comprises a channel layer. The storage device has a gate structure on a rear side of the channel layer, the gate structure having a top surface facing the channel layer. The storage device has a drain structure on a front side of the channel layer opposite the rear side, the drain structure having a first bottom surface facing the channel layer. The first bottom surface does not overlap the top surface along a lateral direction and has a first width along the lateral direction. The storage device has a source structure on the front side of the channel layer and adjacent to the drain structure, the source structure having a second bottom surface facing the channel layer. The second bottom surface overlaps the top surface along the lateral direction.The second underside has a second width along the lateral direction, which differs from the first width. In another aspect of the present disclosure, a method for fabricating a storage device is disclosed. The method comprises forming a first dielectric layer over a base structure. The method comprises forming a word line structure in the first dielectric layer. The method comprises forming a second dielectric layer over the word line structure. The method comprises forming a back-side gate structure in the second dielectric layer, the back-side gate structure extending along a first lateral direction. The method comprises forming a gate dielectric layer with a high k-value over the back-side gate structure. The method comprises forming a semiconductor layer over the gate dielectric layer with a high k-value.The method comprises forming a source structure and a drain structure adjacent to the source structure along a second lateral direction perpendicular to the first lateral direction in a top view of the memory cell, wherein the drain structure has a first underside facing the semiconductor layer, and the source structure has a second underside facing the semiconductor layer. The first underside differs from the second underside in its area across both the first and second lateral directions. For the purposes of this text, the terms "about" and "approximately" generally mean plus or minus 10% of the stated value. For example, "about 0.5" would also include 0.45 and 0.55, "about 10" would also include 9 to 11, and "about 1000" would also include 900 to 1100.

Claims

Storage device (100A; 100B; 100C; 100D), comprising: a channel layer (110); a gate structure (154) on a first side of the channel layer (110), wherein the gate structure (154) has a top surface (TS154) facing the channel layer (110); a drain structure (140) on a second side of the channel layer (110) opposite the first side, wherein the drain structure (140) has a first bottom surface (BS140) in contact with the channel layer (110) and the first bottom surface (BS140) overlaps the top surface (TS154) of the gate structure (154) over a first lateral direction (X);and a source structure (142) on the second side of the channel layer (110) and adjacent to the drain structure (140) along the first lateral direction (X), wherein the source structure (142) has a second underside (BS142) facing the channel layer (110), and the second underside (BS142) overlaps the top side (TS154) of the gate structure (154) across the first lateral direction (X); wherein: the drain structure (140) has a first length along a second lateral direction (Y) perpendicular to the first lateral direction (X) in a top view of the storage device (100A; 100B; 100C; 100D); the source structure (142) has a second length along the second lateral direction (Y); and the first length is smaller than the second length. Storage device (100A; 100B; 100C; 100D) according to claim 1, wherein a first edge of the top side (TS154) of the gate structure (154) is separated along the first lateral direction (X) from a second edge of the second bottom side (BS142). Storage device (100A; 100B; 100C; 100D) according to claim 1 or 2, wherein a first edge of the top (TS154) of the gate structure (154) is vertically aligned with a first edge of the first bottom (BS140). Storage device (100A; 100B; 100C; 100D) according to one of the preceding claims, wherein: the drain structure (140) has a first width along the first lateral direction (X) and the source structure (142) has a second width along the first lateral direction (X), and the first width differs from the second width. Storage device (100A; 100B; 100C; 100D) according to one of the preceding claims, further comprising: a word line structure (155) electrically coupled to the gate structure (154); a bit line structure (180) electrically coupled to the drain structure (140); and a capacitor (200) electrically coupled to the source structure (142). Storage device (100B; 100C) according to one of the preceding claims, wherein a side wall of the gate structure (154) is aligned along a vertical direction (Z) perpendicular to the first lateral direction (X) in a cross-sectional view of the storage device (100B; 100C) with a side wall of the source structure (142). Storage device (100A; 100D) according to one of the preceding claims, wherein a center line of the gate structure (154) is aligned along a vertical direction (Z) perpendicular to the first lateral direction (X) in a cross-sectional view of the storage device (100A; 100D) to a center line of the source structure (142). Storage device (100A; 100B; 100C; 100D), comprising: a channel layer (110); a gate structure (154) on a back side of the channel layer (110), wherein the gate structure (154) has a top side (TS154) facing the channel layer (110); a drain structure (140) on a front side of the channel layer (110) opposite the back side, wherein the drain structure (140) has a first bottom side (BS140) facing the channel layer (110), wherein the first bottom side (BS140) does not overlap the top side (TS154) along a first lateral direction (X) and the first bottom side (BS140) has a first width along the first lateral direction (X);and a source structure (142) on the front side of the channel layer (110) and adjacent to the drain structure (140), wherein the source structure (142) has a second underside (BS142) facing the channel layer (110), the second underside (BS142) overlapping the top side (TS154) along the first lateral direction (X), and the second underside (BS142) having a second width along the first lateral direction (X) that differs from the first width; wherein: the drain structure (140) has a first length along a second lateral direction (Y) perpendicular to the first lateral direction (X) in a top view of the storage device (100A; 100B; 100C; 100D); the source structure (142) has a second length along the second lateral direction (Y); and the first length is smaller than the second length. Storage device (100A; 100B; 100C; 100D) according to claim 8, wherein the first width is smaller than the second width. Storage device (100A; 100B; 100C; 100D) according to claim 8 or 9, further comprising: a bit line structure (180) extending along the first lateral direction (X), a first via structure (178) electrically coupling the drain structure (140) to the bit line structure (180), a capacitor (200) extending in a cross-sectional view of the storage device (100A; 100B; 100C; 100D) along a vertical direction (Z) perpendicular to the first lateral direction (X), and a second via structure (190) electrically coupling the source structure (142) to the capacitor (200). Storage device (100B; 100C) according to one of claims 8 to 10, wherein a side wall of the source structure (142) is aligned along a vertical direction (Z) perpendicular to the first lateral direction (X) in a cross-sectional view of the storage device (100B; 100C) with a side wall of the gate structure (154). Storage device (100A; 100B; 100C; 100D) according to one of claims 8 to 11, further comprising a word line structure (155) coupled to the gate structure (154), wherein the word line structure (155) is aligned along a vertical direction (Z) perpendicular to the first lateral direction (X) in a cross-sectional view of the storage device (100A; 100B; 100C; 100D) to the gate structure (154). Storage device (100A; 100B; 100C; 100D) according to any one of claims 8 to 12, further comprising: a first absorption structure (138) arranged on the front side of the channel layer (110) and between the drain structure (140) and the source structure (142), and a second absorption structure (124) arranged on the back side of the channel layer (110) and next to the gate structure (154), wherein the first absorption structure (138) and the second absorption structure (124) each have a hydrogen absorption layer. Method for fabricating a memory cell (100A; 100B; 100C; 100D), comprising: forming a first dielectric layer (103) over a base structure (102); forming a word line structure (155) in the first dielectric layer (103); forming a second dielectric layer (126) over the word line structure (155); forming a back-side gate structure (154) in the second dielectric layer (126), the back-side gate structure (154) extending along a first lateral direction (X); forming a high k-value gate dielectric layer (152) over the back-side gate structure (154); forming a semiconductor layer (110) over the high k-value gate dielectric layer (152); and forming a source structure (142) and a drain structure (140) next to the source structure (142) along a second lateral direction (Y) perpendicular to the first lateral direction (X) in a top view of the memory cell (100A; 100B; 100C;100D), wherein the drain structure (140) has a first bottom surface (BS140) facing the semiconductor layer (110), and the source structure (142) has a second bottom surface (BS142) facing the semiconductor layer (110), wherein the first bottom surface (BS140) differs from the second bottom surface (BS142) in its area across the first lateral direction (X) and the second lateral direction (Y); wherein the back-side gate structure (154) has a top surface (TS154) facing the semiconductor layer (110), and wherein the top surface (TS154) of the back-side gate structure (154) overlaps the first bottom surface (BS140). Method according to claim 14, wherein a first edge of the top (TS154) of the rear gate structure (154) is separated along the first lateral direction (X) from a second edge of the second bottom (BS142). Method according to claim 14 or 15, wherein a first edge of the top (TS154) of the rear gate structure (154) is vertically aligned with a first edge of the first bottom (BS140). Method according to any one of claims 14 to 16, further comprising: forming a first hydrogen absorption layer (124) between the first dielectric layer (103) and the second dielectric layer (126); and forming a second hydrogen absorption layer (138) over the semiconductor layer (110).

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