semiconductor device

Abstract

A semiconductor device (101) comprises at least three first die pads (11), at least three first semiconductor elements (21) individually mounted on the first die pads (11), a first wire (31) electrically connecting each of the first semiconductor elements (21), at least three second die pads (12) arranged alternately with the first die pads (11), at least three second semiconductor elements (22) individually mounted on the second die pads (12), and a second wire (32) electrically connecting each of the second semiconductor elements (22).

Description

BACKGROUND OF THE INVENTIONField of the invention

[0001] The present disclosure relates to a semiconductor device. Description of the background technology

[0002] Conventionally, as a semiconductor device in which a plurality of semiconductor elements and a control integrated circuit are mounted in a package, a semiconductor device in which a plurality of semiconductor elements are mounted on a die pad is known. For example, in Japanese Patent Application Laid-Open No. 2009-111154, a plurality of sets of pairs of an IGBT chip and a flywheel diode, which are semiconductor elements, are mounted on a die pad portion of a lead frame. Specifically, three sets of the IGBT chip and the flywheel diode on a high-potential side are mounted on one die pad portion, and three sets of the IGBT chip and the flywheel diode on a low-potential side are mounted on three die pad portions. The IGBT chip and the flywheel diode are electrically connected to a predetermined lead frame by a bonding wire.

[0003] In the device of Japanese Patent Application Laid-Open No. 2009-111154, three sets of the IGBT chip and the high-potential-side flywheel diode are mounted on a die pad portion. Therefore, the high-potential-side semiconductor element and the low-potential-side semiconductor element, which need to be electrically connected to each other, are arranged at separate positions. Therefore, a lead terminal connected to the die pad portion mounted with the low-potential-side semiconductor element is bent and arranged to approach the high-potential-side semiconductor element in a direction close to the high-potential-side semiconductor element, and the high-potential-side semiconductor element and the low-potential-side semiconductor element are electrically connected by wire bonding using the bent portion of the lead terminal.

[0004] Therefore, in the device of Japanese Patent Application Laid-Open No. 2009-111154, since a space for disposing the bent lead terminal is required, an area of the die pad portion with respect to an area of the entire device could not be increased by the space for disposing the bent lead terminal, and there was a problem that heat dissipation of the semiconductor element could not be improved by increasing the area of the die pad portion. SUMMARY

[0005] The present disclosure has been made to solve the problems described above, and an object of the present disclosure is to provide a semiconductor device capable of increasing an area of a die pad with respect to a device area and improving heat dissipation compared with a conventional semiconductor device.

[0006] A semiconductor device according to the present disclosure comprises: at least three first die pads; at least three first semiconductor elements individually mounted on the first die pads; a first wire electrically connecting each of the first semiconductor elements; at least three second die pads arranged alternately with the first die pads; at least three second semiconductor elements individually mounted on the second die pads; and a second wire electrically connecting each of the second semiconductor elements.

[0007] According to the semiconductor device of the present disclosure, it is possible to increase an area of a die pad with respect to a device area, thereby improving heat dissipation.

[0008] These and other objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view illustrating a semiconductor device according to a first preferred embodiment of the present disclosure; Fig. 2 is a cross-sectional view illustrating the semiconductor device according to the first preferred embodiment of the present disclosure; Fig. 3 is a plan view illustrating a semiconductor device according to a second preferred embodiment of the present disclosure; Fig. 4 and Fig. 5 are cross-sectional views each illustrating the semiconductor device according to the second preferred embodiment of the present disclosure; Fig. 6 is a plan view illustrating a semiconductor device according to a third preferred embodiment of the present disclosure; Fig. 7 is a plan view illustrating a semiconductor device according to a fourth preferred embodiment of the present disclosure; and Fig. 8 is a plan view illustrating a semiconductor device according to a fifth preferred embodiment of the present disclosure. DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] An example of a semiconductor device according to the present disclosure will be described below with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and their descriptions will not be repeated.

[0010] In this specification, a semiconductor device including a three-phase inverter circuit is described as an example of a semiconductor device in which a plurality of semiconductor elements and an integrated control circuit are mounted in a package. The three-phase inverter circuit is a circuit that converts DC power into three-phase (U-phase, V-phase, W-phase) AC power. First preferred embodiment.

[0011] A first preferred embodiment of the present disclosure relates to a semiconductor device 101 comprising: at least three first die pads; at least three first semiconductor elements individually mounted on the first die pads; a first wire electrically connecting each of the first semiconductor elements; at least three second die pads arranged alternately with the first die pads; at least three second semiconductor elements individually mounted on the second die pads; and a second wire electrically connecting each of the second semiconductor elements. <Konfiguration einer ersten bevorzugten Ausführungsform>

[0012] With reference to Fig. 1 and Fig. 2, a configuration of the semiconductor device 101 according to the first preferred embodiment of the present disclosure will be described. Fig. 1 is a plan view illustrating the semiconductor device 101, and Fig. 2 is a line AA in Fig. 1 taken cross-sectional view. In Fig. 1 and Fig. 2, a sealing resin 70 is omitted to show a structure within the sealing resin 70. In Fig. 1 and Fig. 2, a contour when the sealing resin 70 is present is indicated by a dashed line.

[0013] As in Fig. 1 and Fig. 2, within the sealing resin 70 having a quadrangular shape in plan view, the semiconductor device 101 includes a die pad (11, 12, 51), a semiconductor element (21, 22), a control integrated circuit 52, a wire (31, 32, 33, 34, 53), a terminal (41, 42, 43, 54), and an insulating film 60. Upon sealing, a part of the terminal (41, 42, 43, 54) and at least a part of a lower surface of the insulating film 60 are exposed to the outside of the sealing resin 70. Details of each configuration will be described hereinafter.

[0014] The semiconductor device 101 includes three first die pads 11 and three second die pads 12. The three first die pads 11 and the three second die pads 12 have a quadrangular shape in plan view and are alternately arranged. Specifically, the three first die pads 11 and the three second die pads 12 are alternately arranged in plan view along an extending direction of a first side 71 of the sealing resin 70 having a quadrangular shape in plan view. In other words, in plan view, the first side 71 of the sealing resin 70 is a side extending in a direction in which the first die pad 11 and the second die pad 12 are alternately arranged.

[0015] Fig. 1 illustrates an example in which the first side 71 among the sides of the sealing resin 70 in plan view is a side extending in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, and the first side 71 is a long side of the sealing resin 70 in plan view. However, it is sufficient to arrange the first die pad 11 and the second die pad 12 alternately along a direction from one of the four sides of the sealing resin 70 in plan view. That is, with respect to the first die pad 11 and the second die pad 12 in Fig. 1, the three first die pads 11 and the three second die pads 12 can be arranged, for example, along a short side (a second side 72 or a third side 73 in Fig. 1) of the sealing resin 70.

[0016] The first die pad 11 and the second die pad 12 are plate-shaped components, each having an upper surface and a lower surface. A conductive material with good thermal conductivity, such as copper, is used for the first die pad 11 and the second die pad 12.

[0017] Three first semiconductor elements 21 are individually mounted on the upper surfaces of the three first die pads 11. Furthermore, three second semiconductor elements 22 are individually mounted on the upper surfaces of the three second die pads 12.

[0018] The first semiconductor element 21 and the second semiconductor element 22 are components for constituting a three-phase inverter circuit that converts DC power into three-phase (U-phase, V-phase, W-phase) AC power, and are elements that perform a switching operation. The first semiconductor element 21 is electrically connected between a first main terminal 41 to be described later and an output terminal 43 to be described later to constitute the three-phase inverter circuit described above. Furthermore, the second semiconductor element 22 is connected between the output terminal 43 to be described later and a second main terminal 42 to be described later to constitute the three-phase inverter circuit described above. The first semiconductor element 21 is then connected to an external substrate (not illustrated) on a high-potential side of the DC power in the three-phase inverter circuit.The second semiconductor element 22 is connected to an external substrate (not shown) on a low-potential side of the DC power in the three-phase inverter circuit. In other words, a relatively high potential is applied to the first semiconductor element 21 compared to the second semiconductor element 22. A relatively low potential is applied to the second semiconductor element 22 compared to the first semiconductor element 21.

[0019] The first semiconductor element 21 and the second semiconductor element 22 are, for example, a reverse conducting (RC) insulated gate bipolar transistor (IGBT). The RC-IGBT is an element that includes an IGBT and a flyback diode in one chip, and performs both a switching operation and a flyback operation. Note that it is sufficient that the first semiconductor element 21 and the second semiconductor element 22 can perform the switching operation, and a combination of two or more elements can be used as the first semiconductor element 21 and the second semiconductor element 22. That is, a combination of a switching element and an antiparallel-connected diode can be used as the first semiconductor element 21 or the second semiconductor element 22.For example, an IGBT or a metal oxide semiconductor (MOS) transistor may be combined with a freewheeling diode to be used as the first semiconductor element 21 or the second semiconductor element 22.

[0020] Three first semiconductor elements 21 and three second semiconductor elements 22 are arranged corresponding to a three-phase AC power to be output. A configuration of the three-phase inverter circuit including the first semiconductor element 21 and the second semiconductor element 22 will be described later.

[0021] The semiconductor device 101 includes the first main terminal 41, the second main terminal 42, and three output terminals 43. Among the three first die pads 11, the first main terminal 41 extends from the first die pad 11, which is arranged on one end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged. The second main terminal 42 is arranged on another end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged. Fig. 1, one end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged is a left-end side, and the other end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged is a right-end side. Three of the output terminals extend from at least three of the second die pads.

[0022] The first main terminal 41, the second main terminal 42, and the output terminal 43 protrude outward from a first lateral surface including the first side 71 in the sealing resin 70. Among the sides of the sealing resin 70, the first side 71 is a side extending in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged.

[0023] Please note that Fig. 1 illustrates an example in which the first side 71 included in the first side surface of the sealing resin 70 is a long side of the sealing resin 70 in plan view, but it is sufficient that the first side surface is a side surface that includes one of four sides of the sealing resin 70 having a quadrangular shape in plan view. That is, the first side surface may be a side surface that includes a short side (the second side 72 or the third side 73 in Fig. 1) of the sealing resin 70 in plan view. As shown in Fig. As illustrated in Figure 1, in a case where the first side 71 included in the first lateral surface of the sealing resin 70 is a long side of the sealing resin 70 in plan view, the first main terminal 41, the second main terminal 42, and the output terminal 43 are arranged away from each other compared to a case where the first side is a short side. Thus, a creepage distance between the terminals can be reliably ensured.

[0024] Although Fig. While FIG. 1 illustrates an example in which portions protruding from the sealing resin 70 in the first main terminal 41, the second main terminal 42, and the output terminal 43 have a quadrangular shape in plan view, the present disclosure is not limited thereto. The portions protruding from the sealing resin 70 in the first main terminal 41, the second main terminal 42, and the output terminal 43 may, for example, be a plate-shaped component with a polygonal shape or a rounded shape.

[0025] The first main terminal 41 and the second main terminal 42 are electrically connected to an external substrate (not shown) and arranged to input DC power. The output terminal 43 is electrically connected to an external substrate (not shown) and arranged to output AC power. Similar to the first die pad 11 and the second die pad 12, the first main terminal 41, the second main terminal 42, and the output terminal 43 include a material with conductivity and good thermal conductivity, such as copper, for example.

[0026] As in Fig. 1, the semiconductor device 101 may include an inner lead 41a extending from two first die pads 11 among the three first die pads 11 and completely sealed within the sealing resin 70. Specifically, the inner lead 41a extends from two first die pads 11 arranged on the other end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged. The inner lead 41a is a member extending from the first die pad 11 but, unlike the first main terminal 41, does not protrude from the sealing resin 70. The inner lead 41a is configured for electrical connection within the semiconductor device 101.

[0027] The semiconductor device 101 includes a plurality of wires for electrically connecting the three first semiconductor elements 21 and the three second semiconductor elements 22. Specifically, the semiconductor device 101 includes a first wire 31, a second wire 32, a third wire 33, and a fourth wire 34.

[0028] The first wire 31 is a wire that electrically connects each of the three first semiconductor elements 21 and is arranged to connect between two first die pads 11 that are adjacent to each other with the second die pad 12 interposed therebetween. Specifically, the first wire 31 includes: a first wire 31a arranged to connect between two first die pads 11 on the one end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged; and a first wire 31b arranged to connect between two first die pads 11 on the other end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged. Here, the two first die pads 11 on the one end side are two first die pads 11 arranged on the left end side in Fig. 1, and the two first die pads 11 on the other end side are two first die pads 11 which are arranged on the side at the right end in Fig. 1. That is, the first wire 31 is a general term for wires arranged to connect between the first die pads 11. The first wire 31 may be configured using a plurality of wires or may be arranged to connect by means of one wire.

[0029] The second wire 32 is a wire that electrically connects each of the three second semiconductor elements 22 and is arranged to connect between two second semiconductor elements 22 mounted on two second die pads 12 that are adjacent to each other, with the first die pad 11 interposed therebetween. Specifically, the second wire 32 includes: a second wire 32a arranged to connect between two second semiconductor elements 22 on the other end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged; and a second wire 32b arranged to connect between two second semiconductor elements 22 on the one end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged. Here, the two second semiconductor elements 22 on the one end side are two second semiconductor elements 22 arranged on the left end side in Fig. 1, and the two second semiconductor elements 22 on the other end side are two second semiconductor elements 22 arranged on the right end side in Fig. 1. That is, the second wire 32 is a general term for wires arranged to connect between the second semiconductor elements 22. The second wire 32 may be configured using a plurality of wires or may be arranged to connect by means of one wire.

[0030] The third wire 33 is a wire that electrically connects the second main terminal 42 and the second semiconductor element 22. The third wire 33 is arranged to connect between the second main terminal 42 and the second semiconductor element 22, which is arranged on the other end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged.

[0031] The fourth wire 34 is a wire that electrically connects the first semiconductor element 21 and the second semiconductor element 22, and is arranged to connect between the first semiconductor element 21 and the second die pad 12, which are adjacent to each other.

[0032] As the first wire 31, the second wire 32, the third wire 33 and the fourth wire 34, for example, a bonding wire containing an aluminum wire is used.

[0033] Furthermore, the semiconductor device 101 includes three control integrated circuits 52 for controlling the first semiconductor element 21 and the second semiconductor element 22. Specifically, in response to an external operation command, the control integrated circuit 52 generates and outputs control signals for the first semiconductor element 21 and the second semiconductor element 22. Each of the three control integrated circuits 52 is mounted on an upper surface of a third die pad 51.

[0034] Although Fig. 1 and Fig. 2 illustrates an example in which the three control integrated circuits 52 are arranged, the control integrated circuit 52 is not limited to this, and for example, two control integrated circuits 52 may be arranged.

[0035] Furthermore, the semiconductor device 101 includes a plurality of control terminals 54 electrically connected to the control integrated circuit 52. The control terminal 54 protrudes outward from the sealing resin 70 from a fourth lateral surface, which includes a fourth side 74 opposite the first side 71 of the sealing resin 70 in plan view. The plurality of control terminals 54 are electrically connected to an external substrate (not illustrated) and arranged to receive operating commands to the first semiconductor element 21 and the second semiconductor element 22.

[0036] The semiconductor device 101 further includes a plurality of fifth wires 53 arranged to connect between the first semiconductor element 21 and the control integrated circuit 52, between the second semiconductor element 22 and the control integrated circuit 52, and between the control terminal 54 and the control integrated circuit 52. For example, the plurality of fifth wires 53 are provided for the control integrated circuit 52 to transmit a control signal instructing ON or OFF in the switching operation to the first semiconductor element 21 and the second semiconductor element 22, or for the control integrated circuit 52 to receive operation commands to the first semiconductor element 21 and the second semiconductor element 22 from the outside. For the fifth wire 53, for example, a bonding wire made of a gold wire is used.

[0037] Furthermore, the semiconductor device 101 includes the insulating film 60 as shown in Fig. 2. The insulating film 60 is arranged such that an upper surface of the insulating film 60 faces the lower surfaces of the first die pad 11 and the second die pad 12, that is, surfaces of the first die pad 11 and the second die pad that are opposite to the mounting surfaces of the first semiconductor element 21 and the second semiconductor element 22.

[0038] For the insulating film 60, a material with insulating properties and good thermal conductivity such as, for example, an epoxy resin containing one of BN, SiO2, Si3N4, Al2O3 and AIN as a filler is used.

[0039] In the semiconductor device 101, each structure is sealed with the sealing resin 70 having a quadrangular shape in plan view. Specifically, the sealing resin 70 seals the first die pad 11, the second die pad 12, the third die pad 51, the first semiconductor element 21, the second semiconductor element 22, the control integrated circuit 52, the first wire 31, the second wire 32, the third wire 33, the fourth wire 34, the fifth wire 53, a part of the first main terminal 41, a part of the second main terminal 42, a part of the output terminal 43, a part of the control terminal 54, and a part of the insulating film 60. That is, a part of the first main terminal 41, a part of the second main terminal 42, a part of the output terminal 43, a part of the control terminal 54, and at least a part of the lower surface of the insulating film 60 are exposed to the outside of the sealing resin 70.

[0040] With the above configuration, heat generated by the first semiconductor element 21 and the second semiconductor element 22 is dissipated to the outside of the semiconductor device 101 via the insulating film 60 and via the first die pad 11 and the second die pad 12 in contact with the first semiconductor element 21 and the second semiconductor element 22, respectively.

[0041] Note that the semiconductor device 101 may include a heat dissipation plate (not shown). The heat dissipation plate is disposed on the lower surface of the insulating film 60. By further providing the heat dissipation plate, it is possible to improve the heat dissipation of heat generated by the first semiconductor element 21 and the second semiconductor element.

[0042] As described above, the semiconductor device 101 has a configuration in which the three first semiconductor elements 21, the three second semiconductor elements 22, and the three control integrated circuits 52 for controlling the first semiconductor element 21 and the second semiconductor element 22 are mounted in a package. The semiconductor device 101 includes a three-phase inverter circuit including the three first semiconductor elements 21 and the three second semiconductor elements 22, and a drive circuit including the three control integrated circuits 52. A circuit configuration of the semiconductor device 101 will be described here.

[0043] The three-phase inverter circuit included in the semiconductor device 101 is a circuit that converts DC power into three-phase AC power through the switching operation of the first semiconductor element 21 and the second semiconductor element 22, and outputs the three-phase AC power. The three-phase inverter circuit is configured such that the first semiconductor element 21 on the high-potential side and the second semiconductor element 22 on the low-potential side are electrically connected between the first main terminal 41 on the high-potential side connected to an external substrate (not illustrated) and the second main terminal 42 on the low-potential side connected to an external substrate (not illustrated), and an output side of the AC power from the two connecting connection nodes is to form the output terminal 43.That is, to form the three-phase inverter circuit, the first semiconductor element 21 on the high-potential side and the second semiconductor element 22 on the low-potential side must be electrically connected. Furthermore, the three first semiconductor elements 21 must be electrically connected in parallel. Similarly, the three second semiconductor elements 22 must be electrically connected in parallel.

[0044] As described above, three first semiconductor elements 21 and three second semiconductor elements 22 are provided corresponding to three phases. That is, one first semiconductor element 21 and one second semiconductor element 22 are provided for each phase, and three first semiconductor elements 21 and three second semiconductor elements 22 are provided for three phases. Three output terminals 43 are arranged individually corresponding to the three phases.

[0045] The drive circuit included in the semiconductor device 101 is a circuit that controls the switching operation of the first semiconductor element 21 and the second semiconductor element 22. The drive circuit is configured such that a control integrated circuit 52 controls the switching operation for a set of the first semiconductor element 21 and the second semiconductor element 22, which constitutes one phase among the three phases. That is, one control integrated circuit 52 is arranged for each phase, and three control integrated circuits 52 are arranged for three phases.

[0046] As described above, the semiconductor device 101 controls the switching operation of the three first semiconductor elements 21 and the three second semiconductor elements 22 using the three-phase inverter circuit and the drive circuit, converts DC power into three-phase AC power, and outputs the three-phase AC power.

[0047] Although the example in which the semiconductor device 101 includes three first semiconductor elements 21 and three second semiconductor elements 22 has been described, the semiconductor device 101 may include three or more first semiconductor elements 21 and more than three second semiconductor elements 22. It is sufficient that the semiconductor device 101 includes at least three first semiconductor elements 21 and at least three second semiconductor elements 22. For example, a three-phase, three-level voltage-type inverter circuit can be formed by including six first semiconductor elements 21 and six second semiconductor elements 22. More than three first die pads 11 and three or more second die pads 12 may be arranged according to the number of first semiconductor elements 21 and second semiconductor elements 22. <Verfahren zum Herstellen der ersten bevorzugten Ausführungsform>

[0048] Next, a method for manufacturing the semiconductor device 101 according to the first preferred embodiment of the present disclosure will be described. Note that, in the present preferred embodiment, among processes for manufacturing the semiconductor device 101, processes other than a process for forming the first three die pads 11 can be implemented by appropriately applying a known technology, and therefore, only the process for forming the first three die pads 11 will be described here.

[0049] The first three die pads 11 are formed by punching a copper plate with conductive properties and good thermal conductivity. The first three die pads 11 are formed, for example, by punching the copper plate into a predetermined shape using a mold. <Wirkung und Effekt der ersten bevorzugten Ausführungsform>

[0050] Next, the action and effect of the semiconductor device 101 according to the first preferred embodiment of the present disclosure will be described by comparing a conventional semiconductor device and the semiconductor device 101 of the present disclosure.

[0051] In the conventional semiconductor device, for example, in the device of Japanese Patent Application Laid-Open No. 2009-111154, three sets of the IGBT chip and the high-potential-side flywheel diode are mounted on a die pad portion. Therefore, the device of Japanese Patent Application Laid-Open No. 2009-111154 has a configuration in which the high-potential-side semiconductor element and the low-potential-side semiconductor element, which need to be electrically connected to each other to form the three-phase inverter circuit, are arranged at positions separate from each other. To connect the high-potential-side semiconductor element and the low-potential-side semiconductor element, a terminal extending from a die pad mounted with the low-potential-side semiconductor element is formed into a shape having one or more bent portions.

[0052] Therefore, in the device of Japanese Patent Application Laid-Open No. 2009-111154, an area of the die pad with respect to an area of the entire device could not be increased by a space in which the bent portion of the terminal is arranged, and heat dissipation of the semiconductor element could not be improved by increasing the area of the die pad.

[0053] The semiconductor device 101 according to the first preferred embodiment of the present disclosure includes: at least three first die pads 11; at least three first semiconductor elements 21 individually mounted on the first die pads 11; the first wire 31 electrically connecting each of the first semiconductor elements 21; at least three second die pads 12 arranged alternately with the first die pads 11; at least three second semiconductor elements 22 individually mounted on the second die pads 12; and the second wire 32 electrically connecting each of the second semiconductor elements 22.

[0054] According to the semiconductor device 101 of the first preferred embodiment of the present disclosure, by separating the first die pad 11 mounted with the first semiconductor element 21 corresponding to the semiconductor element on the high potential side into three, and alternately arranging the first die pad 11 and the second semiconductor element 22 mounted with the second semiconductor element 22 corresponding to the semiconductor element on the low potential side, the first semiconductor element 21 and the second semiconductor element 22 that need to be electrically connected to each other can be arranged side by side. By arranging the first semiconductor element 21 and the second semiconductor element 22 side by side, it is no longer necessary to bend and arrange the output terminal 43 corresponding to a terminal extending from the second die pad so that it approaches the direction in which the first semiconductor element 21 is present.That is, the first semiconductor element 21 and the second semiconductor element 22 can be electrically connected to each other without bending the output terminal 43. Therefore, according to the semiconductor device 101 of the first preferred embodiment of the present disclosure, since the output terminal 43 can be arranged without being bent, an area of the first die pad 11 and the second die pad 12 can be increased with respect to an area of the semiconductor device 101 by the space in which the bent terminal is arranged in the conventional device, compared with the conventional semiconductor device.

[0055] Heat generated by the first semiconductor element 21 and the second semiconductor element 22 is dissipated to the outside of the semiconductor device 101 via the first die pad 11 and the second die pad 12. Therefore, according to the semiconductor device 101 of the first preferred embodiment of the present disclosure, compared with the conventional semiconductor device, the area of the first die pad 11 and the second die pad 12 can be increased, so that heat dissipation of the semiconductor device 101 can be improved compared with the conventional semiconductor device. Furthermore, according to the semiconductor device 101 of the first preferred embodiment of the present disclosure, by improving heat dissipation of the semiconductor device 101, an excitation current of the semiconductor device 101 can be increased compared with the conventional semiconductor device. Second preferred embodiment

[0056] In the first preferred embodiment of the present disclosure, the semiconductor device 101 was described, which includes the first main terminal 41, the second main terminal 42, and the third output terminal 43 arranged to protrude from the first side surface of the sealing resin 70, which includes the first side 71, which, among the sides of the sealing resin 70 in plan view, is a side extending in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged. In a second preferred embodiment of the present disclosure, a semiconductor device 102 is described, which includes: an output terminal 43 arranged to protrude from a first side surface of a sealing resin 70;a first main terminal 241 arranged to protrude from a second side surface of the sealing resin 70, which includes a second side 72, which is a side on the one end side in a direction in which a first die pad 11 and a second die pad 12 are alternately arranged, among the sides of the sealing resin 70 in plan view; and a second main terminal 242 arranged to protrude from a third side surface of the sealing resin 70, which includes a third side 73, which is a side on the other end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, among the sides of the sealing resin 70 in plan view.

[0057] In the second preferred embodiment, the same components as those in the first preferred embodiment of the present disclosure are denoted by the same reference numerals, and descriptions of the same or corresponding parts are omitted. Hereinafter, the semiconductor device 102 according to the second preferred embodiment will be described with reference to the drawings. <Konfiguration der zweiten bevorzugten Ausführungsform>

[0058] A configuration of the semiconductor device 102 according to the second preferred embodiment of the present disclosure will be described with reference to Fig. 3, Fig. 4 and Fig. 5 described. Fig. 3 is a plan view illustrating the semiconductor device 102. Fig. 4 is a line AA in Fig. 3 taken cross-sectional view, and Fig. 5 is a line BB in Fig. 3 taken cross-sectional view. In Fig. 3, Fig. 4 and Fig. 5, the sealing resin 70 is omitted to show a structure within the sealing resin 70. Furthermore, in Fig. 3, Fig. 4 and Fig. 5 a contour when the sealing resin 70 is present is indicated by a dashed line.

[0059] As in Fig. 3, Fig. 4 and Fig. 5, the semiconductor device 102 includes: the output terminal 43 arranged to protrude from the first side surface of the sealing resin 70, which includes a first side 71, which is a side extending in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, among the sides of the sealing resin 70 in plan view; the first main terminal 241 arranged to protrude from the second side surface of the sealing resin 70, which includes the second side 72, which is a side on the one end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, among the sides of the sealing resin 70 in plan view;and the second main terminal 242 arranged to protrude from the third lateral surface of the sealing resin 70, which includes the third side 73, which is a side on the other end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, among the sides of the sealing resin 70 in plan view.;

[0060] As described above, by arranging the individual terminals so as to protrude from different side surfaces of the sealing resin 70, the first main terminal 241, the second main terminal 242, and the output terminal 43 are arranged separately from each other.

[0061] Note that in addition to providing the individual terminals so as to protrude from different side surfaces of the sealing resin 70, an area of a portion protruding from the sealing resin 70 may be increased in each terminal. As shown in Fig. 3, Fig. 4 and Fig. 5, in particular, the individual terminals may be provided so as to protrude from different side surfaces of the sealing resin 70, and a width of the portion protruding from the sealing resin 70 in each terminal may be increased in a direction orthogonal to a protrusion direction in plan view. A configuration in which the width of the portion protruding from the sealing resin 70 in each terminal is increased will be described with reference to Fig. 3, Fig. 4 and Fig. 5 described.

[0062] As in Fig. 3, Fig. 4 and Fig. As illustrated in Fig. 5, the first main terminal 241, the second main terminal 242, and the output terminal 43 are arranged to protrude from different side surfaces of the sealing resin 70 so that a width in the direction orthogonal to the protrusion direction in plan view can be increased at the portion protruding from the sealing resin 70 in each terminal. Specifically, in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, a width of the portion protruding from the sealing resin 70 in the output terminal 43 is longer than a width of the second die pad 12. In the direction orthogonal to the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, a width of the portion protruding from the sealing resin 70 in the first main terminal 241 is longer than a width of the first die pad 11.In the direction orthogonal to the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, a width of the portion protruding from the sealing resin 70 in the second main terminal 242 is longer than a width of the second die pad 12.

[0063] For each terminal, as described above, in the portion protruding from the sealing resin 70 in the terminal, the width in the direction orthogonal to the direction in which it protrudes from the side surface of the sealing resin 70 in plan view is increased, thereby increasing the area of each terminal.

[0064] Although Fig. While FIG. 3 illustrates an example in which portions protruding from the sealing resin 70 in the first main terminal 241, the second main terminal 242, and the output terminal 43 have a quadrangular shape in plan view, the present disclosure is not limited thereto. The portions protruding from the sealing resin 70 in the first main terminal 241, the second main terminal 242, and the output terminal 43 may be, for example, a plate-shaped member having a polygonal shape or a rounded shape. <Verfahren zum Herstellen der zweiten bevorzugten Ausführungsform>

[0065] Since a method of manufacturing the semiconductor device 102 according to the second preferred embodiment of the present disclosure is similar to the method of manufacturing the semiconductor device 101 according to the first preferred embodiment, its description will be omitted. <Wirkung und Effekt der zweiten bevorzugten Ausführungsform>

[0066] Next, the action and effect of the semiconductor device 102 according to the second preferred embodiment of the present disclosure will be described.

[0067] The semiconductor device 102 according to the second preferred embodiment of the present disclosure includes: the output terminal 43 arranged to protrude from the first lateral surface of the sealing resin 70, which includes the first side 71, which is a side extending in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, among the sides in plan view of the sealing resin 70 having a quadrangular shape in plan view; the first main terminal 241 arranged to protrude from the second lateral surface of the sealing resin 70, which includes the second side 72, which is a side on the one end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, among the sides of the sealing resin 70 in plan view;and the second main terminal 242 arranged to protrude from the third lateral surface of the sealing resin 70, which includes the third side 73, which is a side on the other end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, among the sides of the sealing resin 70 in plan view.;

[0068] According to the semiconductor device 102 of the second preferred embodiment of the present disclosure, the first main terminal 241, the second main terminal 242, and the output terminal 43 are arranged to protrude from the second side surface, the third side surface, and the first side surface, respectively, which are different side surfaces of the sealing resin 70. Therefore, the first main terminal 241, the second main terminal 242, and the output terminal 43 are arranged away from each other, and a creepage distance between the terminals can be reliably ensured.

[0069] Furthermore, in the semiconductor device 102 according to the second preferred embodiment of the present disclosure, in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, the width of the portion protruding from the sealing resin 70 in the output terminal 43 is longer than the width of the second die pad 12. In the direction orthogonal to the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, the width of the portion protruding from the sealing resin 70 in the first main terminal 241 is longer than the width of the first die pad 11. In the direction orthogonal to the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, the width of a portion protruding from the sealing resin 70 in the second main terminal 242 is longer than the width of the second die pad 12.

[0070] As described above, according to the semiconductor device 102 of the second preferred embodiment of the present disclosure, it is possible to increase the areas of the first main terminal 241, the second main terminal 242, and the output terminal 43 relative to the area of the semiconductor device 102 compared with the first preferred embodiment, while reliably ensuring a creepage distance between the terminals. Heat generated by a first semiconductor element 21 and a second semiconductor element 22 is dissipated to the outside of the semiconductor device 102 via the first main terminal 241, the second main terminal 242, and the output terminal 43.Therefore, according to the semiconductor device 102 of the second preferred embodiment of the present disclosure, by increasing the areas of the first main terminal 241, the second main terminal 242, and the output terminal 43, the heat dissipation of the semiconductor device 102 can be further improved. Furthermore, according to the semiconductor device 102 of the second preferred embodiment of the present disclosure, by improving the heat dissipation of the semiconductor device 102, it is possible to further increase an excitation current of the semiconductor device 102. Third preferred embodiment

[0071] In the second preferred embodiment of the present disclosure, the semiconductor device 102 was described, which includes: the output terminal 43 arranged to protrude from the first lateral surface of the sealing resin 70; the first main terminal 241 arranged to protrude from the second lateral surface of the sealing resin 70; and the second main terminal 242 arranged to protrude from the third lateral surface of the sealing resin 70. In a third preferred embodiment of the present disclosure, a semiconductor device 103 is described, which includes a first main terminal 341, a second main terminal 342, and an output terminal 343, in which at least a part of a portion protruding from a sealing resin 70 is formed in a comb shape.

[0072] In the third preferred embodiment, the same components as those in the first and second preferred embodiments of the present disclosure are denoted by the same reference numerals, and descriptions of the same or corresponding parts are omitted. Hereinafter, the semiconductor device 103 according to the third preferred embodiment will be described with reference to the drawings. <Konfiguration der dritten bevorzugten Ausführungsform>

[0073] With reference to Fig. 6, a configuration of the semiconductor device 103 according to the third preferred embodiment of the present disclosure will be described. Fig. 6 is a plan view illustrating the semiconductor device 103. In Fig. 6, the sealing resin 70 is omitted to show a structure within the sealing resin 70. In Fig. 6, a contour when the sealing resin 70 is present is indicated by a dashed line.

[0074] As in Fig. 6, the semiconductor device 103 includes the first main terminal 341, the second main terminal 342, and the output terminal 343, in which a portion of a portion protruding from the sealing resin 70 is formed in a comb shape. As shown in Fig. For example, as illustrated in FIG. 6, a portion protruding from the sealing resin 70 in each of the first main terminal 341, the second main terminal 342, and the output terminal 343 is a polygon having a side formed into a comb shape in plan view. That is, the portions protruding from the sealing resin 70 in the first main terminal 341, the second main terminal 342, and the output terminal 343, before being formed into a comb shape, have a quadrangular shape in plan view, and are formed by forming a side into a comb shape in a plate-shaped member having a quadrangular shape in plan view.

[0075] It is sufficient to form a part of the portions protruding from the sealing resin 70 into a comb shape in the first main terminal 341, the second main terminal 342, and the output terminal 343. The first main terminal 341, the second main terminal 342, and the output terminal 343 are not limited to those in which one side of the plate-shaped member having the quadrangular shape in plan view at the portion protruding from the sealing resin 70 is completely formed into a comb shape, and may be those in which one side is partially formed into a comb shape. Further, the first main terminal 341, the second main terminal 342, and the output terminal 343 may be formed by forming two or more sides of the plate-shaped member having the quadrangular shape in plan view at the portion protruding from the sealing resin 70 into a comb shape.Further, in the first main terminal 341, the second main terminal 342, and the output terminal 343, the portion protruding from the sealing resin 70 before being formed into a comb shape may not have a quadrangular shape in plan view, and a part of the portion protruding from the sealing resin 70 may be formed into a plate-shaped member having a polygonal or rounded shape in a comb shape.

[0076] Fig. 6 illustrates an example in which the first main terminal 341, the second main terminal 342, and the output terminal 343, in which a part of a portion protruding from the sealing resin 70 is formed in a comb shape, protrude from the second lateral surface, the third lateral surface, and the first lateral surface of the sealing resin 70, respectively, similar to the second preferred embodiment. Without being limited thereto, the first main terminal 341, the second main terminal 342, and the output terminal 343, in which a part of a portion protruding from the sealing resin 70 is formed in a comb shape, may be arranged to protrude from the first lateral surface, for example, similar to the first preferred embodiment.

[0077] As described above, since a part of a portion protruding from the sealing resin 70 in each terminal is formed in a comb shape, an area where each terminal comes into contact with an external substrate or outside air (not illustrated) is increased. <Verfahren zum Herstellen der dritten bevorzugten Ausführungsform>

[0078] Next, a method for manufacturing the semiconductor device 103 according to the third preferred embodiment of the present disclosure will be described. Note that, in the present preferred embodiment, among processes for manufacturing the semiconductor device 103, processes other than a process for forming the first main terminal 341, the second main terminal 342, and the output terminal 343 can be implemented by appropriately applying a known technology. Therefore, only the process for forming the first main terminal 341, the second main terminal 342, and the output terminal 343 will be described here.

[0079] The first main terminal 341, the second main terminal 342, and the output terminal 343 are formed by punching a copper plate with conductivity and good thermal conductivity. The first main terminal 341, the second main terminal 342, and the output terminal 343 are formed, for example, by punching the copper plate into a predetermined shape using a mold. Here, the predetermined shape is, for example, a polygonal shape with one side formed into a comb shape. <Wirkung und Effekt der dritten bevorzugten Ausführungsform>

[0080] Next, the action and effect of the semiconductor device 103 according to the third preferred embodiment of the present disclosure will be described.

[0081] The semiconductor device 103 according to the third preferred embodiment of the present disclosure includes the first main terminal 341, the second main terminal 342, and the output terminal 343, in which a part of a portion protruding from the sealing resin 70 is formed in a comb shape.

[0082] According to the semiconductor device 103 of the third preferred embodiment of the present disclosure, in the first main terminal 341, the second main terminal 342, and the output terminal 343, at least a portion of a portion protruding from the sealing resin 70 is formed in a comb shape. Therefore, an area where each of the first main terminal 341, the second main terminal 342, and the output terminal 343 contacts an external substrate or outside air (not illustrated) can be increased compared to the first and second preferred embodiments. Heat generated by a first semiconductor element 21 and a second semiconductor element 22 is transferred to an external substrate or outside air (not illustrated) via the first main terminal 341, the second main terminal 342, and the output terminal 343 to be discharged to the outside of the semiconductor device 103.Therefore, according to the semiconductor device 103 of the third preferred embodiment of the present disclosure, heat dissipation of the semiconductor device 103 can be further improved by providing the first main terminal 341, the second main terminal 342, and the output terminal 343 in which at least a portion protruding from the sealing resin 70 is formed in a comb shape. Furthermore, according to the semiconductor device 103 of the third preferred embodiment of the present disclosure, by improving heat dissipation of the semiconductor device 103, it is possible to further increase an excitation current of the semiconductor device 103. Fourth Preferred Embodiment

[0083] In the first preferred embodiment of the present disclosure, the semiconductor device 101 was described, which includes the first wire 31, the second wire 32, and the third wire 33. In a fourth preferred embodiment of the present disclosure, a semiconductor device 104 is described in which the number of wires through which current frequently flows is two or more in a first wire 31, a second wire 32, and a third wire 33. <Konfiguration der vierten bevorzugten Ausführungsform>

[0084] A configuration of the semiconductor device 104 according to the fourth preferred embodiment of the present disclosure will be described with reference to Fig. 7 described. Fig. 7 is a plan view illustrating the semiconductor device 104. In Fig. 7, a sealing resin 70 is omitted to show a structure within the sealing resin 70. In Fig. 7, a contour when the sealing resin 70 is present is indicated by a dashed line.

[0085] As in Fig. 7, in the semiconductor device 104, the number of wires is two or more in: the first wire 31, a first wire 31a arranged to connect between two first die pads 11 on the one end side in a direction in which the first die pad 11 and a second die pad 12 are alternately arranged; the second wire 32, a second wire 32a arranged to connect between two second semiconductor elements 22 on the other end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged; and the third wire 33.

[0086] The first wire 31a, the second wire 32a, and the third wire 33 are wires through which current frequently flows, compared with a first wire 31b arranged to connect between two first die pads 11 on the other end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged, and a second wire 32b arranged to connect between two second semiconductor elements 22 on the one end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged. Therefore, by increasing the number of the first wires 31a, the second wires 32a, and the third wires 33, it is possible to reduce a density of the current flowing through a wire and reduce a load due to the current. <Verfahren zum Herstellen der vierten bevorzugten Ausführungsform>

[0087] Since a method of manufacturing the semiconductor device 104 according to the fourth preferred embodiment of the present disclosure is similar to the method of manufacturing the semiconductor device 101 according to the first preferred embodiment, its description will be omitted. <Wirkung und Effekt der vierten bevorzugten Ausführungsform>

[0088] Next, the action and effect of the semiconductor device 104 according to the fourth preferred embodiment of the present disclosure will be described.

[0089] In the semiconductor device 104 according to the fourth preferred embodiment of the present disclosure, the number of wires is two or more in: the first wire 31, the first wire 31a arranged to connect between two first die pads 11 on the one end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged; the second wire 32, the second wire 32a arranged to connect between two second semiconductor elements 22 on the other end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged; and the third wire 33.

[0090] According to the semiconductor device 104 of the fourth preferred embodiment of the present disclosure, it is possible to reduce the density of a current flowing through the first wire 31a, the second wire 32a, and the third wire 33, which are wires through which current frequently flows, and to reduce the load due to the current flowing through each wire. Therefore, according to the semiconductor device 104 of the fourth preferred embodiment of the present disclosure, by reducing the load due to the current flowing through each wire, deterioration of the wire can be suppressed and the power cycle life of the semiconductor device 104 can be improved. Fifth Preferred Embodiment

[0091] In the fourth preferred embodiment of the present disclosure, the semiconductor device 104 was described in which the number of wires in the first wires 31a, the second wires 32a, and the third wires 33, which are wires through which current frequently flows, is two or more. In a fifth preferred embodiment of the present disclosure, a semiconductor device 105 is described in which the wire diameters of a first wire 31a, a second wire 32a, and a third wire 33 are increased. <Konfiguration der fünften bevorzugten Ausführungsform>

[0092] With reference to Fig. 8, a configuration of the semiconductor device 105 according to the fifth preferred embodiment of the present disclosure will be described. Fig. 8 is a plan view illustrating the semiconductor device 105. In Fig. 8, a sealing resin 70 is omitted to show a structure within the sealing resin 70. In Fig. 8, a contour when the sealing resin 70 is present is indicated by a dashed line.

[0093] As in Fig.8, in the semiconductor device 105, a wire diameter is large in: in a first wire 31, the first wire 31a arranged to connect between two first die pads 11 on the one end side in the direction in which the first die pad 11 and a second die pad 12 are alternately arranged; in a second wire 32, the second wire 32a arranged to connect between two second semiconductor elements 22 on the other end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged; and the third wire 33, compared with: a first wire 31b arranged to connect between two first die pads 11 on the other end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged;and a second wire 32b arranged to connect between two second semiconductor elements 22 on the one end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged.;

[0094] As described in the fourth preferred embodiment, the first wire 31a, the second wire 32a, and the third wire 33 are wires through which current flows more frequently than through the first wire 31b and the second wire 32b. Therefore, by increasing the wire diameters of the first wire 31a, the second wire 32a, and the third wire 33, the density of a current flowing through the wire can be reduced and the load due to the current can be reduced. <Verfahren zum Herstellen der fünften bevorzugten Ausführungsform>

[0095] Since a method of manufacturing the semiconductor device 105 according to the fifth preferred embodiment of the present disclosure is similar to the method of manufacturing the semiconductor device 101 according to the first preferred embodiment, its description will be omitted. <Wirkung und Effekt der fünften bevorzugten Ausführungsform>

[0096] Next, the action and effect of the semiconductor device 105 according to the fifth preferred embodiment of the present disclosure will be described.

[0097] In the semiconductor device 105 according to the fifth preferred embodiment of the present disclosure, a wire diameter is large in: in the first wire 31, the first wire 31a arranged to connect between two first die pads 11 on one end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged; in the second wire 32, the second wire 32a arranged to connect between two second semiconductor elements 22 on the other end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged; and the third wire 33, compared with: the first wire 31b arranged to connect between two first die pads 11 on the other end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged;and the second wire 32b arranged to connect between two second semiconductor elements 22 on the one end side in the direction in which the first die pad 11 and the second die pad 12 are alternately arranged;

[0098] According to the semiconductor device 105 of the fifth preferred embodiment of the present disclosure, it is possible to reduce the density of a current flowing through the first wire 31a, the second wire 32a, and the third wire 33, which are wires through which current frequently flows, and to reduce the load due to the current flowing through each wire. Therefore, according to the semiconductor device 105 of the fifth preferred embodiment of the present disclosure, by reducing the load due to the current flowing through each wire, deterioration of the wire can be suppressed and the power cycle life of the semiconductor device 105 can be improved.

[0099] Although the present disclosure has been described above based on each preferred embodiment, the present disclosure is not limited to each preferred embodiment. Furthermore, appropriate combination, modification, or omission of each preferred embodiment is also included within the scope of the technical idea of the present disclosure.

[0100] These and other objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when taken in conjunction with the accompanying drawings. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2009-111154 [0002, 0003, 0004, 0051, 0052]

Claims

[1] A semiconductor device (101 - 105), comprising: at least three first die pads (11); at least three first semiconductor elements (21) individually mounted on the first die pads (11); a first wire (31) electrically connecting each of the first semiconductor elements (21); at least three second die pads (12) arranged alternately with the first die pads (11); at least three second semiconductor elements (22) individually mounted on the second die pads (12); and a second wire (32) electrically connecting each of the second semiconductor elements (22). [2] The semiconductor device (101-105) according to claim 1, further comprising: a first main terminal (41, 241, 341) extending from a first die pad (11) among the first die pads (11), the first die pad (11) being arranged on one end side in a direction in which the first die pads (11) and the second die pads (12) are alternately arranged; a second main terminal (42, 242, 342) arranged on another end side in the direction in which the first die pads (11) and the second die pads (12) are alternately arranged; at least three output terminals (43, 343) extending from at least three of the second die pads (12); and a sealing resin (70) configured to seal the first die pads (11), the second die pads (12), the first semiconductor elements (21), the second semiconductor elements (22), the first wire (31), the second wire (32), a part of the first main terminal (41, 241, 341), a part of the second main terminal (42, 242, 342), and a part of each of the output terminals (43, 343). [3] A semiconductor device (101 - 105) according to claim 2, wherein the sealing resin (70) has a square shape in plan view and the first main terminal (41, 241, 341), the second main terminal (42, 242, 342) and the output terminals (43, 343) are arranged to protrude from a first lateral surface comprising a first side in the sealing resin (70), wherein the first side among the sides of the sealing resin (70) in plan view is a side extending in the direction in which the first die pads (11) and the second die pads (12) are alternately arranged. [4] A semiconductor device (101 - 105) according to claim 2, wherein the sealing resin (70) has a square shape in plan view, the output terminals (43, 343) are arranged to protrude from a first lateral surface comprising a first side in the sealing resin (70), wherein the first side among the sides of the sealing resin (70) in plan view is a side extending in the direction in which the first die pads (11) and the second die pads (12) are alternately arranged, the first main terminal (41, 241, 341) is arranged to protrude from a second lateral surface comprising a second side in the sealing resin (70), the second side among the sides of the sealing resin (70) being, in plan view, a side on the one end side in the direction in which the first die pads (11) and the second die pads (12) are alternately arranged, and the second main terminal (42, 242, 342) is arranged to protrude from a third lateral surface comprising a third side in the sealing resin (70), the third side among the sides of the sealing resin (70) being, in plan view, a side on the other end side in the direction in which the first die pads (11) and the second die pads (12) are alternately arranged. [5] Semiconductor device (101 - 105) according to claim 4, wherein in the direction in which the first die pads (11) and the second die pads (12) are alternately arranged, a width of a portion protruding from the sealing resin (70) in each of the output terminals (43, 343) is longer than a width of each of the second die pads (12), in a direction orthogonal to the direction in which the first die pads (11) and the second die pads (12) are alternately arranged, a width of a portion protruding from the sealing resin (70) in the first main terminal (41, 241, 341) is longer than a width of each of the first die pads (11) and in a direction orthogonal to the direction in which the first die pads (11) and the second die pads (12) are alternately arranged, a width of a portion protruding from the sealing resin (70) in the second main terminal (42, 242, 342) is longer than a width of each of the second die pads (12). [6] The semiconductor device (101-105) according to any one of claims 2 to 5, wherein in the first main terminal (41, 241, 341), the second main terminal (42, 242, 342) and the output terminals (43, 343), at least a part of a portion protruding from the sealing resin (70) is formed in a comb shape. [7] A semiconductor device (101 - 105) according to any one of claims 2 to 5, further comprising a third wire (33) electrically connecting the second main terminal (42, 242, 342) to a second semiconductor element (22) among the second semiconductor elements (22), wherein the first wire (31) is arranged to connect between two of the first die pads (11) which are adjacent to each other, wherein one of the second die pads (12) is arranged between the two of the first die pads (11), the second wire (32) is arranged to connect between two of the second semiconductor elements (22) individually mounted on two of the second die pads (12) that are adjacent to each other, one of the first die pads (11) being arranged between the two of the second die pads (12), and the third wire (33) is arranged to connect between the second semiconductor element (22) and the second main terminal (42, 242, 342), wherein the second semiconductor element (22) is mounted on a second die pad (12) among the second die pads (12), the second die pad (12) being arranged on the other end side in the direction in which the first die pads (11) and the second die pads (12) are alternately arranged. [8] The semiconductor device (101-105) according to claim 7, wherein a number of wires is two or more in: in the first wire (31), the first wire (31a) arranged to connect between two of the first die pads (11) on the one end side in the direction in which the first die pads (11) and the second die pads (12) are alternately arranged; in the second wire (32), the second wire (32a) arranged to connect between two of the second semiconductor elements (22) on the other end side in the direction in which the first die pads (11) and the second die pads (12) are alternately arranged; and the third wire (33). [9] The semiconductor device (101-105) according to claim 7, wherein a wire diameter is large in: in the first wire (31), the first wire (31a) arranged to connect between two of the first die pads (11) on the one end side in the direction in which the first die pads (11) and the second die pads (12) are alternately arranged; in the second wire (32), the second wire (32a) arranged to connect between two of the second semiconductor elements (22) on the other end side in the direction in which the first die pads (11) and the second die pads (12) are alternately arranged; and the third wire (33), in comparison with a wire diameter of the first wire (31b) arranged to connect between two of the first die pads (11) on the other end side and the second wire (32b) arranged to connect between two of the second semiconductor elements (22) on the one end side.

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